KR20180050929A - Chip scale packaged light emitting diode - Google Patents

Abstract

Provided is a chip scale package light emitting diode. According to an embodiment of the present invention, the light emitting diode is separated from an opening part of a lower insulating layer which exposes an ohmic reflective layer on which opening parts of an upper insulating layer exposing a pad metal layer are formed on a mesa. Therefore, a solder, particularly Sn, is diffused, thereby preventing the ohmic reflective layer from being contaminated. The light emitting diode comprises: a first conductive semiconductor layer; the mesa; the ohmic reflective layer; the lower insulating layer; a first pad metal layer; a second pad metal layer; and the upper insulating layer.

Description

[0001] CHIP SCALE PACKAGED LIGHT EMITTING DIODE [0002]

The present invention relates to a light emitting diode, and more particularly, to a light emitting diode in the form of a chip scale package.

In general, nitrides of a Group III element such as gallium nitride (GaN) and aluminum nitride (AlN) have excellent thermal stability and have a direct bandgap energy band structure. Recently, nitride materials for visible light and ultraviolet Has received a lot of attention. In particular, blue and green light emitting diodes using indium gallium nitride (InGaN) are utilized in various applications such as large-scale color flat panel displays, traffic lights, indoor lighting, high density light sources, high resolution output systems and optical communication.

2. Description of the Related Art In recent years, light emitting diodes are being studied in the form of a chip scale package in which a packaging process is performed at a chip level. Such a light emitting diode is smaller in size than a general package and does not require a separate packaging process, which further simplifies the process and saves time and money.

The light emitting diode in the form of a chip scale package generally has a flip chip electrode structure, and thus has excellent heat dissipation characteristics. However, such a light emitting diode is generally manufactured to have a flip chip electrode structure, and further, there is a problem that the structure of the light emitting diode is considerably complicated in order to prevent diffusion of solder used in flip bonding. However, the solder, particularly Sn, may diffuse into the light emitting diode to contaminate the ohmic reflective layer, resulting in a failure of the light emitting diode.

Accordingly, efforts are being made to provide a reliable light emitting diode while simplifying the structure of the light emitting diode.

SUMMARY OF THE INVENTION The present invention provides a light emitting diode capable of effectively preventing diffusion of a bonding material, such as solder, without increasing the complexity of the structure of the light emitting diode, thereby improving reliability.

According to an embodiment of the present invention, a light emitting diode includes: a first conductive semiconductor layer; A mesa on the first conductivity type semiconductor layer, the mesa including an active layer and a second conductivity type semiconductor layer; An ohmic reflective layer disposed on the mesa and electrically connected to the second conductive semiconductor layer; A lower insulating layer covering the mesa and the ohmic reflective layer, the lower insulating layer including a first opening exposing the first conductivity type semiconductor layer and a second opening exposing the ohmic reflective layer; A first pad metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the first opening; A second pad metal layer disposed on the lower insulating layer and electrically connected to the ohmic reflective layer through the second opening; And an upper insulating layer covering the first pad metal layer and the second pad metal layer, the upper insulating layer including a first opening exposing the first pad metal layer and a plurality of second openings exposing the second pad metal layer, And the second openings of the upper insulating layer are spaced apart from the second openings of the lower insulating layer so as not to overlap.

According to embodiments of the present invention, it is possible to prevent the second openings of the upper insulating layer from overlapping with the second openings of the lower insulating layer, thereby preventing the solder, particularly Sn, from diffusing through the openings of the lower insulating layer into the ohmic reflective layer The reliability of the light emitting diode can be improved.

Other advantages and effects of the present invention will become more apparent from the detailed description.

1 is a schematic plan view illustrating a light emitting diode according to an embodiment of the present invention.
2 is a cross-sectional view taken along the perforated line AA of FIG.
3A and 3B are schematic plan views for explaining openings of a lower insulating layer and an upper insulating layer in connection with the embodiment of FIG.
4 is a schematic plan view illustrating a light emitting diode according to another embodiment of the present invention.
5 is a schematic plan view illustrating a light emitting diode according to another embodiment of the present invention.
6 is a schematic plan view illustrating a light emitting diode according to another embodiment of the present invention.
7 is a cross-sectional view taken along the perforation line BB in Fig.
8 is a schematic plan view illustrating a light emitting diode according to another embodiment of the present invention.
9 is a sectional view taken along the perforated line CC in Fig.
10A and 10B are schematic plan views for explaining openings of a lower insulating layer and an upper insulating layer in connection with the embodiment of FIG.
11 is a schematic plan view illustrating a light emitting diode according to another embodiment of the present invention.
12 is an exploded perspective view illustrating a lighting apparatus to which a light emitting diode according to an embodiment of the present invention is applied.
13 is a cross-sectional view illustrating a display device to which a light emitting diode according to another embodiment of the present invention is applied.
14 is a cross-sectional view illustrating a display device to which a light emitting diode according to another embodiment of the present invention is applied.
15 is a sectional view for explaining an example in which a light emitting diode according to another embodiment of the present invention is applied to a headlamp.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can sufficiently convey the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. It is also to be understood that when an element is referred to as being "above" or "above" another element, But also includes the case where another component is interposed between the two. Like reference numerals designate like elements throughout the specification.

According to an embodiment of the present invention, a light emitting diode includes: a first conductive semiconductor layer; A mesa on the first conductivity type semiconductor layer, the mesa including an active layer and a second conductivity type semiconductor layer; An ohmic reflective layer disposed on the mesa and electrically connected to the second conductive semiconductor layer; A lower insulating layer covering the mesa and the ohmic reflective layer, the lower insulating layer including a first opening exposing the first conductivity type semiconductor layer and a second opening exposing the ohmic reflective layer; A first pad metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the first opening; A second pad metal layer disposed on the lower insulating layer and electrically connected to the ohmic reflective layer through the second opening; And an upper insulating layer covering the first pad metal layer and the second pad metal layer, the upper insulating layer including a first opening exposing the first pad metal layer and a plurality of second openings exposing the second pad metal layer, And the second openings of the upper insulating layer are spaced apart from the second openings of the lower insulating layer so as not to overlap.

The diffusion path of the solder can be reduced by forming the plurality of second openings in the upper insulating layer, and furthermore, the plurality of second openings are separated from the second openings of the lower insulating layer in the upper insulating layer, Can be blocked.

The light emitting diode may include: a first bump pad connected to the first pad metal layer through a first opening of the upper insulating layer; And a second bump pad connected to the second pad metal layer through a plurality of second openings of the upper insulating layer. The first conductive semiconductor layer may be disposed on a substrate.

In some embodiments, the shortest distance from the second opening of the lower insulating layer to the second opening of the upper insulating layer may be greater than the shortest distance between the second openings of the upper insulating layer.

In some embodiments, the lower insulating layer may include a plurality of second openings, and the shortest distance from the second opening of the lower insulating layer to the second opening of the upper insulating layer may be a distance 2 < / RTI >

The upper insulating layer and the lower insulating layer prevent the solder from diffusing, but the solder can reach the second opening of the lower insulating layer along the interface of the lower insulating layer and the second pad metal layer. Thus, by spacing the second opening of the lower insulating layer away from the second opening of the upper insulating layer within a limited design range, the diffusion path of the solder can be increased, thereby preventing defects due to solder diffusion.

The first opening of the lower insulating layer exposes the first conductive type semiconductor layer along the mesa, and the first pad metal layer has an external contact portion contacting the first conductive type semiconductor layer along the mesa . The first pad metal layer contacts the first conductivity type semiconductor layer along the mesa periphery, so that the current dispersion performance of the light emitting diode can be improved.

In addition, the mesa may include an indentation for exposing the first conductivity type semiconductor layer, and the first opening of the lower insulation layer may further expose the first conductivity type semiconductor layer in the indent. Furthermore, the first pad metal layer may further include an internal contact portion that contacts the first conductive type semiconductor layer in the indentation portion. Since the first pad metal layer contacts the first conductivity type semiconductor layer at the mesa periphery and inside the mesa, the current dispersion performance of the light emitting diode is further enhanced.

Further, the inner contact portion may be connected to the outer contact portion, but the present invention is not limited thereto, and the inner contact portion and the outer contact portion may be spaced apart from each other.

In some embodiments, the mesa has a via hole that exposes the first conductive semiconductor layer through the second conductive semiconductor layer and the active layer, and the first opening of the lower insulating layer is exposed to the via hole And the first pad metal layer may have an internal contact portion contacting the first conductive semiconductor layer exposed in the via hole.

Furthermore, the first pad metal layer may include external contacts that are in contact with the first conductive type semiconductor layer outside the mesa, and the external contacts may be spaced apart from each other.

Meanwhile, the lower insulating layer may include a plurality of second openings, and the second bump pad may cover an upper portion of at least one second opening of the lower insulating layer. Furthermore, the second bump pad may cover the entire upper portions of the second openings of the lower insulating layer.

In addition, the first and second bump pads may seal the first and second openings of the upper insulating layer, respectively. The first and second bump pads prevent the first and second pad metal layers from being exposed to the solder. It is also possible to reduce the diffusion path of the solder diffused into the first and second pad metal layers through the first and second bump pads by forming a plurality of the first and second openings of the upper insulating layer, Can be delayed.

Meanwhile, the first bump pad may cover the upper portion of at least one second opening of the lower insulating layer. As long as the first bump pad is insulated from the second pad metal layer, the position and the shape of the first bump pad may be variously modified, and the position and the shape of the second bump pad may be variously changed as long as they are insulated from the first pad metal layer. For example, the second bump pad may include a protrusion between the first bump pad and the first bump pad. Furthermore, at least one of the second openings of the lower insulating layer may be located below the protrusion.

Meanwhile, the second pad metal layer may be surrounded by the first pad metal layer. Accordingly, a boundary region in which the lower insulating layer is exposed may be formed between the first pad metal layer and the second pad metal layer. This boundary region can be covered by the upper insulating layer.

In some embodiments, the lower insulating layer includes a plurality of second openings, and at least one of the second openings of the upper insulating layer may be disposed between the two second openings of the lower insulating layer .

A plurality of mesas may be disposed on the first conductive semiconductor layer, and the second openings of the lower insulating layer and the second openings of the upper insulating layer may be located on each mesa, The second bump pads may be disposed over the plurality of mesas, respectively. Further, the first pad metal layer may cover the mesas and the second pad metal layer may be disposed on each mesa.

In some embodiments, the second bump pad may be located within the second pad metal layer upper region, but is not limited thereto, and the second bump pad may partially overlap the first pad metal layer It is possible.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic plan view for explaining a light emitting diode according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along a perforated line A-A of FIG.

1 and 2, the light emitting diode includes a substrate 21, a first conductive semiconductor layer 23, an active layer 25, a second conductive semiconductor layer 27, an ohmic reflective layer 31, A first pad metal layer 35a, and a second pad metal layer 35b) and an upper insulating layer 37. The upper insulating layer 37 is formed of an insulating layer 33, a first pad metal layer 35a, and a second pad metal layer 35b. Furthermore, the light emitting diode may further include a preliminary insulating layer 29, and may further include a first bump pad 39a and a second bump pad 39b.

The substrate 21 is not particularly limited as long as it is a substrate capable of growing a gallium nitride based semiconductor layer. Examples of the substrate 21 include a sapphire substrate, a gallium nitride substrate, a SiC substrate, and the like, and may be a patterned sapphire substrate. The substrate 21 may have a rectangular or square shape as shown in the plan view (a), but is not limited thereto. The size of the substrate 21 is not particularly limited and may be variously selected.

The first conductive type semiconductor layer 23 is disposed on the substrate 21. The first conductive semiconductor layer 23 is a layer grown on the substrate 21 and may be a gallium nitride-based semiconductor layer. The first conductive semiconductor layer 23 may be a gallium nitride-based semiconductor layer doped with an impurity, for example, Si.

A mesa (M) is disposed on the first conductivity type semiconductor layer (23). The mesa M may be located within the region surrounded by the first conductivity type semiconductor layer 23 so that the regions near the edges of the first conductivity type semiconductor layer are not covered by the mesa M, Exposed.

The mesa M includes a second conductivity type semiconductor layer 27 and an active layer 25. The active layer 25 is interposed between the first conductivity type semiconductor layer 23 and the second conductivity type semiconductor layer 27. The active layer 25 may have a single quantum well structure or a multiple quantum well structure. The composition and thickness of the well layer in the active layer 25 determine the wavelength of the generated light. In particular, by controlling the composition of the well layer, it is possible to provide an active layer that generates ultraviolet light, blue light or green light.

On the other hand, the second conductivity type semiconductor layer 27 may be a p-type impurity, for example, a gallium nitride based semiconductor layer doped with Mg. Although the first conductive semiconductor layer 23 and the second conductive semiconductor layer 27 may each be a single layer, the present invention is not limited thereto, and may be a multiple layer or a superlattice layer. The first conductivity type semiconductor layer 23, the active layer 25 and the second conductivity type semiconductor layer 27 are formed by a known method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) And may be formed on the substrate 21 by growing.

1, the mesa M may be formed with an indentation 30 penetrating into the mesa M, and the mesa M may be formed on the upper surface of the first conductivity type semiconductor layer 23 by the indentation 30, Lt; / RTI > The indentation 30 may be formed long inside the mesa M from one edge of the mesa M toward the opposite edge thereof. The length of the indentation 30 is not particularly limited, and may be 1/2 or more of the mesa M length. In addition, although two indentations 30 are shown in FIG. 1, the number of indentations 30 may be one or three or more. As the number of the indentations 30 increases, the number of inner contact portions 35a2 of the first pad metal layer 35a to be described later increases to improve the current dispersion performance.

On the other hand, the indentation 30 has a round shape as its width becomes wider at the end portion. By doing this, the lower insulating layer 33 can be formed in a similar shape. Particularly, when the lower insulating layer 33 includes the distributed Bragg reflector, if the width is not widened at the end portion as shown in FIG. 1, a severe double step is formed on the side wall of the distributed Bragg reflector and the inclination angle of the side wall becomes large, Breakage of the pad metal layer 35a is likely to occur. Thus, by forming the shape of the end of the depression 30 and the shape of the end of the first opening 33a2 of the lower insulating layer 33, the lower insulating layer 33 is formed to have a gentle inclination angle And the yield of the light emitting diode can be improved.

On the other hand, the ohmic reflective layer 31 is disposed on the mesa M and contacts the second conductive type semiconductor layer 27. The ohmic reflective layer 31 may be disposed over substantially the entire area of the mesa M in the mesa M upper region. For example, the ohmic reflective layer 31 may cover 80% or more of the upper region of the mesa (M), and moreover, 90% or more.

The OMR reflective layer 31 may include a reflective metal layer so that the light generated in the active layer 25 and traveling to the OMR reflective layer 31 can be reflected to the substrate 21 side. For example, the ohmic reflective layer 31 may be formed of a single reflective metallic layer, but is not limited thereto, and may include an ohmic layer and a reflective layer. As the ohmic layer, a metal layer such as Ni or a transparent oxide layer such as ITO may be used. As the reflective layer, a metal layer having high reflectance such as Ag or Al may be used.

On the other hand, the preliminary insulating layer 29 can cover the mesa M around the ohmic reflective layer 31. The preliminary insulating layer 29 may be formed of, for example, SiO _2, and may cover the side surface of the mesa M and further cover a part of the region of the first conductivity type semiconductor layer 23. In another embodiment, the pre-insulating layer 29 may be disposed only on the periphery of the ohmic reflective layer 31 at the top of the mesa M only.

The lower insulating layer 33 covers the mesa M and the ohmic reflective layer 31. The lower insulating layer 33 may also cover the first conductivity type semiconductor layer 23 along the mesa M and the first conductivity type semiconductor layer 23 . The lower insulating layer 33 covers the side surface of the mesa M in particular.

The lower insulating layer 33 has first openings 33a1 and 33a2 for exposing the first conductivity type semiconductor layer and second openings 33b for exposing the ohmic reflective layer 31. The first opening 33a1 and the second opening 33a2 are formed in the lower insulating layer 33, The first opening 33a1 exposes the first conductivity type semiconductor layer 23 along the mesa M and the first opening 33a2 exposes the first conductivity type semiconductor layer 23 ). As shown in FIG. 1, the first opening 33a1 and the first opening 33a2 may be connected to each other. However, the present invention is not limited thereto, and the first openings 33a1 and 33a2 may be spaced apart from each other.

And the second opening 33b exposes the OMR reflective layer 31. A plurality of second openings 33b may be formed and these second openings 33b may be disposed near one edge of the substrate 21 facing the indentation 30. [ The position of the second openings 33b will be described later.

On the other hand, the lower insulating layer 33 covers the preliminary insulating layer 29 and is integrated with the preliminary insulating layer 29. It is understood that the preliminary insulating layer 29 is included in the lower insulating layer 33 unless otherwise specified. The lower insulating layer 33 may be formed of a single layer of SiO ₂ or Si ₃ N ₄ , but is not limited thereto. For example, the lower insulating layer 33 may have a multi-layer structure including a silicon nitride film and a silicon oxide film, and may include a distributed Bragg reflector in which a silicon oxide film and a titanium oxide film are alternately laminated.

The first pad metal layer 35a is disposed on the lower insulating layer 33 and is insulated from the mesa M and the ohmic reflective layer 31 by the lower insulating layer 33. [ The first pad metal layer 35a contacts the first conductive semiconductor layer 23 through the first openings 33a and 33a2 of the lower insulating layer 33. [ The first pad metal layer 35a may include an external contact portion 35a1 contacting the first conductive semiconductor layer 23 along the mesa M and a first conductive semiconductor layer 23 within the recessed portion 30. [ And an inner contact portion 35a2 that contacts the contact portion 35a2. The external contact portion 35a1 contacts the first conductivity type semiconductor layer 23 near the edge of the substrate 21 along the periphery of the mesa M and the internal contact portion 35a2 contacts the inside of the region surrounded by the external contact portion 35a1 And is in contact with the first conductivity type semiconductor layer 23. The external contact portion 35a1 and the internal contact portion 35a2 may be connected to each other, but not limited thereto, and may be spaced apart from each other.

The second pad metal layer 35b is disposed on the upper portion of the mesa M on the lower insulating layer 33 and electrically connected to the ohmic reflective layer 31 through the second opening 33b of the lower insulating layer 33 Respectively. The second pad metal layer 35b may be surrounded by the first pad metal layer 35a and a boundary region 35ab may be formed therebetween. The lower insulating layer 33 is exposed in the boundary region 35ab and the boundary region 35ab is covered with the upper insulating layer 37 described later.

The first pad metal layer 35a and the second pad metal layer 35b may be formed of the same material in the same process. The first and second pad metal layers 35a and 35b may include an ohmic reflective layer such as an Al layer and the ohmic reflective layer may be formed on an adhesive layer such as Ti, Cr, or Ni. Further, a protective layer of a single layer or a multiple layer structure such as Ni, Cr, Au or the like may be formed on the ohmic reflective layer. The first and second pad metal layers 35a and 35b may have a multilayer structure of Cr / Al / Ni / Ti / Ni / Ti / Au / Ti, for example.

The upper insulating layer 37 covers the first and second pad metal layers 35a and 35b. The upper insulating layer 37 may cover the first conductive semiconductor layer 23 along the mesa M. However, the upper insulating layer 37 may expose the first conductivity type semiconductor layer 23 along the edge of the substrate 21.

The upper insulating layer 37 has a first opening 37a for exposing the first pad metal layer 35a and a plurality of second openings 37b for exposing the second pad metal layer 35b. The first opening 37a and the second opening 37b may be disposed in the upper region of the mesa M and may be arranged to face each other. In particular, the first opening 37a and the second opening 37b may be arranged close to both side edges of the mesa M.

The second opening 33b of the lower insulating layer 33 described above may be disposed near the second opening 37b of the upper insulating layer 37. [ The second opening 33b of the lower insulating layer 33 is spaced not only from the first opening 37a of the upper insulating layer 37 but also from the second opening 37b. This prevents the solder from diffusing into the second opening 33b of the lower insulating layer 33 even if the solder penetrates through the second opening 37b of the upper insulating layer 37, So that contamination of the reflective layer 31 can be prevented.

The upper insulating layer 37 may be formed of a single layer of SiO ₂ or Si ₃ N ₄ , but is not limited thereto. For example, the upper insulating layer 37 may have a multilayer structure including a silicon nitride film and a silicon oxide film, and may include a distributed Bragg reflector in which a silicon oxide film and a titanium oxide film are alternately laminated.

On the other hand, the first bump pad 39a is in electrical contact with the first pad metal layer 35a exposed through the first opening 37a of the upper insulating layer 37, and the second bump pad 39b is electrically connected to the second And is in electrical contact with the exposed second pad metal layer 35b through the opening 37b. The first bump pad 39a covers and seals the first openings 37a of the upper insulating layer 37 and the second bump pad 39b covers the upper insulating layer 37, And the second openings 37b of the second opening 37b. In addition, the second bump pad 39b covers the upper region of the second opening 33b of the lower insulating layer 33. That is, the second bump pad 39b covers the upper insulating layer 37 above the second opening 33b of the lower insulating layer 33. The second bump pad 39b may cover all of the second openings 33b of the lower insulating layer 33 but is not limited thereto and a part of the openings 33b may be formed on the outer side of the second bump pad 39b As shown in FIG.

Further, as shown in Fig. 1, the second bump pad 39b may be located within the upper region of the second pad metal layer 35a. However, the present invention is not limited thereto, and a part of the second bump pad 39b may overlap with the first pad metal layer 35a. However, the upper insulating layer 37 may be disposed between the first pad metal layer 35a and the second bump pad 39b to insulate them.

3A and 3B are schematic plan views for explaining the second openings 33b and 37b of the lower insulating layer and the upper insulating layer in relation to the embodiment of FIG.

3A shows the arrangement of the second openings 33b of the lower insulating layer 33 and the second openings 37b of the upper insulating layer 37 arranged in the same manner as the embodiment of FIG. Shows another modification.

3A and 3B, L 1 represents the shortest distance between the second opening 33 b and the second opening 37 b, L 2 represents the shortest distance between the second openings 33 b, 2 < / RTI > openings 37b.

In Fig. 3A, the second opening 33b and the second opening 37b are arranged up and down, and the second opening 33b and the second opening 37b are alternately arranged in the lateral direction. In this arrangement L1 is relatively short compared to L2 or L3. At least one of the second openings 37b is disposed between the second openings 33b.

In FIG. 3B, the same second openings 33b or 37b are arranged up and down, and the second openings 33b and the second openings 37b are alternately arranged in the lateral direction. In this arrangement L1 is relatively longer than L2 or L3. Also, at least one of the second openings 37b is disposed between the second openings 33b.

Considering the diffusion of the solder, it is advantageous to move away the second opening 33b and the second opening 37b, so that the arrangement of Figure 3b may be more advantageous than the arrangement of Figure 3a.

3A and 3B, the distance between the vertically disposed openings is shorter than the distance between the horizontally arranged openings. Alternatively, the distance between the left and right openings may be longer It may be short. In this case, the second openings 33b and the second openings 37b are arranged vertically so as to arrange the second openings 33b and the second openings 37b relatively farther apart, It is more advantageous to prevent solder diffusion that the first openings 33b are continuously arranged to the left and the second openings 37b are arranged continuously to the left and right.

However, the number and arrangement of the second openings 33b and the second openings 37b are selected in consideration of not only the contamination of the ohmic reflective layer 31 by the solder but also the efficiency of current dispersion and the symmetry of the light emission pattern. And thus can be modified in various ways.

4 is a schematic plan view illustrating a light emitting diode according to another embodiment of the present invention.

Referring to FIG. 4, the light emitting diode according to this embodiment is substantially similar to the light emitting diode described with reference to FIGS. 1 and 2, but the shape of the first pad metal layer 35a and the second pad metal layer 35B, The arrangement of the second opening 33b of the second bump pad 33 and the shape of the second bump pad 39b are different.

That is, the second openings 33b of the lower insulating layer 33 are added near the indentation 30 as compared with the embodiment of FIG. The added second openings 33b are disposed closer to the center of the mesa M than the edge of the mesa M in which the second openings 37b of the upper insulating layer 37 are disposed. Although the added second openings 33b are shown to be biased toward the edge side of the mesa M in which the second openings 37b of the upper insulating layer 37 are disposed, But the present invention is not limited thereto and may be located at the center of the mesa M or may be biased to the side of the edge of the mesa M where the first bump pad 39b is disposed.

And the second pad metal layer 35b is disposed so as to cover the second openings 33b. As shown in FIG. 4, the second pad metal layer 35b may have a concavo-convex shape having a concave portion near the depressed portion 30. The first pad metal layer 35a may have a concavo-convex shape so that the boundary 35ab region with the first pad metal layer 35b has a constant width.

On the other hand, the second bump pad 39b may have a shape similar to the second pad metal layer 35b and may cover the upper area of the added second openings 33b.

According to the present embodiment, the second openings 33b of the lower insulating layer 33 can be distributed relatively widely, which can help to distribute the current in the ohmic reflective layer 31. FIG.

5 is a schematic plan view illustrating a light emitting diode according to another embodiment of the present invention.

Referring to FIG. 5, the light emitting diode according to the present embodiment is substantially similar to the light emitting diode described with reference to FIG. 4, but the arrangement of the second openings 33b and the second openings 37b, There is a difference in the shape of the pads 39a and 39b.

That is, the first bump pad 39a extends to the upper region of the second pad metal layer 35b and covers the upper region of at least a part of the second openings 33b. However, the second openings 37b are spaced apart from the first bump pad 39a and located outside the first bump pad 39a. The second bump pad 39a covers the second openings 37b and may cover a part of the second openings 33b.

In this embodiment, the first bump pad 39a partially overlaps the second pad metal layer 35b. Alternatively, the second bump pad 39b may partially overlap the first pad metal layer 35a.

FIG. 6 is a schematic plan view for explaining a light emitting diode according to another embodiment of the present invention, and FIG. 7 is a schematic cross-sectional view taken along a perforated line B-B in FIG.

6 and 7, the light emitting diode according to the present embodiment is substantially similar to the light emitting diode described with reference to FIGS. 1 and 2, except that a via hole is formed instead of the recessed portion 30. FIG.

That is, the mesa M has a via hole 130 which exposes the first conductivity type semiconductor layer 23 through the second conductivity type semiconductor layer 27 and the active layer 25. The via hole 130 is surrounded by the second conductivity type semiconductor layer 27 and the active layer 25. The mesa M may have a plurality of via holes 130, and the via holes 130 may be regularly arranged in the mesa M. Although FIG. 6 shows nine via holes 130, it is not particularly limited. 6, recesses may be formed in the mesa M along the edge of the mesa M.

The lower insulating layer 133 covers the mesa M and the ohmic reflective layer 31 and includes a first opening 133a1 for exposing the first conductivity type semiconductor layer 23 from the outside of the mesa M, The first opening 133a2 may expose the first conductivity type semiconductor layer 23 in the first conductive semiconductor layer 23a. The lower insulating layer 133 has second openings 133b for exposing the ohmic reflective layer 31 on the mesa M. In addition,

The first pad metal layer 135a includes external contacts 135a1 and first openings 133a2 that are in contact with the first conductivity type semiconductor layer 23 through the first openings 133a1 of the lower insulating layer 133, And inner contact portions 135a2 contacting the first conductivity type semiconductor layer 23 through the second contact holes 135a1. The internal contacts 135a2 may be evenly distributed within the mesa M for current spreading. 6, the external contacts 135a1 may be distributed on three sides except for one side of the mesa M, but the present invention is not limited thereto and may be distributed on four sides. Further, the external contact portion 135a1 may be continuously formed along the mesa M as in the previous embodiments.

On the other hand, the second pad metal layer 135b is electrically connected to the ohmic reflective layer 31 through the second openings 133b of the lower insulating layer 133. The second pad metal layer 135b is spaced apart from the via holes 130. [ The second openings 133b of the lower insulating layer 133 may be located in the region surrounded by the via holes 130 and the second pad metal layer 135b may be located in the second openings 133a, (133b). Accordingly, the first pad metal layer 135a and the second pad metal layer 135b may be formed to have a concavo-convex shape.

The upper insulating layer 37 has a first opening 37a for exposing the first pad metal layer 135a and a second opening 37b for exposing the second pad metal layer 135b. The first openings 37b and the second openings 37b may be disposed near the opposite edges. In particular, the second openings of the upper insulating layer 27 are spaced apart from the second openings 133b of the lower insulating layer 133 so as not to overlap.

The first bump pad 139a and the second bump pad 139b are electrically connected to the first pad metal layer 135a and the second pad metal layer 135b through the first and second openings 37a and 37b of the upper insulating layer 37, And is electrically connected to the pad metal layer 135b.

As shown in FIG. 6, the second bump pad 139b may have a concavo-convex shape to enclose the via holes 130. In addition, the second bump pad 139b may cover at least a part of the second openings 133b of the lower insulating layer 133. 7, the second bump pad 139b may include second openings 133b disposed in the vicinity of a central portion of the mesa M among the second openings 133b of the lower insulating layer 133 133b of the second openings 133b. However, the present invention is not limited thereto, and may cover the entire upper region of the second openings 133b.

FIG. 8 is a schematic plan view illustrating a light emitting diode according to another embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along a perforated line C-C of FIG.

8 and 9, the light emitting diode according to the present embodiment is substantially similar to the light emitting diode described with reference to FIGS. 1 and 2, but differs in that it includes a plurality of mesas M1, M2, and M3 have.

That is, in the embodiment of FIGS. 1 and 2, a single mesa M has a recessed portion 30, whereas the light emitting diode according to the present embodiment has mesas M1, M2, and M3 spaced from each other . The mesas M1, M2, and M3 may be disposed parallel to each other along the longitudinal direction. This structure corresponds to, for example, a structure in which the indentation 30 is connected from one edge to the other edge in the embodiment of FIG. As a result, the shapes of the OMR reflective layer 231 and the first and second pad metal layers 235a and 235b are deformed.

The ohmic reflective layer 231 is located on each of the mesas M1, M2, and M3 and is in ohmic contact with each of the second conductivity type semiconductor layers 27. [ The OMR reflective layers 231 are confined within the upper region of the mesas M1, M2, and M3, respectively, and are spaced apart from each other.

On the other hand, the preliminary insulating layer 229 may cover the mesas M1, M2, and M3 around the ohmic reflective layers 231. [ The preliminary insulating layer 229 may be formed of, for example, SiO _2, and may cover a portion of the first conductivity type semiconductor layer 23 to cover the sides of the mesas M1, M2, and M3. In another embodiment, the pre-insulating layer 229 may be disposed only around the ohmic reflective layer 231 above the mesas M1, M2, and M3.

On the other hand, the lower insulating layer 233 covers the mesas M1, M2, and M3 and the ohmic reflective layers 231. The lower insulating layer 233 has first openings 233a1 for exposing the first conductivity type semiconductor layer 23 along the edge of the substrate 21 and a first opening 233a1 between the mesas M1, -Type semiconductor layer 23 is exposed through the first openings 233a2.

The lower insulating layer 233 also has second openings 233b that expose the ohmic reflective layer 231 on each of the mesas M1, M2, and M3. The shape of the second openings 233b may be circular in the same manner as in the embodiment of FIG. 1, but is not limited thereto, and may be a long rounded rectangular shape as shown in FIG.

The first pad metal layer 235a covers the mesas M1, M2 and M3 and is electrically connected to the first conductivity type semiconductor layer 23 through the first openings 233a1 and 233a2. The first pad metal layer 235a is formed between the first contact portions 235a1 contacting the first conductivity type semiconductor layer 23 through the first opening 233a1 and the first contact portions 235b1 between the mesas M1, 233a2 to contact the first conductivity type semiconductor layer 23, as shown in FIG.

On the other hand, the second pad metal layers 235b are disposed on the mesas M1, M2, and M3, respectively. Each second pad metal layer 235b may be surrounded by a first pad metal layer 235a and thus a ring shaped boundary 235ab may be formed on each of the mesas M1, M2, and M3. The second pad metal layers 235b are electrically connected to the ohmic reflective layer 231 on each of the mesas M1, M2, and M3 through the second openings 233b of the lower insulating layer 233.

The upper insulating layer 237 covers the first pad metal layer 235a and the second pad metal layer 235b and includes first openings 237a for exposing the first pad metal layer 235a and second openings 237b for exposing the second pad metal layer 235b And the second openings 237b. The second pad metal layers 235b on each of the mesas M1, M2, and M3 are exposed through the second openings 237b. The first openings 237a may also be disposed on each of the mesas M1, M2, and M3.

Meanwhile, the first bump pad 239a and the second bump pad 239b may be formed over the mesas M1, M2, and M3, respectively. The first bump pad 239a contacts the first pad metal layer 235a through the first openings 237a of the upper insulating layer 237 and the second bump pad 239b contacts the first pad metal layer 235a via the first insulating layer 237a And contacts the second pad metal layer 235b through the second openings 237b. The second bump pad 239b may also cover the upper region of the second openings 233b of the lower insulating layer 233.

In this embodiment, the second openings 233b of the lower insulating layer 233 and the second openings 237b of the upper insulating layer 237 may be arranged in various ways. In this embodiment, the second openings 233b and 237b are arranged in the same number on the mesas M1, M2 and M3, and the second openings 233b and the second openings 237b are arranged on the upper and lower sides And has a mirror-surface symmetrical structure as a whole.

10A and 10B are schematic plan views illustrating various arrangements of the second openings 233b of the lower insulating layer 233 and the second openings 237b of the upper insulating layer 237. FIG.

10A, the second openings 233b of the lower insulating layer 233 and the second openings 237b of the upper insulating layer 237 are arranged to be shifted from each other in comparison with the embodiment of FIG. 8 . These openings 233b and 237b are also arranged so as to have a generally mirror-symmetrical structure as a whole.

10B, the second openings 233b of the lower insulating layer 233 are disposed above and below each other on the first mesa M1 and the third mesa M3, Two openings 237b are also disposed above and below. On the other hand, on the second mesa M2, the second opening 233b and the second opening 237b are arranged above and below. In the embodiment of FIG. 10B, these openings 233b and 237b are arranged so as to have a mirror-symmetrical structure as a whole.

The second openings 233b and 237b are arranged so as to have a mirror-surface symmetrical structure, so that a symmetrical light emission pattern can be realized. However, the present invention is not limited to this, and the arrangement of the openings 233b and 237b may be variously modified and may not have a mirror surface symmetrical structure.

11 is a schematic plan view illustrating a light emitting diode according to another embodiment of the present invention.

Referring to FIG. 11, the light emitting diode according to this embodiment is substantially similar to the light emitting diode described with reference to FIGS. 8 and 9, but differs in the number of mesas and the shape of the first opening 337a of the upper insulating layer . 8 and 9, detailed description thereof will be omitted, and differences will be mainly described.

In this embodiment, four mesas M1 to M4 are disposed on the first conductivity type semiconductor layer 23. However, the number of mesas is not particularly limited, and may be more or less.

Meanwhile, the first openings 337a of the upper insulating layer may be circular as shown in FIG. 8, or may have a long rounded rectangular shape as shown in FIG. The second opening 237b of the upper insulating layer may have the same shape, but the sizes of the first opening 337a and the second opening 237b may be different from each other or may be the same.

By making the shape of the first opening 337a long and rounded, it is possible to secure a sufficient distance between the first openings 337a disposed adjacent to the left and right sides while increasing the size of the opening. Furthermore, the shape of the first opening 337a is not particularly limited to this, and can be variously modified.

On the other hand, in this embodiment, the second opening 237b of the upper insulating layer and the second opening 233b of the lower insulating layer are arranged vertically and laterally. 8, in this embodiment, the second opening 237b of the upper insulating layer and the second opening 233b of the lower insulating layer on each of the mesas M1 to M4 may be arranged in the same pattern have. Accordingly, the arrangement of the openings 233b and 237b is not mirror-symmetrical. The arrangement of the openings 233b and 237b may be variously modified as described with reference to FIG. 10, and the second openings 233b of the lower insulating layer and the second openings 237b of the upper insulating layer may be formed, May be arranged to be larger than the shortest distance between the second openings 233b of the lower insulating layer and the shortest distance of the second openings 237b of the upper insulating layer.

On the other hand, the first bump pad 339a is formed over the mesas M1 to M4 and covers the first openings 337a of the upper insulating layer. The first bump pad 339a connects to the first pad metal layer 235a as in the embodiment of FIG. On the other hand, the first bump pad 339a may be provided with a cathode mark Mc for displaying the cathode. For example, as shown in Fig. 11, the corner portion may be omitted in the first bump pad 339a having a rectangular shape to form the cathode mark Mc.

The second bump pad 339b is formed over the mesas M1 to M4 and covers the second openings 337b of the upper insulating layer. The second bump pad 339b connects to the second pad metal layers 235b as in the embodiment of FIG. The second bump pad 339b may also cover the upper region of the second openings 233b of the lower insulating layer.

12 is an exploded perspective view illustrating a lighting apparatus to which a light emitting diode according to an embodiment of the present invention is applied.

Referring to FIG. 12, the illumination device according to the present embodiment includes a diffusion cover 1010, a light emitting device module 1020, and a body part 1030. The body 1030 may receive the light emitting module 1020 and the diffusion cover 1010 may be disposed on the body 1030 to cover the upper portion of the light emitting module 1020.

The body part 1030 is not limited as long as it can receive and support the light emitting element module 1020 and supply the electric power to the light emitting element module 1020. For example, as shown, the body portion 1030 may include a body case 1031, a power supply 1033, a power supply case 1035, and a power connection 1037. [

The power supply unit 1033 is accommodated in the power supply case 1035 and is electrically connected to the light emitting device module 1020, and may include at least one IC chip. The IC chip may control, convert, or control the characteristics of the power supplied to the light emitting device module 1020. The power supply case 1035 can receive and support the power supply device 1033 and the power supply case 1035 in which the power supply device 1033 is fixed can be located inside the body case 1031 . The power connection portion 115 is disposed at the lower end of the power source case 1035 and can be connected to the power source case 1035. [ The power connection unit 1037 is electrically connected to the power supply unit 1033 in the power supply case 1035 so that external power can be supplied to the power supply unit 1033.

The light emitting element module 1020 includes a substrate 1023 and a light emitting element 1021 disposed on the substrate 1023. The light emitting device module 1020 is provided on the body case 1031 and can be electrically connected to the power supply device 1033.

The substrate 1023 is not limited as long as it is a substrate capable of supporting the light emitting element 1021, and may be, for example, a printed circuit board including wiring. The substrate 1023 may have a shape corresponding to the fixing portion on the upper portion of the body case 1031 so as to be stably fixed to the body case 1031. [ The light emitting device 1021 may include at least one of the light emitting diodes according to the embodiments of the present invention described above.

The diffusion cover 1010 is disposed on the light emitting element 1021 and may be fixed to the body case 1031 to cover the light emitting element 1021. [ The diffusion cover 1010 may have a light-transmitting material and may control the shape and the light transmittance of the diffusion cover 1010 to control the directivity characteristics of the illumination device. Accordingly, the diffusion cover 1010 can be modified into various forms depending on the purpose and application of the illumination device.

13 is a cross-sectional view illustrating a display device to which a light emitting diode according to another embodiment of the present invention is applied.

The display device of this embodiment includes a display panel 2110, a backlight unit for providing light to the display panel 2110, and a panel guide for supporting the lower edge of the display panel 2110.

The display panel 2110 is not particularly limited and may be, for example, a liquid crystal display panel including a liquid crystal layer. At the edge of the display panel 2110, a gate driving PCB for supplying a driving signal to the gate line may be further disposed. Here, the gate driving PCB may not be formed on a separate PCB, but may be formed on the thin film transistor substrate.

The backlight unit includes a light source module including at least one substrate and a plurality of light emitting elements (2160). Furthermore, the backlight unit may further include a bottom cover 2180, a reflective sheet 2170, a diffusion plate 2131, and optical sheets 2130.

The bottom cover 2180 may open upward to accommodate the substrate, the light emitting element 2160, the reflective sheet 2170, the diffusion plate 2131, and the optical sheets 2130. Further, the bottom cover 2180 can be engaged with the panel guide. The substrate may be disposed below the reflective sheet 2170 and surrounded by the reflective sheet 2170. However, the present invention is not limited thereto, and it may be placed on the reflective sheet 2170 when the reflective material is coated on the surface. In addition, the substrate may be formed in a plurality, and the plurality of substrates may be arranged in a side-by-side manner, but not limited thereto, and may be formed of a single substrate.

The light emitting device 2160 may include the light emitting diode according to the embodiments of the present invention described above. The light emitting elements 2160 may be regularly arranged in a predetermined pattern on the substrate. In addition, a lens 2210 is disposed on each light emitting element 2160, so that the uniformity of light emitted from the plurality of light emitting elements 2160 can be improved.

The diffusion plate 2131 and the optical sheets 2130 are placed on the light emitting element 2160. The light emitted from the light emitting element 2160 may be supplied to the display panel 2110 in the form of a surface light source via the diffusion plate 2131 and the optical sheets 2130.

As described above, the light emitting device according to the embodiments of the present invention can be applied to the direct-type display device as in the present embodiment.

14 is a cross-sectional view illustrating a display device to which a light emitting diode according to another embodiment of the present invention is applied.

The display device including the backlight unit according to the present embodiment includes a display panel 3210 on which an image is displayed, and a backlight unit disposed on the back surface of the display panel 3210 and configured to emit light. The display device further includes a frame 240 supporting the display panel 3210 and receiving the backlight unit and covers 3240 and 3280 surrounding the display panel 3210.

The display panel 3210 is not particularly limited and may be, for example, a liquid crystal display panel including a liquid crystal layer. At the edge of the display panel 3210, a gate driving PCB for supplying a driving signal to the gate line may be further disposed. Here, the gate driving PCB may not be formed on a separate PCB, but may be formed on the thin film transistor substrate. The display panel 3210 is fixed by the covers 3240 and 3280 located at the upper and lower portions thereof and the cover 3280 located at the lower portion can be engaged with the backlight unit.

The backlight unit for providing light to the display panel 3210 includes a lower cover 3270 having a part of the upper surface opened, a light source module disposed on one side of the inner side of the lower cover 3270, And a light guide plate 3250 that converts light into light. The backlight unit of the present embodiment includes optical sheets 3230 positioned on the light guide plate 3250 and diffusing and condensing light, light directed downward of the light guide plate 3250 disposed below the light guide plate 3250 And a reflective sheet 3260 that reflects light toward the display panel 3210. [

The light source module includes a substrate 3220 and a plurality of light emitting devices 3110 disposed on a surface of the substrate 3220 at predetermined intervals. The substrate 3220 is not limited as long as it supports the light emitting element 3110 and is electrically connected to the light emitting element 3110, for example, it may be a printed circuit board. The light emitting device 3110 may include at least one light emitting diode according to the above-described embodiments of the present invention. The light emitted from the light source module is incident on the light guide plate 3250 and is supplied to the display panel 3210 through the optical sheets 3230. Through the light guide plate 3250 and the optical sheets 3230, the point light source emitted from the light emitting elements 3110 can be transformed into a surface light source.

As described above, the light emitting device according to the embodiments of the present invention can be applied to the edge display device as in the present embodiment.

15 is a sectional view for explaining an example in which a light emitting diode according to another embodiment of the present invention is applied to a headlamp.

15, the head lamp includes a lamp body 4070, a substrate 4020, a light emitting element 4010, and a cover lens 4050. Furthermore, the head lamp may further include a heat dissipating unit 4030, a support rack 4060, and a connecting member 4040.

Substrate 4020 is fixed by support rack 4060 and is spaced apart on lamp body 4070. The substrate 4020 is not limited as long as it can support the light emitting element 4010, and may be a substrate having a conductive pattern such as a printed circuit board. The light emitting element 4010 is located on the substrate 4020 and can be supported and fixed by the substrate 4020. [ Also, the light emitting device 4010 may be electrically connected to an external power source through the conductive pattern of the substrate 4020. In addition, the light emitting device 4010 may include at least one light emitting diode according to the embodiments of the present invention described above.

The cover lens 4050 is located on the path through which light emitted from the light emitting element 4010 travels. For example, as shown, the cover lens 4050 may be disposed apart from the light emitting device 4010 by the connecting member 4040, and may be disposed in a direction in which light is to be emitted from the light emitting device 4010 . The directional angle and / or color of the light emitted from the headlamp to the outside by the cover lens 4050 can be adjusted. The connecting member 4040 may serve as a light guide for fixing the cover lens 4050 to the substrate 4020 and for arranging the light emitting element 4010 to provide the light emitting path 4045. [ At this time, the connection member 4040 may be formed of a light reflective material or may be coated with a light reflective material. The heat dissipation unit 4030 may include a heat dissipation fin 4031 and / or a heat dissipation fan 4033 to dissipate heat generated when the light emitting device 4010 is driven.

As described above, the light emitting device according to the embodiments of the present invention can be applied to a head lamp, particularly, a headlamp for a vehicle as in the present embodiment.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, the elements or components described in relation to one embodiment can be applied to other embodiments without departing from the technical idea of the present invention.

Claims (20)

A first conductive semiconductor layer;
A mesa on the first conductivity type semiconductor layer, the mesa including an active layer and a second conductivity type semiconductor layer;
An ohmic reflective layer disposed on the mesa and electrically connected to the second conductive semiconductor layer;
A lower insulating layer covering the mesa and the ohmic reflective layer, the lower insulating layer including a first opening exposing the first conductivity type semiconductor layer and a second opening exposing the ohmic reflective layer;
A first pad metal layer disposed on the lower insulating layer and electrically connected to the first conductive semiconductor layer through the first opening;
A second pad metal layer disposed on the lower insulating layer and electrically connected to the ohmic reflective layer through the second opening; And
And an upper insulating layer covering the first pad metal layer and the second pad metal layer, the upper insulating layer including a first opening exposing the first pad metal layer and a plurality of second openings exposing the second pad metal layer,
And the second openings of the upper insulating layer are spaced apart from the second openings of the lower insulating layer so as not to overlap with each other. The method according to claim 1,
A first bump pad connected to the first pad metal layer through a first opening of the upper insulating layer; And
And a second bump pad connected to the second pad metal layer through a plurality of second openings of the upper insulating layer. The method of claim 2,
Wherein the shortest distance from the second opening of the lower insulating layer to the second opening of the upper insulating layer is larger than the shortest distance between the second openings of the upper insulating layer. The method of claim 3,
Wherein the lower insulating layer includes a plurality of second openings,
Wherein the shortest distance from the second opening of the lower insulating layer to the second opening of the upper insulating layer is larger than the shortest distance between the second openings of the lower insulating layer. The method of claim 2,
Wherein the first opening of the lower insulating layer exposes the first conductivity type semiconductor layer along the mesa,
Wherein the first pad metal layer has an external contact portion contacting the first conductive semiconductor layer along the mesa. The method of claim 5,
Wherein the mesa includes a recessed portion for exposing the first conductive type semiconductor layer,
Wherein the first opening of the lower insulating layer further exposes the first conductivity type semiconductor layer in the indent,
Wherein the first pad metal layer further includes an internal contact portion that contacts the first conductive semiconductor layer in the indentation portion. The method of claim 6,
And the inner contact portion is connected to the outer contact portion. The method of claim 2,
The mesa has a via hole penetrating the second conductivity type semiconductor layer and the active layer to expose the first conductivity type semiconductor layer,
Wherein the first opening of the lower insulating layer exposes the first conductive type semiconductor layer exposed in the via hole,
Wherein the first pad metal layer has an inner contact portion that contacts the first conductive semiconductor layer exposed in the via hole. The method of claim 8,
Wherein the first pad metal layer includes external contacts that contact the first conductive type semiconductor layer outside the mesa, the external contacts being spaced apart from each other. The method of claim 2,
Wherein the lower insulating layer includes a plurality of second openings,
And the second bump pad covers an upper portion of at least one second opening of the lower insulating layer. The method of claim 10,
Wherein the first and second bump pads each cover and seal the first and second openings of the upper insulating layer. The method of claim 10,
Wherein the first bump pad covers an upper portion of at least one second opening of the lower insulating layer. The method of claim 2,
Wherein the second pad metal layer is surrounded by the first pad metal layer. 14. The method of claim 13,
And the second bump pad includes a protrusion between the first bump pad and the first bump pad. 15. The method of claim 14,
And at least one of the second openings of the lower insulating layer is located below the protrusion. The method of claim 2,
Wherein the lower insulating layer includes a plurality of second openings,
Wherein at least one of the second openings of the upper insulating layer is disposed between two second openings of the lower insulating layer. The method of claim 2,
A plurality of mesas are disposed on the first conductivity type semiconductor layer,
The second opening of the lower insulating layer and the second openings of the upper insulating layer are located on each mesa,
Wherein the first bump pad and the second bump pad are disposed over the plurality of mesas, respectively. 18. The method of claim 17,
The first pad metal layer covers the mesas,
Wherein the second pad metal layer is disposed on each mesa. The method of claim 2,
Wherein the second bump pad is confined within the second pad metal layer upper region. The method of claim 2,
And the second bump pad partially overlaps with the first pad metal layer.

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