KR20180049376A - Gate driving circuit and display device having in-cell touch sensor using the same - Google Patents

Abstract

The present invention relates to a gate driving circuit and a display device with an in-cell touch sensor using the same. The gate driving circuit includes: an (N-1)^th stage for outputting an (N-1)^th gate pulse; an N^th stage for outputting an N^th gate pulse; and a bridge circuit which is arranged between the (N-1)^th stage and the N^th stage, outputs a first output voltage according to a first clock generated in a finish point of a touch sensing period, and outputs a second output voltage according to a second clock generated by the number of times more than the number of times of the first clock during the touch sensing period. Accordingly, the present invention can drive pixels and touch sensors without the degradation of image quality.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a display device having a gate driving circuit and an in-cell touch sensor using the same,

The present invention relates to a gate driving circuit and a display device having an insensitive touch sensor using the gate driving circuit.

A user interface (UI) enables a user (a user) to communicate with various electric or electronic devices, allowing the user to easily control the device as desired. Representative examples of the user interface include a keypad, a keyboard, a mouse, an on-screen display (OSD), a remote controller having infrared communication or radio frequency (RF) communication functions. User interface technology has been developed to enhance the user's sensibility and ease of operation. Recently, the user interface has been developed into a touch UI, a voice recognition UI, a 3D UI, and the like.

The touch UI implements a touch screen on the display panel to sense the touch input and transmit the user input to the electronic device. Touch UI is essential for portable information devices such as smart phones, and is being applied to notebook computers, computer monitors, and home appliances.

Techniques for implementing a touch screen using a technique of incorporating touch sensors in a pixel array of a display panel (hereinafter referred to as " In-cell touch sensor ") have been applied to various display devices. The touch sensors can be implemented as a capacitive type touch sensor that senses a touch based on a change in capacitance before and after the touch.

The in-line touch sensor technology (C1 to C4) as shown in FIG. 1 can be installed on the display panel without increasing the thickness of the display panel. The in-line touch sensors C1 to C4 are connected to the touch sensing unit 2 through the sensor lines 4. [ The touch sensing unit 2 supplies electric charge to the touch sensor electrodes C1 to C4 through the sensor lines 4 and supplies the electric charges to the touch sensor electrodes C1 to C4 based on the capacitive variation of the sensors C1 to C4, Lt; / RTI > In Fig. 1, " Cs " represents the capacitance of the in-line touch sensor.

Since the in-line touch sensors C1 to C4 are embedded in the pixel array of the display panel 100, the in-line touch sensors C1 to C4 are coupled to the pixels through the parasitic capacitance. In order to reduce mutual influence due to the coupling of the pixels with the in-line touch sensors (C1 to C4), the in-cell touch sensor technique time-divides one frame period into the display period and the touch sensing period. The common voltage Vcom, which is the reference voltage of the pixel, is supplied to the in-line touch sensors C1 to C4 during the display period. During the touch sensing period, the in-line touch sensors (C1 to C4) are driven to sense the touch input.

The display device includes a data driver for supplying a data voltage to the data lines of the display panel, a gate driver (or a scan driver) for supplying a gate pulse (or a scan pulse) to the gate lines of the display panel, .

The gate driver sequentially shifts gate pulses applied to the gate lines by using a shift register. The gate pulse sequentially selects the pixels to be charged with the data voltage of the input image, that is, the pixel voltage, one by one. The shift register includes stages that are connected in a dependent manner. The stage of the shift register receives a start signal or a carry signal received from a previous stage as a start pulse, and generates an output when a clock is input.

The shift register of the gate driver may be mounted together with the pixel array on the substrate of the display panel. Hereinafter, the shift register mounted on the substrate of the display panel will be referred to as a " GIP (Gate in Panel) circuit ".

A screen of the display device may be divided into two or more blocks and a touch sensing interval may be allocated therebetween. For example, during the first display period, the pixels of the first block are driven to update the data of the first block to the current frame data, and then the touch sensing period is shifted to sense the touch input. Then, The pixels of the block may be driven to update the data of the second block with the current frame data. However, this method may cause degradation of the output characteristics of the gate pulse supplied to the gate lines, resulting in poor image quality. For example, in a stage of a shift register that outputs a first gate pulse in a second block driven immediately after a touch sensing period, the voltage of the Q node may be discharged due to a leakage current during a touch sensing period. Since the Q node is connected to the gate of the pull-up transistor, if the voltage of the Q node becomes lower, the bootstrapping operation for turning on the pull-up transistor becomes incomplete, so that the voltage of the gate pulse whose voltage rises by the pull- target voltage. As a result, the voltage of the first gate pulse generated when the pixels of the second block starts to be driven is lowered, so that the brightness of the pixels arranged in the first line of the second block is lowered, and as a result, Degradation can be seen.

A bridge circuit (or a dummy stage) can be added to the gate driver. The bridge circuit charges the Q node of the stage that generates the first output when the pixels of the next block are driven immediately after the touch sensing period, during the touch sensing period to suppress the discharge of the Q node.

The Q node of the bridge circuit maintains the charged state during the touch sensing period and the first Q node voltage of the next block generating the output immediately after the touch sensing period due to the voltage output from the bridge circuit is charged The time is getting longer. As a result, the DC gate bias stress of the pull-up transistor connected to the Q node of the bridge circuit and the pull-up transistor connected to the Q node of the stage generating the first output of the next block becomes larger. Due to the deterioration of the pull-up transistors, a voltage different from the output of the other stages may be outputted, so that image quality degradation such as line dim can be seen.

The present invention provides a gate driving circuit capable of driving pixels and touch sensors without any stress variation between stages of a GIP circuit and without degrading picture quality, and a display device having an insensitive touch sensor using the same.

The gate driving circuit of the present invention includes a shift register for sequentially supplying gate pulses to the gate lines of the display panel.

The shift register includes: an (N-1) th stage for outputting an Nth gate pulse (N is a positive integer equal to or greater than 2) -1; An Nth stage for outputting an Nth gate pulse; And a second output circuit which is disposed between the (N-1) th and (N-1) th stages and outputs a first output voltage according to a first clock generated at the end of the touch sensing interval, And a bridge circuit for outputting a second output voltage in accordance with a second clock generated a number of times.

Each of the N-1 stage, the N-th stage, and the bridge circuit comprises: a Q node connected to a gate of a pull-up transistor; And a Q-node charging transistor for pre-charging the Q-node according to an input signal inputted through a start input terminal.

And a first output voltage from the bridge circuit is supplied to a start input terminal of the Nth stage.

The second output voltage of the bridge circuit is supplied to the start input terminal of the other bridge circuit.

And a plurality of the bridge circuits are connected between the (N-1) th stage and the (N-1) th stage. The bridge circuits sequentially generate the first and second output voltages, and a first output voltage of the last bridge circuit in which the Q node is finally charged is supplied to the start input terminal of the Nth stage.

The Q-node voltage of the N-th stage holds the gate-off voltage for the remaining time except for the first clock time in the touch sensing period and is pre-charged for the first clock time.

A first transistor including a gate connected to the Q node of the bridge circuit, a first electrode to which the first clock is applied, and a second electrode connected to a first output terminal to which the first output voltage is output; A second transistor including a gate coupled to the QB node of the bridge circuit, a first electrode coupled to the first output terminal, and a second electrode to which the gate-off voltage is applied; A third transistor including a gate connected to the Q node of the bridge circuit, a first electrode to which the second clock is applied, and a second electrode connected to a second output terminal to which the second output voltage is output; And a fourth transistor including a gate coupled to the QB node of the bridge circuit, a first electrode coupled to the second output terminal, and a second electrode to which the gate-off voltage is applied.

Each of the transistors of the bridge circuit includes an oxide semiconductor pattern.

At least one of the transistors of the bridge circuit includes an oxide semiconductor pattern exposed to external light.

And the transistors of the (N-1) th and (N-1) th stages are oxide semiconductor patterns that are not exposed to external light.

A display device of the present invention is characterized in that data lines and gate lines are crossed, pixels are arranged in a matrix, a screen including pixels and touch sensors is divided into at least first and second blocks, A display panel in which two blocks are time-divisionally driven with a touch sensing interval therebetween; The pixels of the first block are driven during the first display period and the pixels of the second blocks are driven during the second display period after the touch sensing period to write the data of the input image to the pixels of the first and second blocks A display driver; And a touch sensing unit for sensing the touch input by driving the touch sensors during the touch sensing driving period.

The display driver includes a shift register for sequentially supplying gate pulses to the gate lines. The shift register includes the (N-1) th stage, the N-th stage, and the bridge circuit.

The present invention is characterized in that an output of a bridge circuit arranged between an (N-1) stage for outputting a last gate pulse in a first block of a screen and an (N) -th stage for outputting a first gate pulse in a second block of a screen after a touch sensing interval, Into a first output voltage to be applied to the start input terminal (VST terminal) of the Nth stage and an output voltage to be input to the start input terminal of the next bridge circuit. As a result, the Q-node stress of the N-th stage can be reduced, the stress variation between the N-th stage and other stages can be minimized, and the lifetime of the gate driving circuit can be improved, and the pixels and the touch sensors can be driven without deterioration in image quality.

1 is a view showing touch sensors and a touch sensing unit.
2 is a block diagram schematically showing a display device according to an embodiment of the present invention.
3 is a diagram illustrating an example in which a screen is divided into a plurality of blocks in order to time-division-drive the pixels of the screen and the insole touch sensor.
4 is a diagram showing shift clocks and start pulses applied to GIP circuits arranged on both sides of the screen.
5 is a circuit diagram showing the circuit configuration of the insole touch sensors and the touch sensing unit.
6 and 7 are views showing driving signals of a display device according to an embodiment of the present invention.
8 and 9 are views schematically showing a part of a GIP circuit disposed at a boundary between neighboring blocks.
10 is a view schematically showing one stage for outputting gate pulses in the GIP circuit.
11 is a waveform diagram showing the operation of the stage shown in Fig.
Figs. 12 and 13 are views showing one stage in detail in the GIP circuit 104. Fig.
FIG. 14 is a detailed circuit diagram of a bridge circuit according to an embodiment of the present invention.
15 is a waveform diagram showing the operation of the bridge circuit shown in Fig.
FIG. 16 is a waveform diagram showing an example in which deterioration of the transistor becomes worse when the output is not separated in the bridge circuit shown in FIG. 14, and a deterioration deviation occurs between the stages. FIG.
17 is a circuit diagram showing a switch element for Q node reset of the bridge circuit shown in Fig.
18 is a waveform diagram showing a Q-node resetting method of a stage for outputting a last gate pulse immediately before a touch sensing period starts.
19 is a diagram showing an example in which a plurality of bridge circuits are arranged between GIP circuits that are responsible for neighboring blocks.
20 is a diagram showing Q-node stress of a bridge circuit when one bridge circuit is disposed between GIP circuits that are responsible for neighboring blocks.
21 is a graph showing Q-node stress of a bridge circuit when two bridge circuits are arranged between GIP circuits that are responsible for neighboring blocks.
22 is a diagram showing deterioration of a GIP circuit for outputting a gate pulse and deterioration of a bridge circuit.
23 is a view showing a cross-sectional structure of transistors taken along the line A-A 'in the plane of the oxide transistor.
FIG. 24 is a graph showing a simulation result of the stress of the oxide transistor to which the photoexposure design is applied and the positive exposure bias (PBST) stress of the oxide transistor.
25 is a diagram showing a result of a simulation of applying a DC bias voltage and an AC bias voltage to an oxide transistor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The display device of the present invention can be implemented as a flat panel display device such as a liquid crystal display (LCD), an organic light emitting display (OLED) display, or the like. In the following embodiments, the liquid crystal display device will be described as an example of the flat panel display device, but the present invention is not limited thereto. For example, the present invention can be applied to any display device including an Insel touch sensor.

In the gate driving circuit of the present invention, the switching elements may be implemented as n-type or p-type metal oxide semiconductor field effect transistor (MOSFET) transistors. In the following embodiments, an n-type transistor (NMOS) is exemplified, but it should be noted that the present invention is not limited to this. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Within the transistor, the carriers begin to flow from the source. The drain is an electrode from which the carrier exits from the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, the direction of current flows from drain to source because electrons flow from source to drain. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, the current flows from the source to the drain because the holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET may be changed depending on the applied voltage. In the following description of the embodiment, the source and the drain of the transistor will be referred to as first and second electrodes. It should be noted that the invention is not limited by the source and drain of the transistor in the following description.

The transistors constituting the gate drive circuit of the present invention include a transistor including an oxide semiconductor (hereinafter, referred to as an "oxide transistor"), a transistor including an amorphous silicon (a-Si) But may be implemented with one or more of the transistors including Low Temperature Poly Silicon (LTPS).

In the display device according to the embodiment of the present invention, the driving circuit includes a display driver and a touch sensing unit. The display driver drives the pixels of the first block during the first display period and drives the pixels of the second blocks during the second display period to write data of the input image to the pixels of the first and second blocks. The touch sensing unit senses a touch input by driving the touch sensors during a touch sensing driving period between the first display period and the second display period.

2 to 5, a display apparatus according to the present invention includes a display panel 100 and a display panel 100 in which data of an input image is written to pixels 11 of a pixel array 10 of a display panel 100 A touch sensing unit 110 for driving the insole touch sensors, and the like.

The display panel 100 is formed in a matrix form defined by the data lines 12, the gate lines 14 orthogonal to the data lines 12, and the data lines 12 and gate lines 14. [ And a pixel array 10 in which pixels are arranged. The pixel array 10 implements a screen on which an input image is displayed.

The pixels of the pixel array 10 may comprise red (R), green (G), and blue (B) subpixels for color implementation. Each of the pixels may further include white (W, W) subpixels in addition to RGB subpixels.

One frame period of the display panel 100 is divided into one or more display periods and one or more touch sensing intervals in order to drive the pixels 11 and the insensitive touch sensors C1 to C4 incorporated in the pixel array . The pixel array of the display panel 100 is time-divisionally driven to two or more blocks B1 to BM as shown in FIG. The pixel array of the display panel 100 is dividedly driven into separate display periods with a touch sensing interval during which the in-line touch sensors C1 to C4 are driven.

The blocks B1 to BM on the screen need not be physically divided. The blocks B1 to BM are time-division driven with the touch sensing interval therebetween. For example, after the pixels of the first block B1 are driven and the current frame data is written to the pixels 11 during the first display period, the touch input is sensed in the entire screen during the first touch sensing period. Following the first touch sensing period, the pixels 11 of the second block B2 are driven during the second display period to write the current frame data to the pixels 11 thereof. Then, the touch input is sensed in the entire screen during the second touch sensing period. Such a method of driving the insole touch sensor can make the touch report rate faster than the frame rate of the screen. The frame rate is a frequency for updating frame data on the screen, and is 60 Hz in the National Television Standards Committee (NTSC) scheme. The touch report rate is a frequency that generates touch input coordinates for the entire screen. According to the present invention, the screen is divided and driven in units of preset blocks, and the insole touch sensor is driven between the display intervals to generate coordinates, thereby increasing the touch sensitivity by increasing the touch report rate by at least twice the frame rate of the screen.

The pixel array 10 of the display panel 100 can be divided into a TFT array and a color filter array. A TFT array may be formed on the lower panel of the display panel 100. [ The TFT array includes TFTs (Thin Film Transistors) formed at intersections of the data lines 12 and the gate lines 14, pixel electrodes for charging data voltages, storage capacitors Storage Capacitor, Cst), and the like. Sensor lines 16 in the TFT array and electrodes of the incelel touch sensors C1 to C4 connected to the sensor lines 16. [

A color filter array may be formed on the upper panel or the lower panel of the display panel 100. The color filter array includes a black matrix, a color filter, and the like. In the case of a color filter on TFT (COT) or a TFT on color filter (TOC) model, a color filter and a black matrix together with a TFT array can be arranged on one substrate.

The in-line touch sensors C1 to C4 may be implemented by capacitive touch sensors, for example, a mutual capacitance sensor or a self capacitance sensor. The self-capacitance is formed along a conductor wiring of a single layer formed in one direction. The mutual capacitance is formed between two orthogonal conductor wirings. Although FIG. 5 shows a self-capacitance type touch sensor, the in-line touch sensors of the present invention are not limited thereto.

The in-line touch sensors (C1 to C4) may be implemented with electrodes divided from the common electrode of the pixels (11). The in-line touch sensors (C1 to C4) are connected to the touch sensing unit (110) through the sensor lines (16).

The display driver includes a data driver 102 and gate drivers 104 and 108, and writes data of the input image to pixels of the display panel 100.

The data driver 102 includes one or more source drive ICs. The source drive IC may be mounted on a chip on film (COF) and connected between the display panel 100 and a PCB (Printed Circuit Board). The source driver IC (SIC) may be directly bonded on the substrate of the display panel 100 by a COG (chip on glass) process.

The data driver 102 converts digital video data of an input image received from a timing controller (TCON) 106 into a gamma compensation voltage to output a data voltage. The data voltages output from the data driver 102 are supplied to the data lines 12. [ A multiplexer (not shown) may be disposed between the data driver 102 and the data lines 12. The multiplexer distributes the data voltages input from the data driver 102 to the data lines 12 under the control of the timing controller 106. In the case of the 1: 3 multiplexer, the multiplexer time-divides the data voltages input through one output channel of the data driver 102 and supplies the data voltages to the two data lines in a time division manner. When the 1: 3 multiplexer is used, the number of channels of the data driver 102 can be reduced to one third.

The gate drivers 104 and 108 include a level shifter (LS) 108 and a GIP circuit 104. The level shifter 108 is disposed between the timing controller 106 and the GIP circuit 104. The GIP circuit 104 may be formed directly on the lower panel of the display panel 100 together with the TFT array.

The GIP circuit 104 includes a shift register. The GIP circuit 104 may be formed on the bezel BZ at one side edge of the display panel 100 outside the pixel array or may be formed at the bezel BZ at both side edges thereof. The level shifter 108 shifts the swing width of the gate timing control signal received from the timing controller 106 to the gate on voltage and the gate off voltage and outputs the swing width to the GIP circuit 104. In the NMOS, the gate-on voltage is a gate-on voltage (VGH) higher than the threshold voltage of the NMOS and the gate-off voltage is a gate-off voltage (VGL) lower than the threshold voltage of the NMOS. In the case of PMOS, the gate-on voltage is the gate-off voltage (VGL) and the gate-off voltage is the gate-on voltage (VGH). Hereinafter, the transistors of the GIP circuit 104 will be described with reference to NMOS, but the present invention is not limited thereto.

Each of the GIP circuits 104 sequentially shifts the gate pulse according to the shift clock CLK to sequentially supply gate pulses to the gate lines 14 as shown in FIG. The shift clock (CLK) may be a two-phase clock to an eight-phase clock. 6 illustrates an 8-phase clock, but the shift clock CLK is not limited thereto.

The gate pulse output from the GIP circuit 104 swings between VGH and VGL. VGH is the gate-on voltage higher than the TFT's threshold voltage of the pixel. VGL is lower than VGH and is a gate-off voltage lower than the TFT threshold voltage of the pixel. The pixels of the pixels are turned on in response to VGH of the gate pulse to supply the data voltage from the data line 12 to the pixel electrode.

4 is an example in which the GIP circuit 104 is disposed on the left and right sides of the display panel 100 with the pixel array 10 left and right. The left and right GIP circuits 104 are synchronized by the timing controller 106. The left GIP circuit 104 may be connected to the odd-numbered gate lines 14 of the pixel array 10 to sequentially supply gate pulses to the gate lines 14. [ The right GIP circuit 104 may be coupled to the even gate lines 14 of the pixel array 10 to sequentially output gate pulses to the gate lines 14. [ The left GIP circuit 104 and the right GIP circuit 104 may be connected to all the gate lines and simultaneously supply gate pulses to the same gate line.

The shift registers of the GIP circuit 104 are connected in cascade connection as shown in FIG. 8 and are connected to stages S (N-1), S (N), and S (N) for shifting the gate pulse in accordance with the shift clock Each of the stages S (N-1), S (N) and S (N + 1) sequentially supplies gate pulses to the gate lines 14, and a carry signal Carry signal CAR (N), CAR (N + 1) to another stage The gate pulse and the carry signal are either the same signal output through one output terminal in each stage or two output terminals Lt; / RTI >

The timing controller 106 transmits the digital video data of the input image received from the host system (not shown) to the data driver 102. The timing controller 106 inputs a timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a main clock MCLK received in synchronization with the input video data And outputs a data timing control signal for controlling the operation timing of the data driver 102 and a gate timing control signal for controlling the operation timing of the level shifter 108 and the operation timing of the GIP circuit 104. [ The timing controller 106 generates a synchronization signal Tsync for synchronizing the display driving units 102, 104, and 108 and the touch sensing unit 110 using the timing signals received in synchronization with the input image data .

The gate timing control signal includes a start pulse (VST), a shift clock (GCLK), an output enable signal (GOE), and the like. The output enable signal (GOE) may be omitted. The start pulse VST is input to the VST terminal in the first stage of the GIP circuit 104 to control the output timing of the first gate pulse that occurs first in one frame period. The shift clock GCLK controls the output timing of the gate pulse in each of the stages of the GIP circuit 104 to control the shift timing of the gate pulse.

The touch sensing unit 110 drives the in-line touch sensors C1 to C4 during a touch sensing period in response to the synchronization signal Tsync received from the timing controller 106. [ The touch sensing unit 110 supplies a touch driving signal to the in-line touch sensors C 1 to C 4 through the sensor lines 16 during a touch sensing period, The capacitance change of the in-line touch sensors C1 to C4 which varies depending on the presence or absence of the in-cell touch sensors C1 to C4. The touch sensing unit 110 compares the capacitive change amount of each of the in-line touch sensors C1 to C4 with a preset threshold value to determine the in-line touch sensor whose charge amount has changed by a threshold value or more as a touch input position, . The coordinate information of the touch input position is transmitted to the host system.

The host system may be implemented in any one of a television system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system. The host system converts the digital video data of the input image into a format suitable for display on the display panel 100. [ The host system transmits timing signals (Vsync, Hsync, DE, MCLK) to the timing controller 106 together with the digital video data of the input video. The host system executes the application program associated with the coordinate information of the touch input received from the touch sensing unit 110. [

5 is a circuit diagram showing the circuit configuration of the insole touch sensors and the touch sensing unit.

Referring to FIG. 5, the electrode patterns of the in-cell touch sensors C1 to C4 may be formed as a divided pattern of the common electrode connected to the plurality of pixels 11. FIG. One in-line touch sensor is connected to a plurality of pixels 11 to supply a common voltage to a plurality of pixels 11 during a display period, and is driven by the touch sensing unit 110 during a touch sensing period, Sensing.

The touch sensing unit 110 includes a multiplexer 111, a sensing circuit 112, and a micro control unit (MCU) 113.

The multiplexer 111 selects the sensor lines 16 connected to the sensing circuit 112 under the control of the MCU 113. The multiplexer 111 can supply the common voltage Vcom under the control of the MCU 113. [ Each of the multiplexers 111 can reduce the number of channels of the sensing circuit 112 by sequentially connecting the N sensor lines 16 to the channel of the sensing circuit 112. [

The sensing circuit 112 supplies charge to the incelel touch sensors C1 to C4 through the multiplexer 111 and the sensor lines 16 and supplies the charge to the incelel touch sensors C1 to C4 received via the multiplexer 111. [ Amplifies and integrates the amount of charge of the touch sensor and converts it into digital data to sense capacitance change of the insole touch sensor according to presence or absence of touch input. To this end, the sensing circuit 112 includes an amplifier for amplifying the received touch sensor signal, an integrator for accumulating the output voltage of the amplifier, and an analog-to-digital converter (hereinafter referred to as "Quot; ADC ") and the like. The digital data output from the ADC is the MCU 113 as touch raw data indicating the capacity change of the in-line touch sensors C1 to C4 before and after the touch input.

The MCU 113 controls the multiplexer 111 to sequentially connect the sensor lines 16 to the sensing circuit 112 in a predetermined channel order. The MCU 113 compares data received from the sensing circuit 112 with a predetermined threshold value to determine a touch input. The MCU 113 executes a predetermined touch sensing algorithm to calculate coordinates for each touch input position, generates touch coordinate data XY, and transmits the coordinate data XY to the host system.

6 and 7 are views showing driving signals of a display device according to an embodiment of the present invention.

Referring to FIGS. 6 and 7, one frame period may be time-divided into display periods D1 and D2 and touch sensing periods S1 and S2. When the display frame rate is 60 Hz, one frame period is approximately 16.7 ms. One touch sensing interval S1 and S2 is allocated between the display intervals D1 and D2.

The display driving units 102, 104 and 108 write the current frame data to the pixels of the first block B1 during the first display period D1 and update the image reproduced in the first block B1 as the current frame data do. The pixels of the block B2 other than the first block B1 hold the previous frame data during the first display period D1 and the touch sensing unit 110 drives the incelel touch sensors C1 to C4 Do not. The touch sensing unit 110 sequentially drives all of the touch sensors C1 to C4 in the screen during the first touch sensing period S1 to sense the touch input and outputs coordinate information for each touch input A touch report including information (ID) is generated and transmitted to the host system.

The display driver 102, 104 and 108 write the current frame data to the pixels of the second block B2 during the second display period D2 and update the image reproduced in the second block B2 as the current frame data do. During the second display period D2, the pixels of the first block B1 hold the current frame data, and the touch sensing unit 110 does not drive the touch sensors. The touch sensing unit 110 sequentially drives all the touch sensors in the screen during the second touch sensing period S2 to sense the touch input, and generates a touch report including coordinate information and identification information (ID) for each touch input To the host system.

The touch sensing unit 110 supplies a sensor driving signal to the touch sensor through the sensor lines 16 during the touch sensing period S1 and S2 to detect the amount of charge of the touch sensor before and after the touch input and compare the amount of charge with the threshold voltage Thereby determining the touch input. The touch sensing unit 110 transmits coordinate information of the touch input to the host system every touch sensing interval S1 and S2. Therefore, the touch report rate is faster than the frame rate.

Since the in-line touch sensors C1 to C4 are connected to the pixels 11, the parasitic capacitance between the in-line touch sensors C1 to C4 and the pixels is large. Since the in-line touch sensors C1 to C4 and the pixels 11 are coupled through the parasitic capacitance, the pixels 11 and the in-line touch sensors C1 to C4 ) Is time-divisionally driven.

The data driver 102 applies an AC signal having the same phase as the sensor driving signal during the touch sensing period S1 and S2 in order to reduce the parasitic capacitance between the pixels 11 and the incelel touch sensors C1 to C4. (LFD) to the data lines 12. < RTI ID = 0.0 > The parasitic capacitance between the data line 12 and the in-cell touch sensors C1 to C4 is minimized if there is no voltage difference between the parasitic capacitances. Therefore, when an AC signal LFD having the same phase as the sensor driving signal is applied to the data lines 12 when the sensor driving signal is supplied to the in-line touch sensors C1 to C4, The parasitic capacitance between the in-cell touch sensors C1 to C4 can be minimized.

Likewise, the GIP circuit 104 may be configured to reduce the parasitic capacitance between the pixels 11 and the incelel touch sensors C1 to C4 by applying alternating currents of the same phase as the sensor driving signal during the touch sensing periods S1 and S2 It is possible to supply the signal LFD. The parasitic capacitance between the gate line 14 and the in-cell touch sensors C1 to C4 is minimized if there is no voltage difference between the parasitic capacitances. Therefore, when an AC signal LFD having the same phase as the sensor driving signal is applied to the gate lines 14 when the sensor driving signal is supplied to the in-line touch sensors C1 to C4, The parasitic capacitance between the touch sensors can be minimized.

The touch sensing unit 110 may supply the AC signal LFD to sensor lines other than the sensor line connected to the touch sensors currently sensing the touch input to minimize the parasitic capacitance between neighboring touch sensors.

(LFD) of the same phase as the sensor driving signal to the data lines 12, gate lines 14 and sensor lines 16 of the display panel 100 during the touch sensing periods S1 and S2 , It is possible to minimize the transfer of the parasitic capacitance of the display panel 100. The parasitic capacitance of the in-cell touch sensors C1 to C4 is reduced to improve the signal-to-noise ratio (SNR) of the in-cell touch sensors C1 to C4, Thereby widening the margin and improving the touch input and the touch sensitivity.

In Fig. 6, Vout (N-1) is the output voltage of the Nth (N is a positive integer equal to or greater than 2) -1 stage S (N-1) lastly generated in the first display period D1. Vout (N) is the output voltage of the N-th stage S (N) that is generated first in the second display period D2 in which pixel driving is resumed immediately after the first touch sensing period S1. Accordingly, after the first touch sensing period S1 has elapsed after the (N-1) -th gate pulse Vout (N-1) is applied to the (N-1) -th gate line 14, N) is applied to the Nth gate line 14. [ The N-1 stage S (N-1) and the N-th stage S (N) are part of the GIP circuit 104 connected to the gate lines in the neighboring blocks. The Nth stage S (N-1) and the Nth stage S (N) are connected to each other with the bridge circuit 200 interposed therebetween, admit.

8 and 9 are views schematically showing a part of the GIP circuit 104 disposed at the boundary between the neighboring blocks B1 and B2.

8 and 9, the GIP circuit 104 operates as a shift register using the stages S (N-1) to S (N + 1) which are connected in a dependent manner. Each of the stages S (N-1) to S (N + 1) is connected to the gate lines 14 through an output terminal to sequentially supply gate pulses to the gate lines 14 according to the shift clock . Each of the stages S (N-1) to S (N + 1) includes a start pulse VST received at the VST terminal or carry signals CAR (N-1) and CAR (N) And starts outputting the gate pulse by raising the voltage of the output terminal to the gate-on voltage VGH when the shift clocks CLK1 and CLK7 are input.

Each of the stages S (N-1) to S (N + 1) may be implemented by a known gate driver or a GIP circuit, and thus is not limited to a specific circuit. Each of the stages S (N-1) to S (N + 1) charges the output terminal OUT (n) in response to the Q node voltage as shown in FIGS. 10 and 11, A pull-up transistor Tb for pulling up the output terminal OUT (n) in response to the QB node voltage and for pulling up the output voltage by pulling up the output terminal OUT (n) And a switch circuit 70 for charging and discharging the Q node and the QB node. The output terminal OUT (n) is connected to the gate line 14 of the display panel 100. The output voltage Vout n) are applied to the gate line 14.

The pull-up transistor Tu charges the output terminal up to the VGH of the shift clock CLK when the shift clock CLK is input to the drain in a state where the Q node is precharged by VGH. When the shift clock CLK is inputted to the drain of the pull-up transistor Tu, the voltage of the Q node floated through the parasitic capacitance between the drain and gate of the pull-up transistor Tu is higher than VGH by bootstrapping It can be raised to about 2 VGH. At this time, the pull-up transistor Tu is turned on by the voltage of the Q node, and the voltage of the output terminal rises to VGH. The pull-down transistor Td supplies the gate-off voltage VGL to the output terminal to discharge the output voltage Vout (n) to VGL when the QB voltage is charged to VGH.

The switch circuit 70 charges the Q node in response to the start pulse VST inputted through the VST terminal or the carry signal CAR (N-1) received from the previous stage, and receives the RST terminal or the VNEXT terminal And the Q node is discharged in response to the signal RST terminal is applied with a reset signal for simultaneously discharging the Q nodes of all the stages S (N-1), S (N), and S (N + 1). The VNEXT terminal is a carry signal generated from the next stage. The switch circuit 70 can charge and discharge the QB node as opposed to the Q node using an inverter.

8 and 9, the stages S (N-1) and S (N-1) are arranged at the boundary between the blocks B1 and B2 adjacent to the N-1stage S (N-1) and Vout (N) of the output signals S (N) and S (N) The output voltages Vout (N-1) and Vout (N) may be the voltage of the gate pulse applied to the gate line or the voltage of the carry signal outputted simultaneously with the gate pulse and applied to the other stage.

The (N-1) th stage (S (N-1)) generates the last gate pulse, i.e., the (N-1) th gate pulse Vout (N-1) in the first display period. The Nth stage S (N) generates a first gate pulse, i.e., an Nth gate pulse Vout (N), in the second display period immediately after the touch sensing period. The gate line connected to the N-1 stage S (N-1) and the gate line connected to the N-th stage S (N) may be adjacent to each other at the boundary between the blocks B1 and B2, .

The GIP circuit 104 has a bridge circuit 200 connected at least one between neighboring stages S (N-1) and S (N) per block-to-block boundary. 9, " GIP_B1 " is a first GIP circuit for outputting gate pulses to the gate lines of the first block B1 and " GIP_B2 " is a gate pulse for outputting gate pulses to gate lines of the second block B2 And a second GIP circuit. "BR (1)" is a first bridge circuit connected between a stage for outputting the last gate pulse in the first GIP circuit (GIP_B1) and a stage for outputting the first gate pulse in the second GIP circuit (GIP_B2). &Quot; BR (2) " represents a stage for outputting the last gate pulse in the second GIP circuit (GIP_B2) and a stage for outputting the first gate pulse in the third GIP circuit 2 bridge circuit.

The bridge circuit 200 precharges the Q node according to the output voltage of the (N-1) th stage S (N-1), generates the first output voltage Vc_BR in accordance with the timing of the bridge clock BRCLK , And generates the second output voltage Vout_BR in accordance with the timing of the shift clock signal CLK. The bridge clock BRCLK is generated in the touch sensing periods S1, S2, ..., Sn and generated in each of the touch sensing periods S1, S3, ... Sn. The shift clock CLK1 applied to the bridge circuit 20 is also applied to one or more stages outputting gate pulses. A plurality of shift clocks CLK1 are generated consecutively during the display interval and are generated once at the end of the touch sensing intervals S1, S3, ... Sn. Therefore, the shift clock CLK1 applied to the bridge circuit 20 maintains the gate-off voltage VGL or the low level for most of the touch sensing period except for one clock time.

Figs. 12 and 13 are views showing one stage in detail in the GIP circuit 104. Fig. The circuits shown in Figs. 12 and 13 can be applied to stages (S (N-1), S (N)) for outputting gate pulses in FIGS. 8 and 9, (N) are not limited to those shown in Figs.

The GIP circuit 104 shown in Fig. 12 includes a pull-up transistor T6 connected to the Q node, a pull-down transistor T7 connected to the QB node, and switch circuits T1, T3N, T3, T4 and T5. In this GIP circuit, there is one Q node and one QB node. The Q node and the QB node are charged and discharged with the DC voltage (VDD, VSS). The gate-on voltage VGH is applied to the VDD terminal, and the gate-off voltage VGL is applied to the VSS terminal. Vout (n-4) is the carry signal received from the previous stage via the VST terminal. The transistor T1 supplies the gate-on voltage VGH to the Q-node in response to the start pulse or the carry signal Vout (N-4) received via the VST terminal to supply the Q- to be. Vout (n + 4) is the carry signal of the next stage received via the VNEXT terminal. The transistor T3 connects the Q node to the VSS terminal in response to the carry signal Vout (N + 4) to discharge the Q node. Transistors T4 and T5 are transistors constituting an inverter that charges and discharges the QB node according to the Q node voltage.

The GIP circuit 104 shown in Fig. 13 separates the QB node into QB_ODD and QB_EVEN and charges / discharges the QB nodes QB_ODD and QB_EVEN alternately for a predetermined time to generate pull-down transistors T7N, MT11, MT13, MT26, The DC gate bias stress of the transistor can be reduced. Each of the stages of the GIP circuit generates the first output voltages Vout1 and Vout2 and the second output voltages Vc1 and Vc2. The first output voltages Vout1 and Vout2 are gate pulses applied to the gate line. The second output voltages Vc1 and Vc2 are carry signals applied to the VST terminal or the VNEXT terminal of the other stages.

In order to reduce the GIP circuit area in the high-resolution display device, the GIP circuit 104 shown in Fig. 13 has a structure in which QB nodes (QB_ODD, QB_EVEN) and VNEXT terminals are shared in two stages. Each of the stages of the GIP circuit 104 includes pull-up transistors T7N, MT11, MT13, MT26, and MT16 connected to the QB nodes QB_ODD and QB_EVEN, which are connected to the Q nodes Q1 and Q2, MT27, switch circuits MT0 to MT10, MT14 to MT24, and the like. When the carry signal from the previous stage is inputted through the VST terminals VST1 and VST2, the Q-node charging transistors MT1 and MT14 are turned on and the Q-node Q1 of the first stage and the Q- The gate-on voltage VGH from the VDD terminal is applied to the Q-nodes Q1 and Q2 to pre-charge the Q-nodes Q1 and Q2. The transistors MT12 and MT15 discharge the Q nodes Q1 and Q2 in response to the carry signal of the next stage received via the VNEXT terminal. The transistors MT5 to MT8 and MT18 to MT21 charge the QB nodes Q_ODD and Q_EVEN with the AC voltage VDD_O and VDD_E according to the Q node voltage and connect the QB node Q_ODD and Q_EVEN to the VSS terminal, . In this GIP circuit 104, the voltage at the VSS terminal can be divided into VGL1 and VGL2 to reduce the deterioration of the pull-up transistors T6N, MT12, and MT25 and reduce the voltage [Delta] Vp of the pixels. VGL2 (-10V) applied to the VSS2 terminal may be set to a voltage lower than VGL1 (-5V) applied to the VSS1 terminal.

14 and 15 are views showing a bridge circuit 200 according to an embodiment of the present invention and its operation.

14 and 15, the bridge circuit 200 is disposed between the N-1 stage S (N-1) and the Nth stage S (N) And outputs the first output voltage Vout_BR at the timing of the shift clock (CLK) generated at the timing of the shift clock (CLK). The bridge circuit 200 outputs the second output voltage Vc_BR at the timing of the bridge clock BRCLK generated more times than the shift clock CLK during the touch sensing period S1.

The bridge circuit 200 includes a Q node, a QB node, first output circuits T101 and T102 for generating a first output voltage Vout_BR and second output circuits T103 and T104 for generating a second output voltage Vc_BR ) And the like.

The bridge circuit 200 further includes a switch circuit 70 for charging and discharging the Q node and the QB node. The switch circuit 70 may be implemented by a switch circuit of a known GIP circuit, or a switch circuit shown in Figs. 12 and 13. Fig. The fifth transistor T105 is a switch element for Q-node charging that is turned on according to the second output voltage of the previous bridge circuit to supply the gate-on voltage VGH from the VDD terminal to the Q-node to precharge the Q-node .

The first output voltage Vout_BR is output through the first output terminal of the bridge circuit 200. The first output voltage Vout_BR is applied to the VST terminal VST_S (N) of the Nth stage S (N) driven in the second display period D2 after the touch sensing period S1. The Q node of the Nth stage S (N) is precharged when the first output voltage Vout_BR is input.

The second output voltage Vc_BR is output through the second output terminal of the bridge circuit 200. The second output voltage Vc_BR is applied to the VST terminal (VST_BR (2)) of the next bridge circuit. Next bridge For example, the Q node of the second bridge circuit BR (2) shown in Fig. 9 is precharged when the second output voltage Vc_BR of the previous bridge circuit BR (1) is input.

The first output circuits T101 and T102 include first and second transistors T101 and T102. The first transistor T101 is a pull-up transistor for raising the first output voltage Vout_BR when the shift clock CLK indicated by the dotted circle in FIG. 15 is generated in the pre-charged Q node state. (Drain) of the first transistor T101 when the gate-on voltage VGH of the shift clock CLK is input to the first electrode of the first transistor T101 in the state where the Q node is precharged to the VGH, And the parasitic capacitance between the floating Q node and the floating Q node. When the Q node is raised to a voltage higher than VGH by bootstrapping, the first transistor T101 is turned on. The shift clock CLK for turning on the first transistor T101 is generated once at the end of the touch sensing period. This shift clock (CLK) is maintained at the gate-off voltage (VGL) or low level for most of the touch sensing period except for one clock time. Accordingly, the first transistor T101 is turned on at the end of the touch sensing period S1 to raise the first output voltage Vout_BR to the gate-on voltage VGH. The first transistor T101 includes a gate connected to the Q node, a first electrode to which the shift clock signal CLK is applied, and a second electrode coupled to the first output terminal.

The second transistor T102 is a pull-down transistor that discharges the first output terminal according to the voltage of the QB node to lower the first output voltage Vout_BR to the gate-off voltage VGL. The second transistor T102 includes a gate coupled to the QB node, a first electrode coupled to the first output terminal, and a second electrode coupled to the VSS terminal. And a gate off voltage VGL is applied to the VSS terminal.

The second output circuits T103 and T104 include third and fourth transistors T103 and T104. The third transistor T103 is a pull-up transistor for increasing the first output voltage Vout_BR when the gate-on voltage of the bridge clock BRCLK is generated during the touch sensing period S1 in the precharged Q node state. (Drain) of the third transistor T103 when the gate-on voltage VGH of the bridge clock CLK is input to the first electrode of the third transistor T103 in a state where the Q node is precharged to the VGH, And the parasitic capacitance between the floating Q node and the floating Q node. When the Q node is raised to a voltage higher than VGH by bootstrapping, the third transistor T103 is turned on. The bridge clock BRCLK for turning on the third transistor T103 is generated one or more times during the touch sensing period S1. Accordingly, the third transistor T103 is repeatedly turned on during the touch sensing period S1 to raise the second output voltage Vc_BR to the gate-on voltage VGH. The third transistor T103 includes a gate connected to the Q node, a first electrode to which a bridge clock CLK is applied, and a second electrode connected to the second output terminal.

The fourth transistor T104 is a pull-down transistor for discharging the second output terminal according to the voltage of the QB node to lower the second output voltage Vc_BR to the gate-off voltage VGL. The fourth transistor T104 includes a gate coupled to the QB node, a first electrode coupled to the second output terminal, and a second electrode coupled to the Vss terminal.

8, Vout (N-1) is the output voltage of the Nth stage S (N) generated at the end of the first display period D1. "Vout (N)" is the output voltage of the Nth stage S (N) generated at the start time of the second display period D2 in which the pixels are re-driven after the touch sensing period S1. 1) (FIG. 8, S (N)) generated subsequent to the output voltage Vout (N) of the Nth stage S (N) within the second display period D2 in the (N + 1)). "Q_BR" is the Q node voltage of the bridge circuit 200. Quot; Q_S (N) " is the Q node voltage of the Nth stage S (N) and Q_S (N + 1) is the Q node voltage of the (N + 1) th stage S (N + 1).

The present invention separates the output voltage from the bridge circuit 200 into a first output voltage Vout_BR and a second output voltage Vc_BR and outputs the output voltage Vout_BR at a timing of a shift clock CLK generated at the end of the touch sensing period S1 And applies the first output voltage Vout_BR to the Nth stage S (N). As a result, the Q-node voltage Q_S (N) of the N-th stage S (N) for outputting the first gate pulse of the second block B2 after the touch sensing period S1 N) maintains the gate-off voltage VGL for the remaining time minus one clock time in the touch sensing period S1 as in the Q-node voltage Q_S (N + 1) of the other stages, As shown in FIG. As a result, the present invention can reduce the stress of the pull-up transistor connected to the Q node of the N stage (S (N)).

14, when the voltage Vc_BR output through the second output circuits T103 and T104 is supplied to the VST terminal of the N-th stage S (N), as shown in FIG. 16, The Q-node of the N-th stage S (N) remains charged with the gate-on voltage VGH. Then, the DC gate bias stress of the pull-up transistor connected to the Q node is increased, so that deterioration of the transistor proceeds faster than the pull-up transistor of the other stages. In particular, since the Q-node voltage of the N-th stage is different from the pre-charging time of the Q-node voltage of the other stage, an image quality degradation such as a line dim can be observed between the blocks B1 and B2 by causing an output voltage deviation of the stages . The present invention separates the output of the bridge circuit 200 into a first output voltage Vout_BR and a second output voltage Vout_c and generates a first output voltage Vout_BR using a shift clock generated at the end of the touch sensing period ) Is delayed to reduce the transistor deterioration deviation between the stages.

The bridge circuit 200 further includes a sixth transistor T106 for discharging the Q node as shown in Fig.

The sixth transistor 106 is connected to the output voltage (carry signal) received from the stage S (N) or S (N + 1) of the next block B2 driven after the touch sensing period or the second display period D2 The Q node of the bridge circuit 200 is discharged in response to the shift clock CLK generated during the shift clock signal CLK. The sixth transistor T106 includes a gate to which the output voltage of the next block B2 or the shift clock CLK is applied received via the RST terminal, a first electrode connected to the Q node, and a second electrode connected to the VSS terminal do.

18 is a waveform diagram showing a Q-node resetting method of the stage S (N-1) for outputting the last gate pulse just before the touch sensing period starts.

18, in order to control the Q-node stress of the N-th stage S (N) outputting the last gate pulse in each block to the same level as that of the other stages, The shift clock CLK1_1 generated at the same time as the start is applied to the RST terminal of the N stage (S (N)) to discharge the Q node. As a result, the stress of the transistor for resetting the Q node in the Nth stage S (N) can be controlled in the same manner as the other stages. The gate of the transistor T3N shown in FIG. 12 may be connected to the RST terminal of the N stage (S (N)), for example. The present invention controls the stress of the transistor T3N to the same level as the transistor T3N of the other stages by applying the shift clock CLK1_1 to the gate of the transistor T3N formed in the Nth stage S .

18, " CLK1_2 " is a shift clock applied to the first transistor T101 of the bridge circuit 200. [

Since the Q node of the bridge circuit 200 is charged during the touch sensing period S1 as shown in Figs. 15, 16, and 20, the amount of the Q node is larger than that of the other GIP circuits 104. [ In order to improve this, if two or more bridge circuits 200 are continuously arranged as shown in FIG. 19, the stress of the Q node in the bridge circuit 200 can be reduced.

19 is a diagram showing an example in which a plurality of bridge circuits are arranged between GIP circuits that are responsible for neighboring blocks. 20 is a diagram showing Q-node stress of a bridge circuit when one bridge circuit is disposed between GIP circuits that are responsible for neighboring blocks. 21 is a graph showing Q-node stress of a bridge circuit when two bridge circuits are arranged between GIP circuits that are responsible for neighboring blocks.

19 to 21, two or more bridge circuits BIP1 and BIP2 are provided between a first GIP circuit GIP_B1 responsible for the first block B1 and a second GIP block GIP_B2 responsible for the second block B1. (200) are connected in a dependent manner. A bridge clock (BRCLK) is input to the bridge circuits (200) together with a shift clock (CLK). The shift clock (CLK) and the bridge clock (CLK) are generated in different periods and periods. Each of the bridge circuits 200 may be implemented with the circuit shown in Figs. 14 and 15. Fig.

When n (n is a positive integer equal to or larger than 2) bridge circuits 200 are arranged between the first GIP circuit GIP_B1 and the second GIP circuit GIP_B2, the second output voltage Vc_BR) is applied to the VST terminal of the second bridge circuit BR2. Therefore, the Q node of the second bridge circuit BR2 starts to be precharged when the second output voltage Vc_BR of the first bridge circuit BR1 is generated. Likewise, the Q node of the n-th bridge circuit BRn starts to be precharged when the second output voltage Vc_BR of the n-1-th bridge circuit BRn-1 is generated.

The Q node of the Nth stage S (N) driven after the touch sensing period S1 receives the first output voltage Vout_BR of the last bridge circuit, that is, the nth bridge circuit BRn, at its VST terminal When it begins to be pre-charged. The second output voltage Vc_BR of the nth bridge circuit BRn is applied to the VST terminal of the first bridge circuit BR1 among the bridge circuits BRn disposed between the following blocks and the Q output of the bridge circuit BR1 Pre-charge the node.

When one bridge circuit 200 is disposed between the first GIP circuit GIP_B1 and the second GIP circuit GIP_B2, since the Q node of the bridge circuit 200 is charged during the touch sensing period S1, Stress is great. On the other hand, when a plurality of bridge circuits BR1 to BRn are connected in a dependent manner, the Q node charging time of the bridge circuits BR1 to BRn is divided by n, as shown in FIG.

Oxide transistors are well suited to be applied to the transistors of the pixel array in the high resolution display and the transistors of the GIP circuit 104 including the bridge circuit 200 due to its high mobility and low off current . Such deterioration of the oxide transistor can be reduced by applying a photoexposure design. Since the bridge circuit 200 receives stress during the touch sensing period, the bridge circuit 200 is more stressful than the GIP circuits GIP_B1 and GIP_B2 that are responsible for each block of the screen. Therefore, the transistors of the bridge circuit 200 can be more deteriorated than other GIP circuits as shown in FIG. 22 shows an experiment result in which the threshold voltage of the pull-up transistor of the GIP circuit 104 that outputs the gate pulse and the pull-up transistor of the bridge circuit 200 change with time. 22, the deterioration of the pull-up transistor formed in the bridge circuit 200 is greater than that of the other pull-up transistors of the GIP circuit, so that the threshold voltage shift is large.

The present invention can reduce the deterioration of the transistors by applying a light exposure design as shown in FIG. 23 to at least one of the transistors constituting the bridge circuit 200.

23 shows a cross-sectional structure of transistors (Normal Tr, Bridge Tr) taken along the line A-A 'in the plane of the oxide transistor. 23, "GATE" represents a gate metal pattern, "ACT" represents a semiconductor pattern, and "SD" represents a source-drain metal pattern. "Normal Tr" is a sectional structure of a transistor formed in stages (S (N-1), S (N), S (N + 1)) of a general GIP circuit for outputting gate pulses. Bridge Tr is a cross-sectional structure of a transistor of a bridge circuit.

23, transistors (Normal Tr) of general stages S (N-1), S (N) and S (N + 1) for outputting gate pulses can sufficiently cover the semiconductor pattern ACT And a gate metal pattern (GATE) of a certain size. An insulating film GI exists between the semiconductor pattern ACT and the gate metal pattern GATE.

On the other hand, the gate metal pattern GATE of at least one transistor constituting the bridge circuit 200, for example, the pull-up transistors T101 and T103 is connected to the light incident from the back surface through the substrate SUBS, (N-1), S (N), and S (N + 1) in order to expose the source region (s). By applying such a light exposure design, the transistor degradation level of the bridge circuit 200 can be adjusted to the same level as the transistor degradation procedure of a general stage.

FIG. 24 is a stress simulation result of an oxide transistor to which a stress exposure (Positive Bias Temperature Stress (PBTS)) and a light exposure design are applied without a light exposure design. In this simulation, the Vgs of the transistor was 30 V, the temperature was 60 DEG C, the time was 3600 sec, and the luminance of the display panel was 4500 nits. As a result of this experiment, when the threshold voltage (? Vth) of the oxide transistor without light exposure is shifted to 2.5 V, the oxide transistor to which the light exposure design is applied has a small degradation since its threshold voltage (? Vth) is 0 V.

Since the threshold voltage shift is restored by applying the AC bias voltage to the a-Si transistor, the AC bias voltage can be applied as a method of compensating the deterioration of the a-Si transistor. However, as can be seen from the simulation results of FIG. 25, the oxide transistor is shifted in a similar manner to the threshold voltage (Vth) DC bias voltage (30 V DC bias) at the AC bias voltage (30 V AC bias). In this simulation result, 2 ms, 40 ms, and 200 ms are periods (Td) of alternating bias voltages. The alternating bias voltage swings between 0V and 30V. Therefore, it is difficult to compensate the deterioration of the oxide transistor by applying the alternating bias voltage to the oxide transistor. The present invention can reduce the deterioration of the oxide transistor constituting the GIP circuit 104 by reducing the stress of the GIP circuit 104 by separating the output from the stressed bridge circuit 200. [

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

102: Data driver 104: GIP circuit (Gate driver)
106: timing controller 108: level shifter (gate driver)
100: display panel 110: touch sensing unit
200: bridge circuit

Claims (16)

And a shift register for sequentially supplying gate pulses to the gate lines of the display panel,
The shift register
An (N-1) th stage for outputting a N-th (N is a positive integer equal to or greater than 2) -1 gate pulse;
An Nth stage for outputting an Nth gate pulse; And
And outputs a first output voltage in accordance with a first clock generated between the (N-1) th and (N) -th stages and occurring at the end of a touch sensing interval, And a bridge circuit for outputting a second output voltage in accordance with a second clock generated by the bridge circuit,
Each of the N-1 stage, the N-th stage, and the bridge circuit comprises: a Q node connected to a gate of a pull-up transistor; And
And a Q-node charging transistor for pre-charging the Q-node according to an input signal inputted through a start input terminal,
And a first output voltage from the bridge circuit is supplied to a start input terminal of the Nth stage. The method according to claim 1,
And a second output voltage of the bridge circuit is supplied to a start input terminal of another bridge circuit. The method according to claim 1,
A plurality of the bridge circuits are connected between the (N-1) th stage and the (N)
Wherein the bridge circuits sequentially generate the first and second output voltages, and a first output voltage of a last bridge circuit in which the Q node is finally charged is supplied to the start input terminal of the Nth stage. The method according to claim 1,
Wherein the Q-node voltage of the N-th stage holds the gate-off voltage for the remaining time except for the first clock time in the touch sensing period and is pre-charged for the first clock time. The method according to claim 1,
The bridge circuit comprising:
A first transistor including a gate connected to a Q node of the bridge circuit, a first electrode to which the first clock is applied, and a second electrode connected to a first output terminal to which the first output voltage is output;
A second transistor including a gate coupled to the QB node of the bridge circuit, a first electrode coupled to the first output terminal, and a second electrode to which the gate-off voltage is applied;
A third transistor including a gate connected to the Q node of the bridge circuit, a first electrode to which the second clock is applied, and a second electrode connected to a second output terminal to which the second output voltage is output; And
And a fourth transistor including a gate coupled to the QB node of the bridge circuit, a first electrode coupled to the second output terminal, and a second electrode to which the gate-off voltage is applied. 5. The method of claim 4,
Each of the transistors of the bridge circuit including an oxide semiconductor pattern. The method according to claim 6,
Wherein at least one of the transistors of the bridge circuit includes an oxide semiconductor pattern exposed to external light. 8. The method of claim 7,
And each of the transistors of the (N-1) th and (N) th stages includes an oxide semiconductor pattern which is not exposed to external light. The data lines and the gate lines are crossed, the pixels are arranged in a matrix, the screen including the pixels and the touch sensors is divided into at least first and second blocks, A display panel which is time-divisionally driven with a space therebetween;
The pixels of the first block are driven during the first display period and the pixels of the second blocks are driven during the second display period after the touch sensing period to write the data of the input image to the pixels of the first and second blocks A display driver;
And a touch sensing unit for sensing the touch input by driving the touch sensors during the touch sensing driving period,
The display driver may include:
And a shift register for sequentially supplying gate pulses to the gate lines,
The shift register
An (N-1) th stage for outputting a N-th (N is a positive integer equal to or greater than 2) -1 gate pulse;
An Nth stage for outputting an Nth gate pulse; And
And a second output voltage output circuit for outputting a first output voltage in accordance with a first clock, which is disposed between the (N-1) and N-th stages, at the end of the touch sensing period, And a bridge circuit for outputting a second output voltage in accordance with a second clock generated by the number of times,
Each of the N-1 stage, the N-th stage, and the bridge circuit comprises: a Q node connected to a gate of a pull-up transistor; And
And a Q-node charging transistor for pre-charging the Q-node according to an input signal inputted through a start input terminal,
And the first output voltage from the bridge circuit is supplied to the start input terminal of the Nth stage. 10. The method of claim 9,
And the second output voltage of the bridge circuit is supplied to the start input terminal of the other bridge circuit. 10. The method of claim 9,
A plurality of the bridge circuits are connected between the (N-1) th stage and the (N)
Wherein the bridge circuits sequentially generate the first and second output voltages, and a first output voltage of a last bridge circuit in which the Q node is finally charged is supplied to the start input terminal of the Nth stage. 10. The method of claim 9,
Wherein the Q-node voltage of the N-th stage holds the gate-off voltage for the remaining time except for the first clock time in the touch sensing period and is pre-charged for the first clock time. 10. The method of claim 9,
The bridge circuit comprising:
A first transistor including a gate connected to a Q node of the bridge circuit, a first electrode to which the first clock is applied, and a second electrode connected to a first output terminal to which the first output voltage is output;
A second transistor including a gate coupled to the QB node of the bridge circuit, a first electrode coupled to the first output terminal, and a second electrode to which the gate-off voltage is applied;
A third transistor including a gate connected to the Q node of the bridge circuit, a first electrode to which the second clock is applied, and a second electrode connected to a second output terminal to which the second output voltage is output; And
And a fourth transistor including a gate connected to the QB node of the bridge circuit, a first electrode connected to the second output terminal, and a second electrode to which the gate-off voltage is applied. 14. The method of claim 13,
And each of the transistors of the bridge circuit includes an oxide semiconductor pattern. 15. The method of claim 14,
Wherein at least one of the transistors of the bridge circuit includes an oxide semiconductor pattern exposed to external light. 16. The method of claim 15,
Wherein the transistors of the (N-1) th and (N-1) th stages are oxide semiconductor patterns that are not exposed to external light.

Images