KR20180045033A - Process control method and system using flexible sampling - Google Patents

Abstract

The production of the flexible sparse metrology sample plan of the present invention includes receiving a complete set of metrology signals from one or more wafers from a metrology tool, determining a set of wafer characteristics based on the entire set of metrology signals, Calculating at least one independent characterization metric based on the entire set of measurement signals, and determining a set of wafer characteristics, a wafer characteristic metric, and a flexible rare < RTI ID = 0.0 > And generating a sample plan. The at least one independent characterization metric of the at least one characteristic calculated from the measurement signals from the flexible sparse sample plan is within a threshold selected from one or more independent characterization metrics of one or more characteristics calculated with the entire set of metrology signals.

Description

Process control method and system using flexible sampling

This application is related to the application (s) listed below ("Related Applications") and claims the benefit of the best available effective filing date (s) from this application (s) For any and all parent, grandparent, and grandparent applications of applications, the applicant shall, unless otherwise claimed, claim the best available priority date, or, in the case of a patent application, in accordance with 35 USC § 119 (e) Based on benefits).

For purposes of the USPTO's special regulatory requirements, the present application is referred to as "COMPOSITE WAFER CONTROL USING FLEXIBLE SAMPLING" by Onur Demirer, William Pierson, and Roie Volkovich as inventors Filed June 18, 2015, the entirety of which is incorporated herein by reference in its entirety.

For the purposes of the USPTO's special regulatory requirements, the present application is based on the inventors Mark Wagner, Roie Volkovich, Dana Klein, Bill Pierson and Onudemier ( No. 62 / 221,588 filed on September 21, 2015 entitled " OPTIMIIZING SAMPLING BASED ACCURACY "by Onur Demirier, which is incorporated herein by reference in its entirety, Which is incorporated herein by reference.

The present invention relates generally to wafer metrology for lithography process control and more particularly to flexible sampling for reducing noise and improving feedback process tool feedback correction. To the creation of plans (flexible sampling plans).

Manufacturing semiconductor devices, such as logic and memory devices, generally involves processing a substrate, such as a wafer, using a vast number of fabrication processes to form various features and multiple levels of semiconductor devices. For example, lithography is a manufacturing process involving transferring a pattern from a reticle / mask to a resist arranged on a wafer. Further examples of manufacturing processes include, but are not limited to, chemical-mechanical polishing (CMP), etching, deposition, and ion implantation.

The term "wafer" as used throughout this specification generally refers to a substrate formed of a semiconductor or non-semiconductor material. For example, the semiconductor or non-semiconductor material may include, but is not limited to, monocrystalline silicon, gallium arsenide, or indium phosphide. The wafer may comprise one or more layers. For example, these layers may include, but are not limited to, resist, dielectric material, conductive material and semiconductive material. Many different types of such layers are known in the art, and the term wafer as used herein is intended to encompass a wafer on which all these types of layers may be formed. The one or more layers formed on the wafer may or may not be patterned. For example, the wafer may include a plurality of dies, each having repeatable patterned features. The formation and processing of such material layers may ultimately lead to finished devices. Many different types of devices can be formed on a wafer, and the term wafer used herein is intended to encompass a wafer on which any type of device known in the art can be fabricated.

The metrology processes are being used at various stages in the semiconductor manufacturing process to monitor process control during device fabrication. Types of metrology processes used in process control include overlay metrology, critical dimension (CD) metrology, wafer geometry metrology, and the like. During a processing step, such as, for example, a lithographic processing step, an overlay error may occur between the current layer and the previous layer of the semiconductor device. The overlay is defined as the mismatch between the current layer of the semiconductor device and one or more previous layers of the semiconductor device. Overlay errors can occur for various reasons, including lithography tool (scanner) errors, wafer shape induced errors, etch induced errors, and the like. In order to control the overlay and minimize the overlay errors during manufacturing of the semiconductor device, a feedback control system is applied. The feedback control system may be configured to: i) measure the overlay using a metrology tool; ii) calculate a scanner correctable that minimizes the overlay; and iii) use an improved process control (APC) And to re-supply the correction. Conventional overlay control schemes rely on measuring a fixed subset of overlay targets (i.e., static sample plan) on wafers to model overlay errors and calculate scanner correctable factors.

Previous applications for overlay metrology use static sample plans, where all wafers measured in all lots receive the same sample plan. In this case, the sample plan represents a selected subset of all available overlay targets on the wafers. As a result, periodic "dense map" measurements are often performed, since some wafers are measured using a very dense overlay sample plan (e.g., thousands of targets) Lt; / RTI > This periodic measurement requires time and effort. In addition, this procedure must be repeated for correction of highly irregular, high-order overlay signatures. An additional approach involves relying on an improved field-specific extrapolation modeling technique that is used to calculate field-specific corrections without relying on periodic dense map measurements from the static sample plan. This approach requires extensive optimization and careful configuration. Also, extrapolation techniques are less useful for some irregular overlay signatures.

As the dimensions of semiconductor devices are reduced, metrology processes are becoming more important for the successful manufacture of acceptable semiconductor devices. Thus, it may be desirable to provide a system and method for providing improved metrology capabilities and remedying the drawbacks of the prior art approaches as described above.

A system for forming a virtual dense sample map using a plurality of flexible sparse sample plans is disclosed. In one embodiment, the system includes a metrology subsystem configured to perform one or more metrology measurements on one or more of a number of wafers. In another embodiment, the system includes a controller communicatively coupled to one or more portions of the metering subsystem. In another embodiment, the controller includes one or more processors configured to execute program instructions, wherein the program instructions cause the one or more processors to generate a plurality of measurements based on one or more metrology measurements of one or more wafers received from the metrology subsystem To create flexible sparse sampling plans of the flexible sparse sampling plan and direct the metrology subsystem to perform the metrology measurements for two or more wafers at the locations of the plurality of flexible sparse sampling plans, Associated with one of the two or more wafers, to form a virtual dense map of the measurement signals by combining the results from the measurement measurements performed at the locations of the plurality of flexible sample plans, Process tool correctable factor based on It is configured to calculate a set.

A system for generating one or more flexible sparse sample plans is disclosed. In one embodiment, the system includes a metrology subsystem configured to perform one or more metrology measurements on one or more wafers. In another embodiment, the system includes a controller communicatively coupled to one or more portions of the metering subsystem. The controller includes one or more processors configured to execute program instructions, the program instructions causing the one or more processors to receive a full set of measurement signals from one or more wafers from a metrology subsystem, Determine a set of wafer characteristics based on the set and to calculate a wafer characteristic metric associated with the set of wafer characteristics, calculate one or more independent characterization metrics based on the entire set of measurement signals, And one or more independent characterization metrics of the one or more characteristics calculated with the metrology signals from the flexible sparse sample plan based on at least one independent characterization metric, The metric is within a threshold selected from one or more independent characterization metrics of one or more characteristics calculated as the entire set of metrology signals.

A system for generating one or more flexible sparse sample plans is disclosed. In one embodiment, the system includes a metrology subsystem configured to perform one or more metrology measurements on one or more wafers. In another embodiment, the system includes a controller communicatively coupled to one or more portions of the metering subsystem. The controller includes one or more processors configured to execute program instructions, the program instructions causing the one or more processors to receive a full set of measurement signals from one or more wafers from a metrology subsystem, Determine a set of wafer characteristics based on the set and calculate a set of accuracy merits for the set of wafer characteristics, calculate a statistical metric associated with each of the set of accuracy merits for the set of wafer characteristics, And to generate a flexible sparse sampling plan based on a statistical metric associated with each of the set of merits.

A system for generating one or more flexible sparse sample plans is disclosed. In one embodiment, the system includes a metrology subsystem configured to perform one or more metrology measurements on one or more wafers. In another embodiment, the system includes a controller communicatively coupled to one or more portions of the metering subsystem. The controller includes one or more processors configured to execute program instructions, the program instructions causing the one or more processors to receive a full set of measurement signals from one or more wafers from a metrology subsystem, Determine a set of wafer characteristics based on the set and to calculate a set of accuracy merits for a set of wafer characteristics, and to generate a flexible sparse sampling plan based on the set of accuracy merits, Is generated by identifying within the overall sampling plan target locations that represent the accuracy merit values below the selected threshold.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the general description, serve to explain the principles of the invention.

Numerous advantages of the present invention may be better understood by those skilled in the art by reference to the accompanying drawings in which:
FIG. 1A is a conceptual block diagram of a metrology system for measuring metrology targets of a semiconductor wafer in accordance with an embodiment of the invention. FIG.
Figure IB illustrates a top view of a semiconductor wafer having a demarked field in accordance with one embodiment of the present invention.
Figure 1C illustrates a top view of an individual field of a semiconductor wafer showing a plurality of targets in a field in accordance with an embodiment of the present invention.
1D is a block diagram of an imaging-based metrology system for measuring metrology targets of a semiconductor wafer in accordance with an embodiment of the present invention.
1e is a block diagram of a scatterometry-based metrology system for measuring measurement targets of semiconductor wafers in accordance with an embodiment of the present invention.
2 is a flow chart illustrating steps performed in a method for providing a process tool correctable factor through a plurality of flexible sparse sample plans in accordance with an embodiment of the present invention.
3A is a flow chart illustrating steps performed in a method of generating one or more flexible sparse sample plans in accordance with one embodiment of the present invention.
Figure 3B is a top view of the entire sample plan and the flexible rare sample plan according to one embodiment of the present invention.
4 is a flow chart illustrating steps performed in a method for generating one or more flexible sparse sample plans in accordance with one embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The details of the present invention, which is shown and described in the accompanying drawings, will now be described in detail.

Referring generally to FIGS. 1A-4, a method and system for generating flexible sampling plans for use in process tool correction in accordance with the teachings of the present invention is described. Embodiments of the present invention are directed to the creation of a flexible sparse sample plan that represents a subset of the available measurement target positions of one or more wafers of a number of wafers. Additional embodiments of the present invention are directed to the generation of complex wafer definitions using metrology data obtained using a number of flexible scarce plans. Flexible sparse sampling plans may be used to generate a patterned metric such as a process signature metric (e.g., PSQ), a patterned wafer shape metric (e.g., PWG), an overlay target asymmetric metric (e.g., Qmerit), or an overlay target accuracy metric But may be based on analysis of one or more independent metrics (e.g., accuracy merits).

Figure 1A illustrates a conceptual block diagram of a metrology system 100 that performs one or more metrology measurements in accordance with one or more embodiments of the present invention. In one embodiment, the system 100 includes a metrology subsystem 102. The metrology subsystem 102 is configured to measure one or more characteristics of the one or more metrology targets 111 of the wafer 112. For example, the metrology subsystem 102 may be configured to measure / characterize one or more overlay metrology targets, optical critical dimension (CD) targets, or focus / dose targets. For example, the metrology subsystem 102 may measure one or more metrology targets 116 in one or more fields 113 of a wafer, as shown in Figures 1B and 1C.

It is noted that for the sake of simplicity, the metrology system 100 is shown in a simplified block diagram. The city, including its components and geometry, is not intended to be limiting and is provided for illustrative purposes only. As used herein, the metrology system may be based on metrology measurement techniques such as contrast-based imaging, scatterometry, ellipsometry, SEM and / or AFM techniques, It is recognized that it may also include any number of optical elements, illumination sources and detectors for performing the metrology processes (e.g., overlay metrology, CD metrology, focus / dose metrology) .

In one embodiment, the metering subsystem 102 includes an overlay metrology subsystem or tool. In one embodiment, as shown in FIG. 1D, the metering subsystem 102 is an imaging-based metering subsystem. For example, the imaging-based metrology subsystem is configured to measure one or more contrast-based field images of one or more targets 111 of a wafer 112 disposed on a stage 136.

In one embodiment, in the case of imaging-based metrology, system 100 includes an illumination source 122 configured to generate illumination 134, and one or more wafers 112 (e.g., And one or more optical elements configured to collect reflected light from one or more metrology targets 111 of the substrate (e.g., one or more wafers in a lot). In one embodiment, one or more optical elements (e.g., beam splitter 126, etc.) provide a first portion of the illumination from illumination source 122 along the object path 132 onto the stage 136 To at least one metrology target (111) disposed on at least one processing layer of the wafer (112) disposed on the wafer (112). In addition, a second portion of the light from the illumination source 122 is directed to the one or more reference optics 140 along a reference path 138.

The illumination source 122 of the system 100 may include any illumination source known in the art. In one embodiment, the illumination source 122 may comprise a broadband light source. For example, illumination source 122 may include, but is not limited to, a halogen light source (HLS), an arc lamp, or a laser maintenance plasma light source. In another embodiment, the illumination source 122 may include a narrowband light source. For example, the illumination source 122 may include, but is not limited to, one or more lasers.

In one embodiment, one or more optical elements of system 100 may include, but are not limited to, one or more beam splitters 126. For example, beam splitter 126 may split light rays 134 from illumination source 122 into two paths, object path 132 and reference path 138. In this sense, object path 132 and reference path 138 may form part of two beam interference optical systems. For example, beam splitter 126 may be configured to transmit a first portion of the beam of light from illumination path 134, while allowing a second portion of the beam of light from illumination path 134 to be transmitted along reference path 138. [ May be directed along the object path 132. Beam splitter 126 may transmit a portion of the light from illumination path 134 along reference path 138 to reference optics 140 such as but not limited to a reference mirror.

The reference path 138 and the reference optics 140 may be any type of optical element that is known in the art of image based overlay metrology including but not limited to a shutter configured to selectively block the reference mirror, And may include any optical elements. In a general sense, a two-beam interference optical system may be configured as a Linnik interferometer. Linnik interferometers are described generally in U.S. Patent No. 4,818,110, issued April 4, 1989, and U.S. Patent No. 6,172,349, issued January 9, 2001, which are incorporated herein by reference in their entirety .

In another embodiment, the system 100 may include an objective lens 128. The objective lens 128 may help direct light to the surface of the wafer 112 disposed on the stage 136 along the object path 132. Following the splitting process by the beam splitter 126, the objective lens 128 splits the light from the object path 132, which may be colinear with the primary optical axis, onto the measurement targets 111 of the wafer 112 . Any objective lens known in the art may be suitable for implementation in this embodiment.

A part of the light impinging on the surface of the wafer 112 can be reflected, scattered or diffracted by the measurement targets 111 of the wafer 112 and transmitted through the objective lens 128 and the beam splitter 126, And may be directed to the detector 130 along the optical axis 124. It should further be appreciated that intermediate optics such as an intermediate lens, a mirror, an additional beam splitter, a filter, a polarizer, an imaging lens, etc. may be disposed between the objective lens 128 and the detector 130.

In another embodiment, the detector 130 may be arranged to collect image data from the surface of the wafer 112. For example, after reflecting or scattering from the surface of the wafer 112, light may travel along the primary optical axis 124 to the detector 130. It is recognized that any detector system known in the art is suitable for implementation in this embodiment. For example, the detector 130 may comprise a charge coupled device (CCD) based camera system. As another example, the detector 130 may include a time delay integrated (TDI) -CCD based camera system. In another aspect, the detector 130 may be communicatively coupled to the controller 104. In this regard, the digitized image data is transmitted from the detector 130 to the controller 104 via a signal such as a wired signal (e.g., copper wire, fiber optic cable, etc.) or a wireless signal . The controller 104 then calculates a set of process tool correctable factors based on the metrology measurements received from the detector 130 and provides a correction to the process tool 105 (e.g., For example, a scanner).

The scalable measurement and calculation techniques for imaging-based overlay metrology described herein are described in U.S. Patent No. 8,330,281, issued December 11, 2012, and U.S. Patent No. 7,355,291, issued April 8, 2008 Each of which is incorporated herein by reference in its entirety.

In one embodiment, as shown in FIG. 1E, the metrology subsystem 102 is a scatterometry-based metrology subsystem. For example, the scatterometry-based metrology subsystem is a scatterometry-based overlay metrology tool and is configured to measure a pupil image of one or more targets 111 of the wafer 112. As another example, the metering subsystem 102 includes a CD metrology tool adapted to measure one or more CD parameters from one or more CD targets disposed on a wafer 112. The CD measurement tool may be configured to measure any CD parameter known in the art. For example, the CD measurement tool may determine the following parameters from one or more CD targets: height, CD (e.g., lower CD, middle CD or upper CD) and sidewall angle SWA (e.g., lower SWA, middle SWA, SWA) can be measured. In this embodiment, the metrology subsystem 102 may be configured in any manner for performing scatterometry or ellipsometry measurements.

1E, the measurement subsystem 102 may include an illumination source 150, a polarization element 152, an analyzer 154, and a detector 160. In one embodiment, In another embodiment, the metrology subsystem 102 may include additional optical elements 156,158. For example, optical elements 156 and 158 may include one or more lenses (e.g., focusing lenses), one or more mirrors, one or more filters and / or one or more collimators, But is not limited thereto.

The use of scatterometry to detect overlay error is generally described in U.S. Patent No. 9,347,879, issued May 24, 2016, which is incorporated herein by reference in its entirety. The use of scatterometry to detect overlay error is generally described in U.S. Patent No. 6,689,519, issued February 10, 2004, which is incorporated herein by reference in its entirety. The principle of Eli Lip Sometri is Harland of William Andrew, Inc. Harland G. Tompkins and Eugene A.. Are generally provided in the first edition of the Euless Sometri Handbook published by Eugene A. Irene in 2005, which are incorporated herein by reference in their entirety.

Referring again to FIG. 1A, in one embodiment, the metrology system 100 includes a controller 104. In one embodiment, the controller 104 is communicatively coupled to the metering subsystem 102. For example, as shown in Figures 1d-1e, the controller 104 may be coupled to the outputs of the detectors 130, 160 of the metering subsystem 102. [ The controller 104 may be coupled to the detector in any suitable manner (e.g., by one or more transmission media, indicated by dashed lines) so that the controller 104 may receive the output generated by the metrology subsystem 102 .

In one embodiment, the controller 104 includes one or more processors 106. The one or more processors 106 are configured to execute a set of program instructions. Program instructions may perform any of the processing steps described throughout this disclosure.

The one or more processors 106 of the controller 104 may comprise any one or more processing elements known in the art. In this sense, the one or more processors 106 may comprise any microprocessor-type device configured to execute software algorithms and / or instructions. In one embodiment, one or more of the processors 106 may be a desktop computer, a mainframe computer system, a workstation, an image computer, a personal computer, a personal computer, a personal computer, A parallel processor, or other computer system (e.g., a network computer). It should be appreciated that the steps described throughout this disclosure may be performed by a single computer system or alternatively by multiple computer systems. In general, the term "processor" may be broadly defined as including any device having one or more processing elements for executing program instructions from non-volatile memory medium 108. Moreover, different subsystems (e.g., a metering subsystem, display, or user interface) of the system 100 may include processors or logic elements suitable for performing at least some of the steps described throughout this disclosure. Therefore, the above description should not be construed as limiting the invention, but merely as an example.

The memory media 108 or memory may include any storage medium known in the art suitable for storing program instructions executable by one or more processors 106 associated therewith. For example, memory media 108 may include non-volatile memory media. For example, memory media 108 may include read-only memory, random access memory, magnetic or optical memory devices (e.g., disks), magnetic tape, solid state drives, But are not limited thereto. Note that in another embodiment, memory 108 is configured to store one or more results from metrology subsystem 102 and / or output of the various steps described herein. It is further noted that the memory 108 may be housed in a common controller housing with one or more processors 106. In an alternative embodiment, the memory 108 may be remotely located relative to the physical location of the processor 106. For example, one or more of the processors 106 of the controller 104 may access a remote memory (e.g., a server) accessible via a network (e.g., Internet, intranet, etc.). In another embodiment, memory media 108 includes program instructions that cause one or more processors 106 to perform the various steps described herein.

In another embodiment, the controller 104 of the system 100 may be configured to receive data or information from other systems (e.g., test results from the inspection system, etc.) from other systems by a transmission medium, which may include wired and / And / or obtain measurement results from the metrology system). In this manner, the transmission medium may serve as a data link between the controller 104 and other subsystems of the system 100. Moreover, the controller 104 may transmit data to an external system via a transmission medium (e.g., a network connection).

In another embodiment, the system 100 includes a user interface (not shown). In one embodiment, the user interface is communicatively coupled to one or more processors 106 of the controller 104. In another embodiment, the user interface device may be utilized by the controller 104 to accept selections and / or commands from the user. In some embodiments described further herein, a display may be used to display data to a user (not shown). The user may then enter selection and / or commands (e.g., user selection of field sites for the measured field sites or regression process) in response to the data displayed to the user via the display device.

The user interface device may comprise any user interface known in the art. For example, the user interface may be a keyboard, a keypad, a touch screen, a lever, a knob, a scroll wheel, a track ball, a switch, a dial, a sliding bar, a scroll bar, a slide, a paddle, a steering wheel, a joystick, a bezel input device, and the like. For touch screen interface devices, it should be appreciated by those skilled in the art that a number of touch screen interface devices may be suitable for implementation in the present invention. For example, the display device may be integrated with (but not limited to) a touch screen interface such as a capacitive touch screen, a resistive touch screen, a surface acoustic based touch screen, an infrared based touch screen, In the general sense, any touch screen interface that can be integrated with the display portion of the display device is suitable for implementation in the present invention. In other embodiments, the user interface may include but is not limited to a bezel mounted interface.

The display device (not shown) may include any display device known in the art. In one embodiment, the display device may include, but is not limited to, a liquid crystal display (LCD). In another embodiment, the display device may include, but is not limited to, an organic light emitting diode (OLED) based display. In another embodiment, the display device may include, but is not limited to, a CRT display. Those skilled in the art will appreciate that a variety of display devices may be suitable for implementation in the present invention and that the particular choice of display device may vary depending on a variety of factors including, but not limited to, form factor, cost, You should know. In the general sense, any display device that can be integrated with a user interface device (e.g., a touch screen, bezel mounted interface, keyboard, mouse, trackpad, etc.) is suitable for implementation in the present invention.

Embodiments of the system 100 shown in Figs. 1A-1E may be further configured as described herein. In addition, the system 100 may be configured to perform any other step (s) of the embodiment (s) of the method described herein.

2 is a flow chart illustrating steps performed in a method 200 of process control using a plurality of flexible sparse sampling plans in accordance with one or more embodiments of the present invention.

In step 202, a number of flexible sparse sampling plans are created. The use of flexible sparse sampling plans allows optimization (or at least improvement) of sampling based on acquisition of accuracy / independent metric information from metrology subsystem 102. The metrology subsystem 102 may be a stand-alone metrology tool, an integrated metrology tool (e.g., a scatterometry or imaging-based metrology tool), or a combination thereof. The accuracy / independent metric information based optimization of this approach serves to shorten the sampling size and metrology measurement duration by selecting a subset of measured targets representing a full set or a sufficient set of targets. Methods for generating flexible sparse sampling plans based on independent metric information, such as accuracy merit values, are described in further detail herein.

At 204, metrology measurements are performed on one or more wafers at the locations of the plurality of flexible sampling plans. At step 206, a virtual compact map of the metrology measurements is formed by combining the results from the metrology measurements performed at the locations of the multiple flexible sampling plans. The application of the flexible sample plan herein permits the creation of field-specific corrections from the virtual dense map generated in step 206. [ This approach does not require periodic dense map measurements.

Furthermore, the formation of the virtual grid map in step 206 does not involve merely composing a plurality of flexible sample plans. Rather, the formation of the virtual dense map involves first removing the grid signatures from each flexible sample wafer through the controller 104. One or more algorithms executed by the controller 104 may then filter the noise by applying a weighted combination of adjacent fields for each field. The noise filtering function of method 200 is particularly useful as inter-wafer variations and lot-to-lot variations increase. By using this approach, zone variations for the wafer 112 can be captured more accurately, and field-specific settings can be calculated using a virtual dense map.

In step 208, a process tool correctable factor is calculated based on a virtual dense map of metrology measurements. For example, in the formation of a virtual dense sample map that includes various metrology signals related to the location of the virtual dense sample map, the controller 104 may calculate one or more correctable factors based on the virtual dense sample map. The correctable factor may be calculated using any known correctable factor calculation procedure known in the art of process tool correction. In a further step, the process tool correctable factor is used to adjust one or more of the process tools 105. 1A, once the process tool correctable factor is calculated by the controller 104, the controller 104 may determine one or more operating parameters of the process tool 105 (e.g., a scanner) Can be adjusted. Calculation of process tool correctable factors and use of the overlay function in the calculation of process tool correctable factors is described in U.S. Patent No. 7,876,438, issued January 25, 2011, which is incorporated herein by reference in its entirety Integrated. Examples of modeling used in the context of semiconductor metrology systems are generally described in U.S. Patent Nos. 6,704,661; U.S. Patent No. 6,768,967; U.S. Patent No. 6,867,866; U.S. Patent No. 6,898,596; U.S. Patent No. 6,919,964; U.S. Patent No. 7,069,153; U.S. Patent No. 7,145,664; U.S. Patent No. 7,873,585; And U. S. Patent Application No. 12 / 486,830, all of which are incorporated herein by reference in their entirety.

FIG. 3A is a flow chart illustrating steps performed in a method 300 for generating a flexible rare-instrumentation sampling plan, in accordance with one embodiment of the present invention. It should be noted that the steps of the method 300 herein may be implemented in whole or in part by the system 100. However, it is additionally recognized that the method 300 is not limited to the system 100 in that additional or alternative system-level embodiments may perform all or part of the steps of the method 300. It should also be noted that the steps and embodiments associated with the method 200 described hereinabove may be interpreted to extend to the method 300. [ In this regard, the steps of method 200 and method 300 may be combined in any suitable manner.

At step 302, a complete set of measurement signals from one or more wafers 112 is acquired. 1A, the metrology subsystem 102 acquires one or more metrology measurements from one or more wafers 112 and transmits the metrology measurements to the controller 104. The metrology subsystem 102, as shown in FIG. For example, the metrology subsystem 102 may collect a full or sufficient set of metrology signals from a representative set of wafers 112 of many wafers. It should be noted that the full sampling of step 302 is not limited to measuring a single wafer, but may be comprised of subsampling from different wafers.

In one embodiment, the metrology subsystem 102 may include an imaging-based metrology tool (see FIG. 1d) configured to acquire one or more images of one or more targets 111. In another embodiment, the metrology subsystem 102 may include a scatterometry-based metrology tool (see FIG. 1e) configured to collect light scattered or reflected (otherwise diverging) from the wafer 112. For example, the metrology signals collected by the metrology subsystem 102 may include one or more scatterometry-based pupil images collected from scatterometry overlay (SCOL) targets and / or multilayer SCOL targets via the metrology subsystem 102 Lt; / RTI > As another example, the metrology signals collected by the metrology subsystem 102 may include one or more contrast-based field images collected from image-based overlay (IBO) targets and / or multilayer IBO targets via metrology subsystem 102 .

The measurement signals obtained in step 302 may be obtained from any number of locations on the wafer 112. For example, the measurement signals may be collected from any of the targets 111 of the wafer 112. In one embodiment, the metrology signals may be collected from a set of similar targets. In another embodiment, the metrology signals may be collected from different types of targets. For example, some of the metrology signals may be collected from an overlay metrology target of a first type, while a second portion of metrology signals may be collected from an overlay metrology target of a second type. As another example, some of the metrology signals may be collected from the overlay metrology target, while a second portion of the metrology signals may be collected from the optical CD and / or focus / dose targets.

The term "a full set of measurement signals" and "a sufficient set of measurement signals" are used interchangeably herein and are interpreted such that the addition of one or more measurement signals describes the level of signal acquisition that does not improve process control or tracking It should be noted.

In step 304, a set of wafer characteristics is determined and a wafer characteristic metric associated with the set of wafer characteristics is calculated. For example, after receiving the entire set of measurement signals from the measurement subsystem 102, the controller 104 may determine a set of wafer characteristics from the entire set of measurement signals. The controller 104 may then calculate one or more wafer property metrics associated with the set of wafer properties. For example, the controller 104 may determine a set of overlay values corresponding to each position of the entire set of measurement signals. The controller 104 may then calculate one or more metrics associated with the set of overlay values. For example, the controller 104 may determine one or more statistical metrics associated with the distribution of overlay values obtained with the entire sample plan. The one or more statistical metrics may comprise any statistical metric known in the art. For example, the controller 104 may calculate an average, a standard deviation (?) Or a standard deviation multiple (e.g., 3?) Associated with an overlay value distribution obtained with the entire sample plan.

As another example, the controller 104 may determine a set of SWA values corresponding to targets at the location of the entire set of metrology signals from the previous layer. The controller 104 may then calculate one or more metrics associated with the set of SWA values. For example, the controller 104 may determine one or more statistical metrics associated with the distribution of SWA values obtained with the entire sample plan. For example, the controller 104 may calculate an average, a standard deviation (?) Or a standard deviation multiple (e.g., 3?) Associated with the SWA value distribution obtained with the entire sample plan. It should be noted that the scope of the present invention is not limited to the examples provided above. It is recognized herein that the present specification can be extended to any wafer property (e.g., CD value) known in the art and any wafer property metric (e.g., statistical metric) known in the art .

At step 306, one or more independent characterization metrics are calculated. For purposes of the present invention, the term "independent characterization metric" is interpreted to mean a characterization metric that is independent of the wafer characteristics (e.g., overlay, SWA, CD, etc.) Provides additional information on the given wafer characteristics. For example, the one or more independent characterization metrics may include one or more accuracy benefits. For example, the one or more accuracy benefits may include, but are not limited to, an overlay target accuracy metric such as an overlay target accuracy flag. For example, one such overlay target accuracy flag is a pupil 3σ accuracy flag. The pupil 3σ flag is derived by measuring the pupil image and calculating 3σ for all pixels in the pupil. The pupil 3? Flag indicates target quality and other accuracy related issues such as arcs. The relationship between the overlay and the pupil 3σ accuracy flag is described in Gutjahr et al., " Root cause analysis of overlay metrology excursions with scatterometry overlay technology (SCOL) , Proc. SPIE 9778, Metrology, Inspection, and Process Control for Microlithography al. < / RTI >

It should be noted that the scope of the disclosure of the present invention is not limited to the overlay target accuracy flag as described above. The one or more independent characterization metrics of step 306 may include at least one of a process signature metric (e.g., PSQ), a patterned wafer shape metric (e.g., PWG), an overlay target asymmetric metric (e.g., Qmerit), and an overlay target accuracy metric Flags), such as, but not limited to, any feature metric or accuracy benefit known in the art of wafers. These metrics can be used to identify overlay signature changes, problem areas on the wafer, locations to more closely measure for diagnostic purposes, and locations that can be avoided due to poor measurement confidence. Quality metrics for measuring overlay target asymmetry (i. E. Qmerit) are described in U.S. Patent Application No. 13 / 508,495, filed May 7, 2012, which is incorporated herein by reference in its entirety.

At step 308, one or more flexible sparse sample plans are generated. FIG. 3B illustrates a conceptual diagram of an entire sample plan 310 and a flexible sparse sample plan 320. FIG. In one embodiment, the one or more flexible sparse sample plans are generated based on a set of wafer characteristics, a wafer characteristic metric, and / or one or more independent characteristic metrics.

In one embodiment, the one or more flexible sparse sample plans may include one or more independent characterization metrics of one or more wafer characteristics obtained with a flexible sparse sampling plan, the one or more independent characterization metrics of one or more of the one or more wafer characteristics obtained with the full set of measurement signals (To be within the selected tolerance level) to be equivalent to an independent characterization metric.

In one embodiment, the one or more flexible sparse sample plans include one or more independent characterization metrics of the characteristics of one or more wafers obtained with a flexible sparse sampling plan, and one or more of the one or more wafer characteristics obtained with the full set of measurement signals Are defined to be equivalent if the above independent characterization metrics are within a selected threshold value for each other. In another embodiment, the one or more flexible sparse sample plans may include one or more independent characterization metrics of the characteristics of one or more wafers obtained with a flexible sparse sampling plan and one or more independent characterization metrics of one or more of the one or more wafer characteristics obtained with the full set of measurement signals If the independent characterization metric is within a statistical parameter of each other (e.g., a multiple of sigma).

In one embodiment, one or more flexible sparse sample plans are generated by simultaneously optimizing all wafer properties simultaneously. For example, wafer characteristics, corresponding accuracy metrics, target layout and signal parameters (e.g., intensity, sensitivity, etc.) can be optimized to find the most accurate result set. In another embodiment, for at least one wafer characteristic, the at least one wafer characteristic metric is accompanied by a joint optimization of wafer characteristics.

In one embodiment, a number of flexible sparse sampling plans are created such that each wafer in the wafer lot or each successive lot in the wafer lot uses a different sample plan than the other wafers. In one embodiment, the flexible sparse plans are generated so that they are uniformly distributed over one or more wafers 112 and meet local and global test balancing criteria (i.e., balanced test iterations). It should be noted that, in the case of overlay measurements, these properties provide the ability to accurately model the grid overlay in a flexible sparse sample plan. In another embodiment, the flexible sparse sample plans generated in step 308 can be used to filter grid noise from measurement signals measured from each wafer. It should be noted that the grid overlay represents the degree to which the exposure field is misaligned.

In addition, one or more flexible sparse sample plans 320 provide accuracy and robustness at small sample sizes. As a result, flexible sparse sample plans 320 can be used to measure each wafer in a given wafer lot and calculate very small sample sizes (e. G., ≪ RTI ID = 0.0 > , 20 to 50 targets per wafer) with integrated metrology tools. The flexible sparse sample plans 320 can be generated such that each flexible sparse sample plan has a certain amount of overlap with the remaining sample plans while meeting the same balancing criteria as the static sample plans.

For example, the user can minimize the overlap between the flexible sparse sample plans 320 to maximize (or at least increase) the total targets measured by the different sample plans. As another example, use may consistently compare a plurality of wafers within each other using some overlap between the flexible sparse sample plans 320. The flexible sampling approach of the present invention may also be applied to other types of metrics such as process signature metrics (e.g., PSQ), patterned wafer shape metrics (e.g., PWG), overlay target asymmetric metrics (e.g. Qmerit), and overlay target accuracy metrics And runtime updates to flexible sparse sample plans 320 based on independent characterization metrics such as, for example, but not limited to, overlay target accuracy flags.

4 is a flow chart illustrating steps performed in a method 400 of generating a flexible rare-instrumentation sampling plan in accordance with an embodiment of the present invention. It should be noted that the steps of the method 400 herein may be implemented in whole or in part by the system 100. However, it is additionally recognized that the method 400 is not limited to the system 100 in that additional or alternative system level embodiments may perform all or part of the steps of the method 400. It should also be noted that the steps and embodiments associated with the method 200, 300 previously described herein are interpreted as extending to the method 400. In this regard, the steps of the method 200, 300, 400 may be combined in any suitable manner.

In step 402, a full set of measurement signals is acquired from one or more wafers 112. In step 404, a set of wafer properties is determined and a set of accuracy merits associated with the set of wafer properties is calculated. In step 406, a statistics metric is calculated that is associated with each of the set of accuracy merits for the set of wafer properties. In step 408, a flexible sparse sampling plan is generated based on a statistical metric associated with each of the set of accuracy merits.

The calculated accuracy merit can be expressed as:

Where OVL_A represents the accuracy merit associated with the overlay, m represents the type of accuracy merit, and i, j represents the target location on the wafer. It should be noted that the above description is not limited to overlays and may be extended to any type of wafer characteristic, such as, but not limited to, one or more CD parameters (e.g., SWA). As previously described herein, the types of accuracy merit include a process signature metric (e.g., PSQ), a patterned wafer shape metric (e.g., PWG), an overlay target asymmetric metric (e.g., Qmerit) And an overlay target accuracy metric (e.g., an overlay target accuracy flag).

The statistical metrics associated with each of the sets of accuracy merits for a set of wafer characteristics may include any statistical metric known in the art. For example, the statistical metric calculated in step 406 may include, but is not limited to, an average value (e.g., normal distribution), a standard deviation, and the like of a wafer characteristic distribution.

In one embodiment, the flexible sparse sampling plan of step 408 is generated by identifying within the overall sampling plan a target location indicative of an accuracy merit value below a statistically defined threshold. For example, for each accuracy merit type, the statistically defined threshold may include a multiple of σ greater than or equal to the average value of the accuracy merit. For example, a statistically defined threshold may include the following equation:

At the statistically defined threshold values described above, the flexible sparse sample plan will consist of a target location with the accuracy merit below the sum provided above.

In another embodiment, selected areas of the wafer may be selectively targeted. In one embodiment, the calculation of the one or more statistical metrics of step 404 includes one or more statistical metrics associated with each of a set of accuracy merits for a set of wafer properties for at least one of a center of one or more wafers, Lt; / RTI > A statistically defined threshold may then be applied to the set of accuracy merits using one or more statistical metrics associated with the accuracy merits obtained from the centers and / or edges of one or more wafers.

In an alternative embodiment, the flexible sparse sampling plan may be generated using a selected threshold level. In this regard, method 400 may be executed without step 406. [ For example, a flexible sparse sampling plan can be generated by identifying, within the overall sampling plan, target locations that represent accuracy merit values below a selected threshold for each accuracy type.

All of the methods described herein may include storing results of one or more of the method embodiments on a storage medium. The results may include any results described herein and may be stored in any manner known in the art. The storage medium may comprise any of the storage media described herein or any other suitable storage medium known in the art. After the results are stored, the results can be accessed in a storage medium, used by any method or system embodiment described herein, formatted for display to a user, System or the like. Moreover, the results may be stored "permanently", "semi-permanently", "temporarily" or for a period of time. For example, the storage medium may be random access memory (RAM), and the results do not necessarily have to last indefinitely in the storage medium.

Although specific embodiments of the inventive subject matter described herein have been shown and described, it will be appreciated that, based on the teachings herein, changes and modifications may be made without departing from the spirit of the disclosure and the broader aspects set forth herein It will be apparent to those skilled in the art that the appended claims are to encompass within their scope all such changes and modifications as are within the true spirit and scope of the subject matter described herein.

Moreover, it is to be understood that the invention is defined by the appended claims. In general, those skilled in the art will understand that the terms used herein, and in particular the appended claims (for example, the subject matter of the appended claims), are generally intended to be "open" It is to be understood that the term " comprising " should be interpreted as "including but not limited to ", and" having " should be interpreted as having at least, Do "and so on). It is to be understood that the intention is to be clearly expressed in the appended claims and should not be construed as further undermining the understanding of those embodiments by those skilled in the art that such intent is not intended to be so, . For example, to facilitate understanding, the following appended claims are intended to cover the use of the phrases "at least one" and "one or more" The use of such phrases, however, is not intended to limit the scope of the appended claims to the scope of the appended claims, including the scope of such claims, Unless the same claim includes the introductory phrases " at least one "or" at least one "(e.g., the singular expressions generally denote" at least one " The same shall apply to the use of explicit provisions used to introduce the claims of the claims). In addition, even if a specific number of the description of the introduced claims is explicitly cited, those skilled in the art will recognize that such description is typically to be construed to mean at least a quoted number (for example, Two substrates "as used herein means typically at least two substrates or two or more substrates). Moreover, when an agreement similar to "at least one of A, B and C" is used, such a configuration is generally intended to mean that a person skilled in the art can understand the convention (for example, "at least one of A, B and C Includes, but is not limited to, systems having A alone, B alone, C alone, A and B together, A and C together, B and C together and / or A, B and C together ). Where an agreement similar to "at least one of A, B, or C" is used, such a convention is generally intended to mean that the person skilled in the art can understand the agreement (eg, "at least one of A, Includes, but is not limited to, systems having A alone, B alone, C alone, A and B together, A and C together, B and C together and / or A, B and C together ). Virtually any separable word and / or phrase that suggests two or more alternative terms in the description, the claims, or the figures of the invention may include any one of the terms, any one of the terms, or both terms As will be appreciated by those of ordinary skill in the art. For example, the phrase "A or B" will be understood to include the possibility of "A" or "B" or "A and B".

It is to be understood that the description disclosed herein and many of the attendant advantages may be understood by the foregoing description, and that various changes in form, arrangement, and arrangement of components, without departing from the disclosure or sacrificing all of the physical advantages, It will be clear that The described modes are merely illustrative and it is the intent of the following claims to encompass such changes.

Claims (33)

As a metrology system,
A metrology subsystem configured to perform one or more metrology measurements for one or more wafers; And
A controller communicatively coupled to one or more portions of the metrology subsystem
Lt; / RTI >
The controller comprising one or more processors configured to execute program instructions,
Wherein the program instructions cause the one or more processors to:
Receive a full set of measurement signals from the one or more wafers from the metrology subsystem,
Determine a set of wafer characteristics based on the entire set of measurement signals and calculate wafer characteristic metrics associated with the set of wafer characteristics,
Cause one or more independent characterization metrics to be calculated based on the entire set of measurement signals,
And to generate a flexible sparse sample plan based on the set of wafer characteristics, the wafer characteristic metric, and the one or more independent characterization metrics,
Wherein the at least one independent characterization metric of the at least one characteristic calculated with the measurement signals from the flexible sparse sampling plan is within a threshold selected from one or more independent characterization metrics of the at least one characteristic calculated with the full set of measurement signals Measurement system. 2. The metrology system of claim 1, wherein the controller is further configured to generate at least one additional flexible sparse sample plan. 3. The system of claim 2, wherein the controller is configured to instruct the metrology subsystem to perform one or more metrology measurements at locations of the flexible sparse sample plan and at least the additional flexible sparse sample plan Measuring system. 4. The method of claim 3, wherein the controller is further configured to combine results from the one or more metrology measurements performed at locations of the flexible sparse sample plan and at least the additional flexible sparse sample plan to generate a virtual dense sample map dense sample map). 5. The system of claim 4, wherein the controller is further configured to calculate one or more correctable based on the virtual dense sample map. 6. The metrology system of claim 5, wherein the controller is further configured to adjust one or more processing tools based on the correctable factor. 2. The metrology system of claim 1, wherein the metrology subsystem comprises an imaging-based metrology tool. 2. The metrology system of claim 1, wherein the metrology subsystem comprises a scatterometry-based metrology tool. 2. The metrology system of claim 1, wherein the metrology subsystem comprises an integrated metrology tool. 2. The metrology system of claim 1, wherein the set of wafer characteristics determined by the controller includes a set of overlay values. The metrology system of claim 1, wherein the set of wafer characteristics determined by the controller includes a set of sidewall angular values. The metrology system of claim 1, wherein the set of wafer characteristics determined by the controller comprises a set of critical dimension values. 2. The metrology system of claim 1, wherein the wafer characteristic metric calculated by the controller comprises a metric metric. 14. The metrology system of claim 13, wherein the statistical metric comprises at least one of an average or a standard deviation. 2. The metrology system of claim 1, wherein the at least one independent characterization metric is independent of the set of wafer characteristics. The metrology system of claim 1, wherein the at least one independent characterization metric comprises one or more accuracy merits. 17. The system of claim 16, wherein the at least one accuracy merit comprises at least one of a process signature metric, a patterned wafer shape metric, an overlay target asymmetric metric, or an overlay target accuracy metric. As a measurement system,
A metrology subsystem configured to perform one or more metrology measurements for one or more wafers; And
A controller communicatively coupled to one or more portions of the metrology subsystem
Lt; / RTI >
The controller comprising one or more processors configured to execute program instructions,
Wherein the program instructions cause the one or more processors to:
Receive a full set of measurement signals from the one or more wafers from the metrology subsystem,
Determine a set of wafer characteristics based on the entire set of measurement signals and calculate a set of accuracy merits for the set of wafer characteristics,
To calculate a statistical metric associated with each of a set of accuracy merits for the set of wafer characteristics,
And to generate a flexible sparse sampling plan based on a statistical metric associated with each of the set of accuracy merits. 19. The metrology system of claim 18, wherein the flexible sparsely sampled plan is generated by identifying within the overall sampling plan target locations that represent accuracy merit values less than a statistically defined threshold. 19. The method of claim 18, further comprising calculating a statistical metric associated with each of the set of accuracy merits for the set of wafer properties,
Calculating a statistical metric associated with each of a set of accuracy merits for a set of wafer properties for at least one of a center of one or more wafers or an edge of one or more wafers. 19. The metrology system of claim 18, wherein the controller is further configured to generate at least one additional flexible sparse sample plan. 22. The system of claim 21, wherein the controller is configured to instruct the metrology subsystem to perform one or more metrology measurements at locations of the flexible sparse sample plan and at least the additional flexible sparse sample plan Measuring system. 23. The system of claim 22, wherein the controller is further configured to combine the results from one or more metrology measurements performed at locations of the flexible sparse sample plan and at least the additional flexible sparse sample plan to form a virtual dense sample map Wherein the measurement system is configured to measure the temperature of the system. 24. The system of claim 23, wherein the controller is further configured to calculate one or more correctable factors based on the virtual dense sample map. 25. The metrology system of claim 24, wherein the controller is further configured to adjust one or more processing tools based on the correctable factor. 19. The metrology system of claim 18, wherein the metrology subsystem comprises an imaging-based metrology tool. 19. The metrology system of claim 18, wherein the metrology subsystem comprises a scatterometry-based metrology tool. 19. The metrology system of claim 18 wherein the metrology subsystem comprises an integrated metrology tool. 19. The system of claim 18, wherein the set of wafer characteristics determined by the controller includes a set of overlay values. 19. The metrology system of claim 18, wherein the set of wafer characteristics determined by the controller includes a set of critical dimension values. 19. The metrology system of claim 18, wherein the set of accuracy merits comprises at least one of a process signature metric, a patterned wafer shape metric, an overlay target asymmetric metric, or an overlay target accuracy metric. As a measurement system,
A metrology subsystem configured to perform one or more metrology measurements for one or more wafers; And
A controller communicatively coupled to one or more portions of the metrology subsystem
Lt; / RTI >
The controller comprising one or more processors configured to execute program instructions,
Wherein the program instructions cause the one or more processors to:
Receive a full set of measurement signals from the one or more wafers from the metrology subsystem,
Determine a set of wafer characteristics based on the entire set of measurement signals and calculate a set of accuracy merits for the set of wafer characteristics,
And to generate a flexible sparse sampling plan based on the set of accuracy merits,
Wherein the flexible sparse sampling plan is generated by identifying within the overall sampling plan target locations that represent accuracy merit values less than a selected threshold. As a measurement system,
A metrology subsystem configured to perform one or more metrology measurements on one or more wafers of a number of wafers; And
A controller communicatively coupled to one or more portions of the metrology subsystem
Lt; / RTI >
The controller comprising one or more processors configured to execute program instructions,
Wherein the program instructions cause the one or more processors to:
Cause a plurality of flexible sparse sampling plans to be generated based on one or more metrology measurements of one or more wafers received from the metrology subsystem,
Direct the metrology subsystem to perform metrology measurements on two or more wafers at locations of a plurality of flexible sparse sampling plans, each flexible sparse sampling plan being associated with one of two or more wafers -,
To form a virtual dense map of measurement signals by combining results from metrology measurements performed at locations of the plurality of flexible sample plans,
And to calculate a set of process tool correctable factors based on a virtual dense map of the measurement signals.

Images