KR20180041473A - Method And Computer Program of Implementing Virtual NAND Flash - Google Patents

Abstract

Disclosed are a method for implementing a virtual NAND flash and a computer program recording the same. According to an embodiment of the present invention, in the method for implementing a virtual NAND flash in which a bit error occurs according to an increase in a program/erase (P/E) cycle, provided is the method for implementing a virtual NAND flash, which includes the steps of: collecting measurement data to measure a bit error rate according to the P/E cycle of an actual NAND flash; and inserting the bit error into the virtual NAND flash based on the measurement data. Accordingly, the present invention can provide a test environment without requiring NAND flash hardware.

Description

TECHNICAL FIELD [0001] The present invention relates to a method of implementing a virtual NAND flash,

The present invention relates to a method of implementing a virtual NAND flash. And more particularly, to a method for implementing a virtual NAND flash capable of generating a bit error similar to a real NAND flash and a computer program recording the same.

The contents described in this section merely provide background information on the present embodiment and do not constitute the prior art.

NAND flash memory is used as a storage medium in many embedded systems because of its nonvolatile nature, low power consumption, strong shock resistance, small size, and random I / O capability.

The cell, which is the minimum unit for storing data in the NAND flash, is composed of a floating-gate transistor. The NAND flash memory has a structure in which such cells are connected in series. Applying the voltage to the floating gate transistor to fill the electrons corresponds to the program operation of the data, and the emptying of the electrons corresponds to the erase operation. The read operation is performed by measuring the voltage of the transistor. NAND flash memory represents binary data using the amount of electrons filled in the transistor. It has evolved from single-level-cell (SLC), which stores one bit of a cell, to triple-level-cell (TLC), which increases the level to store three bits in one cell. The TLC method has a unit area capacity four times that of the SLC method.

However, due to the physical characteristics of the NAND flash, there is a problem with the capacity increase in the method using such a single cell multi-voltage level. When a cell is divided into a plurality of voltage levels, it is impossible to clearly distinguish between voltage levels, and a bit error may occur due to interference between cells due to repeated read or write operations. This bit error affects the lifetime of the NAND flash-based storage medium.

The memory area occupies a large portion in the system and greatly affects the stability and reliability of the system. Therefore, the importance of testing NAND flash memory is growing, and studies are being conducted to increase the stability of NAND flash. These studies are basically done using real NAND flash hardware. In a research lab environment using real hardware, it is difficult to switch from a specific NAND flash test environment to another NAND flash test environment, and it takes additional time and expense to construct multiple test environments in parallel.

The present embodiment provides a method of software testing NAND flash. There is provided a method of implementing a virtual NAND flash in which a bit error occurs according to a P / E cycle (Program / Erase cycle), such as NAND flash, and a computer program recording the program.

According to an embodiment of the present invention, there is provided a method for implementing a virtual NAND flash in which a bit error occurs according to an increase in a program / erase cycle, wherein a bit error rate (bit error rate) The present invention provides a method for implementing a virtual NAND flash including a process of collecting measurement data measuring an error rate and a process of inserting a bit error into a virtual NAND flash based on measurement data.

Embodiments of the virtual NAND flash implementation method may further include one or more of the following features.

According to another embodiment of the present invention, a process of inserting a bit error is performed by referring to erase count information of a page when a program operation is performed on a page of a virtual NAND flash, The bit error rate is inserted based on the bit error rate for the bit error rate.

According to another embodiment of the present invention, a process of inserting a bit error is characterized by attempting bit flip to a buffer used for performing a write operation and writing a buffer to a page of a virtual NAND flash device.

According to another embodiment of the present invention, in a virtual NAND flash realization method in which a bit error occurs according to an increase in a P / E cycle, measurement data obtained by measuring a bit error rate according to a P / E cycle of an actual NAND flash is collected A process of constructing a probability model for the bit error rate per P / E cycle by extracting samples from the measurement data and the process data, and referring to the probability model, when a write operation is performed in the virtual NAND flash, The process of inserting bit error based on the error rate, measuring the bit error rate according to the P / E cycle of the virtual NAND flash, comparing the similarity with the measured data, and if the similarity is below a certain level, And reconstructing a probability model by extracting the probability model.

According to the present embodiment, by collecting the bit error rate occurring in the actual NAND flash and implementing the software-like virtual NAND flash, it is possible to provide a test environment that does not require the NAND flash hardware, Thereby facilitating the construction of the environment.

In addition, by implementing a virtual NAND flash for various types of NAND flash, it is possible to provide a test environment for various NAND flashes.

FIG. 1 conceptually shows a basic structure of a NAND flash memory.
2 is a flowchart illustrating a method for implementing a virtual NAND flash according to an embodiment of the present invention.
3 is a diagram illustrating a method of inserting a bit error in a virtual NAND flash according to an embodiment of the present invention.
4 is a flowchart illustrating a method for implementing a virtual NAND flash according to another embodiment of the present invention.
FIG. 5 is a graph illustrating a result of comparing a P / E cycle of a virtual NAND flash implemented according to an embodiment of the present invention with a P / E cycle of an actual NAND flash.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. It should be noted that, in adding reference numerals to the constituent elements of the drawings, the same constituent elements are denoted by the same reference symbols as possible even if they are shown in different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the constituent elements from other constituent elements, and the terms do not limit the nature, order or order of the constituent elements. Throughout the specification, when an element is referred to as being "comprising" or "comprising", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise . In addition, '... Quot ;, " module ", and " module " refer to a unit that processes at least one function or operation, and may be implemented by hardware or software or a combination of hardware and software.

FIG. 1 conceptually shows a basic structure of a NAND flash memory.

The NAND flash memory is composed of a plurality of blocks, and the block is composed of a plurality of pages. Cells constituting a minimum unit for storing data constitute a page, and data read and write operations are performed on a page basis, and erase operations are performed on a block basis. For NAND flash memory, the erase operation must be performed first in order to perform the write operation again for the once written area. During the writing and erasing process, various patterns of bit error occur due to the physical structure of the NAND flash.

The possible bit error patterns are as follows. A retention error refers to a case where data is stored in a floating gate of a NAND flash memory and a charge loss occurs after a long time and data of the corresponding cell is recognized as another data. Time and P / E cycle (program / erase cycle), which causes the most bit errors in the NAND flash. The program interference error is a case where the residual electron quantity in the floating gate changes due to interference of the cell closely related to the write operation as the NAND flash process becomes smaller and the cell density becomes higher. In addition, electrons are accumulated in the oxide film surrounding the floating gate as the P / E cycle increases, so that the residual electrons in the erase / read operation become different from the actual data. Such a difference is accumulated by the repetitive operation, A bit error occurs even if it is done.

The NAND flash simulator is a software implementation of the characteristics of the NAND flash memory. In one embodiment of the present invention, NANDSim is used as a NAND flash simulator. NANDSim is a NAND flash simulator provided by the Linux kernel. When a page write operation occurs in a virtual NAND flash, NANDSim creates a node having information on the number of erase operations for the block to which the page belongs, and manages the node through the link list. It is designed to cause an error if the number of erase times exceeds the P / E cycle (program / erase cycle) threshold value according to the NAND flash type. However, the actual NAND flash has a bit error even before reaching the threshold value of the P / E cycle. In an embodiment of the present invention, a method of realizing a virtual NAND flash memory suitable for reliability testing of NAND flash by generating a bit error even before reaching a threshold value of a P / E cycle like an actual NAND flash is presented.

2 is a flowchart illustrating a method for implementing a virtual NAND flash according to an embodiment of the present invention.

3 is a diagram illustrating a method of inserting a bit error in a virtual NAND flash according to an embodiment of the present invention.

Measurement data measuring the bit error rate according to the P / E cycle of the actual NAND flash is collected (S201). A real NAND flash refers to a hardware NAND flash that exists physically. As the P / E cycle increases, the change of the bit error rate occurring in the NAND flash is measured in units of pages. It is possible to measure the bit error rate by comparing the read data with the actually requested data while repeating a series of processes of writing and reading arbitrarily generated data on all pages in one block of the NAND flash and erasing the corresponding block. Since the erase operation is performed on a block-by-block basis, the bit error rate can be measured by averaging bit errors occurring in all pages within one block.

In order to provide a more detailed NAND flash test environment, bit errors occurring in actual NAND flash can be divided into patterns and data can be collected and a model capable of applying each pattern according to the collected data can be implemented.

For example, if the bit error rate is measured using the amount of electrons that have exited from the floating gate of each cell that constitutes the actual NAND flash according to the P / E cycle, a virtual NAND Flash can be implemented. In addition, by using the data of the proximity between the page where the write operation is performed in the actual NAND flash and the cell where the bit error occurs, a virtual NAND flash capable of detecting a bit error pattern due to the write interference error is implemented .

The process of S201 is performed for each of the SLC, MLC, and TLC types in consideration of the difference in bit error rate depending on the P / E cycle depending on the type of the NAND flash. By using the respective bit error rates, it is possible to implement a virtual NAND flash corresponding to various types of NAND flash.

Based on the measurement data obtained in step S201, a bit error is inserted into the virtual NAND flash (S202). When a write operation is performed on a page of a virtual NAND flash, a bit error is inserted according to the bit error rate for the P / E cycle with reference to the erase count information of the page. Referring to FIG. 3, when a write operation is performed on a page, the P / E cycle of the page is checked and ns_flip, which is a routine for generating a bit error according to the bit error rate for the collected P / E cycle, . When a page write operation occurs in the virtual NAND flash, the added routine ns_flip refers to the erase count information of the page, attempts to bit flip the buffer according to the bit error rate corresponding to the P / E cycle, Write to the page of the NAND flash device.

4 is a flowchart illustrating a method for implementing a virtual NAND flash according to another embodiment of the present invention.

Measurement data measuring the bit error rate according to the P / E cycle of the actual NAND flash is collected (S401). As the P / E cycle increases, the change of the bit error rate occurring in the NAND flash is measured in units of pages. It is possible to measure the bit error rate by comparing the read data with the actually requested data while repeating a series of processes of writing and reading arbitrarily generated data on all pages in one block of the NAND flash and erasing the corresponding block. Since the erase operation is performed on a block-by-block basis, bit errors occurring in all pages within one block can be averaged, and the bit error rate can be measured using the average.

A certain number of samples are extracted from the measurement data obtained in step S401 to construct a probability model for the bit error rate per P / E cycle (S402). The occurrence of bit error between each sample can build a probability model by calculating the bit error rate using linear interpolation.

Based on the probability model constructed in step S402, a bit error is inserted into the virtual NAND flash (S403). When a program operation is performed on a page of a virtual NAND flash, a bit error is inserted according to the bit error rate for the corresponding P / E cycle by referring to the erase count information of the page.

The bit error rate according to the P / E cycle is measured for the virtual NAND flash after the step S403, and the similarity with the bit error rate according to the P / E cycle measured for the actual NAND flash obtained in the step S401 is compared (S404). If the similarity is equal to or less than a certain level, a sample is further extracted from the measurement data to rebuild the probability model (S405). The probability model can be reconstructed by further extracting samples from the measurement data and adding the extracted samples to the existing probability model for the P / E cycle period where the similarity is below a certain level.

FIG. 5 is a graph illustrating a result of comparing a P / E cycle of a virtual NAND flash implemented according to an embodiment of the present invention with a P / E cycle of an actual NAND flash. (b) compares the bit error rate of the MLC NAND flash with the bit error rate of the virtual MLC NAND flash, (c) the bit error rate of the SLC NAND flash, The bit error rate of the TLC NAND flash and the bit error rate of the virtual TLC NAND flash are compared.

As shown, although there is a slight difference between the bit error rate of the virtual NAND flash and the actual bit error rate of the NAND flash, it is confirmed that the bit error rate increases with the increase of the P / E cycle in the virtual NAND flash as in the actual NAND flash . Using this virtual NAND flash, various test environments can be constructed for studying data reliability of NAND flash memory.

The foregoing description is merely illustrative of the technical idea of the present embodiment, and various modifications and changes may be made to those skilled in the art without departing from the essential characteristics of the embodiments. Therefore, the present embodiments are to be construed as illustrative rather than restrictive, and the scope of the technical idea of the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment should be construed according to the following claims, and all technical ideas within the scope of equivalents thereof should be construed as being included in the scope of the present invention.

As described above, the virtual NAND flash implementing method described in FIGS. 2 and 5 can be implemented by a program and recorded in a computer-readable recording medium. A program for implementing a similar mathematical problem retrieval method according to an embodiment of the present invention is recorded, and a computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored. Examples of such computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage, etc., and also implemented in the form of a carrier wave (e.g., transmission over the Internet) . The computer readable recording medium may also be distributed over a networked computer system so that computer readable code is stored and executed in a distributed manner. In addition, functional programs, codes, and code segments for implementing the present embodiment can be easily inferred by programmers in the technical field to which the present embodiment belongs.

Claims (11)

A method for implementing a virtual NAND flash in which a bit error occurs according to an increase in a P / E cycle (Program / Erase cycle)
Collecting measurement data that measures a bit error rate according to a P / E cycle of an actual NAND flash; And
A step of inserting a bit error into the virtual NAND flash based on the measurement data
Gt; NAND flash < / RTI > The method according to claim 1,
The step of inserting the bit error comprises:
When a write operation is performed on a page of the virtual NAND flash, a bit error is inserted based on a bit error rate for the P / E cycle with reference to the erase count information of the page How to Implement Virtual NAND Flash. The method according to claim 1,
The step of inserting the bit error comprises:
The method comprising: attempting a bit flip on a buffer used to perform the write operation; and writing the buffer to the page. The method according to claim 1,
The bit-
Wherein the measurement is performed using averages of errors occurring in all pages in one block of the NAND flash. The method according to claim 1,
The bit-
Wherein the measurement is performed using an amount of electrons that have exited from the floating gate of each cell that constitutes the actual NAND flash according to the P / E cycle. The method according to claim 1,
The measurement data includes:
Wherein the NAND flash memory includes a page in which the write operation is performed for the measurement in the actual NAND flash and a proximity of a position of a cell where a bit error occurs. A method for implementing a virtual NAND flash in which a bit error occurs according to an increase in a P / E cycle,
Collecting measurement data of a bit error rate according to a P / E cycle of an actual NAND flash;
Extracting a sample from the measurement data to construct a probability model for a bit error rate per P / E cycle;
Inserting a bit error into the virtual NAND flash based on a bit error rate according to the P / E cycle when a write operation is performed on a page of the virtual NAND flash with reference to the probability model;
Measuring a bit error rate according to a P / E cycle of the virtual NAND flash, and comparing similarity with the measured data; And
A step of extracting a sample from the measurement data and reconstructing the probability model when the similarity is less than a predetermined level
Gt; NAND flash < / RTI > 8. The method of claim 7,
The step of constructing the probability model includes:
Wherein a bit error rate between each sample is calculated using a linear interpolation method. 8. The method of claim 7,
The process of reconstructing the probability model comprises:
Wherein a sample is further extracted from the measurement data for a P / E cycle interval in which the similarity is less than or equal to a predetermined level. A computer program for creating a scenario recorded on a computer-readable recording medium including computer program instructions executable by a processor, the computer program causing a computing device, when executed by a processor of the computing device,
Collecting measurement data that measures a bit error rate according to a P / E cycle of an actual NAND flash; And
A process of inserting a bit error into the virtual NAND flash based on the measurement data
The computer program product comprising: A computer program for creating a scenario recorded on a computer-readable recording medium including computer program instructions executable by a processor, the computer program causing a computing device, when executed by a processor of the computing device,
Collecting measurement data of a bit error rate according to a P / E cycle of an actual NAND flash;
Extracting a sample from the measurement data to construct a probability model for a bit error rate per P / E cycle;
Inserting a bit error into the virtual NAND flash based on a bit error rate according to the P / E cycle when a write operation is performed on a page of the virtual NAND flash with reference to the probability model;
Measuring a bit error rate according to a P / E cycle of the virtual NAND flash and comparing similarity with a bit error rate according to a P / E cycle of the NAND flash; And
A step of extracting a sample from the measurement data and reconstructing the probability model when the similarity is less than a predetermined level
The computer program product comprising:

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