CN111859791A - Flash memory data storage error rate simulation method - Google Patents
Flash memory data storage error rate simulation method Download PDFInfo
- Publication number
- CN111859791A CN111859791A CN202010650819.8A CN202010650819A CN111859791A CN 111859791 A CN111859791 A CN 111859791A CN 202010650819 A CN202010650819 A CN 202010650819A CN 111859791 A CN111859791 A CN 111859791A
- Authority
- CN
- China
- Prior art keywords
- flash memory
- error rate
- data storage
- data
- page
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000013500 data storage Methods 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000004088 simulation Methods 0.000 title claims abstract description 16
- 238000012360 testing method Methods 0.000 claims abstract description 19
- 239000007787 solid Substances 0.000 claims abstract description 6
- 239000013598 vector Substances 0.000 claims description 29
- 238000013528 artificial neural network Methods 0.000 claims description 15
- 238000012549 training Methods 0.000 claims description 5
- 238000013461 design Methods 0.000 claims description 4
- 230000000694 effects Effects 0.000 claims description 4
- 238000005070 sampling Methods 0.000 claims description 3
- 238000009776 industrial production Methods 0.000 abstract 1
- 230000001737 promoting effect Effects 0.000 abstract 1
- 238000011160 research Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 208000037170 Delayed Emergence from Anesthesia Diseases 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
- G06F30/27—Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G06N3/00—Computing arrangements based on biological models
- G06N3/02—Neural networks
- G06N3/08—Learning methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Artificial Intelligence (AREA)
- Life Sciences & Earth Sciences (AREA)
- Biophysics (AREA)
- Computer Vision & Pattern Recognition (AREA)
- Computer Hardware Design (AREA)
- Health & Medical Sciences (AREA)
- Medical Informatics (AREA)
- Biomedical Technology (AREA)
- Geometry (AREA)
- Computational Linguistics (AREA)
- Data Mining & Analysis (AREA)
- General Health & Medical Sciences (AREA)
- Molecular Biology (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention discloses a flash memory data storage error rate simulation method. With the advent of three-dimensional flash memory technology, flash memory has become increasingly complex in its characteristics as its capacity increases. The establishment of the flash simulator has important significance for deeply analyzing the characteristics of the flash, reducing the workload of flash testing and promoting the progress of the solid state disk to high performance and high reliability. Data storage error rate simulation of a flash memory is an important component of a flash memory simulator, and due to the great reliability difference among flash memory blocks, how to quickly establish error rate simulation through a small number of tests becomes a problem to be solved urgently. Therefore, the method utilizes the condition to generate the countermeasure network, and quickly establishes the flash memory data storage error rate simulator aiming at the problem of reliability reduction caused by data storage through the flash memory test with lower cost, thereby having great significance for establishing a full flash memory simulator, researching the flash memory characteristics and reducing the industrial production cost.
Description
Technical Field
The invention belongs to the field of computer storage, and particularly relates to a flash memory data storage error rate simulation method.
Background
With the rise of hot tide such as big data, internet of things, artificial intelligence, 5G network, unmanned driving and the like, the flash memory gradually replaces the traditional disk storage with the characteristics of high reliability, low delay, low power consumption and the like. The demands for personal storage and enterprise big data storage with smart phones and Solid State Drives (SSDs) as the core are continuously increasing. The application of three-dimensional flash memory alleviates the challenges of mass storage to some extent, but its performance, reliability, etc. characteristics become increasingly complex. And the characteristic analysis is carried out on the flash memory, which is beneficial to designing the solid state disk with higher performance and high reliability.
However, the current testing and characteristic analysis work of the flash memory is extremely complex, and the testing work is time-consuming and labor-consuming in the face of various chip models, flash memory types and complex stacking structures, so that the characteristic analysis work is difficult. The establishment of flash memory emulators can help to quickly generate data for flash memory research, so how to establish a flash memory emulator by using a small amount of test data is a problem to be solved. Aiming at the existing problems, the invention discloses a flash memory data storage time error rate simulation method, which is used for solving the difficulty of data storage error rate simulation in a flash memory simulator and has important significance for the research of flash memory characteristics and the reduction of flash memory test cost.
Disclosure of Invention
Aiming at the above requirements and flash memory characteristic research, the invention provides a flash memory data storage time error rate simulation method, aiming at testing data storage error rate data of a small number of flash memory blocks aiming at huge block-to-block difference, generating a countermeasure network by utilizing conditions, and training to obtain a flash memory data storage error rate simulator, thereby quickly generating error rate data under different data storage which can be comparable to real test data, and realizing an important component of a full flash memory simulator.
To achieve the above object, according to an aspect of the present invention, there is provided a flash memory data saving error rate simulation method, including the steps of:
(1) testing the flash memory, and collecting the error rate of each page of the flash memory block after different data storage time under a specific programming/erasing period;
(2) designing a neural network discriminator D containing a condition vector, and inputting an error rate of each page of a block at different data storage time as a vector, such as [ R (rt is 1, pg is 0), R (rt is 1, pg is 1), … …, R (rt is 30, pg is i), … …, R (rt is N, pg is M) ], where rt represents data storage time, and is day unit, pg represents an intra-block number of the page, and the condition vector is rt;
(3) Repeatedly inputting page error rate data collected by the rest blocks, and training a discriminator D;
(4) designing a neural network error rate generator G containing condition vectors;
(5) generating a group of data containing condition values by using a generator G, and judging whether a simulation effect can be achieved by using a discriminator D;
(6) the generator G parameters are continually adjusted until all of the generated data can pass through the discriminator D.
In the present invention, the blocks tested in step (1) are obtained by randomly sampling blocks that have not undergone an erase/program operation in the flash memory chip.
In the invention, the data storage time of the flash memory can be carried out at high temperature to accelerate aging, and the equivalent accelerated time can be calculated by an Arrhenius equation.
In the present invention, the data storage error rate of the flash memory may be counted in units of pages, or may be counted in sub-pages of 1KB, 2KB, 4KB, or the like, with the condition vector being kept unchanged.
In the invention, when the data storage error rate of the flash memory and the neural network design take sub-pages as units, the input error rate vector can be changed from the original one-dimensional vector to two-dimensional, or the one-dimensional vector is still kept unchanged, but the data of one flash memory page is changed into a plurality of parts, and the input samples are increased.
In the invention, the data written in the test is random, and the data written in different word lines are completely different so as to simulate the scene of storing real data in the solid state disk.
The claimed technical solution is as follows:
a flash memory data storage error rate simulation method comprises the following steps:
(1) testing the flash memory, and collecting the error rate of each page of the flash memory block after different data storage time under a specific programming/erasing period;
(2) designing a neural network discriminator (D) containing condition vectors, and taking the error rate of each page of a block under different data storage time as a vector input;
(3) repeatedly inputting page error rate data collected by the rest blocks, and training a neural network discriminator (D);
(4) designing a neural network error rate generator (G) containing condition vectors;
(5) generating a group of data containing condition values by using a neural network error rate generator (G), and judging whether a simulation effect can be achieved by using a discriminator (D);
(6) the generator (G) parameters are continuously adjusted until all the generated data can pass through the discriminator (D).
Preferably, the blocks tested in step (1) are obtained by randomly sampling blocks in the flash memory chip which have not undergone the erase/program operation.
Preferably, the error rate of the flash memory can be counted in units of pages, or in units of sub-page sizes, and the condition vector is kept unchanged.
Preferably, the sub-page size is any one of 1KB, 2KB, 4KB sizes.
Preferably, when the error rate of the flash memory and the neural network design are in sub-page units, the input error rate vector can be changed from the original one-dimensional vector to a two-dimensional vector, or the one-dimensional vector is still kept unchanged, but the data of the original one flash memory page is changed into multiple parts, and the input samples are increased.
Preferably, the data written during the test is random, and the data written on different word lines are completely different, so as to simulate the scene of storing real data in the solid state disk.
In general, the above technical solutions contemplated by the present invention can achieve the following beneficial effects:
the invention can test the error rate data of a small number of flash memory blocks in different data storage time, generate the confrontation network by using conditions, fully consider the reliability difference between the blocks, establish the flash memory data storage error rate simulator and quickly generate the data storage error rate data which is comparable to the real data. The method has important significance for the research on the characteristics of the flash memory and the reduction of the test cost, and is an important component of a full flash memory simulator.
Drawings
FIG. 1 is a block diagram illustrating the steps of a method for simulating the error rate of data storage in a flash memory according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The overall idea of the invention is that the error rate data of the flash memory block under different programming/erasing periods is obtained through flash memory test, the countermeasure network design error rate generator and the discriminator are generated by applying conditions, and finally the error rate data which can be compared with the real data can be rapidly generated. As shown in fig. 1 in particular, the method comprises the following steps:
(1) testing the flash memory, and collecting the error rate of each page of the flash memory block after different data storage time under a specific programming/erasing period, wherein the statistics of the error rate can also be carried out by taking sub-pages as units;
(2) a neural network discriminator D including a condition vector is designed, and the error rate of each page of a block at different data storage time is input as a vector, such as [ R (rt is 1, pg is 0), R (rt is 1, pg is 1), … …, R (rt is 30, pg is i), … …, R (rt is N, pg is M) ], where rt represents data storage time, and in days, pg represents the intra-block number of the page, and the condition vector is rt. If the error rate statistics in the step (1) takes the sub-page as a unit, the dimensionality and the element number of the vector need to be correspondingly changed, and the input of a discriminator is matched;
(3) Repeatedly inputting the data storage error rate of the residual block acquisition pages, and continuously training a discriminator D;
(4) designing a neural network data storage error rate generator G containing condition vectors;
(5) generating a group of data containing condition values by using a generator G, and judging whether a simulation effect can be achieved by using a discriminator D;
(6) the generator G parameters are continually adjusted until all of the generated data can pass through the discriminator D.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (6)
1. A flash memory data storage error rate simulation method is characterized by comprising the following steps:
(1) testing the flash memory, and collecting the error rate of each page of the flash memory block after different data storage time under a specific programming/erasing period;
(2) designing a neural network discriminator (D) containing condition vectors, and taking the error rate of each page of a block under different data storage time as a vector input;
(3) repeatedly inputting page error rate data collected by the rest blocks, and training a neural network discriminator (D);
(4) Designing a neural network error rate generator (G) containing condition vectors;
(5) generating a group of data containing condition values by using a neural network error rate generator (G), and judging whether a simulation effect can be achieved by using a discriminator (D);
(6) the generator (G) parameters are continuously adjusted until all the generated data can pass through the discriminator (D).
2. The method of claim 1, wherein the blocks tested in step (1) are obtained by randomly sampling blocks in the flash memory chip that have not undergone the erase/program operation.
3. The method as claimed in claim 1, wherein the error rate of the flash memory is counted in page units or sub-page sizes, and the condition vector is kept unchanged.
4. The method as claimed in claim 3, wherein the sub-page size is any one of 1KB, 2KB and 4 KB.
5. The method as claimed in claim 3 or 4, wherein when the error rate of the flash memory and the neural network design are in sub-page units, the input error rate vector can be changed from the original one-dimensional vector to two-dimensional vector, or the one-dimensional vector is kept unchanged, but the data of the original one flash memory page is changed into multiple copies, and the input samples are increased.
6. The method as claimed in claim 1, wherein the data written during the test is random, and the data written on different word lines are completely different, so as to simulate the scenario of storing real data in the solid state disk.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010650819.8A CN111859791B (en) | 2020-07-08 | 2020-07-08 | Flash memory data storage error rate simulation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010650819.8A CN111859791B (en) | 2020-07-08 | 2020-07-08 | Flash memory data storage error rate simulation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111859791A true CN111859791A (en) | 2020-10-30 |
| CN111859791B CN111859791B (en) | 2023-12-26 |
Family
ID=73153318
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010650819.8A Active CN111859791B (en) | 2020-07-08 | 2020-07-08 | Flash memory data storage error rate simulation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111859791B (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090161466A1 (en) * | 2007-12-20 | 2009-06-25 | Spansion Llc | Extending flash memory data retension via rewrite refresh |
| US20110022931A1 (en) * | 2009-07-23 | 2011-01-27 | International Business Machines Corporation | Memory management in a non-volatile solid state memory device |
| US20120226963A1 (en) * | 2011-03-04 | 2012-09-06 | International Business Machines Corporation | Bad block management for flash memory |
| US20140089765A1 (en) * | 2011-05-26 | 2014-03-27 | Memoright (Wuhan) Co., Ltd. | Error estimation module and estimation method thereof for flash memory |
| CN105159840A (en) * | 2015-10-16 | 2015-12-16 | 华中科技大学 | Method for extracting soft information of flash memory device |
| US9747158B1 (en) * | 2017-01-13 | 2017-08-29 | Pure Storage, Inc. | Intelligent refresh of 3D NAND |
| KR20180041473A (en) * | 2016-10-14 | 2018-04-24 | 한국외국어대학교 연구산학협력단 | Method And Computer Program of Implementing Virtual NAND Flash |
| US20180174658A1 (en) * | 2016-12-15 | 2018-06-21 | Fanuc Corporation | Machine learning apparatus, life prediction apparatus, numerical control device, production system, and machine learning method for predicting life of nand flash memory |
| US20180357535A1 (en) * | 2017-06-12 | 2018-12-13 | Western Digital Technologies, Inc. | Identifying memory block write endurance using machine learning |
| CN109817267A (en) * | 2018-12-17 | 2019-05-28 | 武汉忆数存储技术有限公司 | A kind of service life of flash memory prediction technique based on deep learning, system and computer-readable access medium |
-
2020
- 2020-07-08 CN CN202010650819.8A patent/CN111859791B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090161466A1 (en) * | 2007-12-20 | 2009-06-25 | Spansion Llc | Extending flash memory data retension via rewrite refresh |
| US20110022931A1 (en) * | 2009-07-23 | 2011-01-27 | International Business Machines Corporation | Memory management in a non-volatile solid state memory device |
| US20120226963A1 (en) * | 2011-03-04 | 2012-09-06 | International Business Machines Corporation | Bad block management for flash memory |
| US20140089765A1 (en) * | 2011-05-26 | 2014-03-27 | Memoright (Wuhan) Co., Ltd. | Error estimation module and estimation method thereof for flash memory |
| CN105159840A (en) * | 2015-10-16 | 2015-12-16 | 华中科技大学 | Method for extracting soft information of flash memory device |
| KR20180041473A (en) * | 2016-10-14 | 2018-04-24 | 한국외국어대학교 연구산학협력단 | Method And Computer Program of Implementing Virtual NAND Flash |
| US20180174658A1 (en) * | 2016-12-15 | 2018-06-21 | Fanuc Corporation | Machine learning apparatus, life prediction apparatus, numerical control device, production system, and machine learning method for predicting life of nand flash memory |
| CN108228371A (en) * | 2016-12-15 | 2018-06-29 | 发那科株式会社 | Machine learning device and method, life predication apparatus, numerical control device |
| US9747158B1 (en) * | 2017-01-13 | 2017-08-29 | Pure Storage, Inc. | Intelligent refresh of 3D NAND |
| US20180357535A1 (en) * | 2017-06-12 | 2018-12-13 | Western Digital Technologies, Inc. | Identifying memory block write endurance using machine learning |
| CN109817267A (en) * | 2018-12-17 | 2019-05-28 | 武汉忆数存储技术有限公司 | A kind of service life of flash memory prediction technique based on deep learning, system and computer-readable access medium |
Non-Patent Citations (1)
| Title |
|---|
| 阳小珊;朱立谷;张猛;张伟;: "NAND闪存编程干扰错误研究", 中国传媒大学学报(自然科学版), no. 03 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111859791B (en) | 2023-12-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105183993B (en) | A kind of electromagnetic railgun Synthetic Simulation Platform and method | |
| CN112433819A (en) | Heterogeneous cluster scheduling simulation method and device, computer equipment and storage medium | |
| CN102750221A (en) | Performance test method for Linux file system | |
| CN103150228A (en) | Synthesizable pseudorandom verification method and device for high-speed buffer memory | |
| Bakir et al. | High performance simulations of kernel P systems | |
| CN109741774A (en) | A kind of controller and method based on FPGA on piece RAM simulated implementation DDR3 burst | |
| CN103580954A (en) | Device and method for verifying switch chip through software simulation | |
| CN106354515A (en) | SystemC code generation system based on model | |
| CN108959011A (en) | A kind of shared on-line debugging method based in FPGA prototype verification system | |
| CN105893707A (en) | SOC chip module verification and power consumption analysis method | |
| CN111859791B (en) | Flash memory data storage error rate simulation method | |
| CN103207804A (en) | MapReduce load simulation method based on cluster job logging | |
| CN111859792B (en) | Flash memory operation time delay simulation method | |
| Tarnawski et al. | Real-time simulation in non real-time environment | |
| CN105279007A (en) | Multi-core processor simulation method and apparatus | |
| CN115981259A (en) | Industrial full-simulation method and system based on digital twin technology | |
| CN113806860A (en) | Fault feature extraction system, method, storage medium and device based on simulation | |
| CN112464502A (en) | Optimization and acceleration memory simulation verification method and device, storage medium and terminal | |
| CN104765616B (en) | A kind of method and system for automatically generating I/O model | |
| CN105047207A (en) | Dynamic capacity expansion performance testing method and system for storage system | |
| Dishvali et al. | Description of the co-simulation platform for NPP | |
| Nakasato | Oct-tree method on gpu | |
| CN116070530B (en) | Power grid modeling real-time simulation method and device based on data driving | |
| OYMAN SERTELLER et al. | Modeling and simulation of faulty induction motor in dq reference frame using matlab/simulink with matlab/guide for educational purpose | |
| CN115391111A (en) | Aging data processing method, system, equipment and storage medium of storage equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |