CN111859791B - Flash memory data storage error rate simulation method - Google Patents
Flash memory data storage error rate simulation method Download PDFInfo
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- CN111859791B CN111859791B CN202010650819.8A CN202010650819A CN111859791B CN 111859791 B CN111859791 B CN 111859791B CN 202010650819 A CN202010650819 A CN 202010650819A CN 111859791 B CN111859791 B CN 111859791B
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- 238000004088 simulation Methods 0.000 title claims abstract description 16
- 238000012360 testing method Methods 0.000 claims abstract description 19
- 239000007787 solid Substances 0.000 claims abstract description 7
- 239000013598 vector Substances 0.000 claims description 31
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
- G06F30/27—Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
Abstract
The invention discloses a flash memory data storage error rate simulation method. With the advent of three-dimensional flash memory technology, the characteristics of flash memory have become increasingly complex as the capacity increases. The flash memory simulator is established, and has important significance for deeply analyzing the flash memory characteristics, reducing the workload of flash memory test and promoting the solid state disk to advance to high performance and high reliability. The data storage error rate simulation of the flash memory is an important component of a flash memory simulator, and how to quickly establish the error rate simulation through a small number of tests becomes a problem to be solved urgently due to the large reliability difference among flash memory blocks. Therefore, the invention utilizes the condition generation countermeasure network, and through the flash memory test with lower cost, the invention aims at the problem of reliability reduction caused by data storage, rapidly establishes the flash memory data storage error rate simulator, and has great significance for establishing the full flash memory simulator, researching the flash memory characteristics and reducing the industrial production cost.
Description
Technical Field
The invention belongs to the field of computer storage, and in particular relates to a flash memory data storage error rate simulation method.
Background
With the rise of hot flashes of big data, the Internet of things, artificial intelligence, a 5G network, unmanned operation and the like, the flash memory storage gradually replaces the traditional disk storage with the characteristics of high reliability, low delay, low power consumption and the like. Personal storage and enterprise big data storage demands with smart phones, solid state drives (Solid State Drive, SSD) as cores continue to increase. The application of three-dimensional flash memory alleviates challenges presented by mass storage to some extent, but its performance, reliability, etc. characteristics become increasingly complex. And the flash memory is subjected to characteristic analysis, so that the solid state disk with higher performance and high reliability is designed.
However, the existing flash memory test and characteristic analysis work is extremely complex, and faces to various chip types, flash memory types and complex stacking structures, so that the test work is time-consuming and labor-consuming, and the characteristic analysis work is difficult to step. The flash simulator can be built to facilitate rapid data generation for flash research, so how to build the flash simulator by using a small amount of test data is a current urgent problem to be solved. Aiming at the existing problems, the invention discloses a flash memory data storage time error rate simulation method, which aims to solve the difficulty of data storage error rate simulation in a flash memory simulator and has important significance for flash memory characteristic research and flash memory test cost reduction.
Disclosure of Invention
Aiming at the above needs and the research of flash characteristics, the invention provides a flash data preservation time error rate simulation method, which aims at testing the data preservation error rate data of a small number of flash blocks aiming at huge inter-block differences, generating an countermeasure network by using conditions, training to obtain a flash data preservation error rate simulator, thereby rapidly generating the error rate data under different data preservation which is comparable with real test data and realizing an important component part of the full flash simulator.
In order to achieve the above object, according to one aspect of the present invention, there is provided a flash memory data save error rate simulation method, comprising the steps of:
(1) Testing the flash memory, and collecting error rates of each page of the flash memory block after different data storage time under a specific programming/erasing period;
(2) Designing a neural network discriminator D containing condition vectors, and inputting error rates of each page of a block at different data retention times as a vector, such as [ R (rt=1, pg=0), R (rt=1, pg=1), … …, R (rt=30, pg=i), … …, R (rt=n, pg=m) ], wherein rt represents the data retention time in days, pg represents the intra-block number of the page, and the condition vector is rt;
(3) Repeatedly inputting page error rate data acquired by the residual blocks, and training a discriminator D;
(4) Designing a neural network error rate generator G containing a condition vector;
(5) Generating a group of data containing condition values by using a generator G, and judging whether the simulation effect can be achieved by using a judging device D;
(6) The generator G parameters are continuously adjusted until all the generated data can pass through the arbiter D.
In the present invention, the blocks tested in step (1) are obtained by randomly sampling blocks in the flash memory chip that have not undergone an erase/program operation.
In the invention, the data storage time of the flash memory can be performed at high temperature to accelerate aging, and the equivalent acceleration time can be calculated by an Arrhenius equation.
In the invention, the data storage error rate of the flash memory can be counted by taking pages as a unit, and can also be counted by sub pages with the sizes of 1KB, 2KB, 4KB and the like, and the condition vector is kept unchanged.
In the invention, when the data storage error rate of the flash memory and the neural network design take the sub-page as a unit, the input error rate vector can be changed from the original one-dimensional vector to two-dimensional vector, or the one-dimensional vector is still unchanged, but the data of one flash memory page is changed into a plurality of copies, and the input samples are increased.
In the invention, the data written in the test is random, and the data written in different word lines are completely different, so as to simulate the scene of storing real data in the solid state disk.
The technical scheme is as follows:
a flash memory data storage error rate simulation method comprises the following steps:
(1) Testing the flash memory, and collecting error rates of each page of the flash memory block after different data storage time under a specific programming/erasing period;
(2) Designing a neural network arbiter (D) containing a conditional vector, and taking the error rate of each page of a block under different data storage time as a vector input;
(3) Repeatedly inputting page error rate data acquired by the residual blocks, and training a neural network discriminator (D);
(4) Designing a neural network error rate generator (G) containing a condition vector;
(5) Generating a group of data containing condition values by using a neural network error rate generator (G), and judging whether the simulation effect can be achieved by using a discriminator (D);
(6) The generator (G) parameters are continuously adjusted until all the generated data can pass through the arbiter (D).
Preferably, the blocks tested in step (1) are randomly sampled from blocks of the flash memory chip that have not undergone an erase/program operation.
Preferably, the error rate of the flash memory may be counted in units of pages or in units of sub-page sizes, and the condition vector is kept unchanged.
Preferably, the sub-page size is any one of 1KB, 2KB, 4KB sizes.
Preferably, when the error rate of the flash memory and the neural network are designed in units of sub-pages, the input error rate vector of the flash memory can be changed from the original one-dimensional vector to the two-dimensional vector, or the one-dimensional vector is still unchanged, but the data of one flash memory page is changed into a plurality of copies, and the input samples are increased.
Preferably, the data written during testing is random, and the data written on different word lines are also completely different, so as to simulate the scene of storing real data in the solid state disk.
In general, the following beneficial effects can be achieved by the above technical solutions contemplated by the present invention:
the invention can test the error rate data of a small quantity of flash memory blocks under different data storage time, generate an countermeasure network by utilizing conditions, fully consider the reliability difference among the blocks, establish a flash memory data storage error rate simulator and quickly generate data storage error rate data which can be comparable with real data. The method has important significance for flash characteristic research and test cost reduction, and is an important component of the full flash simulator.
Drawings
FIG. 1 is a block diagram illustrating steps of a flash memory data save error rate emulation method according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
The whole idea of the invention is that the error rate data of the flash memory block under different programming/erasing periods is obtained through the flash memory test, the application condition is used for generating the counternetwork design error rate generator and the discriminator, and finally, the error rate data which can be compared with real data can be generated quickly. As shown in fig. 1, the method comprises the following steps:
(1) Testing the flash memory, collecting error rates of each page of the flash memory block after different data storage time under a specific programming/erasing period, wherein statistics of the error rates can also be performed by taking sub pages as units;
(2) A neural network discriminator D is designed which contains condition vectors, and the error rate of each page of a block at different data retention times is input as a vector, such as [ R (rt=1, pg=0), R (rt=1, pg=1), … …, R (rt=30, pg=i), … …, R (rt=n, pg=m) ], where rt represents the data retention time in days, pg represents the intra-block number of the page, and the condition vector is rt. If the error rate statistics in the step (1) is carried out by taking sub pages as units, the dimension and the number of elements of the vector need to be correspondingly changed, and the input of the discriminator is matched;
(3) Repeatedly inputting the data of the acquisition pages of the residual blocks to save the error rate, and continuously training the discriminator D;
(4) Designing a neural network data storage error rate generator G containing a condition vector;
(5) Generating a group of data containing condition values by using a generator G, and judging whether the simulation effect can be achieved by using a judging device D;
(6) The generator G parameters are continuously adjusted until all the generated data can pass through the arbiter D.
It will be readily appreciated by those skilled in the art that the foregoing description is merely a preferred embodiment of the invention and is not intended to limit the invention, but any modifications, equivalents, improvements or alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (6)
1. The flash memory data storage error rate simulation method is characterized by comprising the following steps of:
(1) Testing the flash memory, and collecting error rates of each page of the flash memory block after different data storage time under a specific programming/erasing period;
(2) Designing a neural network arbiter (D) containing a conditional vector, and taking the error rate of each page of a block under different data storage time as a vector input;
(3) Repeatedly inputting page error rate data acquired by the residual blocks, and training a neural network discriminator (D);
(4) Designing a neural network error rate generator (G) containing a condition vector;
(5) Generating a group of data containing condition values by using a neural network error rate generator (G), and judging whether the simulation effect can be achieved by using a discriminator (D);
(6) Continuously adjusting the generator (G) parameters until all the generated data can pass through the discriminator (D);
wherein the condition vector is the data retention time.
2. The method of claim 1, wherein the blocks tested in step (1) are randomly sampled from blocks of the flash memory chip that have not undergone an erase/program operation.
3. The method for simulating the data saving error rate of the flash memory according to claim 1, wherein the error rate of the flash memory is counted in units of page or sub page sizes, and the condition vector is kept unchanged.
4. The method for simulating the data saving error rate of the flash memory according to claim 3, wherein the sub-page size is any one of 1KB, 2KB and 4 KB.
5. The method according to claim 3 or 4, wherein when the error rate of the flash memory and the neural network design are in units of sub-pages, the input error rate vector is changed from the original one-dimensional vector to the two-dimensional vector, or the one-dimensional vector is still unchanged, but the data of the original flash memory page is changed into multiple copies, and the input samples are increased.
6. The method for simulating the storage error rate of flash memory data according to claim 1, wherein the data written during the test is random and the data written on different word lines are completely different to simulate the scene of storing real data in the solid state disk.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105159840A (en) * | 2015-10-16 | 2015-12-16 | 华中科技大学 | Method for extracting soft information of flash memory device |
| US9747158B1 (en) * | 2017-01-13 | 2017-08-29 | Pure Storage, Inc. | Intelligent refresh of 3D NAND |
| KR20180041473A (en) * | 2016-10-14 | 2018-04-24 | 한국외국어대학교 연구산학협력단 | Method And Computer Program of Implementing Virtual NAND Flash |
| CN108228371A (en) * | 2016-12-15 | 2018-06-29 | 发那科株式会社 | Machine learning device and method, life predication apparatus, numerical control device |
| CN109817267A (en) * | 2018-12-17 | 2019-05-28 | 武汉忆数存储技术有限公司 | A kind of service life of flash memory prediction technique based on deep learning, system and computer-readable access medium |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8938655B2 (en) * | 2007-12-20 | 2015-01-20 | Spansion Llc | Extending flash memory data retension via rewrite refresh |
| US8370712B2 (en) * | 2009-07-23 | 2013-02-05 | International Business Machines Corporation | Memory management in a non-volatile solid state memory device |
| US8560922B2 (en) * | 2011-03-04 | 2013-10-15 | International Business Machines Corporation | Bad block management for flash memory |
| CN102163165B (en) * | 2011-05-26 | 2012-11-14 | 忆正存储技术（武汉）有限公司 | Error estimation module and estimation method thereof for flash memory |
| US11049009B2 (en) * | 2017-06-12 | 2021-06-29 | Western Digital Technologies, Inc. | Identifying memory block write endurance using machine learning |
-
2020
- 2020-07-08 CN CN202010650819.8A patent/CN111859791B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105159840A (en) * | 2015-10-16 | 2015-12-16 | 华中科技大学 | Method for extracting soft information of flash memory device |
| KR20180041473A (en) * | 2016-10-14 | 2018-04-24 | 한국외국어대학교 연구산학협력단 | Method And Computer Program of Implementing Virtual NAND Flash |
| CN108228371A (en) * | 2016-12-15 | 2018-06-29 | 发那科株式会社 | Machine learning device and method, life predication apparatus, numerical control device |
| US9747158B1 (en) * | 2017-01-13 | 2017-08-29 | Pure Storage, Inc. | Intelligent refresh of 3D NAND |
| CN109817267A (en) * | 2018-12-17 | 2019-05-28 | 武汉忆数存储技术有限公司 | A kind of service life of flash memory prediction technique based on deep learning, system and computer-readable access medium |
Non-Patent Citations (1)
| Title |
|---|
| NAND闪存编程干扰错误研究;阳小珊;朱立谷;张猛;张伟;;中国传媒大学学报(自然科学版)(第03期);全文 * |
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