KR20180035442A - ESD protection device and method thereof and mobile electronic device with the same - Google Patents

Abstract

Provided are an electrostatic discharge protection element, a manufacturing method thereof and a mobile electronic device provided with the same. The electrostatic discharge element according to an embodiment of the present invention comprises: a varistor substrate including a pair of lower surface electrodes, a pair of upper surface electrodes, a pair of internal electrodes and a pair of connectors connecting the electrode pairs to each other; a capacitor laminated on and connected to the upper surface electrodes of the varistor substrate to be connected in parallel with the varistor substrate and composed of a single component; and a molding unit molding the upper surface of the varistor substrate and the capacitor. The present invention strengthens resistance to electrostatic discharge and enhances capacitance concurrently to enhance product reliability, simplifies a manufacturing process and makes line-ups in accordance with various capacitance values easy to enhance manufacturing efficiency and to reduce manufacturing costs, and supplements temperature characteristics of the varistor substrate to stabilize temperature characteristics of an overall package and to enhance product reliability.

Description

[0001] The present invention relates to an ESD protection device, a method of manufacturing the ESD protection device, and a portable electronic device having the ESD protection device,

The present invention relates to an electrostatic protection device for an electronic device such as a smart phone, and more particularly, to an electrostatic protection device capable of simultaneously improving ESD tolerance, temperature characteristics, and capacitance capacity, And more particularly, to a portable electronic device equipped with the same.

In recent portable electronic devices, there is an increasing tendency to adopt a metal housing to improve esthetics and robustness.

However, since the metal housing is excellent in electrical conductivity due to the nature of the material, an electrical path can be formed between the housing and the built-in circuit depending on the specific device or depending on the location. Particularly, since the metal housing and the circuit part form a loop, when a static electricity having a high voltage instantaneously flows through a conductor such as a metal housing having a large exposed surface area, the circuit part such as an IC can be damaged, Measures are required.

Furthermore, since such static electricity is more likely to flow into the pointed tip than the flat surface due to its nature, there is a need to further strengthen the immunity of static electricity to such portions.

On the other hand, since such a portable electronic device essentially carries a communication function, a high capacitance is required to stably process a communication signal without attenuation. In particular, various capacitances are required depending on a position on a circuit board.

In this case, when a varistor is used as an electrostatic protection element, resistance to static electricity can be enhanced, but it is not easy to achieve a capacitance of a high capacity. Further, since the varistor material has a high temperature change rate due to its characteristics, It causes deterioration of the overall temperature characteristics.

Accordingly, it is urgent to implement various high capacity capacities while at the same time enhancing the electrostatic immunity of the portable electronic device at positions where the static electricity is easy to flow, and at the same time, measures for stabilizing the temperature are urgently required.

KR 10-0684334 B1 (2007.12.12 Enrollment)

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances and provides an electrostatic protection device capable of simultaneously improving resistance to static electricity, And a portable electronic device having the same.

According to an aspect of the present invention, there is provided a varistor comprising: a varistor substrate including a pair of bottom electrodes, a pair of top electrodes, a pair of internal electrodes, and a pair of connecting portions connecting the pair of electrodes; A capacitor formed as a single component laminated on the top surface electrode of the varistor substrate to be connected in parallel with the varistor substrate; And a molding part for molding the capacitor and the upper surface of the varistor substrate.

According to a preferred embodiment of the present invention, the pair of inner electrodes may be spaced apart from each other at regular intervals on the same plane.

In addition, the molding part may be made of epoxy.

In addition, the capacitors may be stacked on the varistor substrate in the form of a flip chip.

Also, the capacitor may be laminated to the varistor substrate by soldering.

In addition, the interval a between the pair of upper surface electrodes may be smaller than the interval b between the pair of lower surface electrodes.

In addition, a space formed by the lower surface of the pair of top electrodes and the capacitor may be filled with a discharge material.

In addition, the discharge material may be made of a non-conductive material or a semiconductor material including metal particles.

In addition, the pair of connection portions may be a conductive via formed through the varistor substrate.

The pair of connection portions may be formed on both sides of the varistor substrate.

The varistor substrate may be made of a semiconductive material containing at least one of ZnO, SrTiO ₃ , BaTiO ₃ and SiC, or a Pr and Bi-based material.

Also, the capacitor may be a COG type LCC.

According to another aspect of the present invention, there is provided a connector comprising: a conductor including a tip portion protruding outward from a conductive case; Circuitry; And an electrostatic protection element electrically connecting the conductor and the circuit portion. Here, the electrostatic protection device may be preferably an electrostatic protection device of various embodiments having the structure and characteristics as described above.

According to a preferred embodiment of the present invention, the conductor may comprise a side key.

The distal end portion may include one end of a connector insertion port for connection with an external device.

According to another aspect of the present invention, there is provided a method of manufacturing a varistor substrate, the method comprising: forming a pair of inner electrodes, a pair of upper electrodes, a pair of lower electrodes, and a pair of connection portions, A step of soldering and laminating a capacitor made of a single part to the upper surface electrode in a flip chip form; Molding an upper surface of the varistor substrate and the capacitor with an epoxy film; And a step of cutting each of the unit areas.

According to a preferred embodiment of the present invention, the method for fabricating an electrostatic discharge protection device may further include filling a space between the pair of top electrodes with a discharge material after the forming.

The method of fabricating the electrostatic discharge protection device may further include filling a space formed by the pair of upper electrodes and the lower surface of the capacitor with a discharge material after the combining step.

Also, the molding may be performed by disposing an epoxy film on the varistor substrate and the capacitor.

In the forming, the upper surface electrode and the lower surface electrode may be formed such that an interval (a) between the pair of upper surface electrodes is smaller than an interval (b) between the pair of lower surface electrodes.

According to the present invention, since the electrostatic protection function and the capacitor function are separately provided and a single package is formed, the resistance to static electricity is enhanced and the capacitance capacity is improved at the same time, so that the reliability of the product can be improved.

Further, since the electrostatic protection function and the capacitor function are separately provided in the form of a single component of a varistor substrate and an MLCC, it is possible to simplify the manufacturing process and improve the manufacturing efficiency by improving the lineup according to various capacities, .

In addition, the present invention realizes capacitance by using a COG-type MLCC single component, thereby stabilizing the temperature characteristic of the entire package by compensating the temperature characteristic of the electrostatic protection function, thereby improving the reliability of the product.

Further, since a single MLCC part is used, the degree of freedom in designing the capacitance is increased, so that a lineup of various capacities can be realized, so that it is possible to quickly respond to the request of the customer without changing the process.

Further, since the MLCC single component and the varistor substrate are molded and packaged in a single package, the MLCC single component and the varistor substrate can be protected, the size of the entire chip size can be uniformly regulated, and the pick- Therefore, no extra effort is required for picking up the electrostatic protection element, and the manufacturing efficiency can be further improved.

In addition, the present invention can mass-produce the epoxy film by using a large-area varistor substrate and curing the epoxy film, thereby reducing the amount of raw materials to be discarded, thereby further reducing manufacturing cost and contributing to environmental improvement.

Further, since the varistor is constituted by a single layer, it is possible to sufficiently secure a space for forming a capacitance, and to easily realize a high capacitance, or to uniformize the chip size while using a single capacitor having a relatively large volume .

In addition, since the interval between the upper surface electrodes of the varistor substrate is made smaller than the interval between the lower surface electrodes, electrostatic discharge can be performed through the space between the upper surface electrodes, so that a discharging path of static electricity is added, Can be improved.

1 is a cross-sectional view of an electrostatic discharge protection device according to an embodiment of the present invention,
FIG. 2 is an exploded perspective view showing a state where the molding part is removed in FIG. 1,
3 is a cross-sectional view showing a relationship between a distance between upper surface electrodes and an interval between lower surface electrodes of a substrate in an electrostatic discharge protection element according to an embodiment of the present invention,
4 is a cross-sectional view illustrating an example of a varistor substrate in an electrostatic protection device according to an embodiment of the present invention.
5 is a sectional view showing another example of a varistor substrate in an electrostatic protection device according to an embodiment of the present invention,
6 is a cross-sectional view of an MLCC in an electrostatic protection device according to an embodiment of the present invention,
7 is a cross-sectional view illustrating an electrostatic discharge protection device according to an embodiment of the present invention,
8 is a flowchart illustrating a method of manufacturing an electrostatic protection device according to an embodiment of the present invention.
9 to 12 are cross-sectional views illustrating respective steps of a method of manufacturing an electrostatic discharge protection device according to an embodiment of the present invention,
13 is a graph showing the temperature change rate of the varistor and the dielectric.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art to which the present invention pertains. The present invention may be embodied in many different forms and is not limited to the embodiments described herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and the same reference numerals are assigned to the same or similar components throughout the specification.

The electrostatic protection device 100 according to an embodiment of the present invention includes a varistor substrate 110, a capacitor 120, and a molding part 130, as shown in FIGS. 1, 4 and 7.

4, the varistor substrate 110 includes a pair of bottom electrodes 111a and 111b, a pair of top electrodes 112a and 112b, a pair of internal electrodes 113a and 113b, And the connecting portions 114a and 114b of the connecting portions 114a and 114b.

The pair of bottom electrodes 111a and 111b are for mounting the electrostatic protection device 100 on the circuit board and may be formed on both sides of the bottom surface of the varistor substrate 110. [

The pair of top electrodes 112a and 112b are connected to the capacitor 120 in parallel and may be formed on both sides of the top surface of the varistor substrate 110. [ At this time, as shown in FIG. 2, a space 101 may be formed between the pair of top electrodes 112a and 112b. This space 101 can form a discharge path of electrostatic discharge (ESD) through the pair of top electrodes 112a and 112b.

That is, the electrostatic discharge can be performed through the space 101 between the pair of the top electrodes 112a and 112b, so that the discharge path of the static electricity is added separately from the pair of the internal electrodes 113a and 113b of the varistor substrate 110 The resistance to static electricity can be further improved.

3, the interval a between the pair of top electrodes 112a and 112b may be smaller than the interval b between the pair of the bottom electrodes 111a and 111b. Thus, the static electricity flowing from the outside can be discharged only through the pair of top electrodes 112a and 112b before being discharged through the pair of bottom electrodes 111a and 111b.

The pair of inner electrodes 113a and 113b may be spaced apart from each other at regular intervals on the same plane.

Since the electrostatic protection device 100 includes a separate single-component capacitor 120, it is not necessary to implement the capacitance by the varistor substrate 110. Moreover, since the varistor substrate 110 has a high temperature change rate, If the capacitance is formed in the inside, the capacitance is changed depending on the temperature, which adversely affects the capacitance of the entire package. Therefore, it is preferable to dispose the electrode on the same plane by eliminating the lamination structure which forms the capacitance as much as possible.

Thus, the thickness of the varistor substrate 110 can be reduced. Therefore, even when the capacitor 120 is stacked, it is easy to prevent an increase in the total thickness of the electrostatic protection device 100 and standardize it to a constant chip size.

That is, as the varistor substrate 110 is made thinner, a space for forming a capacitance within a chip size of a certain size relatively increases, so that a sufficient space can be secured and a capacitance of a high capacity can be easily realized. It is possible to regularize the entire chip size while using the large single-part capacitor 120. [

The pair of inner electrodes 113a and 113b may be connected to a pair of upper electrodes 112a and 112b and a pair of lower electrodes 111a and 111b through a pair of connection portions 114a and 114b. That is, one internal electrode 113a is connected to the top electrode 112a and the bottom electrode 111a through the connecting portion 114a, and the other internal electrode 113b is connected to the top electrode 112b And the lower electrode 111b, respectively.

The pair of connection portions 114a and 114b may be conductive vias 114a and 114b formed through the varistor substrate 110. [ Here, the pair of conductive vias 114a and 114b may be filled with a conductive material after forming a through hole passing through the varistor substrate 110. [ The varistor substrate 110 may be connected in parallel with the capacitor 120 by the pair of conductive vias 114a and 114b.

Here, since the pair of conductive vias 114a and 114b are formed inside the varistor substrate 110, the distance d1 between the pair of internal electrodes 113a and 113b is reduced and the capacity thereof is limited In order to overcome this, a pair of side electrodes 114a 'and 114b' may be provided on both sides of the varistor substrate 110.

4, the distance d1 between the pair of internal electrodes 113a and 113b is limited to between the pair of conductive vias 114a and 114b, so that the size of the breakdown voltage Vbr is limited do.

In order to increase the magnitude of the breakdown voltage Vbr, as shown in FIG. 5, the varistor substrate 110 'may be formed on both sides of the varistor substrate 110'. That is, the pair of connection portions may be a pair of side electrodes 114a 'and 114b'.

Here, the pair of side electrodes 114a 'and 114b' may be formed by drilling or punching a part of the side surface of the varistor substrate 110 to form hemispherical grooves, applying a conductive material to the surface of the formed groove, .

At this time, since the interval d2 between the pair of internal electrodes 113a and 113b connected to the pair of side electrodes 114a 'and 114b' increases in comparison with that in Fig. 4, the breakdown voltage Vbr is increased .

The varistor substrate 110 is made of a varistor material, for example, a semiconductive material containing at least one of ZnO, SrTiO ₃ , BaTiO ₃ , and SiC, or a Pr and Bi-based material. . Here, the varistor substrate 110 may be formed such that the interval d1 between the pair of internal electrodes 122a and 122b and the diameter of the varistor material satisfy the breakdown voltage Vbr.

The capacitor 120 is stacked on the pair of top electrodes 112a and 112b of the varistor substrate 110 so as to be connected in parallel with the varistor substrate 110. [ This capacitor 120 is made up of a single part.

For example, the capacitor 120 may be a multilayer ceramic capacitor (MLCC) of the COG type. Here, the COG characteristic satisfies a temperature coefficient of 0 ± 30 ppm / ° C. within the operating temperature range of -55 to 125 ° C., as specified by EIA (Electrical Industries Association). Therefore, since the COG type capacitor 120 has a very small temperature change rate, it is possible to provide a temperature compensation function for the varistor substrate 110 having a large temperature change rate.

That is, since the varistor substrate 110 has a large rate of change in temperature due to the characteristics of the material, when the temperature of the varistor substrate 110 changes frequently due to the use thereof, the varistor substrate 110 may affect other components. It is possible to compensate for the characteristic deterioration due to the temperature change of the varistor substrate 110.

On the other hand, when the temperature change rate of the varistor material and the dielectric material is compared (see FIG. 13), it can be seen that the dielectric material has a temperature change rate of less than 1% over the entire temperature range, . Particularly, since the varistor material may have a rate of change of 5% or more, it is difficult to realize the capacitance within the error range when the capacitance value should be controlled within 5% due to the signal characteristics. Therefore, the capacitance is implemented by using the dielectric desirable.

At this time, it is difficult to provide linear ESD protection if the dielectric alone implements the ESD protection function.

Therefore, the ESD protection device 100 according to an embodiment of the present invention provides an ESD function and improves the temperature characteristic. In order to standardize the ESD protection function, the ESD protection function is implemented as a varistor material. .

By using the COG type MLCC, the temperature characteristics of the substrate 210 such as a varistor having a high rate of temperature change can be compensated for, and the temperature characteristics of the entire package can be stabilized, so that the reliability of the product can be improved.

In addition, by using the MLCCs manufactured using various existing capacities, the degree of freedom in designing the capacitors is increased, so that a lineup of various capacities can be performed without any process change, so that the MLCC can quickly respond to the demands of customers.

As an example, the capacitor 120 may include a pair of external electrodes 121a and 121b and a plurality of capacitor electrodes 122a and 122b, as shown in FIG.

A pair of external electrodes 121a and 121b are provided on both sides of the capacitor 120 and can be coupled to a pair of top electrodes 112a and 112b of the varistor substrate 110 through soldering.

A plurality of capacitor electrodes 122a and 122b may be formed on the plurality of sheet layers 120a, respectively.

Such a capacitor 120 may be a stack of a plurality of sheet layers 120a (see FIG. 6). Here, each of the plurality of sheet layers may be made of an insulator having a dielectric constant, and may be made of a ceramic material. In one example, the ceramic material comprises Er ₂ O _3, Dy ₂ O _3, Ho ₂ O _3, V ₂ O _5, CoO, MoO _3, SnO _2, BaTiO _3, and Nd ₂ O ₃ or more of the selected one kinds Based oxide compound.

Such a capacitor 120 may be laminated in a flip chip form on a pair of top electrodes 112a and 112b of the varistor substrate 110. [ At this time, the capacitor 120 may be laminated to the varistor substrate 110 by soldering.

On the other hand, in order to improve the discharge function by the space 101 between the pair of top electrodes 112a and 112b, a space (not shown) formed by the lower surfaces of the pair of top electrodes 112a and 112b and the capacitor 120 101 may be partially or entirely filled with a discharge material.

Here, the discharge material has a low dielectric constant, no conductivity, and no short circuit when an overvoltage is applied. To this end, the discharge material may be made of a nonconductive material including metal particles, and may be made of a semiconductor material including SiC or a silicon-based material.

The molding part 130 molds the varistor substrate 110 and the capacitor 120 by a molding member. That is, the molding part 130 is molded so as to cover the upper surface of the varistor substrate 110 and the capacitor 120. In one example, the molding member may be made of epoxy. Here, the molding part 130 may be formed by curing the epoxy film.

The varistor substrate 110 and the capacitor 120 are molded by the molding unit 130 and then packaged into a single package to protect the varistor substrate 110 and the capacitor 120 and to protect the varistor substrate 110 and the capacitor 120, The entire chip size can be uniformly standardized. As a result, the pick-up performance can be improved in the manufacturing process, so that no extra effort is required for picking up the electrostatic protection element 100, and the manufacturing efficiency can be further improved.

As described above, since the varistor substrate 110 and the capacitor 120 are formed into a single package, the varistor substrate 110 and the capacitor 120 can be independently provided without being affected by different materials, And the capacity of the capacitance is simultaneously improved, so that the reliability of the product can be improved.

In particular, by using a single component MLCC, it is possible to easily implement various capacitances by using MLCCs of various capacities manufactured in the related art, so that it is possible to construct lineups of various capacities without changing the additional process, .

Such an electrostatic protection device 100 may be arranged in a portable electronic device to electrically connect a circuit such as a conductor, such as an external metal case. At this time, the electrostatic protection device 100 is directly connected to the ground of the circuit part, and the static electricity introduced can be bypassed to the ground without transmitting the static electricity to the circuit part.

Alternatively, if the electrostatic protection element 100 is not directly connected to the ground of the circuitry, i. E., Only electrically connects the conductor and circuitry to pass static electricity, the portable electronic device may be configured to bypass static electricity to ground A separate protection element may be provided. Such a shelter may be a surgeon or a varistor.

Here, the portable electronic device may be in the form of a portable electronic device that is portable and portable. For example, the portable electronic device may be a portable terminal such as a smart phone, a cellular phone, and the like, and may be a smart watch, a digital camera, a DMB, an electronic book, a netbook, a tablet PC, Such electronic devices may comprise any suitable electronic components including antenna structures for communication with external devices. In addition, it may be a device using local area network communication such as WiFi and Bluetooth.

In this case, the conductor may include a tip portion protruding outward from the conductive case. In one example, the conductor may include a side key. The distal end portion may include one end of a connector insertion port into which a connector, for example, an earphone, a charging cable, a data cable, or the like, is inserted.

That is, the electrostatic discharge protection device 100 according to the embodiment of the present invention has a resistance against electrostatic discharge (ESD), temperature (temperature) when connecting an outwardly protruding portion or a sharp- Characteristics, and capacitance can be improved at the same time.

Hereinafter, a method of manufacturing an electrostatic discharge protection device according to an embodiment of the present invention will be described with reference to FIGS.

8, a method 800 of manufacturing an electrostatic protection device according to the present invention includes forming an inner / outer electrode on a varistor substrate 110 (S810), stacking a capacitor 120 on a varistor substrate 110 Steps S820, S830 and S840, and a step S850 of cutting into a unit device.

9, a large area varistor substrate 110a is provided with a pair of lower electrodes 111a and 111b, a pair of upper electrodes 112a and 112b, A pair of internal electrodes 113a and 113b, and a pair of connection portions 114a and 114b connecting the pair of electrodes are formed (Step S810).

Here, in the large area varistor substrate 110a, a pair of the internal electrodes 113a and 113b may be spaced apart from each other at regular intervals on the same plane.

At this time, a pair of lower electrodes 111a and 111b are formed on the lower surface of the large-area varistor substrate 110a such that a gap between the pair of upper electrodes 112a and 112b is smaller than a gap between the pair of lower electrodes 111a and 111b. And a pair of top electrodes 112a and 112b may be formed on the top surface of the large area varistor substrate 110a.

Here, the pair of connection portions 114a and 114b may be a conductive via or a side electrode. At this time, the pair of conductive vias 114a and 114b may be formed by forming a through-hole in the unit area of the large-area varistor substrate 110a and filling the through-hole with a conductive material.

The pair of side electrodes 114a 'and 114b' may be formed by forming a through hole on the boundary surface of the unit area in the large-area varistor substrate 110a, that is, on the cut surface c and then filling the through hole with a conductive material And may be formed by applying a conductive material to the inner wall of the through hole.

Next, as shown in FIG. 10, the capacitors 120 are soldered to the pair of top electrodes 112a and 112b in a flip-chip manner and laminated (step S820). Here, the capacitor 120 may be a COG type MLCC as a single component, or it may be a pre-fabricated or existing product.

At this time, the pair of external electrodes 121a and 121b of the capacitor 120 may be laminated to be coupled to the pair of top electrodes 112a and 112b of the large area varistor substrate 110a. Thus, the capacitors 120 can be connected in parallel with the varistor substrate 110 for each unit area of the large area varistor substrate 110a.

Next, as shown in Fig. 11, the molding film 130a is disposed on the upper surface of the large-area varistor substrate 110a and on the upper side of the capacitor 120 (step S830). At this time, the molding film 130a may be a large-area film having the same size as that of the large-area varistor substrate 110a. Here, the molding film 130a may be an epoxy film.

In this state, the epoxy film 130a may be thermally fused to cover the upper surface of the large-area varistor substrate 110a and the capacitor 120 (step S840). At this time, the epoxy film 130a is melted and the upper surface of the large-area varistor substrate 110a and the capacitor 120 can be epoxy molded, as shown in FIG.

As a result, mass production is easy, so that the raw materials to be discarded are reduced, thereby further reducing the manufacturing cost and contributing to the improvement of the environment.

After the molding is completed in this manner, the unit areas are cut along the boundary line c. Thereby, the electrostatic protection device 100 can be manufactured for each unit area. At this time, when the electrode is formed by the through hole at the boundary line c of the large area varistor substrate 110a, the pair of side electrodes 114a 'and 114b' may be exposed to the outside along the cut surface of the boundary line c have.

On the other hand, a discharge material may be formed in the space 101 in order to improve discharge characteristics for the space 101 between the pair of top electrodes 112a and 112b.

For example, as shown in FIG. 9, after the pair of top electrodes 112a and 112b are formed, the space 101 between the pair of top electrodes 112a and 112b may be filled with a discharge material.

Alternatively, after the capacitor 120 is laminated on the large-area varistor substrate 110a, as shown in Fig. 10, a space (not shown) formed by the lower surfaces of the pair of top electrodes 112a and 112b and the capacitor 120 101) can be filled with a discharge material.

Here, the discharge material has a low dielectric constant, no conductivity, and no short circuit when an overvoltage is applied. To this end, the discharge material may be made of a nonconductive material including metal particles, and may be made of a semiconductor material including SiC or a silicon-based material.

As described above, since the varistor substrate 110 and the capacitor 120 of a single component are separately provided and formed into a single package, the fabrication process can be simplified by using substantially the substrate forming process and the package process. Particularly, by using the capacitor 120 as a single part, it is possible to improve the manufacturing efficiency, reduce the manufacturing cost, and promptly respond to the demands of the customers, by facilitating the lineup according to various capacities required by the customer.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

100: electrostatic protection element 101: space
110, 110 ': Varistor substrate 110a: Large area varistor substrate
111a, 111b: lower electrode 112a, 112b: upper electrode
113a, 113b, 113a ', 113b': internal electrodes 114a, 114b: conductive vias
114a ', 114b': side electrode 120: capacitor
121a, 121b: external electrodes 122a, 122b: capacitor electrodes
130: a molding part 130a; Epoxy film

Claims (20)

A varistor substrate including a pair of bottom electrodes, a pair of top electrodes, a pair of inner electrodes, and a pair of connecting portions connecting each pair of electrodes;
A capacitor formed as a single component laminated on the top surface electrode of the varistor substrate to be connected in parallel with the varistor substrate; And
And an upper surface of the varistor substrate and a molding part for molding the capacitor. The method according to claim 1,
Wherein the pair of inner electrodes are spaced apart from each other at regular intervals on the same plane. The method according to claim 1,
Wherein the molding part is made of epoxy. The method according to claim 1,
Wherein the capacitor is laminated to the varistor substrate in the form of a flip chip. 5. The method of claim 4,
Wherein the capacitor is laminated to the varistor substrate by soldering. The method according to claim 1,
Wherein an interval (a) between the pair of upper surface electrodes is smaller than an interval (b) between the pair of lower surface electrodes. The method according to claim 1,
Wherein a space formed by the pair of upper surface electrodes and the lower surface of the capacitor is filled with a discharge material. 8. The method of claim 7,
Wherein the discharge material is made of a nonconductive material or a semiconductor material including metal particles. The method according to claim 1,
Wherein the pair of connection portions are conductive vias formed through the varistor substrate. The method according to claim 1,
Wherein the pair of connection portions are formed on both sides of the varistor substrate. The method according to claim 1,
The varistor substrate ZnO, SrTiO _3, BaTiO _3, semiconductive material, or Pr and electrostatic protection element consisting of one of a Bi-based material comprising at least one of SiC. The method according to claim 1,
Wherein the capacitor is a COG type MLCC. A conductor including a tip portion protruding outward from the conductive case;
Circuitry; And
A portable electronic device comprising the electrostatic protection element according to any one of claims 1 to 12 for electrically connecting the conductor to a circuit part. 14. The method of claim 13,
Wherein the conductor comprises a side key. 14. The method of claim 13,
Wherein the leading end includes one end of an insertion port of a connector for connection with an external device. Forming a pair of inner electrodes, a pair of top electrodes, a pair of bottom electrodes, and a pair of connection portions each of the pair of electrodes on a large area varistor substrate per unit area;
A step of soldering and laminating a capacitor made of a single part to the upper surface electrode in a flip chip form;
Molding an upper surface of the varistor substrate and the capacitor with an epoxy film; And
And cutting each of the unit areas. 17. The method of claim 16,
After the forming step,
Further comprising the step of filling a space between the pair of top electrodes with a discharge material. 17. The method of claim 16,
After said combining,
Further comprising the step of filling a space formed by the pair of upper electrodes and the lower surface of the capacitor with a discharge material. 17. The method of claim 16,
Wherein the molding step comprises curing the epoxy film by disposing the epoxy film on the varistor substrate and the capacitor. 17. The method of claim 16,
Wherein the forming step forms the upper surface electrode and the lower surface electrode such that an interval (a) between the pair of upper surface electrodes is smaller than an interval (b) between the pair of lower surface electrodes.

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