KR20180021281A - Memory module test system - Google Patents

Abstract

A memory module test system according to an embodiment of the present invention includes a mother board; a main module socket and a submodule socket disposed on the motherboard; and a controller for transmitting at least one data signal to the main module socket through one channel. The data signal includes a first bit group and a second bit group. The first bit group of the data signal is inputted to a memory module inserted in the main module socket. The second bit group of the data signal is transferred to the submodule socket through the main module socket and is inputted to the memory module inserted in the submodule socket. It is possible to test a plurality of memory modules simultaneously without affecting test speed and time.

Description

[0001] MEMORY MODULE TEST SYSTEM [0002]

The present invention relates to memory module testing, and more particularly to memory module testing systems.

Semiconductor chips can operate as a single product, but as applications diversify and capacities become highly integrated, various kinds of semiconductor chips are modularized into one. A typical example is a memory module formed by modularizing a plurality of memory chips into one.

It is necessary to test the memory module correctly to check whether the memory module is operating normally. There are two ways to test a memory module: using a memory test device and testing it directly on a system that uses a memory module.

An embodiment of the present invention is to provide a memory module test system capable of simultaneously testing a plurality of memory modules without affecting test speed and time.

A memory module test system according to an embodiment of the present invention includes a mother board; A main module socket and a submodule socket disposed on the motherboard; And a controller for transmitting at least one data signal to the main module socket through one channel. Wherein the data signal comprises a first bit group and a second bit group, the first bit group of the data signal is input to a memory module inserted in the main module socket, and the second bit group of the data signal is Module socket through the main module socket and input to the memory module inserted in the sub-module socket.

A memory module testing system according to an embodiment of the present invention includes: a first module socket into which a first memory module is inserted; A second module socket having a second memory module inserted therein and electrically and physically connected to the first module socket; And a controller for transmitting at least one N-bit data to the first module socket, wherein lower N / 2-bit data out of the N-bit data is input to the first memory module, / 2-bit data is input to the second memory module.

According to the present embodiment, since the number of memory modules that can be tested at one time increases, the productivity of the product can be improved.

In addition, according to the present embodiment, since the two memory modules per channel are tested and one memory module is tested per channel from the viewpoint of the controller, it is possible to prevent the controller from lowering the test speed and increasing the test time.

1 is a perspective view schematically illustrating a memory module test system according to an embodiment of the present invention.
2 is a cross-sectional view taken along the line AA 'in FIG.
3 is a perspective view showing the fastening structure of the memory module and the module socket.
4 is a view conceptually showing the connection relationship between the first main module socket of the first module socket set of FIG. 1 and the socket pins of the first submodule socket.
5 is a conceptual view illustrating a memory module testing process using a memory module test system according to an embodiment of the present invention.

Hereinafter, embodiments of the present technology will be described in more detail with reference to the accompanying drawings.

FIG. 1 is a perspective view schematically showing a memory module test system according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line AA 'of FIG. 1, and FIG. 3 is a view showing a fastening structure of a memory module and a module socket It is a perspective view.

The memory module test system 10 according to the present embodiment may include a motherboard 110, a module socket group 120, and a controller 130.

The motherboard 110 is basic and physical hardware that includes basic circuitry and components within a computer to set up an execution environment for the system, e.g., a computer, to maintain its information, to allow the computer to be stably driven, It facilitates data input / output between all devices of the computer.

In the present embodiment, the motherboard 110 is a motherboard for testing JEDEC standard DIMMs, which is a known matter, so a detailed description thereof will be omitted.

The module socket group 120 may be mounted on the motherboard 110. The module socket group 120 may include a first module socket set 121 and a second module socket set 123. Although the module socket group 120 is shown as including two sets of module sockets in FIGS. 1 and 2, the number of module socket sets included in the module socket group 120 is not particularly limited thereto.

The first module socket set 121 may include a first main module socket 121M and a first submodule socket 121S. The second module socket set 123 may include a second main module socket 123M and a second submodule socket 123S.

The first main module socket 121M, the first submodule socket 121S, the second main module socket 123M and the second submodule socket 123S are inserted into the memory module substrate (MMS, see FIG. 3) And may include a slot (S).

As shown in FIG. 3, a plurality of connector pins CP may be formed on at least one side of the memory module substrate (MMS) inserted into the slot S at equal intervals. The first main module socket 121M, the first sub module socket 121S, the second main module socket 123M and the second sub module socket 123S are disposed in the slot S, respectively, And a plurality of socket pins SP electrically connected to the connector pins CP of the MMS.

The memory modules MM inserted into the slots S of the first main module socket 121M, the first sub module socket 121S, the second main module socket 123M and the second sub module socket 123S May be electrically connected to the motherboard 110. [ The memory modules MM also receive the socket pins SP of the first main module socket 121M, the first sub module socket 121S, the second main module socket 123M and the second sub module socket 123S Commands, addresses, data, and the like from the controller 130 through the control unit 130. [

2, the first main module socket 121M and the first sub module socket 121S of the first module socket set 121 can be connected to the controller 130 through the first channel CH1 have. In addition, the second main module socket 123M and the second submodule socket 123S of the second module socket set 123 can be connected to the controller 130 through the second channel CH2.

For example, the controller 130 may include two channels: a first channel CH1 and a second channel CH2. The first main module socket 121M of the first module socket set 121 may be connected to the first channel CH1 and the second sub module socket 121S may be connected to the first main module socket 121M. The second main module socket 123M of the second module socket set 123 may be connected to the second channel CH2 and the second submodule socket 123S may be connected to the second main module socket 123M. have.

The first main module socket 121M and the first submodule socket 121S can be electrically and physically connected and the second main module socket 123M and the second submodule socket 123S can be electrically and physically connected have. This will be described later in detail with reference to FIG.

In general, a plurality of memory chips may be mounted on at least one side of the memory module MM, as shown in FIG. At this time, corresponding connector pins (CP) groups may be formed for each memory chip on at least one side of at least one side of the memory module substrate (MMS) as the number of memory chips. Each connector pin group (CP) may include a plurality of connector pins (CP). For example, each connector pin group CP may include at least one power pin, at least one command pin, at least one address pin, and a plurality of data pins.

The module sockets 121M, 121S, 123M, and 123S into which the memory module MM having the plurality of memory chips mounted therein are inserted into the plurality of sockets corresponding to each connector pin group of the memory module MM Pins (SP) groups. Each socket pin group SP may include at least one power pin, at least one command pin, at least one address pin, and a plurality of data pins.

4 is a view conceptually showing the connection relationship between the first main module socket 121M of the first module socket set 121 of FIG. 1 and the socket pins of the first submodule socket 121S. Although only the first module socket set 121 is shown in FIG. 4, the connection relationship of the socket pins of the second module socket set 123 may also be the same as that of the first module socket set 121.

For convenience of explanation, it is assumed that the first main module socket 121M and the first sub module socket 121S accommodate a test memory module on which one x8 memory chip is mounted, respectively. Also, the first main module socket 121M and the first sub module socket 121S are provided with socket pins each including N data pins, one command pin, one address pin, and one power supply pin I suppose. Here, N may be eight.

4, the socket pins of the first main module socket 121M and the socket pins of the first submodule socket 121S are connected to eight data pins DP0 to DP7 through which 8-bit data signals are input and output, respectively. , One command pin (CP), one address pin (AP), and one power pin (PP).

The data pins DP0 to DP7 of the first main module socket 121M are connected to the lower main data pin group LMDPG to which the lower L bits of the data signal are inputted and to the upper main data pin group UMDPG). The data pins DP0 to DP7 of the first sub module socket 121S are connected to the lower sub data pin group LSDPG to which the lower L bits of the data signal are inputted and to the upper sub data pins Group (USDPG). Here, L and U may be N / 2, respectively.

4, the lower 4 bits and the upper 4 bits of the data signal are input to the lower main data pin group LMDPG and the upper main data pin group UMDPG of the first main module socket 121M, respectively . Also, the lower 4 bits and the upper 4 bits of the data signal can be input to the lower sub data pin group (LSDPG) and the upper sub data pin group (USDPG) of the first submodule socket 121S, respectively.

The lower main data pin group LMDPG of the first main module socket 121M can be electrically and physically connected to the upper sub data pin group USDPG of the first submodule socket 121S. The upper main data pin group UMDPG of the first main module socket 121M can be electrically and physically connected to the lower sub data pin group LSDPG of the first sub module socket 121S.

For example, the first to fourth data pins DP0 to DP3 of the first main module socket 121M are connected to the fifth to eighth data pins DP4 to DP7 of the first submodule socket 121S, respectively, May be connected using a conductive line as shown in FIG. The fifth to eighth data pins DP4 to DP7 of the first main module socket 121M are connected to the first to fourth data pins DP0 to DP3 of the first submodule socket 121S by dotted lines And can be connected using a conductive line.

Accordingly, the lower 4 bits of the 8-bit data signal input from the controller 130 (see FIG. 5) to the data pins DP0 to DP7 of the first main module socket 121M are transmitted to the second submodule socket 121S Data is transferred to the upper sub data pin group (USDPG), and the upper 4 bits can be transferred to the lower sub data pin group (LSDPG) of the second sub module socket 121S.

The address pin AP of the first main module socket 121M, the command pin CP and the power supply pin PP are connected to the address pin AP of the first submodule socket 121S, the command pin CP ), And a power supply pin (PP), as indicated by a dotted line. Accordingly, the address signal, the command signal, and the power signal input from the controller 130 to the address pin AP, the command pin CP, and the power supply pin PP of the first main module socket 121M are respectively The command pin CP, and the power pin PP of the sub module socket 121S.

4, a main module socket and a submodule socket that accommodate a memory module on which one x8 memory chip is mounted have been described. However, the connection relationship of the socket pins described above may include a memory module having a plurality of x8 memory chips mounted therein The same applies to the main module socket and the submodule socket.

For example, if the first main module socket 121M and the first submodule socket 121S accommodate the memory module on which the eight x8 memory chips are mounted, the first main module socket 121M and the second submodule socket 121M, Each of the socket pins 121S may include eight socket pin groups. Each socket pin group includes eight data pins DP0 to DP7, a command pin CP, an address pin AP, and a power pin PP .

Each socket pin group of the first main module socket 121M may include a lower main data pin group LMDPG and an upper main data pin group UMDPG, May include a lower sub data pin group (LSDPG) and an upper sub data pin group (USDPG). That is, the first main module socket 121M may include first through eighth lower main data pin groups LMDPG and first through eighth upper main data pin groups UMDPG, The first to eighth lower sub data pin groups (LSDPGs) and the first to eighth upper sub data pin groups (USDPG).

The first to eighth lower main data pin groups LMDPG of the first main module socket 121M are connected to the first to eighth upper sub data pin groups USDPGs of the first submodule socket 121S, May be electrically and physically connected. The first to eighth upper main data pin groups UMDPG of the first main module socket 121M are connected to the first to eighth lower sub data pin groups LSDPGs of the first submodule socket 121S, May be electrically and physically connected. That is, upper data pins and lower data pins may be staggered for each socket group.

5 is a conceptual view illustrating a memory module testing process using a memory module test system according to an embodiment of the present invention. For convenience of explanation, it is assumed that a memory module with one x8 memory chip is tested.

In FIG. 5, the memory modules inserted in the first module socket set 121 and the second module socket set 123 are omitted for the sake of simplicity. In FIG. 5, the use of each signal, that is, data, address, command, power supply, etc., is indicated by the original color in the memory module. That is, if the circle is black, it indicates that the signal is used in the memory module, and if the circle is white, it indicates that the signal is not used in the memory module.

The first main module socket 121M and the first sub module socket 121S of the first module socket set 121 and the second main module socket 123M of the second module socket set 123, When the test memory module is inserted into the socket 123S, the controller 130 connects the first main module socket 121M and the second main module socket 123M through the first channel CH1 and the second channel CH2, As shown in FIG. The first main module socket 121M and the second main module socket 123M can transmit the transmitted power signal to the first sub module socket 121S and the second sub module socket 123S. Accordingly, power is supplied to the test memory modules inserted in the first main module socket 121M, the first sub module socket 121S, the second main module socket 123M, and the second sub module socket 123S .

When power is applied to the test memory modules, the operation of converting the I / O mode of each memory chip mounted in the test memory modules from x8 to x4 can be performed first. The operation of converting the I / O mode of the memory chip from x8 to x4 may be performed in the memory module test system according to the present embodiment, or may be performed by an externally input I / O mode conversion signal. Here, the external may mean an external device or a user.

Thus, as the I / O mode of each memory chip is converted from x8 to x4, four data pins among the data pins D0 to D7 of each memory chip, for example, data pins D4 to D7 ) May not be used in the test. In this embodiment, the upper 4-bit data pins D4 to D7 are not used. However, the present invention is not limited to this, and the lower 4-bit data pins D0 to D3 may be used Do.

The controller 130 transmits 8-bit data signals, address signals, and write signals to the first main module socket 121M and the second main module socket 123M through the first channel CH1 and the second channel CH2, Commands, and the like. At this time, the address signal and the write command transmitted to the first main module socket 121M and the second main module socket 123M can be simultaneously transmitted to the first submodule socket 121S and the second submodule socket 123S have.

However, since only the lower four data pins D0 to D3 among the data pins of the memory chips mounted on the memory modules inserted in the module sockets 121M, 121S, 123M, and 123S are used as described above, The signal of the upper 4 bits of the 8-bit data signal input to the main module socket 121M is input to the first sub module 121M, which is electrically and physically connected to the upper four data pins D4 to D7 of the first main module socket 121M, And can be input to the lower four data pins D0 to D3 of the socket 121S. Likewise, the upper 4-bit signal of the 8-bit data signal input to the second main module socket 123M is electrically and physically connected to the upper four data pins D4-D7 of the second main module socket 123M Module socket 123S to the lower four data pins D0 to D3 of the second submodule socket 123S.

That is, the 8-bit data signal transmitted to the first main module socket 121M by the controller 130 through the first channel CH1 is transmitted to the first main module socket 121M and the first sub module socket 121 121S in each memory chip mounted on the memory module inserted into the memory module. Similarly, an 8-bit data signal transmitted by the controller 130 to the second main module socket 123M through the second channel CH2 is transmitted to the second main module socket 123M and the second sub module socket 123S in the memory chip mounted on the memory module.

The controller 130 may then transmit a read command and an address signal to the first main module socket 121M and the second main module socket 123M respectively via the first channel CH1 and the second channel CH2 . At this time, the address signal and the read command transmitted to the first main module socket 121M and the second main module socket 123M can be simultaneously transmitted to the first submodule socket 121S and the second submodule socket 123S have.

The first main module socket 121M and the first submodule socket 121S respectively transmit the lower 4-bit data signal and the upper 4-bit data signal to the first channel CH1 corresponding to the read request of the controller 130, Lt; / RTI > Similarly, in response to the read request of the controller 130, the second main module socket 123M and the second submodule socket 123S respectively transmit the lower 4-bit data signal and the upper 4-bit data signal to the second channel CH1 To the controller 130 via the network.

The controller 130 controls the first main module socket 121M and the first sub module 121M based on the lower 4 bits of the 8-bit data signal and the upper 4 bits of the data signal transmitted through the first channel CH1, The memory modules inserted in the socket 121S can be tested. Similarly, the controller 130 selects the second main module socket 123M and the second main module socket 123M based on the lower 4-bit data signal and the upper 4-bit data signal of the 8-bit data signal transmitted through the second channel (CH2) It is possible to test the memory modules inserted in the sub module socket 123S.

As described above, when the test for each memory module is completed, the operation of converting the I / O mode of each memory chip mounted in each memory module from its original state, that is, from x4 to x8, can be performed.

The memory module test system according to the present embodiment increases the number of memory modules that can be tested at one time, thereby improving the productivity of the product.

In addition, since the memory module test system according to the present embodiment tests two memory modules per channel at the same time and tests one memory module per channel from the viewpoint of the controller 130, the test speed decreases and the test time increases .

Thus, those skilled in the art will appreciate that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

10: Memory module test system 110: Motherboard
120: Module socket group 121: First module socket set
121M: first main module socket 121S: first sub module socket
123: Second module socket set 123M: Second main module socket
123S: second sub module socket 130: controller

Claims (13)

Motherboard;
A main module socket and a submodule socket disposed on the motherboard; And
And a controller for transmitting at least one data signal to the main module socket through one channel,
Wherein the data signal comprises a first bit group and a second bit group,
The first bit group of the data signal is input to the memory module inserted in the main module socket and the second bit group of the data signal is transferred to the submodule socket through the main module socket, The memory module being inserted into the memory module. The method according to claim 1,
If the data signal is N bits,
Wherein the first group of bits comprises the lower N / 2 bits of the data signal and the second group of bits comprises the upper N / 2 bits of the data signal. 3. The method of claim 2,
The main module socket includes:
Lower main data pins into which the first bit group of the data signal is input; And
Wherein the second group of bits of the data signal comprises upper main data pins to which are input,
Module socket,
Lower sub data pins electrically and physically connected to the upper main data pins of the main module socket; And
And upper sub data pins electrically and physically connected to the lower main data pins of the main module socket
≪ / RTI > The method according to claim 1,
Wherein the first bit group of the data signal is written to at least one memory chip mounted on the memory module inserted in the main module socket,
Wherein the second group of bits of the data signal is written to at least one memory chip mounted on the memory module inserted in the submodule socket. 5. The method of claim 4,
When the controller transmits a read request signal to the main module socket through the channel,
Wherein the memory chip mounted on the memory module inserted in the main module socket transmits the first group of bits of the data signal to the controller via the channel,
Wherein the memory chip mounted on the memory module inserted in the submodule socket transmits the second group of bits of the data signal to the controller through the main module socket and the channel. 6. The method of claim 5,
The controller tests the memory module inserted in the main module socket and the memory module inserted in the submodule socket based on the first bit group and the second bit group of the data signal received via the channel Memory module test system. The method according to claim 1,
When the controller transmits a plurality of data signals to the main module socket,
The plurality of data signals each including a first bit group and a second bit group,
The first bit group of each data signal is input to the memory module inserted in the main module socket and the second bit group of each data signal is transferred to the submodule socket through the main module socket, A memory module test system that is inserted into a memory module inserted in a module socket. The method according to claim 1,
The controller sends at least one address and at least one command to the main module socket through the channel and the at least one address and the at least one command sent to the main module socket are sent to the submodule socket Simultaneously transferred memory module test system. A first module socket into which a first memory module is inserted;
A second module socket having a second memory module inserted therein and electrically and physically connected to the first module socket; And
And a controller for transmitting at least one N-bit data to the first module socket,
Wherein lower N / 2-bit data of the N-bit data is input to the first memory module, and upper N / 2-bit data of the N-bit data is input to the second memory module. 10. The method of claim 9,
A first memory chip mounted on the first memory module; And
And a second memory chip mounted on the second memory module. 11. The method of claim 10,
Wherein the first memory chip and the second memory chip each include N data pins. 12. The method of claim 11,
The lower N / 2 data pins of the N data pins of the first memory chip are in an active state, the upper N / 2 data pins are in an inactive state, and
Wherein the lower N / 2 data pins of the N data pins of the second memory chip are active and the upper N / 2 data pins are inactive. 13. The method of claim 12,
The lower N / 2 bit data is input to the lower N / 2 data pins of the first memory chip, and
And the upper N / 2 bit data is input to the lower N / 2 data pins of the second memory chip.

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