TWI446171B - Systems, methods, and apparatus with programmable memory control for heterogeneous main memory - Google Patents

Description

System, method and device for programmable memory control with heterogeneous main memory

This application is generally directed to a memory controller for controlling access to a memory module in the main memory.

A computing system can have a homogenous main memory having a type of memory, such as a dynamic random access memory (DRAM) integrated circuit (IC).

The DRAM IC retains data information by storing a specific amount of charge on one of the capacitors in each memory cell to store a logic one or alternatively a logic zero. Over time, and due to the read operation, the stored charge on the capacitor is dissipated in a process commonly referred to as leakage. To preserve the stored charge on a DRAM capacitor and thus maintain the DRAM's ability to retain its memory contents, the stored charge in the memory cell can be increased by a new cycle, which is sometimes performed periodically. The new cycle consumes power again and again.

In the following detailed description, examples of numerous specific embodiments are set forth. However, embodiments may include configurations that include fewer than all of the detailed features and combinations set forth in these examples.

Introduction

In some embodiments, a programmable memory controller is provided to control access to different types of memory modules in a main memory. The non-volatile memory module and the DRAM memory module can be used for the same memory channel, which implements the same memory channel specifications to form a heterogeneous main memory. In some embodiments, the programmable memory controller can be included in a commercially available processor or have a commercially available pin that can reside in a processor socket of a system. For example, the programmable memory controller can have one of the pins of a processor and be inserted into a pre-existing motherboard having a socket that can receive the processor.

Newer memory modules can have greater density and different electrical characteristics. Previously, to gain the benefits of an updated memory module design, a new computer or a new motherboard was purchased to accept a new type of memory module because the memory controller design was tightly coupled for access. The type of memory module. If a new memory module with a different technology is used in the design of a new system, a new hardware design for one of the new memory controllers is typically produced. Designing a new hardware design for a new memory controller may increase the time it takes to sell a new system. In addition to designing a new memory controller from the scratchpad, a programmable memory controller can be programmed to provide control and access to the functionality of the new memory module design and to speed up the sale of new systems.

Computer system with heterogeneous memory channels

Referring now to Figure 1A, a functional block diagram of a computer system 100A having a heterogeneous primary memory is illustrated. The computer system 100A includes a multi-processor motherboard 100A'. A plurality of processor sockets 101A to 101N mounted on the motherboard 100A'. Processors 122A through 122N can be plugged into such processor sockets. The processor sockets 101A-101N are connected to the interconnect fabric 103 via traces 102A-102N. The interconnect fabric 103 may be constructed solely of traces or it may include other integrated circuitry, but the function is to connect various processors, memories, and I/Os together within the motherboard 100A'. Portions of the interconnect fabric logic can be embedded within the processor and memory controller.

One or more programmable heterogeneous memory controllers 107A-107N additionally mounted to the motherboard 100A' are coupled to the interconnect fabric 103 via traces 106A-106N. The programmable heterogeneous memory controllers 107A to 107N control the respective memory channels of the memory channels 123A to 123N, respectively. The printed circuit board traces 110A-110N in the memory channels of the memory channels 123A-123N are coupled to the memory module sockets 108A-108N and the programmable-type heterogeneous memory controllers 107A-107N. between. The memory module sockets can have proprietary pins or can be any of the standard JEDEC pins (eg, DDR2, DDR3, or other memory specifications).

A plurality of different types of memory modules 109A to 109N are inserted into the sockets 108A to 108N of the heterogeneous memory channels. A heterogeneous memory channel is one in which a mixed type or a different type of memory module can be coupled to one of the memory channels of the same memory channel bus. A homogenous memory channel is a memory module in which the same type (eg, memory type (eg, DDR2 DRAM, etc.)) but may have different memory capacities can be coupled to one memory channel of the same memory channel bus. For example, different types of memory modules in a heterogeneous memory channel can be a dynamic random access memory dual in-line memory module (DRAM DIMM) and a non-volatile random access memory dual in-line memory module. (NVRAM DIMM). In some embodiments of the memory modules, different types of memory modules are designed to meet some or all of the DDR2 memory module specifications (or DDR3 or other memory specifications). In other embodiments of the memory module, the new memory module satisfies the DDR2 specification (or DDR3 or other memory specification) and reassigns an existing motherboard interconnect to include different control signals in the memory controller. Interfacing with the new memory modules. The programmable heterogeneous memory controller supports the use of different control signaling for various purposes. For example, new control signals for these new memory modules may increase memory capacity or signal additional device status information through pre-existing channel traces.

The programmable heterogeneous memory controller arbitrates and controls access to the memory channel bus by different types of memory modules. The programmable memory controller can also arbitrate and control access to data busses on internal DIMMs that are connected to integrated circuits within a particular memory module via additional control signaling. For example, a non-volatile memory volume circuit stacked after supporting a wafer may have both a bus bar on the internal DIMM and a memory channel bus that is arbitrated and controlled by the programmable heterogeneous memory controller. access. The programmable heterogeneous memory controller can control a bus multiplexer in each of the support wafers of the DIMM support chips via an additional control signal to allow the memory channel to be selected by selecting a non-volatile memory volume circuit Access to the bus. In this way, the non-volatile memory module can have a larger memory capacity. Typical main memory designs limit the number of DIMMs in a memory channel to a small number due to data skew and other timing considerations. The programmable heterogeneous memory controller allows for additional control signaling so that a memory module and thus an addressable memory capacity within a memory channel can be substantially increased.

The programmable heterogeneous memory controller can be automatically acted upon by a processor. For example, the programmable heterogeneous memory controller can cause all of the memory coupled to the memory module sockets to be visible to the processor system in the system or to use some attached memory as a The memory is cached to improve the overall performance of the memory system. In this case, a faster type of memory module can be selected by the memory controller to be used as a level of a cache memory. In addition, the programmable heterogeneous memory controller can reinterpret the address and read/write commands from a processor as it deems appropriate. This allows, for example, the programmable heterogeneous memory controller to read from an address space containing a memory module while simultaneously performing a write or erase operation within the same module.

One or more I/O subsystems 105A-105N additionally mounted to the motherboard 100A are connected to the interconnect fabric 103 via traces 104A-104N. Alternatively or in combination, one or more I/O subsystems 105' may be mounted to the motherboard 100A and coupled to the programmable heterogeneous memory controllers 107A-107N (or a system controller) to provide Access to the I/O device by the processors.

In FIG. 1A, the memory controllers 107A through 107N are directly coupled to the sockets 108A through 108N in each of the memory channels 123A through 123N by the PCB traces 110A through 110N. However, the memory controller can also be indirectly coupled to the sockets 108A-108N in each memory channel through the secondary memory controller.

Referring now to Figure 2, an alternative multiprocessor system 200 and motherboard 200' are illustrated. In Figure 2, the programmable heterogeneous memory controller can be used to plug into an externally programmable heterogeneous memory controller 212 of an outlet or it can be integrated with a programmable heterogeneous memory control The device 212' is co-packaged in the processor package as part of a processor 211. The processor 211 includes the integrated programmable heterogeneous memory controller 212'. That is, the processor package 211 includes both the processor component and the integrated programmable heterogeneous memory controller 212'. One or more programmable heterogeneous memory controllers may be present within a processor package.

The externally programmable heterogeneous memory controller 212 can be inserted into a processor socket 112B. Inserting the externally programmable heterogeneous memory controller 212 into an open processor socket allows for expansion and upgrade of a pre-existing memory channel to support heterogeneous main memory having a different type of memory module.

In the multiprocessor system 200, the processor sockets 112A-112N are connected to the interconnect fabric 103 via traces 116A-116N of the motherboard 200'. The processor sockets 112A-112N are also connected to the memory channels 113A-113N and 213A-213N via traces 125A-125N. The memory channels 113A-113N are homogenous memory channels for controlling access to the DRAM memory modules 114A-114N inserted into the sockets 115A-115N. The memory channels 213A through 213N are heterogeneous memory channels for controlling access to different or mixed types of memory modules 214A through 214N within each channel, such as insertable into the sockets 115A through 115N. DRAM memory modules and non-volatile memory modules.

In FIG. 2, the main memory 150' may include homogenous memory channels 113A-113N and heterogeneous memory channels 213A-213N, which may be controlled by the heterogeneous memory controllers 212, 212'. Alternatively, a homogenous memory controller 221 can be used to control access to the homogenous memory channels 113A-113N in the main memory. The homogenous memory controller 221 can be packaged with a processor 231 and inserted into a socket 112A.

One or more expansion connectors may also be used to upgrade the systems 100A, 200 to make more memory capacity available and/or reduce power consumption in the main memory of the computer system.

In some embodiments, one or more expansion connectors or slots 121A-121N can be used to upgrade and expand the main memory of the motherboard 100A', 200'. A daughter card or expansion board (not shown) can be used to upgrade the main memory in these computer systems. The daughter card or expansion board then includes a programmable heterogeneous memory controller for controlling access to mixed or different types of memory modules in each channel. In this alternative, the main memory in the computer system can be expanded into one of the heterogeneous main memories of the different types of memory volume circuits.

In FIG. 2, the externally programmable heterogeneous memory controller 212, the processor 211 having the internal programmable heterogeneous memory controller 212', and the memory modules are inserted into the socket for coupling to The motherboard of the system. The programmable heterogeneous memory controller (PHMC) and the memory module (MM) can be coupled to the motherboard of the system in other ways.

Referring now to Figure 3, the memory controllers and the memory modules are coupled to a motherboard 301 of a computer system 300 without the need for a socket, such as by soldering the wafer directly thereto. The computer system 300 includes a motherboard 301 having processors 122A through 122N, a memory controller (programmable heterogeneous memory controllers 107A through 107N, a DRAM memory controller 117D, a non-volatile memory controller) 117NV), support chips 403A to 403N, dynamic random access memory (DRAM) integrated circuits 314A to 314N, static random access memory (SRAM) integrated circuits 315A to 315N, and non-volatile memory volume circuit 402A to The 402N is directly coupled to it without the need for a socket, such as by soldering.

The processors 122A-122N are coupled to the memory controllers (programmable heterogeneous memory controllers 107A-107N, DRAM memory controller 117D, non-volatile memory controller 117NV) to the interconnect The fabrics 103 communicate with each other. Alternatively, one or more memory controllers of the memory controllers may be integrated into the processors to communicate with one another as shown in FIG. Input/output wafers 105A-105N may also be soldered to the motherboard and coupled to the interconnect fabric 103.

The programmable heterogeneous memory controllers 107A-107N are coupled to the memory channel busbars 110 to different types of memory chips (SRAMs 315A-315N, DRAMs 114A-114N) in the heterogeneous memory channels. , NVRAM 402A to 402N) communication. The DRAM memory controller (DMC) 117D is coupled to the memory channel busbar 110' for communication with DRAM type memory chips 314A through 314N in the homogenous memory channel. The non-volatile random access memory controller (NVMC) 117NV is coupled to the memory channel bus 110" to communicate with NVRAM type memory chips 402A-402N in a homogenous memory channel. A plurality of support wafers 403A through 403N are coupled to the individual memory chips and individual memory channel busbars 110, 110' and 110" to provide load isolation. In this context, the support wafers may also be referred to as bridge wafers.

Memory module

Referring now to Figure 4A, a diagram of a non-DRAM type memory module 214 (e.g., a non-volatile memory module) is illustrated. The non-DRAM type memory module 214 can be inserted into the memory module socket 108A of one or more of the heterogeneous memory channels 123A to 123N, 213A to 213N of the system 100A, 200 illustrated in FIGS. 1A and 2, respectively. 108N, 115A to 115N.

A given memory module can have different memory types (SRAM, DRAM or non-volatile memory) and logic or other circuitry on its printed circuit board. Alternatively, a given memory module can have a homogenous type of memory and can include logic or other types of circuitry.

In some embodiments, the non-DRAM type memory module 214 is a non-volatile type of memory module. The non-volatile type of memory module can include at least one NOR gate flash lightning erasable programmable read only memory (EEPROM) integrated circuit in accordance with certain embodiments. In one configuration, the read and write accesses to a non-volatile memory volume circuit are asymmetric. In this case, writing one of the non-volatile memory volume circuits takes more time than reading from one of the non-volatile memory volume circuits. A memory erase operation in a non-volatile memory volume circuit also takes more time than a read access. Certain types of non-volatile memory volume circuits (eg, NOR flash EEPROM integrated circuits) may be configured such that the read access time may be reduced enough for one of the address locations to be presented and the data system returned The level in the main memory. In one configuration, to address the asymmetry between read and write performance, a data communication protocol for erasing and writing data to a non-volatile memory module can be used, where the instruction packet is written. The device then instructs the device to program or erase a large amount of data in the volatile memory.

In FIG. 4A, the non-DRAM type memory module 214 includes a printed circuit board (PCB) 400 having a contact 401 of the edge connector formed thereon (on each side for a DIMM), plural The non-DRAM memory chips 402A to 402N and the plurality of support wafers 403A to 403N. The printed circuit board (PCB) 400 has a low profile memory module form factor (e.g., 30 millimeters (mm) high or higher and approximately 133 mm wide) that is inserted into the socket without occupying more space.

The memory module 214 further includes a plurality of printed circuit board traces (eg, printed leads) 404A-404N and 406A-406L formed on the PCB 400, and the non-DRAM memory chips 402A-402N and the The support wafers 403A to 403N are coupled between the support wafers 403A to 403N and the contacts 401 of the edge connectors. The printed circuit board traces (e.g., printed conductors) 404A through 404N form an internal memory module bus 404 through which the non-DRAM memory chips 402A through 402N can compete for Access to the memory channel bus. The printed circuit board traces (e.g., printed conductors) 406A through 406L (collectively by reference numeral 406) are coupled to the memory channel busbar by contacts 401 of the edge connectors.

At least one of the plurality of support wafers 403A-403N can include one of memory module identifications (MMIDs) 410 that can be stored to provide identification of one of the types of memory modules and for mounting on the PCB 400. The information of the volume bodies circuits 402A to 402N. The plurality of signal lines form a communication port 412 through which the memory module identification (MMID) 410 can be communicated from each memory module to the programmable heterogeneous memory controllers 107, 212, 212'. The support chip having the memory module identification further includes an input/output port 411 coupled to the communication port 412 for transmitting and receiving information through the port 412. If only a few signal lines are available, the communication port 412 can be a serial communication and the I/O port 411 is a serial I/O port that uses serial data for bidirectional communication of information. . The MMID 410 can be polled by a programmable heterogeneous memory controller during initialization to determine the different types of memory modules that can be inserted into each socket. The MMID 410 can be communicated by one of the standards defined by a JEDEC standard or by some other institution.

In some embodiments, the memory module 214 is a dual in-line memory module (DIMM) and the printed circuit board (PCB) 400 has contacts on the front and rear sides of the integrated circuit and the edge connector. One of the DIMM PCBs. The DIMMs can include memory that does not have a deterministic access time. Thus, the DIMMs can signal to the programmable heterogeneous memory controller that it has data available for consumption or ready to receive data. The programmable heterogeneous memory controller can be programmed if a particular DIMM socket has one of the DDR, DDR2 or DDR3 DIMM pins of a particular JEDEC standard type and not one of the DIMMs is plugged into the particular socket It itself re-uses the existing pins of the DIMM socket in a suitable manner to control the type of DIMM inserted into the socket.

In some embodiments, the memory module 214 is a non-volatile memory module of the non-DRAM memory chips 402A-402N, such as a non-volatile memory volume circuit chip, such as NOR. Flash EEPROM integrated circuit chip. The non-volatile memory can be mapped in the same address space as the main memory and can be expected to be slightly slower than the main memory when reading.

Non-volatile memory volume circuit chips typically have an asymmetry between read and write accesses. Due to the nature of a write operation to a non-volatile memory cell, the read access time is typically much less than the write access time. In addition, read accesses can randomly read any location in some non-volatile memory volume circuits. However, write access tends to be block or sector oriented, again due to the nature of the non-volatile memory cells that occur within the non-volatile memory volume circuit due to a write operation. Thus, some non-volatile memory volume circuits can be viewed as randomly reading locations as the same random access memory but as if written to the same hard drive. These longer delays cause the stylized and erase access to the non-volatile memory module to become a non-deterministic event. That is, it may not be known in advance how long it will take for a non-volatile memory module to complete a write operation or an erase operation.

To attempt and mitigate some of the asymmetry with the write operations, each of the non-volatile memory volume circuits 402A-402N can include a write buffer 425 in which a plurality of write operations are stored for appropriate The time is written into one of the sections of the memory unit. The write buffer 425 may store one or more data words before writing the data into the non-volatile memory units, and a data communication protocol may be used to indicate that the non-volatile memory volume circuit is to be Where is the material written?

The programmable heterogeneous memory controller can use one or more DRAM memory modules as cache memory for the non-volatile memory to improve system performance. In this case, the programmable heterogeneous memory controller can include a cache memory controller.

Additionally, the non-volatile memory cells can be organized into memories 426A through 426D of a plurality of non-volatile memory cells. In each memory volume circuit, the memories of the memory banks can be further organized into segments of non-volatile memory cells that provide a predetermined memory capacity. When a write access or write operation is to be used to write to a memory bank, other memory banks can be read by a read access or read operation. An erase operation for erasing a segment of the memory in the non-volatile memory volume circuit can also be performed on one of the sections of the memory while other memories can be accessed or read by a read The operation is read.

Each of the non-volatile memory volume circuits 402A-402N can further include a status register 427 that can be polled by the memory controller to read the status of each memory bank, such as busy writing Mode or a erase mode. In addition, the serial communication port 412 can be used to bidirectionally communicate information, such as status, between the memory controller and the memory modules. The one or more support chips 403A through 403N coupled to the serial communication port can include a register 415 for storing status information regarding the operation of the memory volume circuits 402A through 402N through the communication port 412. Poll (request) and communicate to the memory controller.

Additionally, a feedback control signal (eg, status signal 611F in FIG. 6A) can be communicated from the non-volatile memory module to the memory controller to mitigate write operations to the non-volatile memory modules. Non-deterministic nature. Using the feedback control signal, the memory controller can avoid polling the memory module repeatedly to determine when the memory module completes an operation. One of the one or more support wafers 403A through 403N can receive status information from the memory volume circuits 402A through 402N and generate a status signal 611F that can be communicated to the memory controller via the memory channel bus.

The data strobe signal for accessing the DRAM memory module can be changed to a feedback control signal, which can be communicated from a non-volatile memory module to the memory controller to mitigate the non-volatile memory The non-deterministic nature of the erase and write operations in the module. For example, in the exemplary embodiment illustrated in FIG. 14, when a non-volatile memory module is accessed in a memory module socket of a memory channel, the data strobe signals DQS13, DQS14, DQS15, and DQS16 are respectively Change to status signal RY/BY_N_R1D0, RY/BY_N_R1D1, RY/BY_N_R1D2, RY/BY_N_R1D3. The data strobe signals DQS13, DQS14, DQS15, and DQS16 are used for timing data output from each memory module in a DRAM memory channel. The RY/BY_N_R1D0, RY/BY_N_R1D1, RY/BY_N_R1D2, RY/BY_N_R1D3 signals are status signals for the first rank memory of each DIMM module/socket of the four DIMM modules/sockets in the memory channel. . These status signals are fed back and coupled to the heterogeneous memory controller for more efficient access to the non-volatile memory module. Each status signal indicates whether a rank of the memory in a memory module is busy or prepares another write or erase access to mitigate the non-determination of the erase and write operations on the non-volatile memory module. nature.

Although the non-volatile memory volume circuits may be accessed more slowly than the DRAM, the high data bandwidth can be achieved by the parallel access of a plurality of non-volatile memory volume circuits through the memory channel bus. The relatively low average power consumption of the non-volatile memory volume circuitry allows a larger number to be mounted on a DIMM printed circuit board to achieve greater memory capacity within the same power budget. The programmable heterogeneous memory controller allows a plurality of non-volatile memory volume circuits to be accessed side by side through a memory channel bus in a manner transparent to a processor.

It should be noted that the non-DRAM memory chips 402A-402N may also be other types of non-DRAM type memory volume circuit chips, such as static random access memory volume circuits.

A plurality of support wafers 403A through 403N can be used to buffer the address and/or multiplexed and multiplexed data from and to the non-DRAM memory chips 402A through 402N. Herein, the plurality of support wafers 403A to 403N may also be referred to as a plurality of buffer integrated circuits 403.

The support integrated circuit chip supports (ie, facilitates) reading and writing data of the memory volume circuit stacked in the memory module with different ranks and memory banks by the heterogeneous memory controller. take. In some embodiments, the non-volatile memory volume circuitry is stacked in a single multi-chip package that is subsequently attached to the non-volatile memory module.

Each of the support wafers 403A through 403N may include a plurality of pairs of bus multiplexers 422 and a one-to-many bus multiplexer 424. Alternatively, the many-to-one bus multiplexer 422 and the one-to-many bus demultiplexer 424 may be integrated as a crossbar switch.

The many-to-one bus multiplexer 422 is configured to pass certain printed circuit traces from the plurality of busbars coupled to the memory volume circuits 402A-402N through the printed circuit board traces 406A-406L. The data of lines 404A through 404N is written to the memory channel bus. The many-to-one bus multiplexer 422 allows a large amount of data to be accessed in parallel and then transmitted to the memory controller in a burst cycle. The one-to-many bus multiplexer 424 can be used on a burst cycle to receive data from the memory channel bus through the printed circuit board traces 406A-406L and then drive the data to be coupled by coupling To one of the plurality of data busses formed by the printed circuit board traces 404A through 404N of the memory volume circuits 402A through 402N. A crossbar switch can also be used to provide read and write access to the memory volume circuits 402A-402N.

Due to load and timing considerations, the memory channel busbar can be limited relative to the number of integrated circuits that can be directly coupled thereto. The bus multiplex provided by the plurality of support wafers 403A to 403N on the memory module allows additional memory to be stacked behind the support wafer on each side of the DIMM to have such support The wafer has a larger memory capacity available. The use of the plurality of support wafers 403A through 403N avoids adding additional capacitive loading from the additional memory volume circuitry in the memory module to the memory channel bus. The programmable heterogeneous memory controller can control one or more of the plurality of support wafers and the bus multiplex on the memory channel bus to access the memory stacked behind the support wafers .

In addition, if a non-volatile memory module is inserted into the sockets, it can have a larger memory capacity with less average power consumption. Even if an additional memory volume circuit is installed in the memory module to increase the memory capacity, the average power consumption can be lower if a non-volatile memory volume circuit is used in the memory modules.

Referring now to Figure 4B, there is illustrated a JEDEC standard DRAM DIMM 434 for a DDR2 memory channel bus. The DRAM DIMM 434 includes a plurality of DRAM memory chips 436A through 436N that are mounted to the printed circuit board 434 and coupled directly to the contacts 440 of the edge connector. Thus, the DRAM memory chips 436A through 436N are more directly coupled to the memory channel bus. The memory capacity of the DRAM DIMM 434 can be limited by the amount of memory provided by the DRAM memory chips 436A through 436N coupled directly to the memory channel bus.

The DRAM memory chips 436A through 436N are designed to comply with the specifications of the memory channel bus, such as the DDR2 specification (or DDR3 or other memory specifications). Each memory chip 436A-436N has an address/control and data line that is directly coupled to the edge connector 440.

The DRAM DIMM 434 does not include any further support wafers to multiplex data signals onto and away from the memory channel bus. The only multiplex that can occur is inside the memory chip itself and it then multiplexes the data bit rows of a memory array to the appropriate output pins of the memory chip. The extra multiplex is provided without additional support chips, and the JEDEC standard ECC DRAM DIMM 434 can have only up to thirty-six individual memory chips. One of the memory ranks is usually located on the front side of the PCB 435, and the memory chip is directly coupled to the memory channel bus; and another rank of the memory is usually located on the back side of the PCB 435, and the memory chip is directly coupled to The memory channel bus. Limiting the number of ranks of the memory to a predetermined number limits the data bandwidth of the memory module and the memory channel.

For larger memory capacities, for example, the memory module 214 illustrated in Figure 4A can support up to 144 individual memory chips. Other non-volatile memory modules can be designed to support additional non-volatile memory volume circuits.

The main memory of the motherboard 100A' of Figure 1A can be upgraded in accordance with the teachings of U.S. Provisional Patent Application Serial No. 60/827,421, filed on Sep. 28, 2006, which is hereby incorporated by reference. A non-volatile memory module is used in a memory channel to swap out one or more DRAM memory modules to reduce the average power consumption in a computer system. In this case, the non-volatile memory module 214 is inserted into one or more of the sockets 108A-108N to replace the DRAM memory module in the individual memory channels, and the appropriate memory controller is inserted into the socket.

In some embodiments, each memory controller of the individual memory controllers 107A-107N of the memory channel is a programmable heterogeneous memory controller for controlling the non-volatile memory. Module 214 and read and write access to other types of memory modules that can be inserted into the same memory channel. In some embodiments, a processor package 211 can be used in place of one or more processors in a multi-processor system having an integrated programmable heterogeneous memory controller 212' for controlling Read and write accesses to the non-volatile memory module 214 in individual memory channels.

Integrated programmable heterogeneous memory controller

Referring now to Figures 5A through 5B, the programmable heterogeneous memory controller can be integrated into various wafers to support a memory channel having a mixed type of memory module.

In Fig. 5A, a functional block diagram of a system controller integrated circuit 500A is illustrated. The system controller integrated circuit 500A includes a programmable heterogeneous memory controller 501A, an input/output controller 502A, an extended bus interface (eg, PCI, super channel) 504, and is used to control the memory. A device controller 506 that accesses devices other than the device. The programmable heterogeneous memory controller 501A controls access to a mixed type of memory module in the same memory channel.

In FIG. 5B, a functional block diagram of a central processing unit (CPU) or processor 500B having an integrated or integrated memory controller is illustrated. The central processing unit (CPU) or processor 500B includes a programmable heterogeneous memory controller 501B that can include an input/output controller 502B, a command controller 512, and one or more execution units (EU) 510. The programmable heterogeneous memory controller 501B can be integrated with the processor or only co-packaged in the same package. The programmable heterogeneous memory controller 501B within the processor controls access to a mixed type of memory module in the same memory channel.

Programmable heterogeneous memory controller

Referring now to Figures 6A through 6B, the programmable heterogeneous memory controllers 601A through 601B are programmable to control access to memory modules within a memory channel. It can be programmed to support different types of memory modules that can be plugged into the same memory channel socket. That is, the types of memory modules inserted into the same memory channel can be mixed and the programmable heterogeneous memory controller can be programmed to communicate with each memory module. For example, the memory channel 602A can have any type of memory module 609A that supports specifications for memory channels (eg, DDR2, DDR3, etc.), including a static random access memory module 609C, a non-volatile memory. The body module 609D or a DRAM memory module 609N. The programmable heterogeneous memory controller 601A can be programmed to communicate with memory modules of the plurality of types of memory modules in the same memory channel. Assuming that the memory module is physically inserted into a memory socket 608A-608N, matching a power connection or a subset thereof and not invalidating the memory channel bus, it can be inserted into the same memory channel and The other modules are accessed by the programmable heterogeneous memory controller 601A through the same memory channel bus. For example, a memory module having different data bandwidths (for example, BW1 memory module 629A and BW2 memory module 629C or non-volatile memory module 629D and DRAM memory module 629N) can be inserted into the same memory. The body channel 602N is accessed by the memory controller 601A through the memory channel bus 610N.

A memory channel 602A-602N is a set of wires coupled to a memory controller to form a memory channel busbar 610A-610N having two types of wire interconnects (point-to-point wires and broadcast or bus bar wires). It is in turn coupled to the socket to communicate with the memory module inserted therein. Each of the memory channels 602A to 602N is independent of each other.

Each memory channel bus 610A-610N further has a plurality of broadcast wires (PCB traces 612) that are shared with each of the individual memory channels and each of the sockets 608A-608N. That is, the wires that make up the wires of the broadcast or bus bar wires 612 are coupled to each of the sockets 608A-608N in a given memory channel and to each of the memory modules coupled thereto. Thus, signals written to the broadcast conductors 612 can be read by any of the memory modules inserted into the memory sockets in the individual memory channels 602A through 602N.

Each memory channel busbar 610A-610N has a plurality of point-to-point conductors 611 coupled from the memory controller 601A to each of the individual outlets 608A-608N. A plurality of point-to-point conductors (PCB traces) 611 from the memory controller are independent of the sockets.

In general, according to the JEDEC DDR2 specification, there are four point-to-point conductors for signals S0, S1, ODT0, and ODT1 in each memory channel. These point-to-point conductors can be reassigned to another logic function. In addition, there are approximately 29 address-only, clock and control output signals from the memory controller to each of the memory channels and each socket/DIMM. In addition, there are 72 bidirectional data lines and 36 bidirectional data strobe lines between the memory controller and each of the memory channels and each socket/DIMM (1 data clock for four bits of data) ).

One of the point-to-point conductors 611 can be redefined to generate a status signal 611F by a memory module that is communicated to the memory controller. For example, the status signal 611F can be fed back to the programmable heterogeneous memory controller 601A to know that the memory module is ready for another access. The status signal 611F is particularly useful for accessing non-volatile memory modules because it may take some time to write or erase memory locations therein. Using the status signal 611F, the memory controller does not need to poll the memory module having this capability repeatedly to determine its state and whether it is preparing another erase or write operation.

Referring to Figures 6A through 6B and 9, the heterogeneous memory controllers 601A through 601B can be programmed by software, such as a memory module (MM) software driver 900. The memory module software driver 900 can read the memory module identification (ID) 904 and then load the data into the heterogeneous memory controller; such data can include the memory type 901 (eg, SRAM, DRAM or NVRAM), pin configuration 902, signal timing and logic level 903 (eg, active low or active high).

A memory module can be matched with its memory module software driver through the memory module ID. That is, the memory module ID 410 read from the memory module should match the memory module identification (ID) 904 of the software driver 900. The memory module identification (ID) 410 can be encoded to indicate information about its manufacturer source and memory type, its capacity and speed. In addition, if the programmable heterogeneous memory controllers 601A to 601B are not easily available for one of the memory modules of the given memory module ID, the memory module can be transmitted through a network (eg, the Internet). Networking) Downloading or loading from a disc is similar to the way a new printer driver can be loaded into a computer system.

Referring to FIG. 10, after initialization, the programmable heterogeneous memory controller 601A can poll each socket in each memory channel to determine what type of memory module is inserted into each memory channel. In the socket. 10 illustrates an exemplary memory module socket table that can be stored in a scratchpad or a memory within the programmable heterogeneous memory controller 601A. The leftmost line indicates the socket number and the top line indicates the memory channel number. The items in the table are representative of the memory module identification. For example, the socket one (S1) in the memory channel one (MC1) may have a memory module of the SRAM1 type inserted therein. A socket can be unoccupied or empty. In this case, the table entry may be indicated as unoccupied, as indicated for socket two (S2) in memory channel two (MC2). These items can be used to select an appropriate memory module driver to access each memory module in each individual memory channel.

Referring now to Figures 11A through 11C, different pin configurations 902 are illustrated in the table below the lines that make up the memory channel busbar 610. The first column in each table indicates the pin number. The second column in each table indicates whether the pin is a single input pin (I), a just output pin (O), a bidirectional (both input and output) pin (B) or a power connection. Needle (P) (such as a grounding pin or a power pin). The third column in each table represents the functionality assigned to each pin, such as power (V), ground (G), no connection (NC), data pin (Di), address pin (Ai) Or control the pin (Ci). For example, these different pin configurations can be stored as pin configurations 902 for different memory module drivers 900 (see Figure 9).

A mixed type of memory module in a memory channel can cause the memory controller to instantly change the pin configuration of a memory channel bus when accessing each memory module. For example, the pin configuration illustrated in FIG. 11A can be used to access a first memory module through the memory channel bus 610. For example, in Fig. 11A, the pins numbered 3 and 4 control the input pins C1 and C2, respectively. For example, when accessing one of the second memory modules of the memory channel bus 610, the pin configuration can be changed to the configuration illustrated in FIG. 11B. For example, in Fig. 11B, the pins of numbers 3 and 4 are bidirectional data bus bars D1 and D2, respectively. For example, when accessing one of the third memory modules of the memory channel bus 610, the pin configuration can be changed to the configuration illustrated in FIG. 11C. For example, in Fig. 11C, the pins of numbers 3 and 4 are address input pins A1 and A2, respectively. The programmable heterogeneous memory controller 601A changes the signal functionality and pin assignments as soon as each different memory module is accessed. If the same memory module is inserted into two memory sockets in the same memory channel, the memory controller is stylized as it continuously changes from accessing one memory module to another memory module. There can be no change in it.

It should be noted that the wires for power (V) and ground (G) do not change when accessing different memory modules on the same memory channel. For example, the pins of numbers 1 and 2 are held constant at power (V) and ground (G), respectively. However, not every memory module needs to be connected to each power or ground pin. For example, in FIG. 11B, the memory modules to be accessed using the pin configuration are respectively connected to pins N-1 and N (ground (G) and power (V)) without a connection (NC).

In order to address the additional memory and increase the memory capacity of the main memory, in response to the type of memory module being accessed, a programmable heterogeneous memory controller in a configuration can use an additional pin to form a A larger address is addressed to a larger memory space. In another configuration, in response to the type of memory module being accessed, the programmable heterogeneous memory controller can use a pre-existing address pin on multiple address loops to form a larger The address is addressed to a larger memory space.

14 illustrates an exemplary pin configuration map of a non-volatile memory module in accordance with certain embodiments. When accessing the non-volatile memory module, the pin configuration of the memory channel is changed from a signal name line associated with a DDR2 memory module specification to a signal assignment line for the non-volatile memory module. .

For example, pins 73, 74 are changed from WE#, CAS# to DIMM_ADDR0/ODT0, DIMM_ADDR1/ODT1, respectively, to identify which DIMM socket/DIMM memory module is addressed after initialization and to set the die during initialization. terminal.

As another example, the pins 188, 183, 63, 182, 61, 60, 180, 58, 179, 177, 70, 57, 176, 196, 174, 173, and 54 are respectively from the signal address bits A0, A1. , A2, A3, A4, A5, A6, A7, A8, A9, A10/AP, A11, A12, A13, A14, A15, A16/BA2 change to multi-cycle address bit A0/A17/DSEL_0, A1/A18 /DSEL_1, A2/A19, A3/A20, A4/A21, A10/A27, A11/Reset_N, A12/OE_N, A13/WEO_N, CE2_N/A14, CE3_N/A15, CE1_N/A16 to address each memory module One of the larger memory spaces inside. To indicate whether the upper address byte or the one address low byte on these multi-cycle address pins is available, the pin 195 is changed from ODT0 to ADDR_HIGH, respectively. If the ADDR_HIGH signal is a logic high signal, the address high byte (A17, A18, A19, etc.) is provided on the multi-cycle address bits. If the ADDR_HIGH signal is a logic low signal, the address low byte (eg, A0, A1, A2, etc.) is provided on the multi-cycle address bits.

As another example, pins 193 and 76 retain the same function. These signals select which rank of memory in a memory module is being accessed.

As another example, when the non-volatile memory module is to be accessed in a socket, the pins 125, 134, 146, and 155 are changed from the data strobe signals DQS9, DQS10, DQS11, and DQS12 to RY/BY_N_R0D0, respectively. RY/BY_N_R0D1, RY/BY_N_R0D2, RY/BY_N_R0D3. The RY/BY_N_R0D0, RY/BY_N_R0D1, RY/BY_N_R0D2, and RY/BY_N_R0D3 signals are for the status signal of the zeroth rank memory of each DIMM module/socket of four DIMM modules/sockets in a memory channel. When the non-volatile memory module is to be accessed in a socket, the pins 202, 211, 223, and 232 are changed from the data strobe signals DQS13, DQS14, DQS15, and DQS16 to RY/BY_N_R1D0, RY/BY_N_R1D1, RY, respectively. /BY_N_R1D2, RY/BY_N_R1D3. The RY/BY_N_R1D0, RY/BY_N_R1D1, RY/BY_N_R1D2, and RY/BY_N_R1D3 signals are status signals for the first rank memory of each DIMM module/socket of the four DIMM modules/sockets in the memory channel. These status signals are fed back and coupled to the heterogeneous memory controller for more efficient access to the non-volatile memory module. Each status signal indicates whether a rank of the memory in a memory module is busy or prepares another write or erase operation to mitigate the non-deterministic nature of the erase and write operations on the non-volatile memory module. .

Figures 11A through 11C have been illustrated as changing the signal/pin configuration of the memory channel bus when accessing each different memory module in each socket. However, the signal/pin configuration can also be changed due to a change in one of the specifications of the memory channel busbar designed for a new memory channel.

In FIG. 6A, the memory channel busbars of the memory channel busbars 610A through 610N can be designed to support the DDR2 memory module specifications. However, a new computer system can be designed using a different memory module specification for one of the memory channels and a different pin/signal configuration. Because the heterogeneous memory controller 601A is programmable, it can be easily updated to a new memory module specification and new pin/signal configuration for a new memory channel.

For example, consider Figure 6B. A new memory communication channel specification can be established to define a new pin for each memory channel bus of each of the new memory channel busses 650A through 650N of each of the individual memory channels 602A' through 602N'. Signal configuration. The memory modules can be designed to pair with new pin/signal configurations of the new memory channel busbars 650A-650N. Assuming that the total number of non-power pins is the same, the programmable heterogeneous memory controller 601A can be easily updated by reprogramming to the programmable heterogeneous memory controller 601B illustrated in FIG. 6B. The memory module driver for the new memory channel standard is rewritten to support the new memory channel busses 650A through 650N and the new drivers are loaded into the programmable heterogeneous memory controller 601B. In this way, the logic design of the programmable heterogeneous memory controller can remain the same, which is updated by software by loading a new memory module driver, and the circuit under the logic can be changed to adapt to the new Power supply voltage. That is, the logical network connection tables of the programmable heterogeneous memory controllers 601A and 601B remain the same and the pin configuration is updated by the new memory module driver software. The programmable heterogeneous memory controller 601A can be programmed in this manner to substantially reduce the time required to develop new or proprietary memory channels. Thus, the programmable heterogeneous memory controller can be reused as an IP core block because it can be easily typed for the type of memory channel, memory channel bus, and memory module it will interface with. Stylized. Different processor manufacturers can purchase and program the logical network connection table of the programmable heterogeneous memory controller to meet its specific memory channel requirements.

Referring now to Figures 7A through 7B, a high level functional block diagram of a programmable heterogeneous memory controller (PHMC) 700 is illustrated. In FIG. 7A, the programmable heterogeneous memory controller 700 must be programmed while waiting for the memory module to be inserted into the sockets or slots 705-708. Each memory channel controller 720i includes a particular memory module slot controller 721-724 for each slot or receptacle 705-708. In FIG. 7B, two or more different types of memory modules (eg, type A memory module 701, class A type B memory module 702, a type C memory module 703, and a type D memory module 704) are coupled to each of the memory channels 710i. It should be noted that one or more of the memory modules inserted into the slots/sockets 705 through 708 can be the same type of memory module. In this case, the same program can be used to program two or more of the memory module slot controllers 721 through 724 to handle the same type of DIMM.

For each memory channel 710i, the programmable heterogeneous memory controllers 700 include a memory channel controller 720i. Each memory channel controller of the memory channel controller 720i is coupled between a processor interface 750 and its individual memory channel 710i. Each memory channel controller 720i is coupled to the processor or interconnect fabric interface 750 to communicate with a processor or I/O controller for memory operating instructions and results thereof.

As shown in FIG. 7B, each memory channel controller 720i can include a specific memory module slot controller 721 to 724 for each slot or socket 705 to 708 in which a memory module 701 to 704 can be coupled. . Each memory channel controller 720i further includes a common memory module controller 730 coupled to a memory channel interface 732. The socket/slot A memory module controller 721 is for controlling a memory module of the type coupled to the socket A 705 (eg, type A memory module 701). The socket/slot B memory module controller 722 is for controlling a memory module of the type coupled to the socket B 706 (eg, type B memory module 702). The socket/slot C memory module controller 723 is for controlling a memory module of the type coupled to the socket C 707 (eg, type C memory module 703). The socket/slot D memory module controller 724 is for controlling a type of memory module (eg, type D memory module 704) coupled in the socket D708. The particular memory module controllers 721-724 are used to generate different control signals for each of the different memory modules that can be inserted into the available memory module sockets. Each of the specific memory module controllers 721 through 724 can be programmed by a separate memory module software driver.

The common memory module controller 730 is for generating a common control signal among different memory modules inserted into the available memory module sockets. The data pins and the address pins can remain identical between different memory modules inserted into the available memory module sockets and can be under the control of the common memory module controller 730.

The specific memory module controllers 721 to 724 and the common memory module controller 730 for each memory channel 710i communicate through the memory channel interface 732 to their individual memory modules. The memory channel interface 732 can flexibly allow for a change in the pin configuration of the memory channel bus 610i coupled to the memory modules and the individual sockets.

The memory channel bus 610i in each memory channel 710i includes a plurality of interconnecting wires (PCB traces) that are shared or broadcast to all of the memory modules and the individual sockets. A common or broadcast signal to all of the memory modules can be generated by the common memory module controller 730. The memory channel bus 610i in each memory channel 710i further includes a plurality of interconnecting wires (PCB traces) that are independent and coupled only to the memory modules and one of the individual sockets These signals are specific to the memory module. Specific signals for each individual memory module can be generated by the associated particular memory module controllers 721-724. For example, a specific signal for the type A memory module 701 and its socket 705 can be generated by the socket A memory module controller 721.

Referring now to Figure 8A, a more detailed functional block diagram of one of the programmable heterogeneous memory controllers 800A is illustrated. It should be noted that FIG. 8A illustrates an example of how a programmable heterogeneous memory controller can be organized internally, and a programmable heterogeneous memory controller can be constructed using one of a different configuration of functional blocks. The programmable heterogeneous memory controller 800A includes a processor or interconnect fabric (system) interface 802, an input buffer 803, an output buffer 804, a memory module socket control register 806, and a micro Coded memory 808 (random access memory (RAM) and/or read only memory (ROM)), one or more input/output state machines 810, an elastic input/output port controller, and an elastic memory channel Interfaces 814 (also known as an elastic I/O埠) are coupled together as shown. A direct memory access controller 813 can be provided as needed to transfer data between the memory in the heterogeneous memory controller and some other device in the system.

The processor (system) interface 802 generally allows controlled access to a primary memory by a processor. The processor (system) interface 802 can include a bit address 816 for receiving an address from a processor for accessing the main memory, and a control port 817 for receiving control from the processor Signal to access the main memory; a bidirectional data 818 for reading data from a processor for writing to the memory and for writing data to the processor after reading from the memory; and status/ A register 820 is provided for allowing the processor to read the state of the memory channels and to control access to a memory channel coupled to the memory controller.

The input buffer 803 is used to buffer the address, control and data received from the processor. The output buffer 804 is used to buffer the data to be written to the processor. The input buffer 803 can be combined with the output buffer 804 as a single input/output buffer that is larger than one of the more complex control logics.

The memory module socket registers 806 are provided for storing memory module identifications for each memory module inserted into each of the sockets directly coupled to each of the memory channels of the memory controller 800A ( ID). The memory module socket registers can store information of one of the memory module socket tables illustrated in FIG. Using this information, the memory controller 800A knows which type of memory module it will communicate directly with in each socket.

The microcoded memory 808 (random access memory (RAM) and/or read only memory (ROM)) is used for each of the different types indicated by the memory module socket registers 806. The memory module stores the memory module software drivers 900. The memory module software driver 900 can include the memory type 901 (eg, SRAM, DRAM, or NVRAM), the pin configuration 902, control signal timing, and logic level 903 (eg, low active or high active) And the memory module identification (ID) 904. The information contained in each memory module software driver 900 is coupled to one or more I/O state machines 810. That is, the microcoded memory 808 supplies the memory module software drivers to the I/O state machines.

One or more I/O state machines 810 respond to the type of memory module that is accessed in a given socket and its memory module software driver to establish an appropriate pin configuration in the memory interface 814 and Appropriate logic signals are generated for the pins using appropriate timing. One or more I/O state machines 810 perform such functions each time a given memory module is accessed to perform a write operation, a read operation, or an erase operation. The functions of one or more state machines are also described with reference to Figures 8B, 12A, 12B and 13. One or more I/O state machines 810 signal the resilient I/O controller 812 to establish an appropriate pin configuration in the memory interface 814 for accessing a given socket and memory module.

In response to control signals from one or more I/O state machines 810, the resilient I/O controller 812 establishes an appropriate pin configuration in the memory interface 814 for accessing each given socket and memory. Module.

In response to control from the UI controller 812, the memory interface 814 establishes the state of its input/output buffer. The specific connection for the received signal from the memory channel bus can be an input pin. The additional pins can be just output pins that have an output driver to drive the signals out to the memory channel bus. Other pins (eg, the data pins) can be bidirectional data pins that are selectively controlled as input buffers and write data out to the memory when reading data from the memory channel bus The channel bus is controlled as an output buffer.

The optional DMA controller 813 is for filling data buffers that may be included in memory volume circuits of the memory modules, such as the non-volatile memory volume circuits. The optional DMA controller 813 uses the direct memory access control to flush a series of data written to the memory module or the burst reads a series of data from a memory module and reads the memory controller. The DMA controller 813 can also have one of the cache memory prefetch or cache A memory controller that reduces the latency for a certain type of memory module.

Referring now to Figure 8B, further functional details of one or more I/O state machines 810 are now described. One or more I/O state machines 810 include a memory channel state machine 811A through 811N for each of the memory channels 602A through 602N coupled to the memory controller 800A. Each of the memory channel state machines 811A through 811N includes a controller 825, a bus arbiter 826, and one or more memory module state machines 821A for each memory module and each of its ranks. To 824A, 821B through 824B, they are coupled together as shown.

For example, memory module state machines 821A and 821B are directed to a memory module that can be coupled to socket A. The memory module state machine 821A is for the memory of the first rank inserted into one of the two inline memory modules in the socket A. The memory module state machine 821B is for the memory of the second rank in the double inline memory module inserted into the socket A. Additional memory module state machines may exist for three or more ranks of memory for each individual memory module. Similarly, memory module state machines 822A and 822B (including any additional memory module state machines for additional ranks) are directed to memory of individual ranks that can be coupled to one of the memory modules in socket B. Memory module state machines 823A and 823B (including any additional memory module state machines for additional ranks) are directed to memory of individual ranks that can be coupled to one of the memory modules in socket C. Memory module state machines 824A and 824B (including any additional memory module state machines for additional ranks) are for memory of individual ranks that can be coupled to one of the memory modules in socket D, etc. Additional sockets are available in the body channel). Although the programmable heterogeneous memory controller is described herein with respect to controlling the access to a memory of a rank of a homogenous memory module, the memory controller is adapted to access a memory model. A different type of memory volume circuit in one or more ranks of memory. In this case, the memory module accesses a heterogeneous memory module by a programmable heterogeneous memory controller.

For a non-volatile memory module including a non-volatile random access memory (NVRAM) integrated circuit, if a memory of a given memory ranks a read access (R), write access ( W) and initializing or erasing (I), then each of the memory module state machines 821A through 824A, 821B through 824B (including any additional memory module state machine for additional ranks) Has a sequence of different modes of operation and operation. The memory modules of the memory module state machines 821A through 824A, 821B through 824B are programmed using information from a memory module software driver of the type corresponding to the memory module inserted in the associated socket. state machine. For example, the memory module state machines 821A and 821B will be programmed using a memory module software driver corresponding to the memory module inserted into the associated socket A in the memory channel 602A.

In the case of other types of memory modules, there may be no operation of initializing or erasing the sequence of operations.

The controller 825 is coupled to each of the memory module state machines 821A through 824A, 821B through 824B (including any additional memory module state machines for additional ranks) in response to the type of access requested and access. The location of the memory module in the memory channel (eg, which socket) to control which memory module state machine is active and in which mode (read access (R), write access ( W), initialize or erase (I))

The bus arbitrator 826 is coupled to the memory module of the controller 825 and the memory module state machines 821A through 824A, 821B through 824B (including any additional memory module state machines for additional ranks) The state machine arbitrates access to the memory channel bus when the state machine attempts to communicate with its corresponding memory module.

The memory module state machines of the memory module state machines 821A through 824A, 821B through 824B, along with the controller 825 and the arbiter 826, generate appropriate pin configuration control signals to establish appropriateness in the memory interface. The appropriate logic and timing of the pins and control signals, address signals, and data signals are used to couple data reading and writing to each of the memory modules through the memory channel bus.

Method for heterogeneous memory channel communication

12A illustrates a flow chart of a method of communicating with different types of memory modules in a heterogeneous memory channel of a heterogeneous main memory.

In step 1202, a programmable heterogeneous memory controller is initialized. Each socket in each heterogeneous memory channel is polled to determine a different type of memory module in each socket of each heterogeneous memory channel. The socket in a heterogeneous memory channel can be empty or unoccupied, in which case the programmable heterogeneous memory controller does not require a memory module driver for one of the sockets.

In step 1204, for each access of each different memory module in each heterogeneous memory channel, each pin of a memory channel interface is flexibly configured or adapted to pass through a The wire interconnects of the memory channel bus communicate with individual pins of each different memory module. This is the type of memory module that responds to the access. The memory module software driver can be used to flexibly adapt the pin configuration of the memory channel interface to the type of memory module being accessed. The memory channel interface can also be referred to as an input/output port.

To improve the bandwidth in a heterogeneous memory channel, additional functionality can be assigned to under-used or unused pins so that communication protocols between certain memory modules and the heterogeneity controller can be extended. Additional address control signal lines can be used to address additional rank memory or address more complex types of memory or DIMM architecture extensions, which allow for much larger memory capacities. In addition, a feedback pin can be defined for one of each socket/memory module that is not fully used or not used so that the programmable heterogeneous memory controller can be inserted into the heterogeneous memory controller. Each memory module of each socket receives status information. A status signal can be transmitted from each socket/memory module to the programmable heterogeneous memory controller to know when each memory module is accessible or inaccessible.

In step 1206, for each access of one of the different memory modules in the heterogeneous memory channel, an appropriate logic signal is generated for communication of suitable signal conductors through the wire interconnects of the memory channel bus. Communicate to a memory module. The appropriate logic signals are generated in response to the type of memory module being accessed at that time. For example, depending on the type of memory module being accessed, the logic signals may be high active signals or they may be low active signals. Thus, the appropriate logic signal to be generated can vary with the memory module. The memory module software driver can be used to flexibly change the generation of logic signals for communication through the memory channel bus in response to the type of memory module being accessed.

In step 1208, for each access of one of the different memory modules in the heterogeneous memory channel, a logic signal is generated on the wire interconnect of the memory channel bus with appropriate signal timing to properly The memory module communicates. The appropriate signal timing for driving the logic signal onto the memory channel bus is in response to the type of memory module being accessed at that time. That is, the appropriate signal timing can vary with the memory module. The memory module software driver can be used to flexibly change the timing of the signal generation of the logic signal on the memory channel bus in response to the type of memory module being accessed.

The type of the memory module to be accessed may be appropriately programmed for both the write access and the read access of each of the memory modules of the heterogeneous memory channel. Stylized heterogeneous memory controller.

Referring now to Figure 12B, a flow diagram of one method of communication to a non-volatile memory module in a memory channel is illustrated.

In step 1212, the processor tells the memory controller to notify a non-volatile memory module to erase a segment of the volatile memory or write a data word into the non-volatile memory.

In step 1214, the non-volatile memory module that is accessed uses a feedback status control signal to send back a notification that it is in a busy state. A feedback state control signal from the memory module is coupled to the memory controller by a point-to-point wire interconnect in the memory channel bus. In some embodiments, the feedback status control signal is a status signal 611F as described herein.

In step 1216, the memory controller waits for an undetermined period of time due to the non-deterministic nature of the write and erase operations of the non-volatile memory module. That is, the memory controller waits for an indefinite period of time after receiving a feedback status control signal indicating busy.

In step 1218, the non-volatile memory module that is being accessed uses its feedback status control signal to signal back that it is now ready for another write operation or erase operation. When a write or erase operation is to be processed therein, a write operation can be performed in the memory of a different memory bank by the non-volatile memory module.

In step 1220, after receiving the feedback state control signal, the memory controller initiates another operation of the memory module. The memory controller can initiate another write access or erase unless one of the volatile memory segments. Alternatively, the memory controller can interrupt the processor and send a notification to the non-volatile memory module to prepare for another write or erase operation. The processor can also poll the feedback status control signal to wait for a change.

Figure 13 illustrates a flow chart of a method of initializing one of the programmable heterogeneous memory controllers.

In step 1302, turning on or restarting the computer system causes initialization of the programmable heterogeneous memory controller to occur.

In step 1304, each socket in each memory channel of the main memory is polled to determine whether a memory module is inserted into a socket. After polling a socket, if the programmable heterogeneous memory controller does not hear a response, it can assume that no memory module is plugged into the socket. The socket is unoccupied or empty. The programmable heterogeneous memory controller can store information about the empty or unoccupied sockets in a scratchpad or temporary memory, such as the main memory socket table illustrated in FIG.

In step 1306, if a memory module is inserted into a socket, each memory module identification is read and stored in association with its individual socket number or socket identifier. The memory module identifies an indication of the type of memory module that is inserted into the socket. If a memory module identification cannot be read from a socket, the heterogeneous memory controller can attempt to communicate with a memory module that assumes a different module type and repeat the test until a known type of module Exhausted.

In step 1308, after the memory module is read, it is stored in association with its socket number and memory channel. The memory module identification may be stored in a table of a temporary memory or a temporary memory of the programmable heterogeneous memory controller, such as illustrated by the main memory socket table of FIG.

In step 1310, the memory module software driver is loaded into the programmable heterogeneous memory controller and one or more state machines to enable and match different types of memory in each heterogeneous memory channel. Suitable communication protocols for each memory module of the body module. If only one type of memory module is inserted into a memory channel, it is a homogenous memory channel and only one memory module software driver is required for communication with each memory module.

If there is no local memory module software driver available for the programmable heterogeneous memory controller, it can be obtained from a network source (such as the Internet) or a software disc.

The programmable heterogeneous memory controller is initialized to store as the memory module software drivers are coupled to the programmable heterogeneous memory controller and loaded into one or more of the state machines Take different memory modules in each memory channel.

Conversion memory module for heterogeneous memory channels

In the foregoing description, a programmable heterogeneous memory controller is used to flexibly adapt to communicate with different types of memory modules in a heterogeneous memory channel using different communication protocols. However, the updated memory module can be designed to convert non-DDR signals to DDR signals such that the previous DDR2 memory controller can communicate transparently with the updated different types of memory modules.

Referring now to Figure 1B, the memory controllers 107A' through 107N' can be standard DDR2 memory controllers for communicating with each memory channel bus and memory modules in accordance with the DDR2 specification. However, one or more of the memory modules 109A' to 109N' to 109N' inserted into the sockets 108A to 108N of the memory channels 123A to 123N may be a conversion memory module (TMM). . In FIG. 1B, each of the memory modules of the memory modules 109A' is a conversion memory module. Another memory module 109N-1' in the same memory channel can be a DDR2 standard DRAM DIMM such that the memory channel 123A is a heterogeneous memory channel, and the memory controller 107N' is not known. The conversion memory module (TMM) is designed to convert non-DDR signals into DDR signals for transparent communication of the memory controllers 107A' to 107N' through each memory channel bus. .

Referring now to Figure 4C, a functional block diagram of a conversion memory module (TMM) 454 is illustrated. The conversion memory module 454 includes a printed circuit board 455 having a non-DDR2 memory device 461 coupled to one of the support wafers 462. One or more non-DDR2 memory devices 461 and the support wafer 462 may be packaged together in an integrated circuit package 469 and mounted to the printed circuit board 455. A plurality of non-DDR2 memory devices 461 and a plurality of support wafers 462 can be coupled to the PCB 455. The support wafer 462 is coupled to the PCB 455 and between the non-DDR2 memory 461 and the contact 470 of an edge connector. Contact 470 of the edge connector can be formed as part of the PCB 455. Otherwise, a separate edge connector can be soldered to the PCB 455.

The support chip 462 includes a converter 465, a data transceiver (transmitter and receiver) 466, and an address/control receiver 467 that are coupled together as shown. The converter 465 is coupled between the non-DDR2 memory 461 and the data transceiver 466 and the address/control receiver 467.

The data transceiver 466 and the address/control receiver 467 interface the memory module 434 bidirectionally to the memory channel bus using DDR2 address, control and data signaling.

The converter 465 is a bidirectional converter. The converter 465 converts the non-DDR signal into a DDR2 signal for communicating to the memory controller in a transparent manner through the memory channel bus. The DDR2 signal received from the memory channel bus is converted by the converter 465 into a non-DDR2 signal as understood by the non-DDR2 memory 461 as required. In this manner, a non-DDR2 memory device in a memory module can communicate with a pre-existing memory controller using a pre-existing memory channel bus.

in conclusion

The description includes many specifics, and should not be construed as limiting the scope of the disclosure or the scope of the invention. Particular combinations of features described in this specification in the context of separate embodiments can also be implemented in a single embodiment. Conversely, various features that are described in the context of a single embodiment can be practiced in various embodiments. Moreover, while the features above may be described as acting in a particular combination and even initially claiming that in some cases one or more features from the claimed combination may be excised from the combination, and the claimed combination may belong to a sub-combination Or a change in a sub-combination.

A number of embodiments have been described. It should be understood, however, that various modifications may be made without departing from the spirit and scope of the disclosure. Other embodiments are within the scope of the following patent claims. For example, the memory modules and the memory sockets have been described as dual in-line memory modules (DIMMs) and DIMM sockets. However, for example, the memory modules and memory sockets can have other types of form factors, such as a single inline memory module (SIMM).

100A. . . computer system

100A'. . . motherboard

101A to 101N. . . Processor socket

102A to 102N. . . Trace

103. . . Interconnect fabric

104A to 104N. . . Trace

105'. . . I/O subsystem

105A to 105N. . . I/O subsystem/input/output subsystem

106A to 106N. . . Trace

107A to 107N. . . Programmable heterogeneous memory controller

107A' to 107N'. . . Memory controller

108A to 108N. . . Memory module socket

109A to 109N. . . Memory module

109A' to 109N'. . . Memory module

109N-1'. . . Memory module

110. . . Memory channel bus

110'. . . Memory channel bus

110"...memory channel bus

110A to 110N. . . Printed circuit board trace

112A to 112N. . . Processor socket

112B. . . Processor socket

113A to 113N. . . Homogeneous memory channel

114A to 114N. . . DRAM memory module

114B. . . DRAM DIMM

115A to 115N. . . Memory module socket

116A to 116N. . . Trace

117D. . . DRAM memory controller

117NV. . . Non-volatile random access memory controller (NVMC)

118. . . I/O

120A to 120N. . . Trace

121A to 121N. . . Expansion connector or slot

122A to 122N. . . processor

122B. . . microprocessor

123A to 123N. . . Heterogeneous memory channel

125A to 125N. . . Trace

150'. . . Main memory

200'. . . motherboard

211. . . Processor/processor package

212. . . Externally programmable heterogeneous memory controller

212'. . . Integrated Programmable Heterogeneous Memory Controller / Internal Programmable Heterogeneous Memory Controller

213A to 213N. . . Heterogeneous memory channel

214. . . Non-DRAM type memory module / non-volatile memory module

214A to 214N. . . Memory module

214B. . . Any MM

221. . . Homogeneous memory controller

231. . . processor

300. . . computer system

301. . . motherboard

314A to 314N. . . Dynamic random access memory (DRAM) integrated circuit / memory chip

315A to 315N. . . Static random access memory (SRAM) integrated circuit

400. . . Printed circuit board (PCB)

401. . . Edge connector contact

402A to 402N. . . Non-volatile memory volume circuit / NVRAM / non-DRAM memory chip

402B. . . Non-volatile memory volume circuit / non-DRAM memory chip

403A to 403N. . . Support chip

404. . . Internal memory module bus

404A to 404N. . . Printed circuit board trace

406. . . Printed circuit board trace

406A to 406L. . . Printed circuit board trace

410. . . Memory Module Identification (MMID)

411. . . Input/output埠

412. . . Communication

415. . . Register

422. . . Many-to-one bus multiplexer

424. . . One-to-many bus multiplexer

425. . . Write buffer

426A to 426D. . . Memory of non-volatile memory cells

427. . . Status register

434. . . JEDEC standard DRAM DIMM/memory module

435. . . Printed circuit board / PCB

436A to 436N. . . DRAM memory chip

440. . . Edge connector contact

454. . . Conversion Memory Module (TMM)

455. . . Printed circuit board / PCB

461. . . non-DDR2 memory device

462. . . Support chip

465. . . converter

466. . . Data transceiver

467. . . Address/control receiver

469. . . Integrated circuit package

470. . . Edge connector contact

500A. . . System controller integrated circuit

500B. . . Central processing unit (CPU) or processor

501A. . . Programmable heterogeneous memory controller

501B. . . Programmable heterogeneous memory controller

502A. . . Input/output controller

502B. . . Input/output controller

504. . . Expansion bus interface

506. . . Device controller

510. . . Execution unit (EU)

512. . . Command controller

601A. . . Programmable heterogeneous memory controller

601B. . . Programmable heterogeneous memory controller

602A to 602N. . . Memory channel

602A' to 602N'. . . Memory channel

608A to 608N. . . Memory socket

609A. . . Memory module

609C. . . Static random access memory module

609D. . . Non-volatile memory module

609N. . . DRAM memory module

610. . . Memory channel bus

610A to 610N. . . Memory channel bus

610i. . . Memory channel bus

611. . . Point-to-point wire

611F. . . Status signal

612. . . Broadcast or bus bar

619A. . . DRAM DIMM

619C. . . DRAM DIMM

619D. . . DRAM SIMM

619N. . . DRAM DIMM

629A. . . BW1 memory module

629B. . . BW MM

629C. . . BW2 memory module

629D. . . Non-volatile memory module

629N. . . DRAM memory module

650A to 650N. . . Memory channel bus

650B. . . Memory channel bus

700. . . Programmable Heterogeneous Memory Controller (PHMC)

701. . . Type A memory module

702. . . Type B memory module

703. . . Type C memory module

704. . . Type D memory module

705. . . Socket or slot/socket A

706. . . Socket or slot/socket B

707. . . Socket or slot/socket C

708. . . Socket or slot/socket D

710i. . . Memory channel

720i. . . Memory channel controller

721. . . Socket/slot A memory module slot controller

722. . . Socket/slot B memory module slot controller

723. . . Socket/slot C memory module slot controller

724. . . Socket/slot D memory module slot controller

730. . . Common memory module controller

732. . . Memory channel interface

750. . . Processor interface

800A. . . Programmable heterogeneous memory controller

802. . . Processor or interconnect fabric (system) interface

803. . . Input buffer

804. . . Output buffer

806. . . Memory module socket control register

808. . . Microcoded memory

810. . . Input/output state machine

811A to 811N. . . Memory channel state machine

812. . . Elastic I/O埠 controller

813. . . Direct memory access controller/DMA controller

814A, 814B. . . Elastic output / input 埠 A / B

816. . . Address 埠

817. . . Control

818. . . Two-way data埠

820. . . Status/control register

821A. . . Memory module state machine

821B. . . Memory module state machine

822A. . . Memory module state machine

822B. . . Memory module state machine

823A. . . Memory module state machine

823B. . . Memory module state machine

824A. . . Memory module state machine

824B. . . Memory module state machine

825. . . Controller

826. . . Bus arbitrator

900. . . Memory module (MM) software driver

901. . . Memory type

902. . . Pin configuration

903. . . Signal timing and logic level

904. . . Memory module identification (ID)

Figure 1A is a functional block diagram of a computer system using a programmable heterogeneous memory controller for controlling one of the heterogeneous main memories.

1B is a functional block diagram of a computer system having a heterogeneous main memory including a DRAM memory module and a conversion memory module having different types of memory.

2 is a functional block diagram of another computer system having a programmable memory controller inserted into a processor socket or including a portion of the processor to control the heterogeneous main memory of the heterogeneous main memory. .

3 is a functional block diagram of another computer system having a memory main circuit and a memory controller circuit (including a programmable heterogeneous memory controller) coupled to one of the motherboard's heterogeneous main memories.

4A is a functional block diagram of a non-DRAM type memory module.

4B is a functional block diagram of a DRAM type memory module.

4C is a functional block diagram of a conversion memory module.

Figure 5A is a functional block diagram of a system controller including a programmable heterogeneous memory controller.

Figure 5B is a functional block diagram of a processor or multiprocessor including a programmable heterogeneous memory controller.

6A is a block diagram of a plurality of standard memory channels having different types of memory modules coupled to a programmable heterogeneous memory controller.

Figure 6B is a block diagram of a plurality of newly designated memory channels coupled to a reprogrammed programmable heterogeneous memory controller.

7A-7B are high level functional block diagrams of one embodiment of a programmable heterogeneous memory controller coupled to different types of memory modules in a memory channel.

8A-8B are more detailed functional block diagrams of one embodiment of a programmable heterogeneous memory controller.

Figure 9 is a functional block diagram of a memory module driver for each of the different types of memory modules.

Figure 10 is a table for explaining information stored in a memory module socket register/table for each memory channel in a main memory.

11A through 11C are diagrams for explaining the instantaneous reassignment of a wire interconnection of a memory channel in response to the type of memory module being accessed.

Figure 12A is a flow diagram of one method of heterogeneous communication in a memory channel of one of a different type of memory module.

Figure 12B is a flow diagram of one of the methods of communicating with one of the non-volatile memory modules in a memory channel.

Figure 13 is a flow diagram of a method of initializing one of the programmable heterogeneous memory controllers.

Figure 14 (comprising Figures 14-1 through 14-5) is a table of sample pin configuration remappings for accessing a memory channel of an exemplary non-volatile memory module.

100A. . . computer system

100A'. . . motherboard

101A to 101N. . . Processor socket

102A to 102N. . . Trace

103. . . Interconnect fabric

104A to 104N. . . Trace

105'. . . I/O subsystem

105A to 105N. . . I/O subsystem/input/output chip

106A to 106N. . . Trace

107A to 107N. . . Programmable heterogeneous memory controller

108A to 108N. . . Memory module socket

109A to 109N. . . Memory module

110A to 110N. . . Printed circuit board trace

120A to 120N. . . Trace

121A to 121N. . . Expansion connector or slot

122A to 122N. . . processor

123A to 123N. . . Heterogeneous memory channel

Claims (55)

A main memory, comprising: a programmable heterogeneous memory controller having a first memory channel interface coupled to a first memory channel; the first memory channel coupled to the programmable a heterogeneous memory controller having a first memory channel busbar coupled to the first memory channel interface of the programmable heterogeneous memory controller and a plurality of sockets And coupled to the first memory channel bus, the plurality of sockets respectively capable of receiving a plurality of memory modules; and wherein the programmable heterogeneous memory controller accesses only a first memory module Before the group, the first memory channel interface is instantly adapted to communicate with the first memory module having a first type of memory, and the first is adapted immediately before accessing a second memory module. The memory channel interface communicates with the second memory module having a second type of memory, wherein the second type of memory is different from the first type of memory, and only accesses one Before the three memory modules, the first memory channel interface is instantly adapted to communicate with the third memory module having a third type of memory, wherein the third type of memory is different from the second type of memory body. The main memory of claim 1, wherein: the main memory system is a part of a system, and the system includes a plurality of places a programmable socket, the programmable heterogeneous memory controller is packaged in an integrated circuit package that does not have a processor, and wherein the integrated circuit package has a processor compatible pin and the programmable A heterogeneous memory controller is coupled to one of the plurality of processor sockets. The main memory of claim 1, wherein: the programmable heterogeneous memory controller is co-packaged in an integrated circuit package having a processor coupled to a processor socket. The main memory of claim 1, wherein: at least one socket of the memory channel bus, receiving the at least one DRAM module; and at least another socket of the memory channel bus, Receiving the at least one non-volatile memory module. The main memory of claim 1, wherein: the memory channel bus includes one or more point-to-point wires independently coupled between the memory controller and each individual socket, and a plurality of bus bars, It is coupled to each of the memory controller and the memory channel. The main memory of claim 5, wherein: one of the one or more point-to-point wires communicates with a feedback control signal from each of the memory modules to the memory controller. A main memory comprising: a memory controller having one or more memory channel interfaces for coupling to one or more individual memory channels; a memory channel having a coupling to the memory controller a memory channel bus of a memory channel interface; a first dynamic random access memory module coupled to the memory channel bus; and a first non-volatile memory module coupled to The memory channel busbar; wherein the communication channel through the memory channel busbar is specified by a standard specification having standard specification data and instructions, and wherein the first non-volatile memory module is a conversion memory a module, the conversion memory module includes a printed circuit board; a non-volatile memory volume circuit mounted to the printed circuit board; and a converter mounted to the printed circuit board and coupled to the memory Between the channel bus and the non-volatile memory volume circuit, the converter is configured to convert standard specification data and instructions read from the memory channel bus into The memory data and instructions for the non-volatile memory volume circuit, the converter being further configured to convert data and instructions from the non-volatile memory volume circuit for writing to the memory channel bus Standard specifications and instructions. A computer system comprising: a printed circuit board comprising a plurality of traces; at least one processor coupled to the plurality of traces of the plurality of traces of the printed circuit board; a first heterogeneous memory a body channel, comprising a first plurality of sockets coupled to one of the first memory channel busbars of the printed circuit board, the first plurality of sockets for receiving a first plurality of different types of memory modules a programmable circuit board; and a programmable heterogeneous memory controller coupled between the at least one processor and the first heterogeneous memory channel, the programmable heterogeneous memory controller for controlling the pair Accessing the first plurality of different types of memory modules in the first heterogeneous memory channel; and wherein the programmable heterogeneous memory is controlled only before accessing a first memory module The device first flexibly adapts the first memory channel bus to control access to a first type of memory module in the first heterogeneous memory channel, and only accesses a second memory module prior to, The programmable heterogeneous memory controller flexibly adapts the first memory channel bus to control access to a second type of memory module in the first heterogeneous memory channel, wherein the The second type of memory module is different from the first type of memory module, and the programmable heterogeneity is only before accessing a third memory module. The memory controller flexibly adapts the first memory channel bus to control access to a third type of memory module in the first heterogeneous memory channel, wherein the third type of memory The module is different from the second type of memory module. The computer system of claim 8, wherein: the first memory module coupled to one of the sockets of the first heterogeneous memory channel is a dynamic random access memory module, and coupled to the first a second memory module of another socket in a heterogeneous memory channel, which is a non-volatile memory module; and the third memory coupled to another socket in the first heterogeneous memory channel The body module is a static random access memory module. The computer system of claim 8, wherein: the memory controller is an integrated memory controller integrated with at least one processor on a die and packaged in an integrated circuit package and coupled to Mounted to the second processor socket of the printed circuit board. The computer system of claim 8, wherein: each of the first, second, and third types of memory modules has a memory module identification to indicate the plurality of memory modules coupled to the heterogeneous memory channel This type of memory module in the socket. A method of communicating to different types of memory modules in a memory channel, the method comprising: initializing a programmable heterogeneous memory controller for each memory module coupled to a memory channel bus ; Responding to each of the different types of memory modules that are accessed to adapt each pin of a memory channel interface to communicate with the individual contacts of each memory module through the wire interconnects of the memory channel bus Responding to each different type of memory module that is accessed to generate a logic signal for communicating with each memory module through the wire interconnect of the memory channel bus; and wherein the response is accessed Each of the different types of memory modules generates the logic signals on the wire interconnects of the memory channel busses to communicate with each of the memory modules using appropriate signal timing. The method of claim 12, further comprising: loading one or more memory module software drivers associated with the type of memory module being accessed into the heterogeneous memory controller. The method of claim 13, further comprising: downloading, by a network, at least one of the one or more memory module software drivers. The method of claim 13, wherein the one or more memory module software drivers each include information about the individual pins of the memory module in response to each different type of memory module being accessed. a logic signal for communicating with the memory module and a signal timing for communicating with the memory module. The method of claim 12, wherein the adapting of each of the pins comprises assigning additional functionality to an insufficiently used or unused pin A communication protocol between the one or more memory modules and the programmable heterogeneous memory controller can be extended. The method of claim 16, wherein the address and control signal lines are used in a different manner to address the additional memory to increase the memory capacity. The method of claim 16, wherein the pre-existing address pins are used on a plurality of cycles to form a larger address to address additional memory and increase memory capacity. The method of claim 16, wherein defining a feedback pin enables the programmable heterogeneous memory controller to receive status information from the memory module. The method of claim 12, wherein the generating of the logic signal comprises generating a high active logic signal or a low active logic signal in response to the type of the memory module being accessed. The method of claim 12, wherein the initializing of the programmable heterogeneous memory controller comprises polling each socket in the memory channel for a memory module; reading one from each memory module Memory module identification to determine the type of memory module coupled to each of the sockets; and a memory module software driver for each different type of memory module coupled in the memory channel Enter the programmable heterogeneous memory controller. The method of claim 21, wherein the initializing the programmable heterogeneous memory controller further comprises storing each memory module identifier associated with each socket in the programmable heterogeneous memory control In the device. The method of claim 22, wherein the initializing the programmable heterogeneous memory controller further comprises loading the state machine with the memory module software driver to access the memory module in a given socket . A method of communicating with a non-volatile memory module in a memory channel, the method comprising: signaling a non-volatile memory module to perform an operation; using a feedback status control signal back Sending a message to a memory controller to indicate that the non-volatile memory module is in a busy state; waiting for the non-volatile memory module to complete the non-volatile memory module after the feedback state control signal indicates that the non-volatile memory module is in a busy state Operating; and signaling back to the memory controller using the feedback status control signal to indicate that the non-volatile memory module is now ready to perform another operation. The method of claim 24, wherein the instructing the non-volatile memory module to perform the operation is to erase a sector of the volatile memory. The method of claim 24, wherein The operation of signaling the non-volatile memory module to perform the operation writes a word or data word into the non-volatile memory. The method of claim 24, wherein the feedback state control signal from the non-volatile memory module is coupled to the memory controller via a point-to-point wire interconnect in the memory channel bus. The method of claim 24, further comprising: performing the operation in a first memory of one of the non-volatile memory in the non-volatile memory module; and when the operation is in the non-volatile memory When the first memory bank is to be processed, a read operation is simultaneously performed in the second memory of one of the non-volatile memory in the non-volatile memory module. The method of claim 24, wherein the one of the non-volatile memory modules in the non-volatile memory module is erased by the memory controller initiating the other operation. The method of claim 24, wherein the data operation is initiated by the memory controller to write a data word into the non-volatile memory in the non-volatile memory module. The method of claim 24, further comprising: interrupting a processor to signal the non-volatile memory module to prepare for another operation. A conversion memory module comprising: a printed circuit board having a memory module form factor and a pre-existing memory channel bus for coupling to a main memory An edge connector of a socket; at least one memory volume circuit coupled to the printing plate, the at least one memory volume circuit having a memory for storing and recalling data and for conveying data, address and Controlling a signal to read and write data to a first memory communication protocol in the at least one memory volume circuit; and at least one support wafer coupled to the printed circuit board and coupled to the edge connector and the Between at least one memory volume circuit, the at least one supporting chip includes a bidirectional converter for communicating with the first memory in the first memory communication protocol for the at least one memory volume circuit Converting between a second memory communication protocol of the memory channel of the protocol, the second memory communication protocol for transmitting data, address and control signals through the memory channel bus to read and write data The memory of the conversion memory module. The conversion memory module of claim 32, wherein: the at least one support chip further comprises a data transceiver coupled between the bidirectional converter and the edge connector, the data transceiver for the memory The module is bidirectionally coupled to the memory channel bus and uses the second memory communication protocol to receive and transmit data on the memory channel bus, and an address and control receiver coupled to the bidirectional conversion Between the device and the edge connector, the address and control receiver is configured to interface the memory module to the memory channel bus and use the second memory The communication protocol receives the address and control on the memory channel bus. The conversion memory module of claim 33, wherein: the at least one memory volume circuit is a non-double data rate two (non-DDR2) memory volume circuit and the first memory communication protocol is a non-DDR2 memory a communication protocol, the second memory communication protocol having a DDR2 memory communication protocol of DDR2 address, control and data transmission, the data transceiver transmitting the memory module bidirectionally to the memory using DDR2 data transmission The channel bus, and the address/control receiver receives the DDR2 address transmission and the DDR2 control signaling to interface the memory module to the memory channel bus. The conversion memory module of claim 32, wherein: the at least one memory volume circuit is a non-traditional memory volume circuit, and the at least one support chip comprises the bidirectional converter for communication in the first memory protocol The conversion between the second memory communication protocols causes the non-traditional memory volume circuitry in the memory module to communicate to a pre-existing memory controller using the pre-existing memory channel bus. The conversion memory module of claim 35, wherein: the non-traditional memory volume circuit is a non-volatile memory volume circuit. A memory module includes: a printed circuit board having a memory module form factor and a socket for coupling to a socket of a memory channel bus of a main memory An edge connector; at least one memory volume circuit coupled to the printed circuit board, the at least one memory volume circuit having a memory for storing and recalling data; and at least one support chip coupled to the printed circuit The board is coupled between the edge connector and the at least one memory volume circuit, the at least one support chip includes a memory module identification (MMID) for providing a type of the memory module and the at least one memory One of the volume circuits is identified. The memory module of claim 37, wherein: the memory module identification (MMID) is used to identify the memory module as a non-volatile memory module and identify the at least one memory volume circuit as At least one non-volatile memory volume circuit. The memory module of claim 37, wherein: the at least one support chip further comprises an input/output port coupled to the edge connector to form a communication port to identify the memory module (MMID) communication To a memory controller. The memory module of claim 39, wherein: the input/output is a serial input/output port and the communication is a serial communication port for identifying the memory module (MMID) string. The column communicates to the memory controller. The memory module of claim 37, wherein: the at least one support chip further comprises a register for storing state information about the at least one memory volume circuit, the register being responsive to a request for communicating the status information to a memory controller via a memory channel bus. The memory module of claim 37, wherein: the at least one supporting chip is configured to receive status information from the at least one memory volume circuit and generate a status flag for controlling a memory through a memory channel bus Communication. A programmable heterogeneous memory controller comprising: a processor interface for coupling to a processor, and one or more memory channel controllers coupled to the processor interface and coupled to One or more individual memory channels, each of the memory channel controllers of the one or more memory channel controllers includes a memory channel interface for coupling to a memory channel bus; a common memory module controller coupled to the memory channel interface and the processor interface, the common memory module controller for a plurality of different memories coupled to a plurality of memory module sockets The body module generates a common control signal on the memory channel busbar; and a plurality of memory module controllers coupled to the memory channel interface and the processor interface, the plurality of memory module controllers For the coupling to the individual plurality of memory module sockets Each memory module of a plurality of different memory modules generates different control signals, and each memory module controller of the plurality of memory module controllers is responsive to being coupled to the socket of the individual memory module The type of memory module is programmed by a memory module software driver. The programmable heterogeneous memory controller of claim 43, wherein the non-volatile memory module is coupled to a memory of a first memory channel bus coupled to a first memory channel controller In the module socket, a dynamic random access memory module is coupled to another memory module socket of the first memory channel bus; and the main memory system is a heterogeneous main memory. The programmable heterogeneous memory controller of claim 44, wherein a first memory module controller is programmed by a memory module software driver to generate a first control signal for controlling the non-volatile memory And a second memory module controller is programmed by a different memory module software driver to generate a second control signal for controlling the dynamic random access memory module. The programmable heterogeneous memory controller of claim 44, wherein the common memory module controller converges the non-volatile memory module with the DRAM module in the first memory channel A common control signal is generated on the row. A programmable heterogeneous memory controller comprising: a system interface for coupling to a processor and allowing access to a main memory; a memory interface having one or more elastic input/output (I/O) pins for the memory The body interface is coupled to different memory modules in the socket of one or more individual memory channels; and one or more input/output (I/O) state machines coupled to the system interface and the memory Between the body interfaces, the I/O state machine is configured to respond to the type of the memory module accessed in a given socket and its individual memory module software driver to program the pin configuration and The pins of the memory interface generate a logic signal. The programable heterogeneous memory controller of claim 47, wherein the memory module software driver comprises a memory type, a pin configuration, and a signal associated with the memory module identification of a memory module. Timing and signal logic levels. The programmable heterogeneous memory controller of claim 47, further comprising: an input/output (I/O) buffer coupled to the system interface and the one or more I/O state machines The I/O buffer is configured to buffer the address, control and data received from a processor for the I/O state machine and buffer data from the I/O state machine to write it out to a processor. . The programmable heterogeneous memory controller of claim 47, further comprising: an elastic 埠 controller coupled between the I/O state machine and the memory interface, the elastic 埠 controller being used Should be connected to the configuration to choose The functional pins of the one or more elastic input/output (I/O) ports. The programmable heterogeneous memory controller of claim 47, further comprising: a memory module socket register coupled to the I/O state machine, the memory module socket register being used Storing the memory module identification (ID) of each memory module inserted into each of the sockets in each memory channel; a microcoded memory coupled to the memory module socket register, The microcoded memory is configured to store the memory module software drivers and supply the memory module software drivers to each of the different types of memory modules indicated by the memory module socket registers I/O state machine. The programmable heterogeneous memory controller of claim 47, wherein each of the one or more input/output (I/O) state machines is coupled to the programmable heterogeneous memory for control Each memory channel of the device includes a memory channel state machine, each memory channel state machine including one or more memory module state machines for each memory module and each rank memory thereof The memory module of the one or more memory module states for responding to the access memory module, wherein each of the memory modules is coupled to the memory module through the memory channel bus The type of group is configured to configure the memory interface using an appropriate pin to respond to the type of memory module being accessed to generate the appropriate logic level of the signal and to respond to the memory model being accessed. The type of group is converged in the memory channel at the appropriate time Reading and generating a signal; a controller coupled to the one or more memory module state machines, the controller for controlling which of the one or more memory module state machines are active; And a bus arbitrator coupled to the controller and the one or more memory module state machines, the bus arbitrator arbitrating the memory by the one or more memory module state machines Access to the body channel bus. The programmable heterogeneous memory controller of claim 52, wherein the controller is further responsive to the type of the requested memory access and the location in the memory channel of the memory module being accessed To control the operating mode of the one or more memory module state machines in operation. The programmable heterogeneous memory controller of claim 53, wherein the mode of operation is one of a read (R) access, a write (W) access, or an initialization/erase (I) . The programmable heterogeneous memory controller of claim 53, wherein the location of the memory module is coupled to the socket of the memory module.