KR20180009107A - Semiconductor device - Google Patents

Abstract

According to an embodiment of the present invention, a semiconductor element comprises: a first conductive semiconductor layer; multiple pit generation layers distributed on the first conductive semiconductor layer; an active layer including a pit located on the pit generation layer; and a second conductive semiconductor layer on the active layer. The semiconductor element forms the pit generation layer with a nitride containing a p-type dopant capable of high-temperature growth, thereby reducing operation voltage of the semiconductor element and improving light efficiency.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device for improving light efficiency.

Semiconductor devices including compounds such as GaN and AlGaN have many merits such as wide and easy bandgap energy, and can be used variously as light emitting devices, light receiving devices, and various diodes.

Particularly, a light emitting device such as a light emitting diode or a laser diode using a semiconductor material of Group 3-5 or 2-6 group semiconductors can be applied to various devices such as a red, Blue, and ultraviolet rays. By using fluorescent materials or combining colors, it is possible to realize a white light beam with high efficiency. Also, compared to conventional light sources such as fluorescent lamps and incandescent lamps, low power consumption, , Safety, and environmental friendliness.

In addition, when a light-receiving element such as a photodetector or a solar cell is manufactured using a semiconductor material of Group 3-5 or Group 2-6 compound semiconductor, development of a device material absorbs light of various wavelength regions to generate a photocurrent , It is possible to use light in various wavelength ranges from the gamma ray to the radio wave region. It also has advantages of fast response speed, safety, environmental friendliness and easy control of device materials, so it can be easily used for power control or microwave circuit or communication module.

Accordingly, the semiconductor device can be replaced with a transmission module of an optical communication means, a light emitting diode backlight replacing a cold cathode fluorescent lamp (CCFL) constituting a backlight of an LCD (Liquid Crystal Display) display device, White light emitting diodes (LEDs), automotive headlights, traffic lights, and gas and fire sensors. In addition, semiconductor devices can be applied to high frequency application circuits, other power control devices, and communication modules.

In a conventional semiconductor device, a first semiconductor layer, an active layer, and a second semiconductor layer are sequentially stacked, and a V-Pit is formed in the active layer in order to relax strain applied to the active layer to improve luminous efficiency.

However, since the pit is conventionally grown in a low-temperature atmosphere, the thin film crystallinity of GaN, which is the first semiconductor layer, is deteriorated, thereby increasing the operating voltage and decreasing the light efficiency.

It is an object of the present invention to provide a semiconductor device for improving the luminous efficiency of a semiconductor device.

The semiconductor device according to the embodiment includes a first conductivity type semiconductor layer, a plurality of growth prevention regions distributed on the first conductivity type semiconductor layer, an active layer including pits disposed on the growth prevention region, Type semiconductor layer on the first conductive type semiconductor layer.

In addition, the semiconductor device according to the embodiment may include a first conductivity type semiconductor layer, a first growth prevention region on the first conductivity type semiconductor layer, and a second growth prevention region An active layer including a pit arranged on the growth preventing region, and a second conductive type semiconductor layer on the active layer.

The semiconductor device according to the embodiment has the effect of reducing the operation voltage of the semiconductor device and improving the light efficiency by forming the growth prevention region by high temperature growth.

In addition, the embodiment has the effect of improving the internal quantum efficiency and light output by growing the growth preventing region at a high temperature condition.

In addition, the embodiment has an effect that the crystallinity of the first conductivity type semiconductor layer can be prevented from being lowered by growing the growth preventing region at a high temperature.

In addition, the embodiment has the effect of forming a high-density pit by growing the growth preventing region at a high temperature, and improving the uniformity and the operating voltage.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment.
2 is a schematic cross-sectional view mainly showing a pit generation layer of a semiconductor device according to the first embodiment.
3 is a diagram showing a pit formed on a semiconductor element according to the first embodiment and a distribution chart of a conventional pit.
4 to 10 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the first embodiment.
11 is a cross-sectional view showing a semiconductor device according to the second embodiment.
12 is a schematic cross-sectional view mainly showing the pit generation layer of the semiconductor device according to the second embodiment.
13 is a cross-sectional view showing a semiconductor device package including a semiconductor device according to the third embodiment.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG.

In the description of the embodiment according to the present invention, in the case of being described as being formed "on or under" of each element, the upper (upper) or lower (lower) or under are all such that two elements are in direct contact with each other or one or more other elements are indirectly formed between the two elements. Also, when expressed as "on or under", it may include not only an upward direction but also a downward direction with respect to one element.

The semiconductor device may include various electronic devices such as a light emitting device and a light receiving device. The light emitting device and the light receiving device may include the first conductivity type semiconductor layer, the active layer, and the second conductivity type semiconductor layer.

The semiconductor device according to this embodiment may be a light emitting device.

The light emitting device emits light by recombination of electrons and holes, and the wavelength of the light is determined by the energy band gap inherent to the material. Thus, the light emitted may vary depending on the composition of the material.

2 is a schematic sectional view mainly showing a growth prevention region of a semiconductor device according to the first embodiment, and FIG. 3 is a cross-sectional view of a semiconductor device according to the first embodiment. FIG. And the distribution of conventional pits.

1, a semiconductor device 100 according to a first embodiment includes a substrate 110, a buffer layer 120 disposed on the substrate 110, A conductive semiconductor layer 130, a plurality of growth prevention regions 140 distributed on the first conductivity type semiconductor layer 130, an active layer 150 disposed on the growth prevention region 140, An electron blocking layer 160 disposed on the active layer 150, a second conductive semiconductor layer 170 disposed on the electron blocking layer 160, a first conductive semiconductor layer 130 And a second electrode 190 disposed on the second conductive semiconductor layer 170. The first electrode 180 may be disposed on the second conductive semiconductor layer 170,

The substrate 110 may be formed of a material having excellent thermal conductivity, or may be a conductive substrate or an insulating substrate. For example, the substrate 110 may include at least one of sapphire (Al ₂ O ₃ ), SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, and Ga ₂ O ₃ . In this embodiment, Si may be used as the substrate.

A buffer layer 120 may be disposed on the substrate 110.

The buffer layer 120 relaxes the lattice mismatch between the material of the first conductive type semiconductor layer 130 and the substrate 110. The buffer layer 120 may be formed of at least one of Group III-V compound semiconductor such as GaN, InN, AlN, InGaN, AlGaN, InAlGaN, and AlInN.

The first conductive semiconductor layer 130 may be disposed on the buffer layer 120.

The first conductive semiconductor layer 130 may include, for example, an n-type semiconductor layer. The first conductive semiconductor layer 130 may be formed of a compound semiconductor. The first conductive semiconductor layer 130 may be formed of, for example, a Group II-VI compound semiconductor or a Group III-V compound semiconductor.

The first conductive semiconductor layer 130 may be formed of a semiconductor material having a composition formula of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, 0? _X + y? . The first conductive semiconductor layer 130 may be selected from among GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, An n-type dopant such as Se or Te can be doped.

The growth prevention region 140 according to the first embodiment may be disposed on the first conductivity type semiconductor layer 130.

The growth prevention region 140 can effectively create a V-shaped pit in the active layer 150 to effectively relax the strain applied to the active layer. The growth prevention region 140 will be described later in detail with reference to the drawings.

The active layer 150 may be disposed on the first conductive semiconductor layer 130 except for the growth prevention region 140. A plurality of pits P may be formed in the active layer 150. The pits P may be formed on the growth preventing region 140. [ The active layer 150 may be formed on the first conductivity type semiconductor layer 130 except for the growth prevention region.

The active layer 150 is formed by the electrons (or holes) injected through the first conductive type semiconductor layer 130 and the holes (or electrons) injected through the second conductive type semiconductor layer 170, And is a layer that emits light due to a band gap difference of an energy band according to a forming material of the light emitting layer 150. The active layer 150 may be formed of any one of a single well structure, a multi-well structure, a quantum dot structure and a quantum wire structure, but is not limited thereto.

The active layer 150 may be formed of a compound semiconductor. The active layer 150 may be implemented, for example, from Group II-VI or III-V compound semiconductors. The active layer 150 may be formed of a semiconductor material having a composition formula of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, 0? _X + y? When the active layer 150 is implemented in the multi-well structure, the active layer 150 may be formed by stacking a plurality of well layers and a plurality of barrier layers. For example, the InGaN well layer / GaN barrier layer . ≪ / RTI >

An electron blocking layer 160 (EBL) may be disposed on the active layer 150. A portion of the electron blocking layer 160 may be in contact with the top surface of the growth inhibiting region 140.

The electron blocking layer 160 functions as an electron blocking layer and a cladding of the active layer 150 (MQW cladding), thereby improving the luminous efficiency. The electron blocking layer 160 may be formed of Al _x In _y Ga _(1-xy) N (0? _{X ? 1, 0? Y ? 1} ) based semiconductor and may have a higher energy band gap than that of the active layer 150 An energy bandgap, and may be formed to a thickness of about 100 A to about 600 A, but the present invention is not limited thereto. Alternatively, the electron blocking layer 160 may be formed of a superlattice of Al _z Ga _(1-z) N / GaN (0? _Z ? 1). Alternatively, the electron blocking layer 160 may be formed to form an InAIN / GaN layer.

A part of the electron blocking layer 160 may be disposed in the pits P formed in the active layer 150. The electron blocking layer 160 disposed in the pits P may be faced to the side surface of the active layer 150.

The second conductivity type semiconductor layer 170 may be disposed on the electron blocking layer 160.

The second conductive semiconductor layer 170 may be formed of, for example, a p-type semiconductor layer. The second conductive semiconductor layer 170 may be formed of a compound semiconductor. The second conductive semiconductor layer 170 may be formed of, for example, a Group II-VI compound semiconductor or a Group III-V compound semiconductor.

The second conductive semiconductor layer 170 may be formed of a semiconductor material having a composition formula of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, 0? _X + y? . The second conductivity type semiconductor layer 170 may be selected from GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, A p-type dopant such as Sr, Ba or the like may be doped.

A part of the second conductivity type semiconductor layer 170 may be disposed in the pits P formed in the active layer 150.

Although the first conductive semiconductor layer 130 includes the n-type semiconductor layer and the second conductive semiconductor layer 170 includes the p-type semiconductor layer in the above description, Type semiconductor layer 130 may include a p-type semiconductor layer and the second conductivity type semiconductor layer 170 may include an n-type semiconductor layer.

In addition, a semiconductor layer including an n-type or p-type semiconductor layer may be further formed under the second conductive semiconductor layer 180. Accordingly, the light emitting structure may have at least one of np, pn, npn, and pnp junction structures.

The doping concentration of impurities in the first conductivity type semiconductor layer 130 and the second conductivity type semiconductor layer 170 may be uniform or non-uniform. That is, the structure of the light emitting structure (the first conductivity type semiconductor layer, the active layer, and the second conductivity type semiconductor layer) may be variously formed, but is not limited thereto.

The first electrode 180 and the second electrode 190 may be disposed on the first conductive semiconductor layer 130 and the second conductive semiconductor layer 170, 190 are connected to each other so that the fabrication of the semiconductor device can be completed.

Referring to FIG. 2, the non-growth-prevention-region growth prevention region 140 may be disposed on the first conductivity-type semiconductor layer 130. The growth prevention region 140 may be formed by distributing a plurality of growth inhibition regions 140 in a predetermined region on the first conductivity type semiconductor layer 100. The active layer 150 formed on the growth prevention region 140 is formed on the first conductivity type semiconductor layer between the growth prevention regions 140. Therefore, Lt; / RTI > layer 130 as shown in FIG.

The width A of the growth prevention region 140 may be formed to be 40 nm to 80 nm. When the width A of the growth prevention region 140 is increased, the width C of the pit P can also be increased.

 The shape of the growth prevention region 140 may have various types of cluster shapes. The growth prevention region 140 may be formed in various shapes such as circular, polygonal, and hemispherical. The minimum distance B between the growth prevention regions 140 may be formed twice or more than the width C of the pits P in order to stably form the pits P formed in the active layer 150 . For example, when the width C of the pits P is 300 to 350 nm, the minimum width B between the growth prevention regions 140 may be formed to be 600 nm to 700 nm.

The growth preventing region 140 may include MgN or ZnN. The growth prevention region 140 may include a material having a higher surface thermal energy than the active layer 150. The growth prevention region 140 may be a material having a surface energy higher than that of the GaN material.

The growth preventing region 140 is formed of MgN and ZnN, so that it can be stably formed under high temperature growth conditions.

Conventionally, since the growth preventing region is formed by low-temperature growth, the injection efficiency of the carrier is lowered in the active layer, which causes an increase in the operating voltage and a decrease in the light efficiency.

Alternatively, the embodiment can form a growth prevention region under high temperature growth conditions, thereby reducing the operating voltage and improving the light efficiency.

In addition, the embodiment can form pits of a uniform shape by growing the growth preventing region at a high temperature, and there is an effect that the internal quantum efficiency and the light output can be improved.

In addition, the embodiment has the effect of preventing the crystallinity of the first conductivity type semiconductor layer from deteriorating by growing the growth preventing region at a high temperature.

내지

의 개수로 형성되는 반면, 제1 실시예에 따른 피트 개수는

내지

의 개수로 형성될 수 있다. As shown in FIG. 3, conventionally, the number of pits

To

, Whereas the number of pits according to the first embodiment is

To

As shown in FIG.

That is, in the embodiment, the pits P having a high density (optimum density) can be formed by growing the growth prevention region at a high temperature, and the operation voltage can be improved.

Hereinafter, a manufacturing process of the semiconductor device according to the first embodiment will be described.

4 to 10 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the first embodiment.

As shown in FIG. 4, when the substrate 110 is provided, a step of forming a first buffer layer 120 on one surface of the substrate 110 is performed. The first buffer layer 120 may be formed by depositing AlN on the substrate 110 to a predetermined thickness by MOCVD (Metal Organic Chemical Vapor Deposition). The buffer layer 120 may be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or sputtering in addition to MOCVD.

When the first buffer layer 120 is formed on the substrate 110, the GAN may be deposited by MOCVD to form the first conductive semiconductor layer 130. The first conductive semiconductor layer 130 may be formed by depositing a Group 3-5 or Group 2-6 compound. In addition, the first conductive semiconductor layer 130 may be formed by depositing a silane containing an n-type impurity such as trimethyl gallium gas (TMGa), ammonia gas (NH ₃ ), nitrogen gas (N ₂ ) Gas (SiH ₄ ) may be implanted and formed.

Next, as shown in FIG. 5, the growth preventing region may be formed using Mg and NH ₃ of the first conductivity type semiconductor layer 130. At this time, the growth temperature can be grown at a high temperature condition of 900 to 950 degrees, and the pressure can be 50 torr to 150 torr. When grown under the above-described conditions, a MgN layer is formed on the entire surface of the first conductivity type semiconductor layer 130.

Then, as shown in FIG. 6, when the MgN layer is formed on the entire surface of the first conductivity type semiconductor layer, a treatment is performed for 2 to 3 minutes. When the treatment is performed, a growth prevention region 140 having a size of 40 nm to 80 nm spaced from the first conductivity type semiconductor layer 130 may be formed.

7, when the first conductivity type semiconductor layer 130 is formed in the growth prevention region 140, the active layer 150 may be formed.

The active layer 150 is selectively supplied with a source of H ₂ or / and TMGa (or TEGa), TNin, or TMAI to form a well layer made of GaN or InGaN and a barrier layer made of GaN, AlGaN, InGaN or InAlGaN .

In the initial state of growth of the active layer 150, the active layer 150 is deposited from the region between the growth prevention regions 140 due to a difference in surface thermal energy with the growth preventing region 140. When the active layer 150 is continuously deposited, A V-shaped pit P is formed in the active layer 150, as shown in Fig. That is, the pits have lower binding energy of MgN than GaN, so that the bonding energy of Mg and N is larger than the bonding of GaN and N, so GaN does not accumulate on MgN. As shown in FIG. 9, When the active layer 150 is formed on the first conductive semiconductor layer 130 excluding the first conductive semiconductor layer 140, the electron blocking layer 160 and the second conductive semiconductor layer 170 are sequentially formed on the active layer 150 .

The electron blocking layer 160 may be formed by ion implantation. For example, the electron blocking layer 160 may be formed of AlxInyGa (1-x-y) having an Al composition ranging from 1 to 30%. A portion of the electron blocking layer 160 may be in contact with the growth inhibiting region 140.

The second conductivity type semiconductor layer 170 is formed by injecting bisethylcyclopentadienyl magnesium (EtCp ₂ Mg) {Mg (C ₂ H ₅ C ₅ H ₄ ) ₂ } on the electron blocking layer 160 Accordingly, the second conductive semiconductor layer 170 may be formed of a p-type GaN layer.

10, when the second conductivity type semiconductor layer 170 is formed on the electron blocking layer 160, the mesa etching process may be performed so that a part of the first conductivity type semiconductor layer 130 is exposed. have. For example, a part of the second conductivity type semiconductor layer 170, the electron blocking layer 160, and the active layer 150 may be removed to expose the upper portion of the first conductivity type semiconductor layer 130.

The first electrode 180 may be formed on the first conductivity type semiconductor layer 130 and the second electrode 180 may be formed on the second conductivity type semiconductor layer 170. [ The electrode 190 may be formed to complete the manufacturing process of the semiconductor device according to the embodiment.

FIG. 11 is a cross-sectional view illustrating a semiconductor device according to a second embodiment, and FIG. 12 is a schematic cross-sectional view illustrating a growth prevention region of a semiconductor device according to the second embodiment.

Referring to FIG. 11, a semiconductor device 200 according to the second embodiment includes a substrate 210, a buffer layer 220 disposed on the substrate 210, A conductive semiconductor layer 230, a plurality of growth prevention regions 240 distributed on the first conductivity type semiconductor layer 230, an active layer 250 disposed on the growth prevention region 240, An electron blocking layer 260 disposed on the active layer 250, a second conductive semiconductor layer 270 disposed on the electron blocking layer 260, a first conductive semiconductor layer 230 And a second electrode 290 disposed on the second conductive semiconductor layer 270. The first electrode 280 may be disposed on the second conductive semiconductor layer 270, Here, the configuration except for the growth prevention region 240 is the same as that of the semiconductor device according to the first embodiment, and thus will not be described.

As shown in FIG. 12, the growth prevention region 240 may be disposed on the first conductive semiconductor layer 230. The growth prevention region 240 may be formed in a predetermined region on the first conductive semiconductor layer 230. The active layer 250 formed on the growth inhibiting region 240 is formed in a portion of the first conductivity type semiconductor layer 230 so that the growth prevention region 240 is formed on the first conductivity type semiconductor layer 230, And may be in physical contact with the conductive semiconductor layer 230.

The growth preventing region 240 may include a second growth preventing region 243 having a different size from the first growth preventing region 241. The growth preventing region 240 may be formed to have a width of 40 nm to 80 nm. The width A1 of the first growth preventing region 241 and the width A2 of the second growth preventing region 243 may be the same or different from each other. In addition, the thicknesses of the first growth preventing region 241 and the second growth preventing region 243 may be the same or different from each other. In the figure, the first growth preventing region 241 and the second growth preventing region 243 have different widths and thicknesses.

The width C1 of the first pit P1 formed on the upper portion of the first growth preventing region 241 and the width of the first pit P1 formed on the first growth preventing region 241 are different from each other, And the width C2 of the second pit P2 formed on the upper portion of the second growth prevention region 243 may be formed different from each other.

When the strains applied to the first conductivity type semiconductor layer 130 are different from each other, if the growth prevention regions 240 are formed in different structures, the internal quantum efficiency and the optical output power can be effectively improved .

The first growth preventing region 241 and the second growth preventing region 243 may be appropriately formed between the widths of 40 nm and 80 nm. The shape of the growth preventing region 240 may have various types of cluster shapes. The growth preventing region 240 may be formed in various shapes such as circular, polygonal, and hemispherical. The first growth preventing region 241 and the second growth preventing region 243 may have the same or different shapes.

The minimum distance B between the first growth preventing region 241 and the second growth preventing region 243 is set to be a distance between the pits P1 and P2 in order to stably form the pits P1 and P2 formed in the active layer 250. [ Of the widths C1, C2 of the first and second electrodes. The minimum distance B between the first growth preventing region 241 and the second growth preventing region 243 may be 600 nm to 700 nm when the width of any one of the pits P1 is 300 to 350 nm. have.

The first growth preventing region 241 and the second growth preventing region 243 may include MgN or ZnN. In an embodiment, the first growth preventing region 241 may be MgN, and the second growth preventing region 243 may be ZnN.

13 is a cross-sectional view showing a semiconductor device package including a semiconductor device according to the third embodiment.

The semiconductor device package 300 includes a package body 305, a third electrode layer 313 and a fourth electrode layer 314 disposed on the package body 305, And a molding member 330 surrounding the semiconductor devices 100 and 200. The first electrode layer 313 and the fourth electrode layer 314 are electrically connected to each other. Here, the semiconductor element may include the semiconductor element according to the first embodiment and the semiconductor element according to the second embodiment.

The package body 305 may be formed of a silicon material, a synthetic resin material, or a metal material, and a sloped surface may be formed on the main surface of the semiconductor device 100.

The third electrode layer 313 and the fourth electrode layer 314 are electrically isolated from each other and provide power to the semiconductor devices 100 and 200. The third electrode layer 313 and the fourth electrode layer 314 may function to increase light efficiency by reflecting the light generated from the semiconductor devices 100 and 200, And may serve to discharge heat to the outside.

The semiconductor device 100 may be disposed on the package body 305 or on the third electrode layer 313 or the fourth electrode layer 314.

The semiconductor devices 100 and 200 may be electrically connected to the third electrode layer 313 and / or the fourth electrode layer 314 by wire, flip chip or die bonding. Although the semiconductor devices 100 and 200 are electrically connected to the third electrode layer 313 and the fourth electrode layer 314 through wires, the present invention is not limited thereto.

The molding member 330 may surround the semiconductor device 100 to protect the semiconductor device 100. The molding member 330 may include a fluorescent material 332 to change the wavelength of light emitted from the semiconductor devices 100 and 200.

The above-described semiconductor device is constituted by a semiconductor device package and can be used as a light source of an illumination system, for example, as a light source of an image display device or a lighting device.

When used as a backlight unit of a video display device, it can be used as an edge type backlight unit or as a direct-type backlight unit. When used as a light source of a lighting device, it can be used as a regulator or a bulb type. It is possible.

The semiconductor device includes a laser diode in addition to the light emitting diode described above.

The laser diode may include the first conductivity type semiconductor layer, the active layer and the second conductivity type semiconductor layer having the above-described structure, similarly to the semiconductor device. Then, electro-luminescence (electroluminescence) phenomenon in which light is emitted when an electric current is applied after bonding the p-type first conductivity type semiconductor and the n-type second conductivity type semiconductor is used, And phase. That is, the laser diode can emit light having one specific wavelength (monochromatic beam) with the same phase and in the same direction by using a phenomenon called stimulated emission and a constructive interference phenomenon. It can be used for optical communication, medical equipment and semiconductor processing equipment.

As the light receiving element, a photodetector, which is a kind of transducer that detects light and converts the intensity of the light into an electric signal, is exemplified. As such a photodetector, a photodiode (e.g., a PD with a peak wavelength in a visible blind spectral region or a true blind spectral region), a photodiode (e.g., a photodiode such as a photodiode (silicon, selenium), a photoconductive element (cadmium sulfide, cadmium selenide) , Photomultiplier tube, phototube (vacuum, gas-filled), IR (Infra-Red) detector, and the like.

In addition, a semiconductor device such as a photodetector may be fabricated using a direct bandgap semiconductor, which is generally excellent in photo-conversion efficiency. Alternatively, the photodetector has a variety of structures, and the most general structure includes a pinned photodetector using a pn junction, a Schottky photodetector using a Schottky junction, and a metal-semiconductor metal (MSM) photodetector have.

The photodiode, like the light emitting device, may include the first conductivity type semiconductor layer having the structure described above, the active layer, and the second conductivity type semiconductor layer, and may have a pn junction or a pin structure. The photodiode operates by applying reverse bias or zero bias. When light is incident on the photodiode, electrons and holes are generated and a current flows. At this time, the magnitude of the current may be approximately proportional to the intensity of the light incident on the photodiode.

A photovoltaic cell or a solar cell is a type of photodiode that can convert light into current. The solar cell, like the light emitting device, may include the first conductivity type semiconductor layer, the active layer and the second conductivity type semiconductor layer having the above-described structure.

In addition, it can be used as a rectifier of an electronic circuit through a rectifying characteristic of a general diode using a p-n junction, and can be applied to an oscillation circuit or the like by being applied to a microwave circuit.

In addition, the above-described semiconductor element is not necessarily implemented as a semiconductor, and may further include a metal material as the case may be. For example, a semiconductor device such as a light receiving element may be implemented using at least one of Ag, Al, Au, In, Ga, N, Zn, Se, P, or As, The present invention may be embodied in other forms without departing from the spirit or essential characteristics of the inventive concept, and it is to be understood that the invention is not limited to the disclosed embodiments, It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

110: substrate 120: buffer layer
130: first conductivity type semiconductor layer 140: pit generation layer
150: active layer 160: electron blocking layer
170: second conductivity type semiconductor layer 180: first electrode

Claims (16)

A first conductive semiconductor layer;
A plurality of growth prevention regions distributed on the first conductivity type semiconductor layer;
An active layer including pits disposed on the growth preventing region; And
And a second conductivity type semiconductor layer on the active layer. The method according to claim 1,
Wherein the active layer is in contact with the first conductivity type semiconductor layer between the growth prevention regions. The method according to claim 1,
Wherein the growth preventing region has a width of 40 nm to 80 nm. The method according to claim 1,
And the width between the growth prevention regions is at least twice the width of the pits. 5. The method of claim 4,
And the distance between the growth prevention regions is 600 nm to 700 nm. The method according to claim 1,
The number of the growth preventing regions is

To

≪ / RTI > 7. The method according to any one of claims 1 to 6,
Wherein the growth prevention region is a nitride including a material having a higher surface energy than the active layer. 8. The method of claim 7,
Wherein the growth prevention region includes MgN and ZnN. A first conductive semiconductor layer;
A growth preventing region including a first growth preventing region on the first conductive type semiconductor layer and a second growth preventing region having a different size and spaced apart from the first growth preventing region;
An active layer including pits disposed on the growth preventing region; And
And a second conductivity type semiconductor layer on the active layer. 10. The method of claim 9,
Wherein the thickness of the second growth preventing region is larger than the thickness of the first growth preventing region. 11. The method of claim 10,
And the width of the pit on the second growth preventing region is smaller than the width of the pit on the first growth preventing region. 12. The method according to any one of claims 9 to 11,
Wherein the growth preventing region has a width of 40 nm to 80 nm. 13. The method of claim 12,
And the width between the growth prevention regions is at least twice the width of the pits. 13. The method of claim 12,
And the distance between the growth prevention regions is 600 nm to 700 nm. 13. The method of claim 12,
The number of the growth preventing regions is

To

≪ / RTI > 13. The method of claim 12,
Wherein the first growth preventing region includes MgN, and the second growth preventing region includes ZnN.

Images