KR20180004530A - Cmos image sensor having generating ramp signal - Google Patents

Abstract

The present invention relates to a technique for reducing the size and power consumption of a CMOS image sensor by simplifying a component of a ramp signal generator of the CMOS image sensor. In the CMOS image sensor including the ramp signal generator according to the present invention, the ramp signal generator includes: a lower offset switch and a lower offset voltage source which are serially connected between a ground terminal and a common node; a lower reset switch and a lower reset voltage source which are serially connected between the ground terminal and the common node; an upper current source and an upper switch which are serially connected between a power supply voltage and the common node; and an amplifier which amplifies a voltage outputted through the common node and outputs a ramp voltage according to the amplified voltage.

Description

≪ Desc / Clms Page number 1 > CMOS IMAGE SENSOR HAVING GENERATING RAMP SIGNAL <

The present invention relates to a CMOS image sensor having a lamp signal generator, and more particularly to a CMOS image sensor having a lamp signal generator for simplifying the components of the lamp signal generator and reducing the size and power consumption thereof .

A CMOS image sensor (CIS) converts light received from the outside into electrical signals, and converts the electrical signals thus converted into digital signals. Such a CMOS image sensor requires a high pixel for high image quality and a high frame rate in a moving image mode.

As a single slope analog-digital converter used in a CMOS image sensor, a lamp signal generator is a typical example. The ramp signal generator generates a ramp signal corresponding to the on / off state of the current cell, and the ramp signal thus generated is utilized as a reference signal for an analog-to-digital converter or the like.

Accordingly, the conventional CMOS image sensor has a problem that the number of current cells increases as the resolution of the analog-to-digital converter increases, thereby increasing the size of the CMOS image sensor.

In addition, in order to operate the single slope analog-digital converter at high speed, the frequency of the clock signal must be increased, which consumes a large amount of power.

In addition, crosstalk noise is severely caused by control lines for controlling the operation of the current cell.

SUMMARY OF THE INVENTION The present invention is directed to a CMOS image sensor having a ramp signal generator, in which a current source, a capacitor, and an output buffer are simply formed to reduce size and power consumption.

According to an aspect of the present invention, there is provided a CMOS image sensor having a ramp signal generator, comprising: a pixel array for image sensing; A driver / address decoder for controlling the operation of the pixel array in row or column units; A control circuit for generating a control signal for controlling an operation timing of each component of the CMOS image sensor; And a ramp signal generator for interrupting a current source and a voltage source under the control of the control circuit to generate a ramp voltage according to the ramp signal. The ramp signal generator includes a common node and a ground terminal A sub offset switch and a sub offset voltage source serially connected between the sub offset switch and the sub offset switch; A lower reset switch and a lower reset voltage source serially connected between the common node and the ground terminal; An upper current source and an upper switch connected in series between a power supply voltage and the common node; And an amplifier for amplifying a voltage output through the common node and outputting a ramp voltage according to the amplified voltage.

According to a second aspect of the present invention, there is provided a CMOS image sensor having a ramp signal generator, comprising: a pixel array for image sensing; A driver / address decoder for controlling the operation of the pixel array in row or column units; A control circuit for generating a control signal for controlling an operation timing of each component of the CMOS image sensor; And a ramp signal generator for interrupting a current source and a voltage source under the control of the control circuit to generate a ramp voltage according to the ramp signal. The ramp signal generator includes a common node and a ground terminal An upper offset switch and an upper offset voltage source connected in series between the upper offset switch and the upper offset switch; An upper reset switch and an upper reset voltage source connected in series between the common node and the ground terminal; A lower switch and a lower current source connected between the common node and the ground terminal; A capacitor for a lamp voltage connected between the common node and the ground terminal; And an amplifier for amplifying a voltage output through the common node and outputting a ramp voltage according to the amplified voltage.

According to a third aspect of the present invention, there is provided a CMOS image sensor having a ramp signal generator, comprising: a pixel array for image sensing; A driver / address decoder for controlling the operation of the pixel array in row or column units; A control circuit for generating a control signal for controlling an operation timing of each component of the CMOS image sensor; And a ramp signal generator for interrupting a current source and a voltage source under the control of the control circuit to generate a ramp voltage according to the ramp signal. The ramp signal generator includes a common node and a ground terminal A sub offset switch and a sub offset voltage source serially connected between the sub offset switch and the sub offset switch; A lower reset switch and a lower reset voltage source serially connected between the common node and the ground terminal; An upper offset switch and an upper offset voltage source connected in series between the common node and the ground terminal; An upper reset switch and an upper reset voltage source connected in series between the common node and the ground terminal; A variable upper current source and an upper switch connected in series between a power supply voltage and the common node; A lower switch and a variable sub-current source connected in series between the common node and the ground terminal; A variable capacitor for variable lamp voltage connected between the common node and the ground terminal; And an amplifier for amplifying a voltage output through the common node and outputting a ramp voltage according to the amplified voltage.

In implementing the CMOS image sensor having the ramp signal generator, the present invention can reduce the size and power consumption of the CMOS image sensor by simply configuring the CMOS image sensor with only the current source, the capacitor, and the output buffer.

The present invention has the effect of automatically controlling the value of the reference current according to the clock frequency of the CMOS image sensor.

1 is a block diagram of a CMOS image sensor having a ramp signal generator according to an embodiment of the present invention.
FIG. 2A is a detailed block diagram of a first embodiment of a ramp signal generator in FIG.
2 (a) to 2 (d) are waveform diagrams of FIG. 2a.
FIG. 3A is a detailed block diagram of a second embodiment of a ramp signal generator in FIG.
3 (a) to 3 (d) are waveform diagrams of the respective parts of Fig. 3a.
FIG. 4 shows an example in which the lower offset voltage source and the lower reset voltage source are implemented in a variable manner in the first embodiment.
5 shows an example in which an upper offset voltage source and an upper reset voltage source are implemented as variable strings in the second embodiment.
6A shows an example in which an upper current source and a capacitor for a ramp voltage are implemented in a variable manner in the first embodiment.
6 (a) to 6 (d) are waveform diagrams of the respective portions of Fig. 6a.
FIG. 7A shows an example in which a sub-current source and a capacitor for a ramp voltage are implemented in a variable manner in the second embodiment.
Figs. 7A to 7D are waveform diagrams of respective portions of Fig. 7A.
8A is a block diagram of a third embodiment combining the first embodiment and the second embodiment together.
8A to 8E are waveform diagrams of the respective parts of Fig. 8A.
FIG. 9A is a circuit diagram of the first embodiment of an upper current source in FIG. 2A. FIG.
FIG. 9B is a circuit diagram of the second embodiment for an upper current source in FIG. 2A. FIG.
FIG. 9C is a circuit diagram of the third embodiment of the upper current source in FIG. 2A. FIG.
FIG. 10 is a detailed circuit diagram of an embodiment of the current source in FIG. 8A.
11 is a detailed circuit diagram of an embodiment of the current source unit in FIG.
12A is a circuit diagram showing a variable resistor implemented by a switched capacitor in FIG.
12B shows the switching timing of the switch in Fig. 12A.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a CMOS image sensor having a ramp signal generator according to an embodiment of the present invention. As shown in FIG. 1, the CMOS image sensor 100 includes a pixel array 110, a driver / address decoder 120 A control circuit 130, a ramp signal generator 140, a comparison unit 150, and a counter unit 160.

The pixel array 110 includes a plurality of pixels arranged in a matrix form in order to convert incident light into electrical analog signals by unit elements (e.g., unit pixels) for image sensing and output the converted electrical analog signals.

The driver / address decoder 120 controls the operation of the pixel array 110 in units of rows and / or columns.

The control circuit 130 generates a control signal CTRL1 (CTRL2) for controlling the operation timing of each component of the CMOS image sensor 100. [

The ramp signal generator 140 interrupts the current source and the voltage source according to the control signal CTRL1 and generates a ramp voltage VRAMP corresponding thereto.

The analog pixel signals read from the pixel array 110 are converted into digital signals by an analog-to-digital converter implemented in the comparator 150 and the counter 160. The pixel signals are output and processed in units of columns. For this purpose, the comparator 150 and the counter 160 may include a plurality of comparators 151 and a plurality of counter circuits 161, each of which is provided for each column. By processing the pixel signals of one row at a time in parallel by using a plurality of signal processing means provided on a column by column basis, the CMOS image sensor 100 has improved performance in terms of band performance and noise, Lt; / RTI >

The pixel array 110 sequentially outputs a first analog signal representing a reset component for correlated double sampling and a second analog signal representing an image signal component. In contrast, the analog-to-digital converter performs digital correlation double sampling, i.e., digital double sampling, based on the first analog signal and the second analog signal.

2A is a detailed block diagram of the first embodiment of the ramp signal generator 140. As shown in FIG. 2A, a lower offset switch SW _{OFFSET_BOT} connected in series between the common node N and a ground terminal, of the offset voltage source (V _{OFFSET_BOT),} the common node (N) and the sub-reset switch connected in series between the ground terminal (SW _{RESET_BOT)} and sub-reset voltage source (V _{RESET_BOT),} supply voltage (VDD) and the common node (N) connected in series top between the current source (I _{RAMP_UP)} and an upper switch (SW _UP), the capacitor for the lamp voltage is connected between the common node (N) and a ground terminal (C _rAMP) and outputted through the common node (N) And an amplifier (AMP) for amplifying the voltage and outputting the corresponding ramp voltage (V _RAMP ).

2 (a) to 2 (d) are waveform diagrams of the respective parts of FIG. 2a, and the operation of FIG. 2a will be described with reference to FIG.

Lower offset switch (SW _{_BOT OFFSET)} is timing the switching operation, such as (a) in Figure 2b by a control signal (CTL11) supplied from the control circuit 130. Thus, the voltage of the lower offset voltage source V _{OFFSET_BOT} is supplied to the common node N at the timing shown in FIG. 2B (a).

The lower reset switch SW _{RESET_BOT} is switched by the control signal CTL12 supplied from the control circuit 130 at the timing shown in FIG. 2B (b). Accordingly, it is supplied to the sub-reset voltage source of the voltage of Figure 2b (V _{RESET _BOT)} (b) and a common node (N) with the same timing.

The upper switch SW _UP is switched by the control signal CTL13 supplied from the control circuit 130 at the timing shown in Fig. 2B (c). Accordingly, the current of the high-current source (I _{_UP RAMP)} is fed to (c) and a common node (N) with the same timing as in Figure 2b.

Therefore, the amplifier AMP outputs the ramp voltage V _RAMP of the rising type as shown in (d) of FIG. 2B. That is, the lamp voltage (V _RAMP ) is maintained at the level of the lower offset voltage (V _{OFFSET - - BOT} ) in the section where only the lower reset switch (SW _{RESET - - BOT} ) is ON.

Then, the sub-offset switch (SW _{_BOT OFFSET)} is turned off, the lower the reset switch (SW _{RESET_BOT)} the lamp in the period ondoen voltage (V _RAMP) is held at the level of the sub-reset voltage (V _{RESET_BOT).}

However, the lower-offset switch (SW _{OFFSET _BOT)} and lower reset switch (SW _{RESET_BOT)} is completely turned off, the top switch (SW _UP) is ondoen interval in the following Equation 1 rises in the form of a ramp voltage which is determined by the (V _RAMP ).

Here, the ramp voltage capacitor C _RAMP serves to convert the current (I _{RAMP - - UP} ) supplied for a predetermined period of time t through the common node N into a voltage.

Value of the voltage of the lower-offset voltage source (V _{OFFSET _BOT),} lower reset voltage source (V _{RESET_BOT)} can be determined by the user to adjust the value in a register in the control circuit 130 via the user interface (SPI or I2C Interface) .

3A is a detailed block diagram of a second embodiment of the ramp signal generator 140. As shown in FIG. 3A, an upper offset switch SW _{OFFSET_TOP} connected in series between a common node N and a ground terminal, an offset voltage source (V _{OFFSET_TOP),} coupled between said common node (N) and the higher the reset switch (SW _{RESET_TOP)} and a higher-reset voltage source connected in series between the ground terminal (V _{RESET_TOP),} the common node (N) and the ground terminal and through the lower switch (SW _DN) and a lower current source (I _{RAMP_DN),} the common node (N) and the lamp voltage capacitor (C _rAMP) and the common node (N) connected between the ground terminal to amplify the voltage output And an amplifier (AMP) for outputting a ramp voltage (V _RAMP ) corresponding thereto.

FIG. 3B is a waveform diagram of each part of FIG. 3A. Referring to FIG. 3A, the operation of FIG. 3A will be described below.

Top offset switch (SW _{_TOP OFFSET)} is timing the switching operation, such as (a) of Figure 3b by the control signal (CTL11) supplied from the control circuit 130. Accordingly, the voltage of the upper offset voltage source V _{OFFSET_TOP} is supplied to the common node N at the timing shown in Fig. 3B (a).

The upper reset switch SW _{RESET_TOP} is switched by the control signal CTL12 supplied from the control circuit 130 at the timing shown in FIG. 3B (b). Accordingly, it is supplied to the high-voltage source of the reset voltage of FIG. 3b of (V _{RESET _TOP)} (b) and a common node (N) with the same timing.

The lower switch SW _DN is switched by the control signal CTL13 supplied from the control circuit 130 at the timing shown in FIG. 3B (c). Accordingly, the current of the sub-current source (I _{RAMP DN _)} is supplied to the common node (N) with the same timing as the (c) of Figure 3b.

Therefore, the amplifier AMP outputs the ramp voltage V _RAMP of the falling type as shown in (d) of FIG. 3B. That is, only the lamp voltage in the period ondoen upper reset switch _{(SW RESET _TOP) (V RAMP} ) is held at the level of the upper offset voltage (V _{OFFSET _TOP).}

Then, the top offset switch (SW _{_TOP OFFSET)} is turned off, the upper reset switch (SW _{RESET_TOP)} the lamp in the period ondoen voltage (V _RAMP) is held at the level of the higher reset voltage (V _{RESET_TOP).}

However, the higher is the offset switch (SW _{OFFSET _TOP)} and upper reset switch (SW _{RESET_TOP)} are both turned off, the sub-switch (SW _DN) ondoen section form of falling is determined by the following Equation (2) of the lamp voltage (V _RAMP ).

Here, the ramp voltage capacitor C _RAMP serves to convert the current (I _{RAMP - - UP} ) supplied for a predetermined period of time t through the common node N into a voltage.

Value of the voltage of the higher offset voltage source (V _{OFFSET _TOP),} higher reset voltage source (V _{RESET_TOP)} can be determined by the user to adjust the value in a register in the control circuit 130 via the user interface (SPI or I2C Interface) .

4 is implemented to replace the lower offset voltage source (V _{OFFSET_BOT)} and a lower reset voltage source (V _{RESET _BOT)} a variable lower offset voltage source (V _{OFFSET_BOT_va)} and the variable lower reset voltage source (V _{RESET _BOT_va)} in the first embodiment of Figure 2a An example is shown.

5 is implemented to replace the higher offset voltage source (V _{OFFSET_TOP)} and upper reset voltage source (V _{RESET _TOP)} the variable upper offset voltage source (V _{OFFSET_TOP_va)} and the variable upper reset voltage source (V _{RESET _TOP_va)} in the second embodiment of Figure 3a For example.

6a is implemented by replacing in the first embodiment the upper current source (I _{RAMP_UP)} and capacitors for the lamp voltage (C _RAMP) a variable high-current source (I _{RAMP _UP_Va)} with variable ramp voltage variable capacitor (C _{RAMP_Va)} for in the Fig. 2a For example. In such a case, the ramp voltage V _RAMP may be outputted in a form in which the slope is variable as shown in (d) of FIG.

7a is replaced with a sub-current source (I _{RAMP _ DN} and capacitors for the lamp voltage (C _RAMP) a variable sub-current source (I _{RAMP _ DN _Va)} with variable ramp voltage capacitor (C _{RAMP_Va)} for the second embodiment of Figure 3a In this case, the ramp voltage V _RAMP may be outputted in a form of varying slope as shown in (d) of FIG. 7B.

Meanwhile, FIG. 8A is a block diagram showing a third embodiment combining the first embodiment of FIG. 2A and the second embodiment of FIG. 3A in a combined manner. As shown in FIG. 8A, connected to the lower offset switch (SW _{OFFSET_BOT)} and low offset voltage source (V _{OFFSET_BOT),} the common node (N) and the ground sub-reset switch connected in series between the terminal (SW _{RESET_BOT)} and sub-reset voltage source (V _{RESET_BOT),} the common node An upper offset switch SW _{RESET_TOP} and an upper offset voltage source V _{OFFSET_TOP} connected in series between the common node N and the ground terminal, an upper reset switch SW _{RESET_TOP} connected in series between the common node N and the ground terminal, A variable upper current source I _{RAMP_UP_Va} and an upper switch SW _UP connected in series between the reset voltage source V _{RESET_TOP} , the power source voltage VDD and the common node N, and a series connection between the common node and the ground terminal Child Swear (SW _DN) and a variable sub-current source (I _{RAMP_DN_va),} the common node (N) and a variable capacitor, variable ramp voltage is coupled between the ground terminal (C _{RAMP_Va)} and amplifying the voltage outputted through said common node (N) And an amplifier (AMP) for outputting the corresponding lamp voltage (V _RAMP ).

Switching timing of the switch sub-offset _{(OFFSET _BOT} SW) is equal to (a) of Figure 8b, the switching timing of the sub-reset switch _(RESET SW _{_BOT)} is shown in (b) of Fig. 8b.

The ON and OFF intervals of the upper switch SW _UP are included in the OFF period of one cycle of the lower reset switch SW _{RESET_BOT} as shown in FIGS. 8B and 8B.

As shown in (b) and (d) of FIG. 8B, ON and OFF intervals of the lower switch SW _DN are included in the OFF period of one period of the lower reset switch SW _{RESET_BOT} .

As a result, the rise and fall in the off-period of one period of the output waveform is the sub-reset switch (SW _{RESET _BOT)} as shown in (e) of Figure 8b of the ramp voltage (V _RAMP) is output through the amplifier (AMP) It has a repeated section.

FIG. 9A is a circuit diagram of the first embodiment of the upper current source I _{RAMP_UP} in FIG. 2A, wherein one terminal (source) is connected to the power supply voltage VDD and the other terminal The first MOS transistor M1 is connected to the power supply voltage VDD and the other terminal is connected to the gate of the first MOS transistor M1. And a variable current source R _{BIAS_va} connected between the other terminal of the second MOS transistor M2 and the ground terminal. Here, the MOS transistors M1 and M2 may be P-channel MOS transistors.

FIG. 9B is a circuit diagram of the second embodiment of the upper current source I _{RAMP_UP} in FIG. 2A. Referring to FIG. 9B, the first MOS transistor M1 has one terminal connected to the power supply voltage VDD, A second MOS transistor M2 whose gate is connected to the gate of the first MOS transistor M1 in common and whose one terminal is connected to the other terminal of the first MOS transistor M1, A third MOS transistor M3 for generating an output current to the terminal of the second MOS transistor M2, a first terminal connected to the other terminal of the second MOS transistor M2, and a second terminal connected to the gate of the second MOS transistor M2, A first variable current source R _{BIAS1_va} connected between the other terminal of the fourth MOS transistor M4 and the ground terminal and a second variable current source R _{BIAS1_va} connected to the power source voltage VDD, The three MOS transistors M3 and A fifth MOS transistor M5 commonly connected to the gate of the fourth MOS transistor M4 and a second variable current source R _{BIAS2_va} connected between the other terminal of the fifth MOS transistor M5 and the ground terminal do. Here, the MOS transistors M1-M5 may be P-channel MOS transistors.

The current source used in the ramp signal generator of the CMOS image sensor 100 requires a large output resistance value and a wide output range. However, the upper current source circuit of FIG. 9B is a wide swing cascode current source structure, which assures a relatively wide output range and a large value of output resistance that are not affected by a threshold voltage.

FIG. 9C is a circuit diagram of the third embodiment of the upper current source I _{RAMP_UP} in FIG. 2A. Referring to FIG. 9C, the first MOS transistor M1 has one terminal connected to the power supply voltage VDD, A second MOS transistor M2 whose gate is connected to the gate of the first MOS transistor M1 in common and whose one terminal is connected to the other terminal of the first MOS transistor M1, A third MOS transistor M3 for generating an output current to the terminal of the second MOS transistor M2, a first terminal connected to the other terminal of the second MOS transistor M2, and a second terminal connected to the gate of the second MOS transistor M2, A first variable current source R _{BIAS1_va} connected between the other terminal of the fourth MOS transistor M4 and the ground terminal and a second variable current source R _{BIAS1_va} connected to the power source voltage VDD, 4 of the MOS transistor M4 Sites fifth MOS transistor (M5), the fifth second variable current source connected between the other terminal and the ground terminal of the MOS transistor (M5) (R _{BIAS2_va)} and both input terminals of the first MOS transistor (M1) is connected to the And an operational transconductance amplifier (OTA _N ) connected to the other terminal of the second MOS transistor (M2) and having an output terminal connected to the gate of the third MOS transistor (M3). Here, the MOS transistors M1-M5 may be P-channel MOS transistors.

FIG. 9C illustrates a gain boosting scheme applied to a gain boosting scheme. The output range is similar to that of FIG. 9B. However, when the value of the output resistance becomes larger and the voltage gain becomes equal to A _ota .

9A to 9C, the variable current source is shown in the form of a resistor because it is a form of a variable current source.

FIG. 10 is a detailed circuit diagram of an embodiment of the current source 141 in FIG. 8A. Here, the higher the current source (I _{RAMP _UP)} and a lower current source (I _{RAMP_DN)} can be adjusted to designed on the same principle, to adjust the variable current source (I _{CP1_va)} current source unit configured to (I _{CP2_va)} (141A) output current.

11 is a detailed circuit diagram of an embodiment of the current source unit 141A in FIG. Here, the value of the output current I _CP can be determined by adjusting the variable resistor R _{CP _va} . When the output currents I _CP1 and I _CP2 are adjusted, the values of the output currents I _{RAMP_UP} and I _{RAMP_DN} of the current source 141 are adjusted.

12A is a circuit diagram _{showing a} variable resistor R _{CP _va} in FIG. 11 as a switched capacitor. In this case, the reference current value can be automatically controlled according to the clock frequency f _clk of the CMOS image sensor 100. Equivalent resistance (Req) of the variable resistance (R _{_va CP)} is determined in the following [Equation 3] on the.

의 관계를 이용하여 필요한 저항값에 맞도록 커패시터(C_{CP_va})의 값을 조절할 수 있다. 그리고, 도 12a에서 저역필터(LPF1,LPF2)는 높은 주파수 성분의 노이즈를 필터링하기 위해 사용된 것이다.Therefore, R _CP = R _eq =

The value of the capacitor C _{CP_va} can be adjusted to meet the required resistance value. In FIG. 12A, the low-pass filters LPF1 and LPF2 are used for filtering noise of a high frequency component.

12B shows the switching timings of the switches SW _CP1 and SW _CP2 in Fig. 12A. Where SW _CP1 and SW _CP2 are non-overlapping clocks.

Although the preferred embodiments of the present invention have been described in detail above, it should be understood that the scope of the present invention is not limited thereto. These embodiments are also within the scope of the present invention.

100: CMOS image sensor 110: pixel array
120: driver / address decoder 130: control circuit
140: lamp signal generator 141: current source
150: comparator 160: counter

Claims (18)

A pixel array for image sensing;
A driver / address decoder for controlling the operation of the pixel array in row or column units;
A control circuit for generating a control signal for controlling an operation timing of each component of the CMOS image sensor; And
And a ramp signal generator for interrupting a current source and a voltage source under the control of the control circuit to generate a ramp voltage according to the ramp signal, the CMOS image sensor comprising:
The ramp signal generator
A lower offset switch and a lower offset voltage source connected in series between the common node and the ground terminal;
A lower reset switch and a lower reset voltage source serially connected between the common node and the ground terminal;
An upper current source and an upper switch connected in series between a power supply voltage and the common node; And
And an amplifier for amplifying a voltage output through the common node and outputting a corresponding lamp voltage.
2. The image sensor of claim 1, wherein the CMOS image sensor
And a lamp voltage capacitor connected between the common node and the ground terminal.
The method of claim 1,
Wherein the low reset voltage is maintained at a level of a lower offset voltage in an ON period of the low reset switch.
The method of claim 1,
Wherein the low offset switch is turned off and the low reset voltage is maintained at a level of a low reset voltage in the ON period of the low reset switch.
The method of claim 1,
Wherein the lower offset switch and the lower reset switch are both turned off and the upper switch is turned on in a turned-on period.
2. The CMOS image sensor as claimed in claim 1, wherein the lower offset voltage source and the lower reset voltage source are of a variable type.
2. The CMOS image sensor as claimed in claim 1, wherein the upper current source is a variable type.
The method of claim 1, wherein the upper current source
A first MOS transistor having one terminal connected to the power supply voltage and the other terminal generating an output current;
A second MOS transistor having one terminal connected to the power supply voltage and the other terminal and the gate connected in common to the gate of the first MOS transistor; And
And a variable current source connected between the other terminal of the second MOS transistor and the ground terminal.
The method of claim 1, wherein the upper current source
A first MOS transistor having one terminal connected to a power supply voltage;
A second MOS transistor whose one terminal is connected to the power supply voltage and whose gate is commonly connected to the gate of the first MOS transistor;
A third MOS transistor having one terminal connected to the other terminal of the first MOS transistor and generating an output current at the other terminal;
A fourth MOS transistor having one terminal connected to the other terminal of the second MOS transistor and the other terminal connected to the gate of the second MOS transistor;
A first variable current source connected between the other terminal of the fourth MOS transistor and the ground terminal;
A fifth MOS transistor having one terminal connected to the power supply voltage and the other terminal commonly connected to the gates of the third MOS transistor and the fourth MOS transistor; And
And a second variable current source connected between the other terminal of the fifth MOS transistor and the ground terminal.
The method of claim 1, wherein the upper current source
A first MOS transistor having one terminal connected to a power supply voltage;
A second MOS transistor whose one terminal is connected to the power supply voltage and whose gate is commonly connected to the gate of the first MOS transistor;
A third MOS transistor having one terminal connected to the other terminal of the first MOS transistor and generating an output current at the other terminal;
A fourth MOS transistor having one terminal connected to the other terminal of the second MOS transistor and the other terminal connected to the gate of the second MOS transistor;
A first variable current source connected between the other terminal of the fourth MOS transistor and the ground terminal;
A fifth MOS transistor having one terminal connected to the power supply voltage and the other terminal connected to the gate of the fourth MOS transistor;
A second variable current source connected between the other terminal of the fifth MOS transistor and the ground terminal; And
And an operational transconductance amplifier whose both input terminals are connected to the other terminal of the first MOS transistor and the second MOS transistor and whose output terminal is connected to the gate of the third MOS transistor. CMOS image sensor.
A pixel array for image sensing;
A driver / address decoder for controlling the operation of the pixel array in row or column units;
A control circuit for generating a control signal for controlling an operation timing of each component of the CMOS image sensor; And
And a ramp signal generator for interrupting a current source and a voltage source under the control of the control circuit to generate a ramp voltage according to the ramp signal, the CMOS image sensor comprising:
The ramp signal generator
An upper offset switch and an upper offset voltage source connected in series between the common node and the ground terminal;
An upper reset switch and an upper reset voltage source connected in series between the common node and the ground terminal;
A lower switch and a lower current source connected between the common node and the ground terminal;
A capacitor for a lamp voltage connected between the common node and the ground terminal; And
And an amplifier for amplifying a voltage output through the common node and outputting a corresponding lamp voltage.
12. The method of claim 11,
And the upper reset switch is maintained at a level of the upper offset voltage in an ON period of the upper reset switch.
12. The method of claim 11,
The upper offset switch is turned off, and the upper reset switch is maintained at the level of the upper reset voltage in the ON period.
12. The method of claim 11,
Wherein the upper offset switch and the upper reset switch are both turned off and the lower switch is lowered in a turned-on period.
12. The CMOS image sensor as claimed in claim 11, wherein the upper offset voltage source and the upper reset voltage source are of a variable type.
12. The CMOS image sensor of claim 11, wherein the sub-current source is of a variable type.
A pixel array for image sensing;
A driver / address decoder for controlling the operation of the pixel array in row or column units;
A control circuit for generating a control signal for controlling an operation timing of each component of the CMOS image sensor; And
And a ramp signal generator for interrupting a current source and a voltage source under the control of the control circuit to generate a ramp voltage according to the ramp signal, the CMOS image sensor comprising:
The ramp signal generator
A lower offset switch and a lower offset voltage source connected in series between the common node and the ground terminal;
A lower reset switch and a lower reset voltage source serially connected between the common node and the ground terminal;
An upper offset switch and an upper offset voltage source connected in series between the common node and the ground terminal;
An upper reset switch and an upper reset voltage source connected in series between the common node and the ground terminal;
A current source including a variable upper current source and an upper switch connected in series between a power supply voltage and the common node, and a lower switch and a variable lower current source connected in series between the common node and the ground terminal;
A variable capacitor for variable lamp voltage connected between the common node and the ground terminal; And
And an amplifier for amplifying a voltage output through the common node and outputting a corresponding lamp voltage.
18. The apparatus according to claim 17, wherein the current source unit
And a current source unit for adjusting an output current, wherein the current source unit is a variable resistor composed of a switched capacitor.

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