KR20180002967A - Light valve panel and liquid crystal display device using the same - Google Patents

Abstract

According to the present invention, a light valve panel comprises upper and lower substrates. A light valve common electrode is disposed on the upper substrate. The lower substrate faces the upper substrate with a liquid crystal layer interposed therebetween, and includes a light valve data line, a light valve gate line, and an integrated light valve pixel electrode applied with voltage through a plurality of feed nodes. A region where the light valve data line and the light valve gate line cross each other, is defined as a block. Each block includes a switching transistor and a driving transistor. A drain electrode and a gate electrode of the switching transistor are connected to the light valve data line and the light valve gate line, respectively. The driving transistor is disposed between the switching transistor and the feed nodes to adjust voltage of the feed nodes in accordance with voltage of the gate electrode connected to a source electrode of the switching transistor.

Description

TECHNICAL FIELD [0001] The present invention relates to a light valve panel and a liquid crystal display device using the same. BACKGROUND OF THE INVENTION [0002]

The present invention relates to a light valve panel for adjusting the amount of light incident on a display panel based on a luminance distribution of an input image, and a liquid crystal display using the same.

An organic light emitting diode (OLED) display, a plasma display panel (PDP), an electrophoretic display device (EPD), a liquid crystal display (LCD) Various flat panel display devices have been developed. A liquid crystal display device displays an image by controlling an electric field applied to liquid crystal molecules in accordance with a data voltage. A thin film transistor (hereinafter referred to as "TFT") is formed for each pixel in an active matrix driving liquid crystal display device.

A liquid crystal display device includes a display panel having a liquid crystal layer, a backlight unit (BLU) for irradiating light to the display panel, a source drive integrated circuit (hereinafter referred to as " A gate driver IC for supplying gate pulses (or scan pulses) to the gate lines (or scan lines) of the display panel, and a control circuit for controlling the ICs, a light source of the backlight unit And a light source driving circuit for driving the light source.

The gradation of the input image is expressed by the data voltage applied to the liquid crystal layer of the display panel. The liquid crystal display device has poor reproducibility of dark images due to the backlight. This is because the backlight unit irradiates the entire screen of the display panel with a uniform amount of light irrespective of the luminance distribution of the input image. Therefore, there is a limit in improving the contrast ratio of the liquid crystal display device.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a light valve panel for adjusting the amount of light incident on a display panel according to an input image to improve a contrast ratio, and a liquid crystal display using the same.

A light valve panel according to the present invention includes an upper substrate and a lower substrate. A light valve common electrode is disposed on the upper substrate. The lower substrate faces the upper substrate with the liquid crystal layer interposed therebetween, and includes a light valve data line, a light valve gate line, and an integrated light valve pixel electrode receiving a voltage through the plurality of power supply nodes. The area where the light valve data line and the light valve gate line intersect is defined as a block. Each block includes a switching transistor and a driving transistor. The drain electrode and the gate electrode of the switching transistor are connected to the light valve data line and the light valve gate line, respectively. The driving transistor is disposed between the switching transistor and the power supply node, and adjusts the voltage of the power supply node according to the voltage of the gate electrode connected to the source electrode of the switching transistor.

The present invention can prevent luminance and color distortion at a side viewing angle and prevent a bright line phenomenon by adjusting the luminance to gradation so that the luminance gradually increases or decreases in a block of the light valve panel.

In particular, the present invention can reduce the number of driving signal lines for applying a voltage to a block of a light valve panel, and is suitable for a high-resolution display device.

1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.
2 is a cross-sectional view illustrating a laminated structure of the display panel, the light valve panel, and the backlight unit shown in FIG.
3 is a schematic view showing a planar array structure of a light valve panel according to the present invention.
4 is a plan view showing a light valve panel according to the present invention.
5 is an equivalent circuit diagram of the light valve panel shown in Fig.
6 is a cross-sectional view showing a cross section taken along the line I-I 'shown in FIG.
7 is a cross-sectional view showing a cross-section of II-II 'shown in FIG.
FIG. 8 is a timing chart showing a driving signal applied to the first block shown in FIG. 5 and a voltage change of a main node.
9 is a view showing a resistance distribution between blocks of a light valve panel according to the present invention.
10 is a view showing a plane of a light valve panel according to a comparative example.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

1 is a view showing a liquid crystal display device according to the present invention. FIG. 2 is a cross-sectional view of the liquid crystal display shown in FIG. 1. FIG.

1 and 2, a liquid crystal display device according to the present invention includes a display panel PNL1 having a pixel array, a backlight unit BLU for illuminating the display panel PNL1, a display panel PNL1, A first panel drive circuit 10, 20, 30, a second panel drive circuit 230, 240, 250, and a backlight drive circuit 40. The light valve panel PNL2,

The display panel PNL1 includes a color filter array substrate 100 and a thin film transistor substrate 110 which face each other with a liquid crystal layer interposed therebetween.

A color filter array including a black matrix (BM) and a color filter (CF) is formed on the color filter array substrate 100.

The thin film transistor substrate 110 includes data lines DL, gate lines GL, a common electrode 12, a pixel electrode 11 connected to the TFT, and a storage capacitor Storage Capacitor, Cst) and the like are formed. The TFTs are formed one by one for each subpixel and are connected to the pixel electrode 11. The TFTs may be implemented as an amorphous silicon (a-Si) TFT, a low temperature polysilicon (LTPS) TFT, or an oxide TFT (oxide TFT). The TFTs are connected in a 1: 1 relationship to the pixel electrodes of the subpixels. The common electrode 12 and the pixel electrode 11 are separated with the insulating film therebetween.

The liquid crystal mode of the display panel PNL1 can be applied to any known liquid crystal mode such as TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode.

Polarizing films 13 and 14 are bonded to the color filter array substrate 100 and the thin film transistor substrate 110 of the display panel PNL1 to form an alignment film for setting the pretilt angle of the liquid crystal. A spacer for maintaining the cell gap of the liquid crystal cell may be formed between the upper plate and the lower plate.

The light valve panel PNL2 is disposed between the display panel PNL1 and the backlight unit BLU. The light valve panel PNL2 drives liquid crystal molecules according to a voltage difference applied to the upper substrate 200 and the lower substrate 210 to adjust the amount of light irradiated to the display panel PNL1. The light valve panel PNL2 is a liquid crystal shutter that adjusts the amount of light in synchronization with the input image using electrically controlled liquid crystal molecules.

The liquid crystal of the light valve panel PNL2 can be driven in the TN mode. In the TN mode, the luminance of the liquid crystal cell is adjusted along the transmittance-voltage curve (T-V curve) of Normally White. The lower the voltage, the higher the transmittance of the T-V curve of Normale White increases the luminance of the liquid crystal cell. The higher the voltage, the lower the transmittance and the lower the luminance of the liquid crystal cell. A detailed description of the structure and operation of the light valve panel PNL2 will be given later.

The display panel PNL1 and the light valve panel PNL2 may be bonded with an adhesive, for example, OCA (Optical Clear Adhesive).

The first panel drive circuit (10, 20, 30) writes the data of the input image to the pixels. The first panel drive circuits 10, 20 and 30 include a first timing controller 10, a first data driver 20 and a gate driver 30. The first panel drive circuits 10, 20 and 30 can be integrated into one IC.

The first timing controller 10 transmits the digital video data of the input image received from the host system 5 to the data driver 20. The first timing controller 10 receives timing signals from the host system 5, which are synchronized with the input video data. The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a clock CLK, and the like. The first timing controller 10 controls the operation timings of the data driver 20 and the gate driver 30 based on the timing signals Vsync, Hsync, DE, and CLK received together with the pixel data of the input image. The first timing controller 10 may transmit a polarity control signal for controlling the polarity of the pixel array to each of the source drive ICs of the first data driver 20.

The output channels of the first data driver 20 are connected to the data lines DL of the pixel array. The first data driver 20 receives the digital video data of the input video from the first timing controller 10. The first data driver 20 converts the digital video data of the input image into a positive / negative gamma compensation voltage under the control of the first timing controller 10 to output positive / negative data voltages. The output voltage of the first data driver 20 is supplied to the data lines DL. The first data driver 20 inverts the polarity of the data voltage to be supplied to the pixels under the control of the timing controller 10. [

The gate driver 30 sequentially supplies gate pulses synchronized with the data voltage to the gate lines GL under the control of the first timing controller 10. [ The gate pulse output from the gate driver 30 is synchronized with the data voltage supplied to the data lines DL.

The second panel drive circuits 230, 240 and 250 adjust the amount of light transmitted through the light valve panel PNL2 in synchronization with the input image, thereby improving the contrast ratio of the image reproduced on the display panel PNL1. The second panel drive circuits 230, 240 and 250 include a second timing controller 230, a second gate driver 240, and a second data driver 250. The second panel drive circuits 230, 240, and 250 may be integrated into one IC.

The second timing controller 230 transmits the data of the input image to the second data driver 250. The second timing controller 230 receives timing signals from the host system 5 in synchronization with the input image data. The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a clock CLK, and the like. The second timing controller 230 controls the operation timing of the second data driver 250 based on the timing signals Vsync, Hsync, DE, and CLK received together with the pixel data of the input image.

The gate driver 240 sequentially supplies gate pulses to the light valve gate line LVGL under the control of the second timing controller 230. The gate pulse output from the gate driver 240 is synchronized with the data voltage supplied to the light valve data lines LVDL.

The second data driver 250 receives the digital video data of the input image from the second timing controller 110. The second data driver 250 outputs the data voltage under the control of the second timing controller 230. The output voltage of the second data driver 250 is supplied to the light valve data lines LVDL. The second data driver 250 inverts the polarity of the data voltage to be supplied to the pixels under the control of the second timing controller 230.

The first and second panel driving circuits may be integrated in various forms. For example, the first and second timing controllers 100 and 110 may be integrated into one IC. The first and second panel driving circuits may be integrated into one IC integrated circuit.

The backlight unit (BLU) may be implemented as a direct type backlight unit or an edge type backlight unit. The backlight unit includes a light source LS, a light guide plate LGP, an optical sheet OPT, and the like. The light source LS may be implemented as a point light source such as an LED (Light Emitting Diode). The luminance of the light sources LS is adjusted independently in accordance with the driving voltage supplied from the backlight driver 40. The optical sheet includes at least one prism sheet and at least one diffusion sheet to diffuse light incident from the light guide plate LGP and to guide the light path of light at an angle substantially perpendicular to the light incident surface of the display panel PNL Refract.

The host system 5 may be any one of a TV system, a set top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

The liquid crystal display device of the present invention further includes a power supply unit (not shown). The power supply unit generates voltages required for driving the display panel (PNL1) and the light valve panel (PNL2) by using a DC-DC converter. These voltages include a high potential supply voltage VDD, a logic supply voltage VCC, a gamma reference voltage, a gate high voltage VGH, a gate low voltage VGL, a common voltage Vcom, and the like. The high-potential power supply voltage VDD is the maximum data voltage to be charged in the display panel PNL1 and the pixel. The logic power supply voltage VCC is the IC power supply voltage of the first and second panel drive circuits. The gate high voltage VGH is the high logic voltage of the gate pulse set above the threshold voltage of the TFTs of the pixel array and the gate low voltage VGL is the logic low voltage of the gate pulse set to a voltage lower than the threshold voltage of the TFTs of the pixel array to be. The gate high voltage VGH and the gate low voltage VGL are supplied to the gate driver 30. The gate pulse swings between the gate high voltage (VGH) and the gate low voltage (VGL). The common voltage Vcom is supplied to the common electrode 12 of the liquid crystal cells Clc. The power supply divides the high-potential power supply voltage (VDD) to generate a gamma reference voltage. The gamma reference voltage is divided in the voltage dividing circuit in the data driver 20 and divided into a positive / negative gamma compensation voltage according to the gradation.

3 is a schematic view showing the array structure of the light valve panel, and Fig. 4 is a view showing the plane of the light valve panel. 5 is an equivalent circuit diagram of the first and second blocks shown in FIG. 6 is a cross-sectional view taken along the line I-I 'shown in FIG. 6, and FIG. 7 is a cross-sectional view taken along the line II-II' shown in FIG.

3 to 7, the light valve panel PNL2 according to the embodiment of the present invention is divided into m × n blocks BL. Each block BL can be defined as an area where the light valve data line LVDL and the gate line LVGL cross each other. Each of the blocks BL is provided with a power supply node NV for applying a voltage to be applied to the high potential voltage line VDDL and the light valve pixel electrode PXL.

The light valve panel (PNL2) includes an upper substrate (200) and a lower substrate (210).

The upper substrate 200 includes a first base substrate SUB1 and a light valve common electrode VCOM. The light valve common electrode VCOM is integrally formed over the entire surface of the upper substrate 200 without being divided along the boundary of the block BL. The light valve common electrode VCOM may be formed of a transparent electrode material such as ITO.

The lower substrate 210 includes a second base substrate SUB2, a light valve pixel electrode PXL, a light valve gate line LVGL, a light valve data line LVDL, a storage capacitor Cst, a switching transistor ST, And a driving transistor (dt).

In each of the blocks BL, a light valve data line LVDL and a high potential voltage line VDDL are arranged in the column direction, and a light valve gate line LVGL is arranged in the row direction. That is, n light valve data lines (LVDL) and high potential voltage line (VDDL) are arranged, and m light valve gate lines (LVGL) are arranged.

The switching transistor ST includes a gate electrode G1 connected to the light valve gate line LVGL, a drain electrode D1 connected to the light valve data line LVDL, and a source electrode connected to the first node N1 S1). In response to the light valve gate pulse G, the switching transistor ST writes the light valve data voltage Data to the first node N1.

The driving transistor DT includes a gate electrode G2 connected to the first node N1, a drain electrode D2 connected to the power supply node NV and a source electrode S2 connected to the low potential voltage line VSSL. . The driving transistor DT forms a current path between the power supply node NV and the low potential voltage line VSSL in response to the voltage of the first node N1. As a result, the driving transistor DT applies the high potential voltage VDD to the power supply node NV when turned on and the low potential voltage VSS to the power supply node NV in the turn-off state.

The gate electrode G3 and the drain electrode D3 of the first transistor T1 are connected to the high potential voltage line VDDL and the source electrode S3 is connected to the power supply node NV. The first transistor Tl serves as a rectifier.

6 and 7, on the second base substrate SUB, gate electrodes G1, G2, and G3 of the transistors ST, DT, and T1 formed of the first metal layer and low potential voltage lines VSSL). The first metal layer may be any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper Or an alloy thereof.

On the patterns using the first metal layer, a gate insulating film (GI) is located. The gate insulating film GI may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer thereof.

The source electrodes S1, S2 and S3 and the drain electrodes D1, S2 and S3 of the transistors ST, DT and T1 formed of the second metal layer are located on the gate insulating layer GI. The second metal layer may be a single layer or a multilayer. When the second metal layer is a single layer, the second metal layer may be formed of a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium ), Neodymium (Nd), and copper (Cu), or an alloy thereof.

The first and second active layers A1 and S2 are located between the drain electrode and the source electrode of the switching transistor ST, the driving transistor DT and the first transistor T1, respectively.

The source electrode S1 of the switching transistor ST and the gate electrode G2 of the driving transistor DT are connected through the first contact hole CNT1 passing through the gate insulating film GI.

In addition, the source electrode S2 and the low potential voltage line VSSL of the driving transistor DT are connected through the second contact hole CNT2 passing through the gate insulating film.

A passivation layer (PAS) is located on the second metal layer. A light valve pixel electrode (PXL) is disposed on the passivation layer (PAS) across the entire surface of the second lower substrate (210). The light valve pixel electrode PXL and the drain electrode D2 of the driving transistor DT are connected through the third contact hole CNT and the drain of the driving transistor DT formed through the third contact hole CNT3 The current path path between the electrode D2 and the light valve pixel electrode PXL is defined as a power supply node NV.

8 is a timing chart showing a driving signal of the first block shown in FIG. 5 and a voltage change of a main node.

5 and 8, during the scan period Ts, the first light valve gate line LVGL1 receives the first gate pulse G1 and the first light valve data line LVDL1 receives the first gate pulse G1, And receives the data voltage Data1. The first switching transistor ST1 is turned on in response to the first gate pulse G1. As a result, the first switching transistor ST1 applies the first light valve data voltage Data1 to the first node N1.

After the scan period Ts is terminated, the first gate pulse G1 is inverted to a turn-off voltage, and the first switching transistor ST1 is turned off. The first switching transistor ST1 is turned off so that the first node N1 is in a floating state. The first driving transistor DT1 is turned on when the voltage stored in the first storage capacitor Cst1 is equal to or higher than the threshold voltage Vth, and turned off when the voltage stored in the first storage capacitor Cst1 is not higher than the threshold voltage Vth.

While the first driving transistor DT1 is turned on, the high-potential voltage VDD applied from the high-potential voltage line VDDL is discharged to the low-potential voltage via the first driving transistor DT1. That is, while the first driving transistor DT1 is turned on, the first feeding node NV becomes the voltage level of the high potential voltage VDD.

While the first driving transistor DT1 is turned off, the first feeding node NV becomes the voltage level of the low potential voltage VSS.

The first feed node NV1 of the first block BL1 and the second feed node NV2 of the second block BL2 are connected through the light valve pixel electrode PXL having the high resistance R. As a result, the voltage distributions of the first block BL1 and the second block BL2 are gradated by the voltage of the first feeding node NV and the voltage of the second feeding node NV.

Likewise, since the light valve pixel electrode PXL is integrally formed, the voltage to which each block BL is applied through the power supply node NV is distributed through the front surface of the light valve pixel electrode PXL.

9 is a schematic diagram showing the resistance distribution of the blocks arranged in the first row.

Referring to FIG. 9, each of the first block BL1 to the n-th block BL is electrically connected through a high resistance. Therefore, the voltage applied to the power supply node NV of the specific block BL is distributed to the other blocks BL.

For example, when the high potential voltage VDD is applied to the first feeding node NV1 and the low potential voltage VSS is applied to the nth feeding node NVn, the first block BL1 to the nth block BLn have different voltage values depending on the distance between the first feeding node NV1 and the nth feeding node NVn. That is, the closer to the first feeding node NV1, the voltage level is close to the high potential voltage VDD and the closer to the nth feeding node NV the voltage level is close to the low potential voltage VSS. The voltage difference is not significantly different even at the boundary between the blocks BL adjacent to each other with different voltage values in each of the blocks BL.

Since the voltage applied to the light valve pixel electrode PXL is gradated by the resistance difference, the light valve panel PNL2 according to the present invention distributes the voltage to the light valve pixel electrode PXL, To be distributed in one form. As a result, the display quality of the image displayed on the display panel can be enhanced.

n 개일 경우에, 각각의 블록(BL)에 광 밸브 데이터전압을 공급하기 위한 m

n개의 전압 공급라인(VL)을 필요로 한다. In particular, since the light valve panel PNL2 according to the present invention does not apply a light valve data voltage to each block using a single voltage supply line, the number of voltage supply lines can be reduced. 10, in a general passive type light valve panel, when the number of blocks BL is m

n for supplying the light valve data voltage to each block BL,

n voltage supply lines VL.

n개 경우에, n개의 데이터라인 및 고전위전압 라인과 m개의 게이트라인이 배치된다. 이처럼 본 발명은 광 밸브 패널(PNL2)에 배치되는 광 밸브 데이터라인(LVDL), 고전위전압 라인(VDDL) 및 게이트라인(LVGL)의 개수를 줄일 수 있기 때문에, 대면적 및 고해상도를 갖는 표시패널에 적용하기에 유리하다.On the other hand, since the light valve panel PNL2 according to the present invention uses the transistors disposed in the intersections of the gate lines and the data lines in each block BL region, the voltage lines can be greatly reduced. That is, in the light valve panel PNL2 of the present invention, the number of the blocks BL is m

In the case of n, n data lines and high potential voltage lines and m gate lines are arranged. As described above, the present invention can reduce the number of the light valve data lines LVDL, the high potential voltage lines VDDL and the gate lines LVGL disposed in the light valve panel PNL2, . ≪ / RTI >

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

PNL1: Display panel PNL2: Light valve panel
BLU: backlight unit 10: first timing controller
20: first data driver 30: gate driver
230: second timing controller 240: second gate driver
250: second data driver LVDL: light valve data line
LVGL: Light valve gate line ST: Switching transistor
DT: driving transistor

Claims (10)

An upper substrate on which a light valve common electrode is disposed; And
And a lower substrate facing the upper substrate with a liquid crystal layer interposed therebetween, the light valve pixel electrode including a light valve data line, a light valve gate line, and an integrated light valve pixel electrode receiving a voltage through the plurality of power supply nodes,
Each block defined as a region where the light valve data line and the light valve gate line cross each other
A drain electrode and a gate electrode connected to the light valve data line and the light valve gate line, respectively; And
And a driving transistor disposed between the switching transistor and the power supply node and adjusting a voltage of the power supply node in accordance with a voltage of a gate electrode connected to a source electrode of the switching transistor. The method according to claim 1,
Wherein a drain electrode of the driving transistor is applied with a high potential voltage and a source electrode thereof is connected to a low potential voltage line. 3. The method of claim 2,
The block
A first transistor including a source electrode connected to a drain electrode of the driving transistor, a gate electrode connected to a high potential voltage line, and a drain electrode. 3. The method of claim 2,
Each block
Further comprising a storage capacitor comprising a first electrode connected to a gate electrode of the driving transistor, and a second electrode connected to a source electrode of the driving transistor,
The storage capacitor
And charges the light valve data voltage received from the light valve data line when the switching transistor is turned on. 5. The method of claim 4,
The driving transistor
The voltage of the power supply node is maintained at a high potential voltage,
And maintains the voltage of the power supply node at a low potential voltage in the turn-off state. Wherein the low potential voltage line and the gate electrode of the driving transistor comprise a first metal layer,
Wherein a source electrode of the switching transistor and a source electrode of the driving transistor are formed of a second metal layer on a gate insulating film covering the first metal layer,
And a source electrode of the switching transistor and a gate electrode of the driving transistor are connected through a first contact hole passing through the gate insulating film. The method according to claim 6,
Wherein the storage capacitor is defined as an area where the metal pattern and the low potential voltage line overlap. The method according to claim 6,
And the source electrode and the low potential voltage line of the driving transistor are connected through a second contact hole passing through the gate insulating film. The method according to claim 6,
A drain electrode of the driving transistor is formed of the second metal layer,
Wherein the light valve pixel electrode comprises a third metal layer located on the passivation layer covering the second metal layer,
Wherein the feed node is connected to the drain electrode of the driving transistor and the light valve pixel electrode through a third contact hole passing through the passivation layer. A display panel on which pixels to which an input image is written are arranged;
A backlight unit for emitting light to the display panel; And
And a light valve panel disposed between the display panel and the backlight unit for adjusting an amount of light from the backlight unit according to an input image,
The light valve panel
An upper substrate on which a light valve common electrode is disposed; And
And the light valve data lines and the light valve gate lines intersect with each other. The power supply nodes disposed in each of the blocks are divided into a plurality of blocks, And a lower substrate electrically connected through the pixel electrode,
Each block
A switching transistor disposed at an intersection of the light valve data line and the light valve gate line; And
And a driving transistor disposed between the switching transistor and the power supply node and adjusting a voltage of the power supply node according to a voltage of a gate electrode connected to a source electrode of the switching transistor.

Images