KR20170136961A - Field Effect Transistor and Method of fabricating the same - Google Patents

Abstract

Provided are a field effect transistor, and a method of manufacturing the same. The field effect transistor comprises: a semiconductor substrate made of a first semiconductor material; and a fin structure disposed on the semiconductor substrate, and made of a second semiconductor material having a lattice constant different from that of the first semiconductor material. The fin structure comprises: a lower part extended in a first direction on the semiconductor substrate; and a plurality of upper parts projecting from the lower part and extended in a second direction intersecting the first direction. It is possible to provide a field effect transistor with improved integration and improved electrical characteristics.

Description

FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a field effect transistor.

The semiconductor device includes an integrated circuit composed of MOS (Metal Oxide Semiconductor) FETs. As the semiconductor device is highly integrated, the scale down of the MOS field effect transistors is also being accelerated, which may degrade the operation characteristics of the semiconductor device. Accordingly, various methods for forming a semiconductor device having superior performance while overcoming the limitations of the high integration of the semiconductor device have been researched. Particularly, a method of increasing the mobility of a carrier (electron or hole) to realize a high-performance MOS transistor has been developed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a field effect transistor having a high integration and improved electrical characteristics.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for fabricating a field effect transistor with high integration and improved electrical characteristics.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a field-effect transistor including: a semiconductor substrate made of a first semiconductor material; A fin structure disposed on the semiconductor substrate and made of a second semiconductor material having a lattice constant different from that of the first semiconductor material, the fin structure comprising: a lower portion extending in a first direction on the semiconductor substrate; And a plurality of upper portions projecting from the lower portion and extending in a second direction intersecting the first direction.

According to an aspect of the present invention, there is provided a field-effect transistor including: a semiconductor substrate made of a first semiconductor material; A plurality of pin structures spaced apart from each other on the semiconductor substrate, each of the pin structures comprising: a lower portion extending in one direction on the semiconductor substrate; And a plurality of upper portions projecting from the lower portion and traversing the lower portion; A gate electrode extending in one direction parallel to the bottom portions, the gate electrode crossing the top portions of the pin structures; And source / drain regions provided in the upper portions of the pin structures, on both sides of the gate electrode.

According to an aspect of the present invention, there is provided a method of fabricating a field effect transistor, including: forming a device isolation layer having a lower trench exposing a portion of a semiconductor substrate; Forming a mask pattern having a plurality of upper trenches across the lower trenches on the device isolation layer; Forming an epitaxial layer epitaxially grown from the upper surface of the semiconductor substrate exposed by the lower trench and the upper trenches, wherein the epitaxial layer is composed of a semiconductor material having a lattice constant different from that of the semiconductor substrate A lower portion filling the lower trench, and upper portions filling the upper trenches; Forming a first isolation insulating pattern across the upper portions of the epitaxial layer, thereby separating the epitaxial layer into a plurality of epitaxial patterns; And forming a second isolation insulating pattern across the lower portion of the epitaxial layer, thereby separating each of the epitaxial patterns into a plurality of pin structures.

According to embodiments of the present invention, when forming the pin structures using the selective epitaxial growth method, trapped crystal defects in the lower portion of the pin structures can be prevented from propagating to the upper portions. Accordingly, the upper portions of the pin structures can be made of a semiconductor material substantially free from crystal defects. Therefore, the electrical characteristics of the field effect transistor using the upper portions of the pin structures according to the embodiments of the present invention as a channel can be further improved.

1A to 10A are plan views illustrating a method of manufacturing a semiconductor device according to embodiments of the present invention.
Figs. 1B to 10B are cross-sectional views taken along line II 'and line II-II' in Figs. 1A to 10A.
Figs. 1C to 10C are cross-sectional views taken along line III-III 'and line IV-IV' in Figs. 1A to 10A.
11A and 11B are cross-sectional views of a semiconductor device according to various embodiments of the present invention, wherein FIG. 11A shows a cross section taken along line II 'and II-II' in FIG. 10A, -III 'and IV-IV', respectively.
12 is a perspective view exemplarily showing structural features of a semiconductor device according to embodiments of the present invention.
13 is a perspective view showing a fin structure of a semiconductor device according to embodiments of the present invention.
FIGS. 14A, 14B, 15A, and 15B are views for explaining a semiconductor device according to various embodiments of the present invention. FIG. 14B shows a cross section taken along the line III-III ' 15B shows a cross section taken along the line III-III 'in FIG. 15A.
Figures 16 and 17 illustrate a semiconductor device according to various embodiments of the present invention.
18A to 22A and 18B to 22B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to various embodiments of the present invention.

Hereinafter, a field effect transistor and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the drawings.

1A to 10A are plan views illustrating a method of manufacturing a semiconductor device according to embodiments of the present invention. Figs. 1B to 10B are cross-sectional views taken along lines I-I 'and II-II' in Figs. 1A to 10A. Figs. 1C to 10C are cross-sectional views taken along line III-III 'and line IV-IV' in Figs. 1A to 10A.

11A and 11B are cross-sectional views of a semiconductor device according to various embodiments of the present invention, wherein FIG. 11A shows a cross section taken along line II 'and II-II' in FIG. 10A, -III 'and IV-IV', respectively.

Referring to FIGS. 1A, 1B, and 1C, an element isolation trench 103 may be formed by patterning a semiconductor substrate 100 to define preliminary active patterns 101. FIG.

The semiconductor substrate 100 may be made of a semiconductor material and may be formed of a material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide AlGaAs), or a mixture thereof.

The semiconductor substrate 100 may be a bulk silicon substrate, a silicon on insulator (SOI) substrate, a germanium substrate, a germanium on insulator (GOI) substrate, a silicon-germanium substrate, Or a substrate of an epitaxial thin film obtained by performing selective epitaxial growth (SEG). As another example, the semiconductor substrate 100 may be a III-V compound semiconductor substrate.

In one example, the semiconductor substrate 100 may be a monocrystalline silicon substrate, and the upper surface of the semiconductor substrate 100 may have a (100) crystal plane or a (110) crystal plane.

Forming the device isolation trenches 103 includes forming a first mask pattern 110 that exposes predetermined areas of the semiconductor substrate 100 on the semiconductor substrate 100, And defining the preliminary active patterns 101 by anisotropically etching the semiconductor substrate 100 using the pattern 110 as an etch mask.

The first mask pattern 110 may be in the form of a line extending in the first direction D1 and includes a buffer oxide film pattern 111 and a hard mask pattern 113 stacked in that order. More specifically, the formation of the first mask pattern 110 is performed by sequentially laminating a silicon oxide film and a hard mask film on the semiconductor substrate 100, a step of forming a photo Forming a resist pattern (not shown), and anisotropically etching the hard mask film and the silicon oxide film in order to expose the upper surface of the semiconductor substrate 100 using a photoresist pattern (not shown) as an etching mask have. Here, the silicon oxide film may be formed by thermal oxidation of the semiconductor substrate 100. The hard mask film may be formed of any one material selected from a silicon nitride film, a silicon oxynitride film, and a polysilicon film. The hard mask film may be thicker than the silicon oxide film. The thickness of the hard mask film may vary depending on the depth of the element isolation trenches 103 formed in the semiconductor substrate 100. In embodiments, the first mask pattern may be removed after forming the trench, or may be removed after forming the device isolation film 105.

According to the embodiments, the preliminary active patterns 101 may have a line shape extending in the first direction D1 and may be spaced apart from each other in the second direction D2 perpendicular to the first direction D1. . For example, the interval between the preliminary active patterns 101 may be larger than the width W1 of the preliminary active patterns 101. [ The preliminary active patterns 101 may have a sidewall profile whose width increases toward the bottom.

The device isolation trenches 103 may be substantially perpendicular to the top surface of the semiconductor substrate 100, or may have inclined sidewalls. The depth H1 of the device isolation trench may be larger than twice the width W1 of the preliminary active patterns 101. [ The depth H1 of the device isolation trench may be smaller than the length L1 of the preliminary active pattern in the first direction D1.

Referring to FIGS. 2A, 2B, and 2C, a device isolation film 105 may be formed in the device isolation trench 103. The device isolation film 105 may cover both side walls of the preliminary active patterns 101. [

Formation of the element isolation film 105 may include forming an insulating film filling the element isolation trenches 103 and planarizing the insulating film such that upper surfaces of the preliminary active patterns 101 are exposed. Here, the insulating film filling the element isolation trenches 103 can be deposited using a deposition technique with excellent step coverage. The insulating film may be formed by a deposition technique such as an atomic layer deposition (ALD) method, a chemical vapor deposition (CVD) method, or a plasma enhanced chemical deposition (PE-CVD) The insulating film may be formed of an insulating material having excellent gap fill characteristics. For example, a boron-phosphor silicate glass (BPSG) film, a high density plasma (HDP) oxide film, An etch back process and / or a chemical mechanical polishing (CMP) process may be used as the planarization process for the insulating film. .

The device isolation film 105 may have sidewalls that are substantially perpendicular to the top surface of the semiconductor substrate 100 and may alternatively be formed on the top surface of the semiconductor substrate 100 as shown in Figures 11A and 11B. It may also have sloped sidewalls.

The device isolation film 105 is formed on the semiconductor substrate 100 on the upper surface of the semiconductor substrate 100. The device isolation film 105 is formed on the upper surface of the semiconductor substrate 100, May be formed to expose portions of the substrate.

3A, 3B, and 3C, a second mask pattern 120 having top trenches UR across the pre-active patterns 101 may be formed.

The second mask pattern 120 may be formed by depositing a hard mask film covering the entire surface of the semiconductor substrate 100, depositing a hard mask film on the hard mask film in a second direction D2 perpendicular to the first direction D1, (Not shown), and anisotropically etching the hard mask film so that the upper surface of the semiconductor substrate 100 is exposed using a photoresist pattern (not shown) as an etch mask. According to embodiments, the second mask pattern 120 may be formed of an insulating material having etch selectivity to the semiconductor substrate 100 and the device isolation film 105. The second mask pattern 120 may be formed of, for example, a silicon nitride film or a silicon oxynitride film.

According to embodiments, the upper trenches UR may expose portions of the pre-active patterns 101. [ The upper trenches UR may have a width W2 that is smaller than the width W1 of the preliminary active patterns 101. [ For example, the width W2 of the upper trenches UR may be selected in the range of about 5 nm to 50 nm. The thickness H2 of the second mask pattern 120 (i.e., the height of the upper trenches UR) may be greater than twice the width W2 of the upper trenches UR.

Referring to FIGS. 4A, 4B and 4C, the lower trenches LR are formed under the second mask pattern 120 by removing the pre-active patterns 101 exposed by the second mask pattern 120 .

According to one example, the lower trenches LR may be formed by isotropically etching the preliminary active patterns 101. An etch recipe having etch selectivity for the device isolation film 105 and the second mask pattern 120 may be used in forming the lower trenches LR. For example, when the semiconductor substrate 100 is a single crystal silicon substrate, an etchant including HF, HNO ₃ , or NH ₄ F may be used.

Portions of the lower surface of the second mask pattern 120 and the side walls of the device isolation film 105 may be exposed to the lower trenches LR by an isotropic etching process for the preliminary active patterns 101. [ The lower trenches LR thus formed may extend in the first direction D1 as vacant spaces from which the preliminary active patterns 101 are removed.

The distance from the upper surface of the device isolation film 105 to the bottom surface of the lower trenches LR is smaller than the height of the lower trenches LR, Of the first width W1 of the substrate W1. In other words, the lower trenches LR may have an aspect ratio of about 2: 1 to 3: 1 and the length L1 in the lower direction of the lower trenches LR in the first direction D1 may be less than the length of the lower trenches LR Lt; RTI ID = 0.0 > (Hl) < / RTI > For example, the first width W1 of the lower trenches LR can be selected in the range of about 10 nm to 100 nm. Meanwhile, the present invention is not limited to this, and the length L1 of the lower trenches LR may vary depending on the design of the semiconductor device.

In one example, the height H1 of the lower trenches LR may be substantially the same as the height of the device isolation film 105. Alternatively, since the lower trenches LR are formed by the etching process, the lower surfaces of the lower trenches LR may be located at different levels from the lower surfaces of the device isolation film 105. [ In other words, the first height H1 of the lower trenches LR may be smaller or larger than the height of the device isolation film 105. That is, the lower surfaces of the lower trenches LR may be located below or above the lower surface of the device isolation film 105.

Furthermore, the surface of the semiconductor substrate 100 exposed to the lower trenches LR may have a (100) crystal plane or a (110) crystal plane. In addition, an inclination angle of about 50 to 90 degrees can be established between the surface of the semiconductor substrate 100 exposed to the lower trenches LR and the sidewall of the device isolation film 105.

5A, 5B, and 5C, an epitaxial layer 130 filling the lower trenches LR and the upper trenches UR may be formed.

The epitaxial layer 130 may be formed using a selective epitaxial growth (SEG) process using the semiconductor substrate 100 exposed as the seeds in the lower trenches LR. Examples of the selective epitaxial growth process include Solid Phase Epitaxy (SPE), Vapor Phase Epitaxy (VPE) and Liquid Phase Epitaxy (LPE) Can be used. According to one embodiment, the epitaxial layer 130 may be formed by a chemical vapor deposition (CVD) process, a reduced pressure chemical vapor deposition (RPCVD) process, a high vacuum chemical vapor deposition process (E. G., Hetero-epitaxy) using molecular beam epitaxy (UHCVD) or molecular beam epitaxy (MBE) methods.

In embodiments, the epitaxial layer 130 may be formed of a semiconductor material having a lattice constant different from that of the semiconductor material of the semiconductor substrate 100. The epitaxial layer 130 may comprise, for example, Si, Ge, SiGe, or III-V compounds. In addition, the III-V compounds can be used in a variety of applications including, for example, aluminum phosphide (AlP), gallium phosphide (GaP), indium phosphide (InP), aluminum arsenide gallium arsenide (GaAs), indium arsenide (InAs), aluminum antimonide (AlSb), gallium antimonide (GaSb), or indium antimonide (InSb) .

According to embodiments, the epitaxial layer 130 is selectively etched vertically and horizontally from the surface of the semiconductor substrate 100 exposed to the lower trenches LR by a selective epitaxial growth process, It can be grown. Thus, the epitaxial layer 130 may fill the lower and upper trenches LR, UR. Further, the epitaxial layer 130 may protrude from the upper surface of the second mask pattern 120 by overgrowth during the selective epitaxial growth process.

The epitaxial layer 130 thus formed may include lower portions 130L filled in the lower trenches LR and upper portions 130U filled in the upper trenches UR. The epitaxial layer 130 may be formed as a single body between the lower portions 130L and the upper portions 130U without boundaries. The lower portions 130L of the epitaxial layer 130 may extend along the first direction D1 and the upper portions 130U of the epitaxial layer 130 may extend perpendicular to the first direction D1 And may extend in the second direction D2. That is, the upper portions 130U of the epitaxial layer 130 may extend horizontally on the element isolation films 105 on the lower portions 130L. The sidewalls of the lower portions 130L of the epitaxial layer 130 may be defined by the device isolation layer 105 and the sidewalls of the upper portions 130U of the epitaxial layer 130 may be defined by the second mask pattern 130. [ (120). ≪ / RTI >

As an example, the epitaxial layer 130 may be grown from the upper surface of the monocrystalline silicon substrate having a (100) crystal plane, or alternatively may be grown from the upper surface of the monocrystalline silicon substrate having a (110) crystal plane. The sidewalls of the epitaxial layer 130 may be oriented in the <110> crystal direction. In one example, the sidewalls of the lower portions 130L of the epitaxial layer 130 may be oriented in the [110] crystal direction and the sidewalls of the upper portions 130U of the epitaxial layer 130 may be oriented [1-10 ] Direction.

According to the embodiments, due to the lattice constant difference between the semiconductor material constituting the epitaxial layer 130 and the semiconductor material constituting the semiconductor substrate 100 during the selective epitaxial growth process and the growth rate difference between the crystal planes, the epitaxial layer 130 may include crystal defects. For example, the lower portions 130L of the epitaxial layer 130 may be formed by a variety of methods including threading dislocations, misfit defects, stacking faults, twin boundaries, Or various crystal defects such as anti-phase boundaries.

More specifically, when the epitaxial layer 130 is grown from the surface of the semiconductor substrate 100 (for example, the (001) crystal face of the silicon substrate), crystal defects 130a and 130b (e.g., Threading dislocations can propagate along the (111) crystal plane in the <110> crystal direction. Such crystal defects 130a and 130b propagate at an angle of about 55 degrees with respect to the (001) crystal plane of the silicon substrate .

According to the embodiments, as described with reference to FIGS. 4A, 4B and 4C, since the width W1 and the height H1 of the lower trenches LR satisfy the condition of H1 > 2W1, The crystal defects 130a do not propagate to the upper portions of the lower trenches LR in the widthwise direction (i.e., the second direction D2) of the lower trenches LR, That is, the side wall of the element isolation film 105). That is, the crystal defects 130a in the second direction D2 can be trapped in the lower portion of the lower trench LR.

Since the height H1 of the lower trenches LR is smaller than the length L1 of the lower trenches LR in the longitudinal direction of the lower trenches LR in the first direction D1, The crystal defects 130b in the lower trenches LR can be propagated to the upper portions of the lower trenches LR without being blocked by the sidewalls of the lower trenches LR (i.e., the side walls of the device isolation film 105). In embodiments, propagation of such crystal defects 130b may be blocked by a second mask pattern 120 defining upper trenches UR extending in a second direction D2. Therefore, the upper trenches UR can be filled with the epitaxial layer 130 without crystal defects. That is, the crystal defects can be trapped in the lower trenches LR when the epitaxial layer 130 is grown, and the upper portions 130U of the epitaxial layer 130 filling the upper trenches UR are substantially And can be made of a defect free semiconductor material.

Further, the upper surface of the epitaxial layer 130 may have inclined facets with respect to the upper surface of the semiconductor substrate 100 due to the difference in growth rate depending on the crystal planes during the selective epitaxial growth process. For example, the upper surface of the epitaxial layer 130 may be composed of (111) crystal faces. That is, the protruding portion of the epitaxial layer 130 protruding on the upper surface of the second mask pattern 120 by the overgrowth of the epitaxial layer 130 may have a pyramidal structure.

6A, 6B, and 6C, a process of planarizing the upper surface of the epitaxial layer 130 protruded above the upper surface of the device isolation film 105 is performed after the epitaxial layer 130 is formed . As the planarization process, an etch back method and / or a chemical mechanical polishing (CMP) method may be used. According to embodiments, the top surface of the epitaxial layer 130 may be substantially coplanar with the top surface of the second mask pattern 120 by the planarization process.

Subsequently, first isolation insulating patterns 141 extending in the first direction D1 across the upper portions 130U of the epitaxial layer 130 may be formed.

Forming the first isolation insulating patterns 141 may include forming a mask pattern (not shown) having openings extending in the first direction D1 on the second mask pattern 120, Forming the first isolation insulating film to fill the trench, and planarizing the first isolation insulating film to expose the upper portions of the epitaxial layer. have.

For example, the first isolation insulating patterns 141 may penetrate the upper portions 130U of the epitaxial layer 130 and the device isolation film 105. That is, when forming the trenches extending in the first direction D1, the epitaxial layer 130 and the device isolation film 105 may be etched so that the semiconductor substrate 100 is exposed. Accordingly, the first isolation insulating patterns 141 can be in contact with the semiconductor substrate 100. In one example, the lower surfaces of the first isolation insulating patterns 141 may be located below the lower surface of the element isolation film 105. As another example, the lower surfaces of the first isolation insulating patterns 141 may be located between the upper surface and the lower surface of the element isolation film 105, as shown in Figs. 11A and 11B.

According to the embodiments, by forming the first isolation insulating patterns 141, one epitaxial layer 130 is divided into a plurality of epitaxial patterns 131 spaced from each other in the second direction D2 Can be. Each of the epitaxial patterns 131 may be a single body and includes a lower portion extending in the first direction D1 and a plurality of upper portions 131U extending in the second direction D2. ). In other words, in each of the epitaxial patterns 131, the upper portions 131U can be connected to one lower portion. The first isolation insulating patterns 141 may be formed between the lower portions 131L of the epitaxial patterns 131 and may be formed in parallel with the lower portions 131L of the epitaxial patterns 131 Can be extended.

7A, 7B and 7C, second isolation insulation patterns 143 extending in the second direction D2 across the lower portions 131L of the epitaxial patterns 131 .

Forming the second isolation insulating patterns 143 may include forming a mask pattern having openings extending in a second direction D2 on the second mask pattern 120, using the mask pattern as an etch mask Forming the trenches by anisotropically etching portions of the second mask pattern 120 and the epitaxial patterns 131, filling the second isolation insulating film in the trenches, and exposing the second mask pattern 120 to exposure And planarizing the second isolation insulating film so that the second isolation insulating film is flattened.

As another example, the formation of the second isolation insulating patterns 143 may be performed before forming the first isolation insulating patterns 141.

As another example, the second isolation insulation patterns 143 may be formed simultaneously with the first isolation insulation patterns 141 described with reference to FIGS. 6A, 6B, and 6C. In this case, a mask pattern having openings extending in the first direction D1 and the second direction D2 may be formed on the second mask pattern 120 after the epitaxial layer 130 is formed.

The second isolation insulating patterns 143 may be in contact with the semiconductor substrate 100 through the lower portion 131L of the epitaxial patterns 131. [ The lower surface of the second isolation insulating patterns 143 may be located below the lower surfaces of the device isolation film 105.

According to the embodiments, by forming the second isolation insulating patterns 143, each of the epitaxial patterns 131 is divided into a plurality of pin structures 133 that are separated from each other in the first direction D1. . Each of the pin structures 133 may be a single body and includes a lower portion 133L extending in the first direction D1 and a plurality of upper portions 133L extending in the second direction D2 133U. That is, in each of the pin structures 133, the upper portions 133U may be connected to one lower portion 133L. The second isolation insulating patterns 143 may be formed between the lower portions 133L of the pin structures 133 adjacent to each other in the first direction D1, May be extended in parallel with the grooves 133U.

Referring to FIGS. 8A, 8B, and 8C, the upper surfaces of the second mask pattern 120 and the upper surfaces of the first and second isolation insulating patterns 141 and 143 are recessed, 133 to expose portions of the sidewalls of the upper portions 133U.

In one example, the first and second isolation insulating patterns 141 and 143 may be formed of an insulating material having etch selectivity with respect to the second mask pattern 120. In this case, the recess process for exposing the sidewalls of the upper portions 133U of the pin structures 133 includes an etching process for recessing upper surfaces of the first and second isolation insulating patterns 141 and 143, An etching process for recessing the upper surface of the second mask pattern 120 may be performed in order. As another example, the upper surfaces of the first and second isolation insulating patterns 141 and 143 and the upper surface of the second mask pattern 120 may be simultaneously etched.

The recessed first and second isolation insulating patterns 141 and 143 and the recessed second mask pattern 121 are formed on the lower portions 133L of the pin structures 133, A portion of the upper portions 133U of the upper portion 133 may be surrounded.

9A, 9B, and 9C, a gate insulating film 151 and a gate electrode 153 which cross the upper portions 133U of the pin structures 133 can be formed.

According to embodiments, the gate electrode 153 may extend in a first direction D1 parallel to the lower portions 133L of the pin structures 133. [ The gate insulating film 151 and the gate electrodes 153 can overlap with the lower portions 133L of the pin structures 133 in plan view. That is, the lower portions 133L of the pin structures 133 may be disposed apart from the gate electrode 153 in the first direction D1. In embodiments, the gate electrode 153 may be less than or equal to the width of the lower portions 133L of the pin structures 133. [

The gate insulating film 151 may be formed of a high dielectric film such as hafnium oxide, hafnium silicate, zirconium oxide, or zirconium silicate. The gate insulating layer 151 may be formed using an atomic layer deposition technique and may conformally cover the surfaces of the upper portions 133U of the pin structures 133. [ As another example, the gate insulating film 151 may be formed by thermally oxidizing the surfaces of the upper portions 133U of the pin structures 133 exposed by the recessed second mask pattern 121. [

The gate electrode 153 may be formed of, for example, a doped polysilicon film, an undoped polysilicon film, a silicon germanium film, or a silicon carbide film. As another example, the gate electrodes may be formed of a semiconductor material doped with a dopant (ex, doped silicon, etc.), a metal (ex, tungsten, aluminum, titanium and / or tantalum), a conductive metal nitride (ex, titanium nitride, tantalum nitride and / Or tungsten nitride) and a metal-semiconductor compound (ex, metal silicide).

After the gate electrode 153 is formed, gate spacers 155 may be formed on both sidewalls of the gate electrode 153. Formation of the gate spacers may include forming a gate spacer film that conformally covers the gate electrode 153, anisotropically etching the gate spacer film.

10A, 10B, and 10C, source and drain regions 160 may be formed in the upper portions 133U of the pin structures 133 on both sides of the gate electrode 153. [

According to one example, forming the source and drain regions 160 may include etching portions of the upper portions 133U of the pin structures 133 on either side of the gate electrode 153, Lt; / RTI &gt; Here, the epitaxial layer may consist of a semiconductor material that provides a tensile or compressive strain in the channel region of the field effect transistor. For example, when forming NMOS field effect transistors, the epitaxial layer may be made of silicon carbide (SiC). Alternatively, when forming PMOS field effect transistors, the epitaxial layer may be made of silicon germanium (SiGe). Though not shown in the drawing, a silicide film such as nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, niobium silicide, or tantalum silicide may be formed on the surfaces of the source and drain electrodes.

According to another example, forming the source and drain regions 160 may be performed by using an n-type or p-type (for example, n-type or p-type) gate electrode 153 in the upper portions 133U of the pin structures 133, Ion implantation of impurities.

After the source and drain regions 160 are formed, a first interlayer insulating film 165 covering the gate electrode 153 and the source and drain regions 160 may be formed. For example, the first interlayer insulating film 165 may fill the gap between the gate electrodes 153 to expose the upper surfaces of the gate electrodes 153.

According to some embodiments, after forming the first interlayer insulating films 165, processes of replacing the gate electrodes 153 with the metal gate electrode 170 can be performed. In detail, forming the metal gate electrode 170 includes removing the gate electrode 153 to form the gate region between the gate spacers 155 and forming the gate dielectric layer 171, (173), and a metal film (175) in this order.

The gate dielectric layer 171 may be formed of a high-k film such as hafnium oxide, hafnium silicate, zirconium oxide, or zirconium silicate. The barrier metal film 173 may be formed of a conductive material having a predetermined work function and may be formed of a metal nitride film such as titanium nitride, tantalum nitride, tungsten nitride, hafnium nitride, and zirconium nitride . The metal film 175 may be formed of one of materials having a lower resistivity than the barrier metal film. The metal film 175 may be formed of any one selected from, for example, tungsten, copper, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel and conductive metal nitrides or combinations thereof .

After the metal gate electrodes 170 are formed, a second interlayer insulating film 180 may be formed on the first interlayer insulating film 165 to cover the upper surfaces of the metal gate electrodes 170.

12 is a perspective view exemplarily showing structural features of a semiconductor device according to embodiments of the present invention. 13 is a perspective view showing a fin structure of a semiconductor device according to embodiments of the present invention. For simplicity of explanation, the description of the same technical features as those of the manufacturing method described above with reference to Figs. 1A to 10A, 1B to 10B, and 1C to 10C can be omitted.

12 and 13, a plurality of pin structures 133 may be disposed on the semiconductor substrate 100 in a spaced apart relation to each other. For example, the pin structures 133 may be spaced apart from each other in a first direction D1 and a second direction D2 that intersect with each other.

According to embodiments, the semiconductor substrate 100 may comprise a first semiconductor material, and the pin structures 133 may comprise a second semiconductor material having a lattice constant different from the first semiconductor material. In one example, the second semiconductor material may have a larger lattice constant than the first semiconductor material. The first and second semiconductor materials may be, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide Or mixtures thereof.

Each of the pin structures 133 includes a lower portion 133L extending in the first direction D1 on the semiconductor substrate 100 and a lower portion 133L projecting from the lower portion and intersecting the first direction D1. And a plurality of upper portions 133U extending in two directions D2. Here, the first direction D1 may be the [110] crystal direction, and the second direction D2 may be the [1-10] crystal direction perpendicular to the first direction D1.

13, in each of the pin structures 133, the lower portion 133L has a first length L1 in a first direction D1 and a first length L1 in a second direction D2. 1 &lt; / RTI &gt; width W1. The lower portion 133L may have a first height H1 that is larger than about twice the first width W1. In addition, the first length L1 of the lower portion 133L may be larger than the first height H1.

Each of the upper portions 133U may have a second width W2 that is less than the first width W1 in the first direction D1 and a second width W2 that is less than the first width W2 in the second direction D2. May have a second length L2. And, the upper portions 133U may have a second height H2 that is greater than about twice the second width W2.

In embodiments, each of the pin structures 133 may be a single body. In other words, there may be no interface between the lower portion 133L and the upper portions 133U of each pin structure 133. In each of the pin structures 133, the lower portion 133L may have crystal defects propagated in an oblique direction on the upper surface of the semiconductor substrate 100. [ For example, crystal defects 130a propagating in the second direction D2 from the (111) crystal plane and crystal defects 130b propagating in the first direction D1. Here, the crystal defects propagated in the second direction D2 can be shielded from propagation to the upper portions 133U by the mask pattern disposed between the upper portions 133U of the respective pin structures 133. [ Thus, the upper portions 133U of the pin structures 133 may be made of a second semiconductor material that is defect free.

10A, 10B, and 10C and 12, the lower portions 133L of the pin structures 133 adjacent in the second direction D2 can be spaced from each other by the first distance S1 , And the upper portions 133U may be spaced apart from each other by a second distance S2 smaller than the first distance S1.

The element isolation film 105 may be disposed between the lower portions 133L of the pin structures 133 adjacent to each other in the second direction D2. The first isolation insulating pattern 141 may be disposed between the upper portions 133U of the pin structures 133 adjacent in the second direction D2 and the upper surface of the first isolation insulating pattern 141 May be located below the top surfaces of the upper portions 133U of the pin structures 133. [

The lower portions 133L of the adjacent pin structures 133 in the first direction D1 may be spaced apart by a third distance S3 and may be spaced apart from the adjacent pin structures 133 in the first direction D1. The upper portions 133U of the first and second guide grooves 133A and 133B may be spaced apart by a fourth distance S4 larger than the third distance S3.

The second isolation insulating pattern may be disposed between the lower portions 133L of the pin structures 133 adjacent to each other in the first direction D1 and the upper surface of the second isolation insulating pattern 143 may be disposed between the pin structures & May be located below the upper surfaces of the upper portions 133U of the lower portion 133. [

12, the metal gate electrode 170 may be disposed across the upper portions 133U of the pin structures 133 spaced in the first direction D1. The metal gate electrode 170 may overlap the lower portions 133L of the pin structures 133 spaced apart in the first direction D1 from a plan view. In other words, the lower portions 133L of the adjacent pin structures 133 in the first direction D1 can be spaced apart from each other below the metal gate electrode 170. [

The gate insulating film can be disposed between the metal gate electrode 170 and the upper portions 133U of the pin structure 133 and has a uniform thickness and can cover the surfaces of the upper portions 133U. Source and drain regions 160 may be provided on the upper portions 133U of each pin structure 133 on either side of the metal gate electrode 170. [

FIGS. 14A, 14B, 15A, and 15B are views for explaining a semiconductor device according to various embodiments of the present invention. FIG. 14B shows a cross section taken along the line III-III ' 15B shows a cross section taken along the line III-III 'in FIG. 15A. For simplicity of explanation, the description of the same technical features as in the above-described manufacturing method can be omitted.

14A and 14B, the pin structures 133 may be disposed on the semiconductor substrate 100 in a first direction D1 and a second direction D2. According to this embodiment, the intervals between adjacent pin structures 133 in the first direction D1 can be different from each other. That is, the widths of the second isolation insulating patterns 143a and 143b extending in the second direction D2 may be different from each other.

According to some embodiments, in the pin structures 133, the number of upper portions 133U projecting from the lower portion 133L may be different from each other. In other words, the number of the upper portions 133U in any one of the pin structures 133 may be different from the number of the upper portions 133U in the other.

15A and 15B, the semiconductor substrate 100 may include a first region R1 and a second region R2. The plurality of pin structures 133 may be spaced from each other in the first direction D1 and the second direction D2 intersecting the first direction D1 in the first and second regions R1 and R2 have.

In one example, the device isolation film 105 may be disposed between the pin structures 133 of the first region R1 and the pin structures 133 of the second region R2 in the first direction D1 . In each of the first and second regions R1 and R2, the lower portions 133L of the pin structures 133 adjacent to each other in the first direction D1 are connected by the second isolation insulating pattern 143 to the first Can be spaced by a distance. The lower portions 133L of the pin structures 133 of the first and second regions R1 and R2 adjacent in the first direction D1 are separated by a second distance by the element isolation film 105 . Where the second distance may be greater than the first distance.

The metal gate electrodes 170 may be disposed across the first and second regions R1 and R2 and the upper portions of the pin structures 133 of the first and second regions R1 and R2 It can be traversed through the grooves 133U.

Figures 16 and 17 illustrate a semiconductor device according to various embodiments of the present invention. For simplicity of explanation, the description of the same technical features as in the above-described manufacturing method can be omitted.

16 and 17, the semiconductor substrate 100 may include a first region R1 and a second region R2. For example, the first region R1 may be a region where NMOS field effect transistors are formed, and the second region R2 may be a region where PMOS field effect transistors are formed.

The first fin structure 133N may be disposed on the semiconductor substrate 100 of the first region R1 and the second fin structure 133N may be disposed on the semiconductor substrate 100 of the second region R2. The structure 133P can be disposed. For example, the first pin structure 133N and the second pin structure 133P may be spaced apart from each other in the first direction D1.

According to the embodiment shown in Fig. 16, the first pin structure 133N is formed so as to protrude from the lower portion 133L and the lower portion 133L extending in the first direction D1, And upper portions 133U that extend to the second side D2. The first fin structure 133N may be made of an integral epitaxial material and may have a lattice constant different from that of the semiconductor substrate 100. [ According to an example, the semiconductor substrate 100 may be made of silicon (Si), and the first fin structure 133N may be made of silicon germanium (Si1-xGex).

The second fin structure FS may include a buffer pattern 133P on the semiconductor substrate 100 and channel patterns 137 on the buffer pattern 133P. The buffer pattern 133P of the second fin structure FS may be an integral epitaxial layer. That is, similar to the first pin structure 133N, the buffer pattern 133P protrudes from the lower portion 133L and the lower portion 133L extending in the first direction D1 and in the second direction D2 And may include extended upper portions 133U. The upper surfaces of the upper portions 133U of the buffer pattern 133P in the second pin structure FS may be positioned below the upper surfaces of the upper portions 133U of the first pin structure 133N. The upper surfaces of the channel patterns 137 may be substantially coplanar with the upper surfaces of the upper portions 133U of the first pin structure 133N.

For example, the buffer pattern 133P of the second fin structure FS may be made of the same semiconductor material as the first fin structure 133N. The channel patterns 135 of the second fin structure FS are disposed on the upper portions 133U of the buffer pattern 133P and may be made of a material having an energy band gap difference from the buffer pattern 133P. In one example, the channel patterns 135 may be made of Si or Ge. As another example, the buffer pattern 133P may be made of Si1-xGex, and the channel patterns 135 may be made of Si1-yGey (where y> x). As another example, the buffer pattern 133P and the channel patterns 135 may be made of Group III-V compounds, but their energy bandgaps may be different from each other. According to one example, the channel patterns 137 of the second fin structure FS are formed using a selective epitaxial growth process using the upper surfaces of the upper portions 133U of the buffer pattern 133P as seeds . In addition, a boundary surface may exist between the upper portions 133U of the buffer pattern 133P and the channel patterns 137. [ According to the embodiments, since the upper portions 133U of the buffer pattern 133P are made of a semiconductor material having no crystal defects, crystal defects in the channel patterns 137 can be reduced.

17, the first fin structure FS1 may include a first buffer pattern 133N and first channel patterns 137, and the second fin structure FS2 may include a second fin structure FS2, A buffer pattern 133P and second channel patterns 135. [ Each of the first and second buffer patterns 133N and 133P may be formed of an integral semiconductor material and may include a lower portion 133L and a lower portion 133L extending in the first direction D1. 133L that extend in the first direction D2 and extend in the second direction D2.

The first channel patterns 137 may be formed of a material having an energy band gap difference from the first buffer pattern 133N. In one example, the first buffer pattern 133N may be made of Si _{1 - x} Ge _x , and the first channel patterns 137 may be Si _{1 - y} Ge _y (Where x > y). As another example, the first buffer pattern 133N may be formed of In _{1 - x} Ga _x As, and the first channel patterns 137 may be formed of In _{1 - y} Ga _y As (where x <y) have. According to the embodiments, the first channel patterns 137 may be made of an epitaxial material grown from the upper surface of the upper portions 133U of the first buffer pattern 133N.

The second channel patterns 135 may be formed of a material having an energy band gap difference from the second buffer pattern 133P. In addition, the second channel patterns 135 may be formed of a material different from the first channel patterns 137. For example, when the second buffer pattern 133P is formed of Si _{1 - x} Ge _x , the second channel patterns 135 may be Si _{1 - z} Ge _{z (} where Z> x). As another example, when the second buffer pattern 133P is made of In _{1 - z} Ga _z As, the second channel patterns 135 can be made of In _{1 - w} Ga _w As (where z> w) . According to embodiments, the second channel patterns 135 may be made of an epitaxial material grown from the upper surface of the upper portions 133U of the second buffer pattern 133P.

FIGS. 18A to 22A are cross-sectional views illustrating a method of manufacturing a semiconductor device according to various embodiments of the present invention. FIGS. 18A to 22A are cross-sectional views taken along line II 'and II-II' And FIGS. 18B to 22B show cross-sections taken along line III-III 'and line IV-IV in FIG. 10A.

For simplicity of explanation, the description of the same technical features as those of the manufacturing method described above with reference to Figs. 1A to 10A, 1B to 10B, and 1C to 10C can be omitted.

A device isolation film 105 having a lower trench LR that exposes a portion of the semiconductor substrate 100 and an upper isolation structure 105 which extends across the lower trenches LR on the device isolation film 105, The epitaxial layer 130 filling the lower trenches LR and the upper trenches UR may be formed after the second mask pattern 120 having the plurality of upper trenches UR is formed. The epitaxial layer 130 has a lower portion 133L filling the lower trench LR and upper portions 133U filling the upper trenches UR as described with reference to Figures 5A, 5B and 5C . In one example, the upper portions 133U of the epitaxial layer 130 may fill a portion of the upper trenches UR.

18A and 18B, the first semiconductor layers 210 and the second semiconductor layers 220 are alternately repeatedly stacked on the upper portions 133U of the epitaxial layer 130 . The first and second semiconductor layers 210 and 220 may be made of a semiconductor material having an etch selectivity with respect to each other and may be stacked by performing a selective epitaxial growth (SEG) process. In addition, the first semiconductor layers 210 may be made of a semiconductor material having etch selectivity to the epitaxial layer 130. The second semiconductor layers 210 may be made of the same semiconductor material as the epitaxial layer 130 and may be made of the semiconductor material different from the epitaxial layer 130. In embodiments, the first semiconductor layers 210 may have different lattice constants from the second semiconductor layers 220.

The first and second semiconductor layers 210 and 220 may comprise, for example, Si, Ge, SiGe, or III-V compounds. Herein, the III-V compounds may be, for example, aluminum phosphide (AlP), gallium phosphide (GaP), indium phosphide (InP), aluminum arsenide gallium arsenide (GaAs), indium arsenide (InAs), aluminum antimonide (AlSb), gallium antimonide (GaSb), or indium antimonide (InSb) .

For example, the first semiconductor layers 210 may be made of Ge, and the second semiconductor layers 220 may be made of SiGe. In another example, the first and second semiconductor layers 210 and 220 are made of SiGe, and the germanium concentrations in the first and second semiconductor layers 210 and 220 may be different from each other. As another example, the first semiconductor layers 210 may be made of indium arsenide (InAs), and the second semiconductor layers 220 may be made of gallium antimonide (GaSb).

In embodiments, the first and second semiconductor layers 210 and 220 are formed on the upper portions 133U of the epitaxial layer 130 without crystal defects, so that the first and second semiconductor layers (210 and 220) 210, and 220 can be improved.

The stacked first and second semiconductor layers 210 and 220 may fill the upper trenches UR defined by the second mask pattern 120. Accordingly, the first and second semiconductor layers 210 and 220 may have a line shape extending in the second direction D2.

Referring to FIGS. 19A and 19B, first isolation insulating patterns 141 extending in a first direction D1 may be formed as described with reference to FIGS. 6A, 6A, and 6C, As described with reference to FIGS. 7B and 7C, second isolation insulation patterns 143 extending in the second direction D2 may be formed.

The first isolation insulating patterns 141 may penetrate the first and second semiconductor layers 210 and 220, the upper portions 131U of the epitaxial layer 131, and the isolation layer 105, The second isolation insulating patterns 143 may penetrate the second mask pattern 120 and the lower portions 131L of the epitaxial layer 131. [

A plurality of pin structures 133 separated from each other in the first direction D1 and the second direction D2 may be formed as the first and second isolation insulating patterns 141 and 143 are formed, The first and second semiconductor patterns 211 and 221, which are alternately stacked on the pin structures 133, may be formed. Each of the pin structures 133 may be integrally formed and includes a lower portion 133L extending in the first direction D1 and a plurality of upper portions 133U extending in the second direction D2 can do. The first and second semiconductor patterns 211 and 221 may be alternately stacked on the upper portions 133U of the pin structures 133. [

The upper surface of the second mask pattern 120 and the first and second isolation insulating patterns 141 and 143 are formed after the pin structures 133 and the first and second semiconductor patterns 211 and 221 are formed. Can be recessed. The sidewalls of the first and second semiconductor patterns 211 and 221 can be exposed and portions of the sidewalls of the upper portions 133U of the pin structures 133 can be exposed.

20A and 20B, a sacrificial gate insulating film 231 and sacrificial gate patterns 233 extending in a first direction D1 across the first and second semiconductor patterns 211 and 221 are formed And gate spacers 235 may be formed on both sidewalls of the sacrificial gate patterns 233. In embodiments, the sacrificial gate patterns 233 may be formed of a material having etch selectivity for the gate spacers 235, the second semiconductor patterns 221, and the pin structures 133. For example, the sacrificial gate patterns 233 may be formed of an impurity doped polysilicon film, an undoped polysilicon film, a silicon germanium film, or a silicon carbide film.

Subsequently, portions of the first and second semiconductor patterns 211 and 221 on both sides of the sacrificial gate patterns 233 are etched to form recessed regions, and then the source and drain patterns 240 ) Can be formed.

The source and drain patterns 240 may be formed on the upper portions 133U of the pin structures 133 on both sides of the sacrificial gate patterns 233 and may be formed on the upper portions 133U of the epitaxial It may be a free layer. Here, the source and drain patterns 240 may be made of a semiconductor material that provides tensile or compressive strain to the second semiconductor patterns 221.

Referring to FIGS. 21A and 21B, an interlayer insulating film 250 may be formed to cover the source and drain patterns 240 and expose the upper surface of the sacrificial gate patterns 233.

The gate regions 213 may be formed by sequentially removing the sacrificial gate patterns 233, the sacrificial gate insulating film 231 and the first semiconductor patterns 211 after the interlayer insulating film 250 is formed.

The sacrificial gate patterns 233 can be dry or wet etched using an etch recipe having etch selectivity for the interlayer insulating layer 250 and the gate spacers 235. [ The sacrificial gate insulating film 231 can be removed together while removing the sacrificial gate patterns 233. [ As the sacrificial gate patterns 233 are removed, the upper surface of the second semiconductor pattern 221 disposed on the uppermost layer can be exposed, and the sidewalls of the first and second semiconductor patterns 211 and 221 can be exposed have.

Then, the first semiconductor patterns 211 can be dry-etched or wet-etched using the etch recipe having the etch selectivity with respect to the second semiconductor patterns 221. Thus, the gate regions 213 can extend between the second semiconductor patterns 221. [ As the gate regions 213 are formed as the empty spaces between the second semiconductor patterns 221, a bridge channel or a nano-wire connecting the source and drain patterns 240, The second semiconductor patterns 221 may be formed.

22A and 22B, metal gate electrodes 260 surrounding the second semiconductor patterns 221 may be formed. The metal gate electrodes 260 may extend in the first direction D1 in parallel with the lower portions 133L of the pin structures 133. [ The metal gate electrodes 260 may include a gate dielectric layer 261, a barrier metal layer 263, and a metal layer 265 formed in sequence in the gate regions. Metal gate electrodes 260 may fill between the gate spacers 235 and the second semiconductor patterns 221. That is, the metal gate electrodes 260 may cover the upper surfaces, the lower surfaces, and the side surfaces of the second semiconductor patterns 221.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

Claims (20)

A semiconductor substrate made of a first semiconductor material; And
A fin structure disposed on the semiconductor substrate and made of a second semiconductor material having a lattice constant different from that of the first semiconductor material,
A lower portion extending in a first direction on the semiconductor substrate; And
And a plurality of upper portions projecting from the lower portion and extending in a second direction intersecting the first direction. The method according to claim 1,
A gate electrode extending in the first direction across the upper portions of the pin structure; And
And a gate insulating film disposed between the gate electrode and the upper portions of the fin structure. 3. The method of claim 2,
And source / drain regions provided in the upper portions of the fin structure at both sides of the gate electrode. The method according to claim 1,
The height of the lower portion is greater than twice the width of the lower portion in the second direction,
Wherein the length of the lower portion in the first direction is greater than the height of the lower portion. The method according to claim 1,
Wherein a width of the upper portion in the first direction is smaller than a width of the lower portion in the second direction,
Wherein the height of the top portion is greater than twice the width of the top portion in the first direction. The method according to claim 1,
Wherein the length of the upper portion in the second direction is greater than the width of the lower portion in the second direction. The method according to claim 1,
Wherein the lower portion comprises crystal defects and the upper portions are substantially crystal defect free. The method according to claim 1,
Further comprising: an element isolation layer in contact with both sidewalls of the lower portion facing in the second direction. 9. The method of claim 8,
Further comprising a first isolation insulation pattern in contact with both side walls of the lower portion opposite to each other in the first direction,
And the lower surface of the isolation insulating pattern is located below the lower surface of the isolation film. The method according to claim 1,
And a hard mask pattern disposed between the upper portions of the pin structure and in contact with the upper surface of the lower portion. 11. The method of claim 10,
And a second isolation insulation pattern in contact with both side walls of the upper portions opposite to each other in the first direction. A semiconductor substrate made of a first semiconductor material;
A plurality of pin structures spaced apart from each other on the semiconductor substrate, each of the pin structures comprising:
A lower portion extending in one direction on the semiconductor substrate; And
A plurality of upper portions projecting from the lower portion and traversing the lower portion;
A gate electrode extending in one direction parallel to the bottom portions of the pin structures, the gate electrodes crossing the top portions of the pin structures; And
And source / drain regions provided in upper portions of the pin structures, at both sides of the gate electrode. 13. The method of claim 12,
Wherein the lower portions of the pin structures are spaced apart from one another in the one direction below the gate electrode. 13. The method of claim 12,
Wherein the length of the lower portion in the one direction is greater than the height of the lower portion. 13. The method of claim 12,
And a hard mask pattern disposed between the top portions and in contact with the top surface of the bottom portion, in each of the pin structures. 13. The method of claim 12,
Wherein the pin structures are spaced apart from each other in a first direction and a second direction that intersect each other. 17. The method of claim 16,
Wherein the lower portions of the pin structures are parallel to the first direction and the upper portions of the pin structures are parallel to the second direction,
Wherein in the pin structures adjacent in the second direction, the distance between the upper portions is less than the distance between the lower portions. 17. The method of claim 16,
Wherein the lower portions of the pin structures are parallel to the first direction and the upper portions of the pin structures are parallel to the second direction,
And a device isolation layer disposed between the lower portions of the pin structures adjacent in the second direction and in contact with the sidewalls of the lower portions. 17. The method of claim 16,
And a first isolation insulation pattern extending in the first direction between the pin structures adjacent in the second direction,
Wherein the first isolation insulation pattern is in contact with the upper portions of the pin structures adjacent in the second direction. 17. The method of claim 16,
And a second isolation insulation pattern extending in the second direction between the pin structures adjacent in the first direction,
Wherein the second isolation insulating pattern contacts the lower portions of the pin structures adjacent in the first direction.

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