KR102589730B1 - Field Effect Transistor and Method of fabricating the same - Google Patents

Abstract

A field effect transistor and a method of manufacturing the same are provided. The field effect transistor includes a semiconductor substrate made of a first semiconductor material; A fin structure disposed on the semiconductor substrate and made of a second semiconductor material having a lattice constant different from that of the first semiconductor material, the fin structure comprising: a lower portion extending in a first direction on the semiconductor substrate; and a plurality of upper parts protruding from the lower part and extending in a second direction intersecting the first direction.

Description

Field Effect Transistor and Method of fabricating the same}

The present invention relates to semiconductor devices, and more specifically to field effect transistors.

The semiconductor device includes an integrated circuit comprised of MOS field effect transistors (MOS (Metal Oxide Semiconductor) FET). As these semiconductor devices become more highly integrated, the size down of MOS field effect transistors is also accelerating, which may deteriorate the operating characteristics of the semiconductor device. Accordingly, various methods are being studied to form semiconductor devices with better performance while overcoming the limitations caused by high integration of semiconductor devices. In particular, methods to increase the mobility of carriers (electrons or holes) are being developed to implement high-performance MOS transistors.

The problem to be solved by the present invention is to provide a field effect transistor with high integration and improved electrical characteristics.

The problem to be solved by the present invention is to provide a method of manufacturing a field effect transistor with high integration and improved electrical characteristics.

The problem to be solved by the present invention is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

In order to achieve the problem to be solved, the field effect transistor according to embodiments of the present invention includes a semiconductor substrate made of a first semiconductor material; A fin structure disposed on the semiconductor substrate and made of a second semiconductor material having a lattice constant different from that of the first semiconductor material, the fin structure comprising: a lower portion extending in a first direction on the semiconductor substrate; and a plurality of upper parts protruding from the lower part and extending in a second direction intersecting the first direction.

In order to achieve the problem to be solved, the field effect transistor according to embodiments of the present invention includes a semiconductor substrate made of a first semiconductor material; A plurality of fin structures arranged to be spaced apart from each other on the semiconductor substrate, each of the fin structures comprising: a lower portion extending in one direction on the semiconductor substrate; and a plurality of upper portions protruding from the lower portion and crossing the lower portion; a gate electrode extending in the direction parallel to the lower portions and crossing the upper portions of the fin structures; and source/drain regions provided in upper portions of the fin structures on both sides of the gate electrode.

In order to achieve the above problem, a method of manufacturing a field effect transistor according to embodiments of the present invention includes forming a device isolation film having a lower trench exposing a portion of the semiconductor substrate; forming a mask pattern having a plurality of upper trenches crossing the lower trenches on the device isolation layer; Forming an epitaxial layer epitaxially grown from the upper surface of the semiconductor substrate exposed by the lower trench and the upper trench, wherein the epitaxial layer is made of a semiconductor material having a lattice constant different from that of the semiconductor substrate, , comprising a lower portion filling the lower trench and upper portions filling the upper trenches; forming a first separation insulating pattern across upper portions of the epitaxial layer, thereby separating the epitaxial layer into a plurality of epitaxial patterns; and forming a second separation insulating pattern across a lower portion of the epitaxial layer to separate each of the epitaxial patterns into a plurality of fin structures.

According to embodiments of the present invention, when forming fin structures using a selective epitaxial growth method, crystal defects trapped in lower portions of the fin structures can be prevented from propagating to upper portions. Accordingly, the upper portions of the fin structures may be made of semiconductor material substantially free of crystal defects. Accordingly, the electrical characteristics of the field effect transistor using the upper portions of the fin structures according to embodiments of the present invention as channels can be further improved.

1A to 10A are plan views for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention.
FIGS. 1B to 10B are cross-sectional views taken along lines II' and II-II' of FIGS. 1A to 10A.
FIGS. 1C to 10C are cross-sectional views taken along lines III-III' and IV-IV' of FIGS. 1A to 10A.
FIGS. 11A and 11B are cross-sectional views of semiconductor devices according to various embodiments of the present invention. FIG. 11A shows a cross-section taken along lines II' and II-II' of FIG. 10A, and FIG. 11B shows a cross-section taken along lines III of FIG. 10A. Cross sections cut along the -III' line and IV-IV' line are shown.
FIG. 12 is a perspective view illustrating structural features of a semiconductor device according to embodiments of the present invention.
13 is a perspective view showing a fin structure of a semiconductor device according to embodiments of the present invention.
FIGS. 14A, 14B, 15A, and 15B are diagrams for explaining semiconductor devices according to various embodiments of the present invention. FIG. 14B shows a cross-section taken along line III-III' of FIG. 14A, and FIG. 15b shows a cross section taken along line III-III' in FIG. 15a.
16 and 17 illustrate semiconductor devices according to various embodiments of the present invention.
FIGS. 18A to 22A and FIGS. 18B to 22B are cross-sectional views for explaining a method of manufacturing a semiconductor device according to various embodiments of the present invention.

Hereinafter, the field effect transistor and its manufacturing method according to embodiments of the present invention will be described in detail with reference to the drawings.

1A to 10A are plan views for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention. FIGS. 1B to 10B are cross-sectional views taken along lines II-I' and II-II' of FIGS. 1A to 10A. FIGS. 1C to 10C are cross-sectional views taken along lines III-III' and IV-IV' of FIGS. 1A to 10A.

FIGS. 11A and 11B are cross-sectional views of semiconductor devices according to various embodiments of the present invention. FIG. 11A shows a cross-section taken along lines II-I' and II-II' of FIG. 10A, and FIG. 11B shows a cross-section taken along lines III of FIG. 10A. Cross sections cut along the -III' line and IV-IV' line are shown.

Referring to FIGS. 1A, 1B, and 1C, a device isolation trench 103 defining preliminary active patterns 101 may be formed by patterning the semiconductor substrate 100.

The semiconductor substrate 100 may be made of a semiconductor material, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide ( AlGaAs), or a mixture thereof.

The semiconductor substrate 100 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or It may be a substrate of an epitaxial thin film obtained by performing selective epitaxial growth (SEG). As another example, the semiconductor substrate 100 may be a group III-V compound semiconductor substrate.

In one example, the semiconductor substrate 100 may be a single crystal silicon substrate, and the upper surface of the semiconductor substrate 100 may have a (100) crystal plane or a (110) crystal plane.

According to embodiments, forming the device isolation trench 103 includes forming a first mask pattern 110 on the semiconductor substrate 100 to expose predetermined areas of the semiconductor substrate 100, and forming the first mask pattern 110 on the semiconductor substrate 100. This may include defining preliminary active patterns 101 by anisotropically etching the semiconductor substrate 100 using the pattern 110 as an etch mask.

The first mask pattern 110 may be in the form of a line extending in the first direction D1 and includes a buffer oxide pattern 111 and a hard mask pattern 113 that are sequentially stacked. In more detail, forming the first mask pattern 110 involves sequentially stacking a silicon oxide film and a hard mask film on the semiconductor substrate 100, and forming a photo layer that defines preliminary active patterns 101 on the hard mask film. This may include forming a resist pattern (not shown), and sequentially anisotropically etching the hard mask layer and the silicon oxide layer to expose the top surface of the semiconductor substrate 100 using the photoresist pattern (not shown) as an etch mask. there is. Here, the silicon oxide film may be formed by thermal oxidation of the semiconductor substrate 100. The hard mask layer may be formed of any one material selected from a silicon nitride layer, a silicon oxynitride layer, and a polysilicon layer. Additionally, the hard mask layer may be thicker than the silicon oxide layer. The thickness of the hard mask layer may vary depending on the depth of the device isolation trench 103 formed in the semiconductor substrate 100. In embodiments, the first mask pattern may be removed after forming a trench or may be removed after forming the device isolation layer 105.

According to embodiments, the preliminary active patterns 101 may have a line shape extending in the first direction D1 and are arranged to be spaced apart from each other in the second direction D2 perpendicular to the first direction D1. It can be. For example, the gap between the preliminary active patterns 101 may be larger than the width W1 of the preliminary active patterns 101. The preliminary active patterns 101 may have a sidewall profile whose width increases toward the bottom.

The device isolation trench 103 may have sidewalls that are substantially perpendicular to the upper surface of the semiconductor substrate 100 or may be inclined. The depth H1 of the device isolation trench may be greater than twice the width W1 of the preliminary active patterns 101 . Additionally, the depth H1 of the device isolation trench may be smaller than the length L1 of the preliminary active pattern in the first direction D1.

Referring to FIGS. 2A , 2B , and 2C , a device isolation film 105 may be formed in the device isolation trench 103 . The device isolation layer 105 may cover both side walls of the preliminary active patterns 101 .

Forming the device isolation layer 105 may include forming an insulating layer that fills the device isolation trench 103 and planarizing the insulating layer so that upper surfaces of the preliminary active patterns 101 are exposed. Here, the insulating film filling the device isolation trench 103 may be deposited using a deposition technique with excellent step coating properties. The insulating film may be formed using, for example, a deposition technique such as an atomic layer deposition (ALD) method, a chemical vapor deposition (CVD) method, or a plasma enhanced chemical deposition (PE-CVD) method. Additionally, the insulating film can be formed of an insulating material with excellent gap fill characteristics, for example, a boron-phosphor silicate glass (BPSG) film, a high density plasma (HDP) oxide film, It may be formed of USG (Undoped Silicate Glass) or TOSZ (Tonen SilaZene) material. Additionally, an etch back method and/or CMP (chemical mechanical polishing) method may be used as a planarization process for the insulating film. .

The device isolation layer 105 may have a sidewall that is substantially perpendicular to the upper surface of the semiconductor substrate 100. Alternatively, as shown in FIGS. 11A and 11B, the device isolation layer 105 may have a sidewall that is substantially perpendicular to the upper surface of the semiconductor substrate 100. It may also have sloping side walls.

In the embodiments, the device isolation film 105 is described as being formed within the semiconductor substrate 100, but the present invention is not limited thereto, and the device isolation film 105 is formed on the upper surface of the semiconductor substrate 100. ) may be formed to expose portions of the.

Referring to FIGS. 3A , 3B , and 3C , a second mask pattern 120 having upper trenches UR crossing the preliminary active patterns 101 may be formed.

Forming the second mask pattern 120 involves depositing a hard mask film that covers the entire surface of the semiconductor substrate 100, and forming a line extending in a second direction (D2) perpendicular to the first direction (D1) on the hard mask film. This may include forming a photoresist pattern (not shown) and anisotropically etching the hard mask layer to expose the top surface of the semiconductor substrate 100 using the photoresist pattern (not shown) as an etch mask. According to embodiments, the second mask pattern 120 may be formed of an insulating material having etch selectivity with respect to the semiconductor substrate 100 and the device isolation layer 105. The second mask pattern 120 may be formed of, for example, a silicon nitride film or a silicon oxynitride film.

According to embodiments, the upper trenches UR may expose portions of the preliminary active patterns 101 . The upper trenches UR may have a width W2 that is smaller than the width W1 of the preliminary active patterns 101 . For example, the width W2 of the upper trenches UR may be selected in the range of about 5 nm to 50 nm. The thickness H2 (that is, the height of the upper trenches UR) of the second mask pattern 120 may be greater than twice the width W2 of the upper trenches UR.

4A, 4B, and 4C, lower trenches LR are formed under the second mask pattern 120 by removing the preliminary active patterns 101 exposed by the second mask pattern 120. It can be.

According to one example, the lower trenches LR may be formed by isotropically etching the preliminary active patterns 101 . When forming the lower trenches LR, an etch recipe having etch selectivity for the device isolation layer 105 and the second mask pattern 120 may be used. For example, if the semiconductor substrate 100 is a single crystal silicon substrate, an etchant (enchant) containing HF, HNO ₃ , or NH ₄ F may be used.

Parts of the lower surface of the second mask pattern 120 and sidewalls of the device isolation layer 105 may be exposed to the lower trenches LR through an isotropic etching process for the preliminary active patterns 101 . The lower trenches LR formed in this way are empty spaces where the preliminary active patterns 101 have been removed and may extend in the first direction D1.

According to embodiments, the first height H1 of the lower trenches LR, that is, the distance from the top surface of the device isolation layer 105 to the bottom surface of the lower trenches LR, is equal to the height H1 of the lower trenches LR. It may be about twice or more than the first width (W1) of . In other words, the lower trenches LR may have an aspect ratio of about 2:1 to 3:1, and the length L1 from the lower trenches LR in the first direction D1 is equal to the length of the lower trenches (LR). It may be greater than the first height (H1) of LR). For example, the first width W1 of the lower trenches LR may be selected in the range of about 10 nm to 100 nm. Meanwhile, the present invention is not limited thereto, and the length L1 of the lower trenches LR may vary depending on the design of the semiconductor device.

In one example, the height H1 of the lower trenches LR may be substantially equal to the height of the device isolation layer 105 . In contrast, since the lower trenches LR are formed through an etching process, the lower surfaces of the lower trenches LR may be located at a different level from the lower surfaces of the device isolation layer 105. In other words, the first height H1 of the lower trenches LR may be smaller or larger than the height of the device isolation layer 105 . That is, the lower surfaces of the lower trenches LR may be located below or above the lower surface of the device isolation layer 105.

Furthermore, the surface of the semiconductor substrate 100 exposed to the lower trenches LR may have a (100) crystal plane or a (110) crystal plane. Additionally, an inclination angle of about 50 to 90 degrees may be formed between the surface of the semiconductor substrate 100 exposed to the lower trenches LR and the sidewall of the device isolation layer 105.

Referring to FIGS. 5A, 5B, and 5C, an epitaxial layer 130 may be formed to fill the lower trenches LR and upper trenches UR.

The epitaxial layer 130 may be formed using a selective epitaxial growth (SEG) process that uses the semiconductor substrate 100 exposed in the lower trenches LR as a seed. Selective epitaxial growth processes include, for example, solid phase epitaxy (SPE), vapor phase epitaxy (VPE), and liquid phase epitaxy (LPE) methods. It can be used. According to one embodiment, the epitaxial layer 130 is formed by chemical vapor deposition (CVD), reduced pressure chemical vapor deposition (RPCVD), or ultra high vacuum chemical vapor deposition (Ultra High Vacuum Chemical Vapor Deposition). It may be formed by epitaxial growth (e.g., hetero-epitaxy) using UHCVD) or Molecular Beam Epitaxy (MBE) method.

In embodiments, the epitaxial layer 130 may be formed of a semiconductor material having a lattice constant different from the semiconductor material that makes up the semiconductor substrate 100. The epitaxial layer 130 may include, for example, Si, Ge, SiGe, or group III-V compounds. Additionally, III-V compounds include, for example, aluminum phosphide (AlP), gallium phosphide (GaP), indium phosphide (InP), aluminum arsenide (AlAs), and gallium arsenide. (gallium arsenide: GaAs), indium arsenide (InAs), aluminum antimonide (AlSb), gallium antimonide (GaSb), or indium antimonide (InSb). You can.

According to embodiments, the epitaxial layer 130 is grown vertically and laterally from the surface of the semiconductor substrate 100 exposed to the lower trenches LR by a selective epitaxial growth process. can grow Accordingly, the epitaxial layer 130 may fill the lower and upper trenches LR and UR. Furthermore, during the selective epitaxial growth process, the epitaxial layer 130 may protrude beyond the upper surface of the second mask pattern 120 due to overgrowth.

The epitaxial layer 130 formed in this way may include lower portions 130L filled in the lower trenches LR and upper portions 130U filled in the upper trenches UR. The epitaxial layer 130 may be formed as a single body without boundaries between the lower portions 130L and upper portions 130U. The lower portions 130L of the epitaxial layer 130 may extend along the first direction D1, and the upper portions 130U of the epitaxial layer 130 may extend perpendicular to the first direction D1. It may extend in the second direction D2. That is, the upper portions 130U of the epitaxial layer 130 may extend horizontally from the lower portions 130L onto the device isolation layer 105. Additionally, the sidewalls of the lower portions 130L of the epitaxial layer 130 may be defined by the device isolation layer 105, and the sidewalls of the upper portions 130U of the epitaxial layer 130 may be defined by the second mask pattern. It can be defined by (120).

As an example, the epitaxial layer 130 may be grown from the top surface of a single crystal silicon substrate having a (100) crystal plane. Alternatively, the epitaxial layer 130 may be grown from the top surface of a single crystal silicon substrate having a (110) crystal plane. And, the sidewalls of the epitaxial layer 130 may be oriented in the <110> crystal direction. As an example, the sidewalls of the lower portions 130L of the epitaxial layer 130 may be oriented in the [110] crystal direction, and the sidewalls of the upper portions 130U of the epitaxial layer 130 may be oriented in the [1-10] crystal direction. ] direction.

According to embodiments, during the selective epitaxial growth process, due to the lattice constant difference between the semiconductor material forming the epitaxial layer 130 and the semiconductor material forming the semiconductor substrate 100 and the growth rate difference between crystal planes, the epitaxial layer ( The lower portions 130L of 130 may include crystal defects. For example, the lower portions 130L of the epitaxial layer 130 have threading dislocations, misfit defects, stacking faults, twin boundaries, Alternatively, it may contain various crystal defects such as anti-phase boundaries.

In more detail, when the epitaxial layer 130 is grown from the surface of the semiconductor substrate 100 (e.g., the (001) crystal plane of a silicon substrate), crystal defects 130a and 130b; e.g., threading Dislocations (threading dislocations) may propagate in the <110> crystal direction along the (111) crystal plane.These crystal defects 130a, 130b may propagate at an angle of approximately 55 degrees with respect to the (001) crystal plane of the silicon substrate. You can.

According to embodiments, as described with reference to FIGS. 4A, 4B, and 4C, the width (W1) and height (H1) of the lower trenches (LR) satisfy the condition of H1>2W1, so that the lower trenches In the widthwise direction (i.e., the second direction D2) of (LR), the crystal defects 130a do not propagate to the upper part of the lower trenches LR, but are formed on the sidewalls of the lower trenches LR. That is, it can be blocked by the sidewall of the device isolation film 105. That is, the crystal defects 130a may be trapped in the lower portion of the lower trench LR in the second direction D2.

Meanwhile, since the height (H1 in FIG. 4) of the lower trenches LR is smaller than the length (L1 in FIG. 4), the longitudinal direction (i.e., first direction D1) of the lower trenches LR The crystal defects 130b are not blocked by the sidewalls of the lower trenches LR (that is, the sidewalls of the device isolation layer 105) and may propagate to the upper portion of the lower trenches LR. In embodiments, propagation of these crystal defects 130b may be blocked by the second mask pattern 120 defining upper trenches UR extending in the second direction D2. Therefore, the upper trenches UR can be filled with the epitaxial layer 130 without crystal defects. That is, when growing the epitaxial layer 130, crystal defects may be trapped within the lower trenches LR, and the upper portions 130U of the epitaxial layer 130 filling the upper trenches UR may be substantially It can be made of a defect-free semiconductor material.

Furthermore, during the selective epitaxial growth process, the upper surface of the epitaxial layer 130 may have facets inclined with respect to the upper surface of the semiconductor substrate 100 due to differences in growth rates depending on the crystal plane. For example, the upper surface of the epitaxial layer 130 may be formed of (111) crystal planes. That is, the protruding portion of the epitaxial layer 130 that protrudes onto the upper surface of the second mask pattern 120 due to overgrowth of the epitaxial layer 130 may have a pyramid structure.

Referring to FIGS. 6A, 6B, and 6C, after forming the epitaxial layer 130, a process of planarizing the upper surface of the epitaxial layer 130 protruding above the upper surface of the device isolation film 105 is performed. It can be. As a planarization process, an etch back method and/or CMP (chemical mechanical polishing) method may be used. According to embodiments, the top surface of the epitaxial layer 130 may be substantially coplanar with the top surface of the second mask pattern 120 through the planarization process.

Subsequently, first separation insulating patterns 141 extending in the first direction D1 across the upper portions 130U of the epitaxial layer 130 may be formed.

Forming the first separation insulating patterns 141 includes forming a mask pattern (not shown) having openings extending in the first direction D1 on the second mask pattern 120 and etching the mask pattern. This may include forming trenches by anisotropically etching the epitaxial layer using it as a mask, forming a first isolation insulating film to fill the trench, and planarizing the first isolation insulating film to expose upper portions of the epitaxial layer. there is.

As an example, the first isolation insulating patterns 141 may penetrate the upper portions 130U of the epitaxial layer 130 and the device isolation layer 105. That is, when forming trenches extending in the first direction D1, the epitaxial layer 130 and the device isolation layer 105 may be etched to expose the semiconductor substrate 100. Accordingly, the first separation insulating patterns 141 may contact the semiconductor substrate 100 . In one example, lower surfaces of the first isolation insulating patterns 141 may be located below the lower surface of the device isolation layer 105. As another example, the lower surfaces of the first isolation insulating patterns 141 may be located between the upper and lower surfaces of the device isolation layer 105, as shown in FIGS. 11A and 11B.

According to embodiments, by forming the first separation insulating patterns 141, one epitaxial layer 130 is divided into a plurality of epitaxial patterns 131 spaced apart from each other in the second direction D2. You can lose. Here, each of the epitaxial patterns 131 may be formed as a single body, and may include a lower portion extending in the first direction D1 and a plurality of upper portions 131U extending in the second direction D2. ) may include. In other words, in each epitaxial pattern 131, upper portions 131U may be connected to one lower portion. The first separation insulating patterns 141 may be formed between the lower portions 131L of the epitaxial patterns 131 and are parallel to the lower portions 131L of the epitaxial patterns 131. It may be extended.

Referring to FIGS. 7A, 7B, and 7C, second separation insulating patterns 143 extend in the second direction D2 across the lower portions 131L of the epitaxial patterns 131. can be formed.

Forming the second separation insulating patterns 143 involves forming a mask pattern having openings extending in the second direction D2 on the second mask pattern 120 and using the mask pattern as an etch mask. Anisotropically etching portions of the second mask pattern 120 and the epitaxial patterns 131 to form trenches, filling the trenches with a second isolation insulating film, and exposing the second mask pattern 120. This may include flattening the second isolation insulating film as much as possible.

As another example, forming the second separation insulating patterns 143 may be performed before forming the first separation insulating patterns 141 .

As another example, the second separation insulating patterns 143 may be formed simultaneously with the first separation insulating patterns 141 described with reference to FIGS. 6A, 6B, and 6C. In this case, after forming the epitaxial layer 130, a mask pattern having openings extending in the first direction D1 and the second direction D2 may be formed on the second mask pattern 120.

The second separation insulating patterns 143 may penetrate the lower portion 131L of the epitaxial patterns 131 and contact the semiconductor substrate 100 . The lower surfaces of the second isolation insulating patterns 143 may be positioned below the lower surfaces of the device isolation layer 105 .

According to embodiments, by forming the second separation insulating patterns 143, each of the epitaxial patterns 131 is divided into a plurality of fin structures 133 spaced apart from each other in the first direction D1. You can. Here, each of the fin structures 133 may be formed as a single body, and may include a lower portion 133L extending in the first direction D1 and a plurality of upper portions extending in the second direction D2 ( 133U). That is, in each fin structure 133, upper portions 133U may be connected to one lower portion 133L. The second separation insulating patterns 143 may be formed between the lower portions 133L of the fin structures 133 adjacent in the first direction D1 and the upper portions of the plurality of fin structures 133. It may extend parallel to the fields 133U.

Referring to FIGS. 8A, 8B, and 8C, the upper surface of the second mask pattern 120 and the upper surfaces of the first and second isolation insulating patterns 141 and 143 are recessed to form fin structures ( Parts of the side walls of the upper portions 133U of 133) may be exposed.

In one example, the first and second separation insulating patterns 141 and 143 may be formed of an insulating material that has etch selectivity with respect to the second mask pattern 120 . In this case, the recess process of exposing the side walls of the upper portions 133U of the fin structures 133 includes an etching process of recessing the upper surfaces of the first and second isolation insulating patterns 141 and 143, and An etching process to recess the upper surface of the second mask pattern 120 may be sequentially performed. As another example, the top surfaces of the first and second isolation insulating patterns 141 and 143 and the top surface of the second mask pattern 120 may be etched simultaneously.

In embodiments, the recessed first and second isolation insulating patterns 141 and 143 and the recessed second mask pattern 121 are formed on the lower portions 133L of the fin structures 133. The fields 133 may surround portions of the upper portions 133U.

Referring to FIGS. 9A, 9B, and 9C, a gate insulating film 151 and a gate electrode 153 may be formed across the upper portions 133U of the fin structures 133.

According to embodiments, the gate electrode 153 may extend in the first direction D1 parallel to the lower portions 133L of the fin structures 133. The gate insulating film 151 and the gate electrodes 153 may overlap lower portions 133L of the fin structures 133 in a plan view. That is, the lower portions 133L of the fin structures 133 may be arranged to be spaced apart from each other in the first direction D1 under the gate electrode 153. In embodiments, the gate electrode 153 may be less than or equal to the width of the lower portions 133L of the fin structures 133.

The gate insulating layer 151 may be formed of a high-k dielectric layer such as hafnium oxide, hafnium silicate, zirconium oxide, or zirconium silicate. The gate insulating layer 151 may be formed using atomic layer deposition technology and may conformally cover the surfaces of the upper portions 133U of the fin structures 133. As another example, the gate insulating layer 151 may be formed by thermally oxidizing the surfaces of the upper portions 133U of the fin structures 133 exposed by the recessed second mask pattern 121.

The gate electrode 153 may be formed, for example, of a polysilicon film doped with impurities, an undoped polysilicon film, a silicon germanium film, or a silicon carbide film. As another example, the gate electrodes may be made of a semiconductor material doped with a dopant (e.g., doped silicon, etc.), a metal (e.g., tungsten, aluminum, titanium, and/or tantalum), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and/or or tungsten nitride) and a metal-semiconductor compound (ex, metal silicide).

After forming the gate electrode 153, gate spacers 155 may be formed on both walls of the gate electrode 153. Forming the gate spacers may include forming a gate spacer film conformally covering the gate electrode 153 and anisotropically etching the entire gate spacer film.

Referring to FIGS. 10A, 10B, and 10C, source and drain regions 160 may be formed in the upper portions 133U of the fin structures 133 on both sides of the gate electrode 153.

According to one example, forming the source and drain regions 160 includes etching portions of the upper portions 133U of the fin structures 133 on both sides of the gate electrode 153, and forming the epitaxial layer. It may include forming a . Here, the epitaxial layer may be made of a semiconductor material that provides tensile or compressive strain in the channel region of the field effect transistor. For example, when forming NMOS field effect transistors, the epitaxial layer may be made of silicon carbide (SiC). In contrast, when forming PMOS field effect transistors, the epitaxial layer may be made of silicon germanium (SiGe). Meanwhile, although not shown in the drawing, a silicide film such as nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, niobium silicide, or tantalum silicide may be formed on the surfaces of the source and drain electrodes.

According to another example, forming the source and drain regions 160 uses the gate electrode 153 as an ion implantation mask to form n-type or p-type ions in the upper portions 133U of the fin structures 133. It may include ion implantation of impurities.

After forming the source and drain regions 160, a first interlayer insulating film 165 may be formed covering the gate electrode 153 and the source and drain regions 160. As an example, the first interlayer insulating film 165 may fill the space between the gate electrodes 153 and expose the upper surfaces of the gate electrodes 153.

According to some embodiments, after forming the first interlayer insulating films 165, processes may be performed to replace the gate electrodes 153 with metal gate electrodes 170. In detail, forming the metal gate electrode 170 involves removing the gate electrode 153 to form a gate region between the gate spacers 155 and forming a gate dielectric film 171 and a barrier metal film within the gate regions. It may include sequentially forming (173) and a metal film (175).

The gate dielectric layer 171 may be formed of a high dielectric layer such as hafnium oxide, hafnium silicate, zirconium oxide, or zirconium silicate. The barrier metal film 173 may be formed of a conductive material having a predetermined work function, for example, a metal nitride film such as titanium nitride, tantalum nitride, tungsten nitride, hafnium nitride, and zirconium nitride. . The metal film 175 may be formed of one of materials having a lower resistivity than the barrier metal film. The metal film 175 may be formed of, for example, one or a combination of tungsten, copper, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal nitride. You can.

In this way, after forming the metal gate electrodes 170, the second interlayer insulating film 180 may be formed on the first interlayer insulating film 165 to cover the upper surfaces of the metal gate electrodes 170.

FIG. 12 is a perspective view illustrating structural features of a semiconductor device according to embodiments of the present invention. 13 is a perspective view showing a fin structure of a semiconductor device according to embodiments of the present invention. For simplicity of description, description of the same technical features as in the manufacturing method described above with reference to FIGS. 1A to 10A, 1B to 10B, and 1C to 10C may be omitted.

Referring to FIGS. 12 and 13 , a plurality of fin structures 133 may be arranged to be spaced apart from each other on the semiconductor substrate 100 . As an example, the fin structures 133 may be arranged to be spaced apart from each other in the first direction D1 and the second direction D2 that intersect each other.

According to embodiments, the semiconductor substrate 100 may be made of a first semiconductor material, and the fin structures 133 may be made of a second semiconductor material having a lattice constant different from the first semiconductor material. As an example, the second semiconductor material may have a lattice constant greater than that of the first semiconductor material. The first and second semiconductor materials are, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or these. It may include at least one of a mixture of.

According to embodiments, each of the fin structures 133 includes a lower portion 133L extending in the first direction D1 on the semiconductor substrate 100 and a second portion protruding from the lower portion and intersecting the first direction D1. It may include a plurality of upper portions 133U extending in two directions D2. Here, the first direction D1 may be a [110] crystal direction, and the second direction D2 may be a [1-10] crystal direction perpendicular to the first direction D1.

In more detail, referring to FIG. 13, in each of the fin structures 133, the lower portion 133L has a first length L1 in the first direction D1 and a first length L1 in the second direction D2. It can have a width of 1 (W1). Additionally, the lower portion 133L may have a first height H1 that is approximately twice the first width W1. Additionally, the first length L1 of the lower portion 133L may be greater than the first height H1.

In each of the fin structures 133, each of the upper portions 133U may have a second width W2 that is smaller than the first width W1 in the first direction D1, and It may have a second length (L2). Additionally, the upper portions 133U may have a second height H2 that is approximately twice the second width W2.

In embodiments, each of the fin structures 133 may be formed as a single body. In other words, there may be no boundary between the lower portion 133L and the upper portions 133U of each fin structure 133. In each of the fin structures 133, the lower portion 133L may have crystal defects propagated in an oblique direction to the upper surface of the semiconductor substrate 100. For example, it may include crystal defects 130a propagating in the second direction D2 and crystal defects 130b propagating in the first direction D1 in the (111) crystal plane. Here, crystal defects propagating in the second direction D2 may be blocked from propagating to the upper portions 133U of each fin structure 133 by the mask pattern disposed between the upper portions 133U. Accordingly, the upper portions 133U of the fin structures 133 may be made of a defect-free second semiconductor material.

10A, 10B, and 10C and 12, the lower portions 133L of the fin structures 133 adjacent in the second direction D2 may be spaced apart from each other by a first distance S1. The upper portions 133U may be spaced apart from each other by a second distance S2 that is smaller than the first distance S1.

The device isolation layer 105 may be disposed between lower portions 133L of adjacent fin structures 133 in the second direction D2. The first separation insulating pattern 141 may be disposed between the upper portions 133U of adjacent fin structures 133 in the second direction D2, and the upper surface of the first separation insulating pattern 141 may be It may be located below the upper surfaces of the upper portions 133U of the fin structures 133.

The lower portions 133L of the fin structures 133 adjacent in the first direction D1 may be spaced apart by a third distance S3, and the fin structures 133 adjacent in the first direction D1 may be spaced apart from each other by a third distance S3. The upper portions 133U may be spaced apart by a fourth distance S4 that is greater than the third distance S3.

A second separation insulating pattern may be disposed between lower portions 133L of adjacent fin structures 133 in the first direction D1, and the upper surface of the second separation insulating pattern 143 may be disposed between the fin structures 133L. It may be located below the upper surfaces of the upper portions (133U) of (133).

Referring again to FIG. 12 , the metal gate electrode 170 may be disposed across the upper portions 133U of the fin structures 133 spaced apart in the first direction D1. In addition, the metal gate electrode 170 may overlap the lower portions 133L of the fin structures 133 spaced apart in the first direction D1 from a plan view. In other words, the lower portions 133L of the fin structures 133 adjacent in the first direction D1 may be spaced apart from each other under the metal gate electrode 170.

The gate insulating film may be disposed between the metal gate electrode 170 and the upper portions 133U of the fin structure 133, and may have a uniform thickness and cover the surfaces of the upper portions 133U. Source and drain regions 160 may be provided on the upper portions 133U of each fin structure 133 on both sides of the metal gate electrode 170.

FIGS. 14A, 14B, 15A, and 15B are diagrams for explaining semiconductor devices according to various embodiments of the present invention. FIG. 14B shows a cross-section taken along line III-III' of FIG. 14A, and FIG. 15b shows a cross section taken along line III-III' in FIG. 15a. For simplicity of explanation, description of the same technical features as in the previously described manufacturing method may be omitted.

Referring to FIGS. 14A and 14B , the fin structures 133 may be arranged to be spaced apart from each other in the first direction D1 and the second direction D2 on the semiconductor substrate 100 . According to this embodiment, the spacing between adjacent fin structures 133 in the first direction D1 may be different. That is, the widths of the second separation insulating patterns 143a and 143b extending in the second direction D2 may be different from each other.

According to some embodiments, in the fin structures 133, the number of upper portions 133U protruding from the lower portion 133L may be different. In other words, the number of upper portions 133U in one of the fin structures 133 may be different from the number of upper portions 133U in the other fin structure 133.

Referring to FIGS. 15A and 15B , the semiconductor substrate 100 may include a first region (R1) and a second region (R2). A plurality of fin structures 133 may be spaced apart from each other in the first direction D1 and a second direction D2 crossing the first direction D1 in each of the first and second regions R1 and R2. there is.

In one example, the device isolation layer 105 may be disposed between the fin structures 133 in the first region R1 and the fin structures 133 in the second region R2 in the first direction D1. . In each of the first and second regions R1 and R2, the lower portions 133L of the fin structures 133 adjacent to each other in the first direction D1 are separated from the first by the second separation insulating pattern 143. They can be separated by distance. In addition, the lower portions 133L of the fin structures 133 of the first and second regions R1 and R2 adjacent in the first direction D1 are spaced apart by a second distance by the device isolation layer 105. It can be. Here, the second distance may be greater than the first distance.

The metal gate electrodes 170 may be disposed across the first and second regions R1 and R2, and in the upper portions of the fin structures 133 of the first and second regions R1 and R2. You can cross the field (133U).

16 and 17 illustrate semiconductor devices according to various embodiments of the present invention. For simplicity of explanation, description of the same technical features as in the previously described manufacturing method may be omitted.

Referring to FIGS. 16 and 17 , the semiconductor substrate 100 may include a first region (R1) and a second region (R2). For example, the first region R1 may be a region where NMOS field effect transistors are formed, and the second region R2 may be a region where PMOS field effect transistors are formed.

According to embodiments, a first fin structure 133N may be disposed on the semiconductor substrate 100 in the first region R1, and a second fin may be disposed on the semiconductor substrate 100 in the second region R2. The structure 133P may be disposed. For example, the first fin structure 133N and the second fin structure 133P may be spaced apart from each other in the first direction D1.

According to the embodiment shown in FIG. 16, the first fin structure 133N has a lower portion 133L extending in the first direction D1 and protruding from the lower portion 133L in the second direction, as described above. It may include upper portions 133U extending to (D2). The first fin structure 133N may be made of any epitaxial material and may have a lattice constant different from that of the semiconductor substrate 100. According to one example, the semiconductor substrate 100 may be made of silicon (Si), and the first fin structure 133N may be made of silicon germanium (Si1-xGex).

The second fin structure FS may include a buffer pattern 133P on the semiconductor substrate 100 and channel patterns 137 on the buffer pattern 133P. The buffer pattern 133P of the second fin structure FS may be an integrated epitaxial layer. That is, similar to the first fin structure 133N, the buffer pattern 133P has a lower portion 133L extending in the first direction D1 and protruding from the lower portion 133L in the second direction D2. It may include extending upper portions 133U. In the second fin structure FS, the upper surfaces of the upper portions 133U of the buffer pattern 133P may be positioned below the upper surfaces of the upper portions 133U of the first fin structure 133N. Additionally, the upper surfaces of the channel patterns 137 may be substantially coplanar with the upper surfaces of the upper portions 133U of the first fin structure 133N.

For example, the buffer pattern 133P of the second fin structure FS may be made of the same semiconductor material as that of the first fin structure 133N. The channel patterns 135 of the second fin structure FS are disposed on the upper portions 133U of the buffer pattern 133P, and may be made of a material having an energy band gap difference from that of the buffer pattern 133P. As an example, the channel patterns 135 may be made of Si or Ge. As another example, the buffer pattern 133P may be made of Si1-xGex, and the channel patterns 135 may be made of Si1-yGey (where y>x). As another example, the buffer pattern 133P and the channel patterns 135 are made of a group III-V compound, but their energy band gaps may be different from each other. According to one example, the channel patterns 137 of the second fin structure FS may be formed using a selective epitaxial growth process using the upper surfaces of the upper portions 133U of the buffer pattern 133P as seeds. You can. Additionally, an interface may exist between the upper portions 133U of the buffer pattern 133P and the channel patterns 137. According to embodiments, the upper portions 133U of the buffer pattern 133P are made of a semiconductor material without crystal defects, so crystal defects in the channel patterns 137 may be reduced.

According to the embodiment shown in FIG. 17, the first fin structure FS1 may include a first buffer pattern 133N and first channel patterns 137, and the second fin structure FS2 may include a second It may include a buffer pattern 133P and second channel patterns 135. Here, each of the first and second buffer patterns 133N and 133P may be made of an integrated semiconductor material, as described above, and may include a lower portion 133L extending in the first direction D1 and a lower portion ( It may include upper portions 133U that protrude from 133L and extend in the second direction D2.

The first channel patterns 137 may be formed of a material having an energy band gap difference from the first buffer pattern 133N. In one example, the first buffer pattern 133N may be made of Si _{1 - x} Ge _x , and the first channel patterns 137 may be made of Si _{1 - y} Ge _y. (Here, x>y). As another example, the first buffer pattern 133N may be made of In _{1 - x} Ga _x As, and the first channel patterns 137 may be made of In _{1 - y} Ga _y As (where x < y). there is. According to embodiments, the first channel patterns 137 may be made of an epitaxial material grown from the upper surfaces of the upper portions 133U of the first buffer pattern 133N.

The second channel patterns 135 may be formed of a material having an energy band gap difference from the second buffer pattern 133P. Additionally, the second channel patterns 135 may be made of a different material from the first channel patterns 137 . For example, when the second buffer pattern 133P is formed of Si _{1 - x} Ge _x , the second channel patterns 135 may be formed of Si _{1 - z} Ge _{z (} where Z>x). As another example, when the second buffer pattern 133P is made of In _{1 - z} Ga _z As, the second channel patterns 135 may be made of In _{1 - w} Ga _w As (where z>w). . According to embodiments, the second channel patterns 135 may be made of an epitaxial material grown from the upper surfaces of the upper portions 133U of the second buffer pattern 133P.

FIGS. 18A to 22A and 18B to 22B are cross-sectional views for explaining a method of manufacturing a semiconductor device according to various embodiments of the present invention. FIGS. 18A to 22A are taken along lines II-I' and II-II' of FIG. 10A. Figures 18b to 22b show cross-sections cut along lines III-III' and IV-IV' of Figure 10a.

For simplicity of description, description of the same technical features as in the manufacturing method described above with reference to FIGS. 1A to 10A, 1B to 10B, and 1C to 10C may be omitted.

As described with reference to FIGS. 1 to 4 , a device isolation film 105 having a lower trench LR exposing a portion of the semiconductor substrate 100, and a device isolation film 105 crossing the lower trenches LR After forming the second mask pattern 120 having a plurality of upper trenches UR, the epitaxial layer 130 may be formed to fill the lower trenches LR and the upper trenches UR. As described with reference to FIGS. 5A, 5B, and 5C, the epitaxial layer 130 includes a lower portion 133L that fills the lower trench LR and upper portions 133U that fill the upper trenches UR. It can be included. According to one example, the upper portions 133U of the epitaxial layer 130 may fill a portion of the upper trenches UR.

Continuing to refer to FIGS. 18A and 18B, first semiconductor layers 210 and second semiconductor layers 220 are alternately and repeatedly stacked on the upper portions 133U of the epitaxial layer 130. You can. The first and second semiconductor layers 210 and 220 may be made of a semiconductor material having etch selectivity to each other, and may be stacked by performing a selective epitaxial growth (SEG) process. Additionally, the first semiconductor layers 210 may be made of a semiconductor material that has etch selectivity with respect to the epitaxial layer 130. The second semiconductor layers 210 may be made of the same semiconductor material as the epitaxial layer 130, or may be made of a semiconductor material different from the epitaxial layer 130. In embodiments, the first semiconductor layers 210 may have a different lattice constant than the second semiconductor layers 220 .

The first and second semiconductor layers 210 and 220 may include, for example, Si, Ge, SiGe, or group III-V compounds. Here, III-V compounds include, for example, aluminum phosphide (AlP), gallium phosphide (GaP), indium phosphide (InP), aluminum arsenide (AlAs), and gallium arsenide. (gallium arsenide: GaAs), indium arsenide (InAs), aluminum antimonide (AlSb), gallium antimonide (GaSb), or indium antimonide (InSb). You can.

For example, the first semiconductor layers 210 may be made of Ge, and the second semiconductor layers 220 may be made of SiGe. As another example, the first and second semiconductor layers 210 and 220 may be made of SiGe, but the germanium concentration in the first and second semiconductor layers 210 and 220 may be different. As another example, the first semiconductor layers 210 may be made of indium arsenide (InAs), and the second semiconductor layers 220 may be made of gallium antimonide (GaSb).

In embodiments, the first and second semiconductor layers 210 and 220 are formed on the upper portions 133U of the epitaxial layer 130 free of crystal defects, so that the first and second semiconductor layers ( 210, 220) crystallinity can be improved.

The stacked first and second semiconductor layers 210 and 220 may fill the upper trenches UR defined by the second mask pattern 120 . Accordingly, the first and second semiconductor layers 210 and 220 may have a line shape extending in the second direction D2.

Referring to FIGS. 19A and 19B , first separation insulating patterns 141 extending in the first direction D1 may be formed, as described with reference to FIGS. 6A , 6A , and 6C . As described with reference to FIGS. 7B and 7C , second separation insulating patterns 143 extending in the second direction D2 may be formed.

The first isolation insulating patterns 141 may penetrate the first and second semiconductor layers 210 and 220, upper portions 131U of the epitaxial layer 131, and the device isolation layer 105, The second separation insulating patterns 143 may penetrate the second mask pattern 120 and the lower portions 131L of the epitaxial layer 131.

As the first and second separation insulating patterns 141 and 143 are formed, a plurality of fin structures 133 spaced apart from each other in the first direction D1 and the second direction D2 may be formed, respectively. First and second semiconductor patterns 211 and 221 alternately stacked may be formed on the fin structures 133 . Here, each of the fin structures 133 may be integrally formed and includes a lower portion 133L extending in the first direction D1 and a plurality of upper portions 133U extending in the second direction D2. can do. The first and second semiconductor patterns 211 and 221 may be alternately stacked on the upper portions 133U of each fin structure 133.

After forming the fin structures 133 and the first and second semiconductor patterns 211 and 221, the upper surface of the second mask pattern 120 and the first and second isolation insulating patterns 141 and 143 are formed. The upper surfaces of may be recessed. Accordingly, sidewalls of the first and second semiconductor patterns 211 and 221 may be exposed, and portions of sidewalls of the upper portions 133U of the fin structures 133 may be exposed.

Referring to FIGS. 20A and 20B , a sacrificial gate insulating layer 231 and sacrificial gate patterns 233 extending in the first direction D1 across the first and second semiconductor patterns 211 and 221 are formed. may be formed, and gate spacers 235 may be formed on both walls of the sacrificial gate patterns 233. In embodiments, the sacrificial gate patterns 233 may be formed of a material that has etch selectivity with respect to the gate spacer 235, the second semiconductor patterns 221, and the fin structures 133. For example, the sacrificial gate patterns 233 may be formed of a polysilicon film doped with impurities, an undoped polysilicon film, a silicon germanium film, or a silicon carbide film.

Subsequently, portions of the first and second semiconductor patterns 211 and 221 on both sides of the sacrificial gate patterns 233 are etched to form recess regions, and then source and drain patterns 240 are formed in the recess regions. ) can be formed.

Source and drain patterns 240 may be formed on the upper portions 133U of the fin structures 133 on both sides of the sacrificial gate patterns 233, and may be formed using a selective epitaxial growth process. It may be superficial. Here, the source and drain patterns 240 may be made of a semiconductor material that provides tensile or compressive strain to the second semiconductor patterns 221 .

Referring to FIGS. 21A and 21B , an interlayer insulating film 250 may be formed to cover the source and drain patterns 240 and expose the upper surfaces of the sacrificial gate patterns 233 .

After forming the interlayer insulating layer 250, gate regions 213 may be formed by sequentially removing the sacrificial gate patterns 233, the sacrificial gate insulating layer 231, and the first semiconductor patterns 211.

The sacrificial gate patterns 233 may be dry or wet etched using an etch recipe having etch selectivity for the interlayer insulating film 250 and the gate spacers 235 . While removing the sacrificial gate patterns 233, the sacrificial gate insulating layer 231 may be removed together. By removing the sacrificial gate patterns 233, the top surface of the second semiconductor pattern 221 disposed on the uppermost layer may be exposed, and the sidewalls of the first and second semiconductor patterns 211 and 221 may be exposed. there is.

Subsequently, the first semiconductor patterns 211 may be dry or wet etched using an etch recipe having etch selectivity for the second semiconductor patterns 221 . Accordingly, the gate regions 213 may extend between the second semiconductor patterns 221 . In this way, as the gate regions 213, which are empty spaces between the second semiconductor patterns 221, are formed, a bridge channel or nano-wire connecting the source and drain patterns 240 is formed. ) Second semiconductor patterns 221 may be formed as channels.

Referring to FIGS. 22A and 22B , metal gate electrodes 260 may be formed surrounding the second semiconductor patterns 221 . The metal gate electrodes 260 may extend in the first direction D1 and parallel to the lower portions 133L of the fin structures 133. The metal gate electrodes 260 may include a gate dielectric film 261, a barrier metal film 263, and a metal film 265 sequentially formed in the gate regions. Metal gate electrodes 260 may fill spaces between the gate spacers 235 and the second semiconductor patterns 221 . That is, the metal gate electrodes 260 may cover the top, bottom, and side surfaces of the second semiconductor patterns 221 .

Above, embodiments of the present invention have been described with reference to the attached drawings, but those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features. You will understand that it exists. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims (20)

A semiconductor substrate made of a first semiconductor material;
A fin structure disposed on the semiconductor substrate and made of a second semiconductor material having a lattice constant different from the first semiconductor material, the fin structure comprising:
a lower portion extending in a first direction on the semiconductor substrate; and
comprising a plurality of upper parts protruding from the lower part and extending in a second direction intersecting the first direction and intersecting the lower part; and
A field effect transistor comprising a gate structure extending in the first direction across the upper portions of the fin structure and parallel to the lower portion. According to claim 1,
The gate structure is:
a gate electrode extending in the first direction across the upper portions of the fin structure; and
A field effect transistor including a gate insulating film disposed between the gate electrode and the upper portions of the fin structure. According to claim 2,
A field effect transistor further comprising source/drain regions provided within the upper portions of the fin structure on both sides of the gate electrode. According to claim 1,
The height of the lower portion is greater than twice the width of the lower portion in the second direction,
A field effect transistor wherein the length of the lower portion in the first direction is greater than the height of the lower portion. According to claim 1,
The width of the upper portion in the first direction is smaller than the width of the lower portion in the second direction,
A field effect transistor wherein the height of the upper portion is greater than twice the width of the upper portion in the first direction. According to claim 1,
A field effect transistor wherein the length of the upper portion in the second direction is greater than the width of the lower portion in the second direction. According to claim 1,
A field effect transistor wherein the lower portion includes crystal defects and the upper portion is substantially defect-free. According to claim 1,
The fin structure is a field effect transistor consisting of one body without a boundary between the lower part and the upper part. According to claim 1,
A field effect transistor further comprising a device isolation film in contact with both walls of the lower portion facing in the second direction. According to clause 9,
Further comprising a first separation insulating pattern in contact with both walls of the lower portion facing in the first direction,
A field effect transistor wherein the lower surface of the first isolation insulating pattern is located below the lower surface of the device isolation film. According to claim 1,
A field effect transistor further comprising a hard mask pattern disposed between the upper portions of the fin structure and in contact with an upper surface of the lower portion. According to claim 11,
A field effect transistor further comprising a second isolation insulating pattern in contact with both walls of the upper portions facing in the first direction. A semiconductor substrate made of a first semiconductor material;
A plurality of fin structures arranged to be spaced apart from each other on the semiconductor substrate, each of the fin structures:
a lower portion extending in one direction on the semiconductor substrate; and
comprising a plurality of upper portions protruding from the lower portion and intersecting the lower portion;
a plurality of gate electrodes extending in the one direction parallel to the lower portions of the fin structures and crossing the upper portions of the fin structures; and
A field effect transistor comprising source/drain regions provided in upper portions of the fin structures, on both sides of the gate electrodes. According to claim 13,
A field effect transistor wherein the lower portions of the fin structures are arranged to be spaced apart from each other in the one direction below the gate electrode. According to claim 13,
A field effect transistor wherein the length of the lower portion in the one direction is greater than the height of the lower portion. According to claim 13,
In each of the fin structures, a field effect transistor further comprising a hard mask pattern disposed between the upper portions and in contact with an upper surface of the lower portion. According to claim 12,
A field effect transistor wherein the fin structures are spaced apart from each other in a first direction and a second direction that intersect each other. According to claim 17,
the lower portions of the fin structures are parallel to the first direction and the upper portions of the fin structures are parallel to the second direction,
A field effect transistor wherein, in the fin structures adjacent in the second direction, a distance between the upper portions is smaller than a distance between the lower portions. According to claim 17,
the lower portions of the fin structures are parallel to the first direction and the upper portions of the fin structures are parallel to the second direction,
A field effect transistor further comprising a device isolation film disposed between the lower portions of the fin structures adjacent in the second direction and in contact with sidewalls of the lower portions. According to claim 17,
a first separation insulating pattern extending in the first direction between the fin structures adjacent in the second direction; and
Further comprising a second separation insulating pattern extending in the second direction between the fin structures adjacent in the first direction,
the first isolation insulating pattern contacts the upper portions of the fin structures adjacent in the second direction,
The second isolation insulating pattern is a field effect transistor in contact with the lower portions of the fin structures adjacent to each other in the first direction.

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