KR20170114211A - Organic Light Emitting Display Device - Google Patents

Abstract

The present invention relates to an organic light emitting display device capable of reducing or suppressing a kickback effect within a light emission period for image display and compensating or preventing luminance distortion.
The present invention is characterized in that, when the display is driven, the on / off state of the light emission control TFT connected between the high potential driving power supply and the drain electrode of the driving TFT is controlled so that the drain electrode of the driving TFT is not floated when the switching TFT causing kickback is turned off Design the timing appropriately.

Description

[0001] The present invention relates to an organic light emitting display device,

The present invention relates to an organic light emitting display.

An active matrix type organic light emitting display device includes an organic light emitting diode (OLED) which emits light by itself, and has a high response speed, a high luminous efficiency, a high brightness and a wide viewing angle There are advantages.

The OLED, which is a self-luminous element, includes an anode electrode, a cathode electrode, and an organic compound layer formed therebetween. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). When a power source voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons. As a result, the light emitting layer (EML) Thereby generating visible light.

The organic light emitting display device arranges pixels each including an OLED and a driving TFT (Thin Film Transistor) in a matrix form, and adjusts the brightness of an image implemented in pixels according to gray levels of video data. The driving TFT controls the driving current flowing in the OLED according to the voltage applied between its gate electrode and the source electrode. The light emission amount of the OLED is determined according to the driving current, and the brightness of the image is determined according to the amount of light emitted from the OLED.

In general, when the driving TFT operates in the saturation region, the driving current Ids flowing between the drain and the source of the driving TFT is expressed by the following equation (1).

[Equation 1]

Ids = 1/2 * (μ * C * W / L) * (Vgs-Vth) ²

In the equation (1), μ represents the electron mobility, C represents the capacitance of the gate insulating film, W represents the channel width of the driving TFT, and L represents the channel length of the driving TFT. Vgs represents the gate node-source node voltage (potential difference) of the driving TFT, and Vth represents the threshold voltage (or threshold voltage) of the driving TFT. The gate-source node voltage (Vgs) of the driving TFT corresponds to the difference voltage between the data voltage and the reference voltage. Since the data voltage is an analog voltage corresponding to the gradation of the video data and the reference voltage is a fixed voltage, the gate node-source node voltage (Vgs) of the driving TFT is programmed or set according to the data voltage. Then, the drive current Ids is determined according to the programmed gate-source voltage Vgs.

One frame period in the display driving is divided into a programming period for setting the gate node to source node voltage (Vgs) of the driving TFT and a driving period for driving the OLED with the driving current according to the programmed gate node to source node voltage (Vgs) And a light emission period. During the programming period, the data voltage is applied to either the gate electrode or the source electrode of the driving TFT through the first switch TFT provided in the pixel, and the reference voltage is applied to the gate electrode of the driving TFT through the second switch TFT provided in the pixel, And may be applied to the other one of the electrodes. To this end, the first switch TFT and the second switch TFT are turned on during the programming period, and can be turned off during the light emitting period subsequent to the programming period. On the other hand, in the pixel, a light emission control TFT capable of controlling the current path between the driving TFT and the high potential driving power supply may be further provided. The emission control TFT is turned off during the programming period to cut off the current path between the high potential driving power supply and the driving TFT and to prevent the abnormal emission of the OLED. The light emission control TFT is turned on in the light emission period subsequent to the programming period to connect the high potential driving power source to the driving TFT so that the driving current flows into the OLED during the light emission period.

The inventors of the present invention have continued various research and development to commercialize an organic light emitting display capable of providing an excellent image quality.

The inventors of the present invention have continued various research and development on an organic light emitting display capable of pulse duty driving with various advantages.

The inventors of the present invention have conducted various experiments to realize pulse duty driving and have found that the pixels of the organic light emitting display are affected by kick back due to the parasitic capacitance existing in the TFT in the light emitting period, I recognized the problem that could be distorted.

Specifically, there is a parasitic capacitance between the various electrodes of the TFTs in the pixel depending on the stacking structure. The drain electrode of the drive TFT coupled to the gate electrode of the switch TFT by the parasitic capacitance may be affected by kick back when the switch TFT is turned off in the light emission period. The potential of the drain electrode of the driving TFT is lowered due to the effect of the kickback, and rises to the high potential driving power supply when the light emission control TFT is turned on. At this time, the potential of the gate electrode of the driving TFT can also rise. This is because parasitic capacitance exists also between the gate electrode and the drain electrode of the driving TFT. When the potential of the gate electrode of the driving TFT set in the programming period is changed in the light emission period, the gate node-source node voltage Vgs is changed. In this case, the inventors of the present invention have recognized the problem that the amount of driving current (Ids) passing through the driving TFT is changed to cause luminance distortion of the organic light emitting display device.

That is, the inventors of the present invention have found that when the first switch TFT is turned off in the light emission period in which the pulse duty drive is implemented, the drive TFT is not connected to the high potential drive power source, , A problem that a hump occurs in the luminance-gradation curve due to the influence of the kickback caused by the luminance-gradation curve.

The inventors of the present invention have recognized the problem that not only the kickback phenomenon but also the luminance uniformity between the pixels is lowered due to the electrical characteristic deviation between the pixels of the organic light emitting display device.

Specifically, it has been recognized that electrical characteristics such as the threshold voltage and electron mobility of the driving TFT of each pixel can be a factor that determines the amount of driving current (Ids) of the driving TFT. For example, the electrical characteristic deviations of the driving TFTs are caused by various causes such as process characteristics and time-varying characteristics. Therefore, it has been recognized that when the same data voltage is applied to the pixels having different electric characteristics of the driving TFT, the luminance uniformity between pixels is lowered.

On the other hand, the inventors of the present invention have continued to research and develop narrow bezel technology that can provide excellent image quality and reduce the width of the peripheral region of the pixel region of the organic light emitting display device.

The inventors of the present invention designed compensation circuits to improve the luminance distortion and the problem of lowering the luminance uniformity between pixels. However, when these compensation circuits were added, they recognized various problems that could make it difficult to implement a narrow bezel.

Specifically, when a gate driver is implemented with a compensation circuit for compensating for the electrical characteristic variation of the driving TFT of the pixel and a driving circuit capable of controlling the light emission control TFT, the area of the gate driver is increased and the problem of increasing the bezel area is recognized Respectively.

Specifically, in order to solve the electrical characteristic variation of the driving TFT of the driving pixel, a sensing portion is provided in the source driver and the voltage of the specific node connected to the source electrode of the driving TFT is sensed or the driving current flowing to the driving TFT is sensed The sensing unit must include a plurality of sensing units connected to a plurality of output channels and analog-to-digital converters (ADCs) connected to the sensing units.

In particular, the sensing unit and the ADC should be mounted in the source driver as many as the number of output channels of the source driver. However, since the circuit size of the sensing unit and the ADC is relatively large as compared with other digital circuits, The number of output channels of the source driver increases and the channel spacing becomes rather narrow.

Accordingly, it is recognized that the area of the sensing portion of the high resolution and highly integrated organic light emitting display device increases.

That is, if the various circuits are designed to solve the problems of the luminance distortion of the organic light emitting display device and the degradation of the luminance uniformity between pixels, the difficulty of implementation of the narrow bezel is further increased.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an organic light emitting display device capable of reducing or suppressing a kickback effect and compensating or preventing luminance distortion when implementing pulse duty driving in a light emission period for image display have.

An object of the present invention is to provide an organic light emitting display device capable of reducing the area occupied by a driving circuit in a bezel region, which can compensate for luminance distortion and luminance uniformity between pixels.

An object of the present invention is to provide an organic light emitting diode (OLED) display device capable of reducing the size of a gate driver provided in a display panel of an OLED display.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

In order to achieve the above object, the organic light emitting diode display of the present invention can be implemented as shown in FIGS. 1 to 30.

According to the embodiments of the present invention, there is an advantage that the kickback effect can be reduced or suppressed within the light emission period for displaying an image, and the luminance distortion can be compensated or prevented to enhance the image quality.

The present invention is advantageous in that the luminance uniformity between pixels can be improved in image display and the image quality can be enhanced.

According to the embodiments of the present invention, by reducing the area occupied by a driving circuit capable of compensating for luminance distortion and inter-pixel luminance uniformity in the bezel region, it is possible to realize a narrow bezel while reducing manufacturing cost and flexibility in a high- Can respond.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 is a block diagram schematically illustrating an organic light emitting display according to an embodiment of the present invention.
2 is a schematic circuit diagram of pixels included in a display panel of an OLED display according to an exemplary embodiment of the present invention.
FIG. 3 is a schematic graph illustrating the difference between the gate node and the source node voltage of the driving TFT according to the data voltage in the pixels of the display panel of the organic light emitting diode display according to the embodiment of the present invention shown in FIG. to be.
4 is a schematic circuit diagram of pixels included in a display panel of an OLED display according to another embodiment of the present invention.
FIG. 5 is a schematic graph illustrating the difference in voltage between the gate node and the source node of the driving TFT according to the data voltage in the pixels of the display panel of the OLED display according to another embodiment of the present invention shown in FIG. to be.
Fig. 6 is a schematic diagram for explaining an embodiment of a driving method for adjusting on-duty of the emission control TFT in the light emission period of the pixels of Figs. 2 and 4. Fig.
Fig. 7 is a waveform diagram for driving the pixel array of Fig. 2 as an undesirable comparative example.
Fig. 8 is a schematic equivalent circuit diagram corresponding to Fig. 7, which is an undesirable comparative example.
9 is a waveform diagram schematically illustrating a method of driving an organic light emitting display according to an embodiment of the present invention.
10 is a circuit diagram schematically illustrating the pixel array driving of FIG. 2 according to the driving method of FIG.
Fig. 11 is a waveform diagram for driving the pixel array of Fig. 4 as an undesirable comparative example.
Fig. 12 is a schematic circuit diagram corresponding to Fig. 11 as an undesirable comparative example.
13 is a waveform diagram schematically illustrating a method of driving an organic light emitting display according to another embodiment of the present invention.
FIG. 14 is a circuit diagram schematically illustrating the pixel array driving of FIG. 4 according to the driving method of FIG.
15A is a conceptual diagram schematically illustrating how luminance distortion is generated by a kickback phenomenon when external compensation is applied to undesirable comparative examples.
FIG. 15B is a graph showing that the hump of the luminance-gradation curve is reduced or suppressed when the driving waveform of FIG. 9 or the driving waveform of FIG. 13 according to another embodiment of the present invention is applied according to an embodiment of the present invention. Fig.
FIG. 16 is a circuit diagram schematically showing the configuration of a source driver that can be combined with the pixel of FIG. 10 and the configuration of a switch array in a display panel.
17 is a schematic circuit diagram for explaining display driving according to the pixel of Fig. 10 and the source driver of Fig. 16;
18 is a schematic waveform diagram for explaining the display driving of Fig.
19 is a schematic circuit diagram for explaining sensing driving according to the pixel of Fig. 10 and the source driver of Fig. 16;
20 is a schematic waveform diagram for explaining the sensing drive of Fig.
21 is a circuit diagram schematically illustrating an exemplary configuration of a gate driver capable of supplying the display driving and sensing driving control signals disclosed in Figs. 16 to 20. Fig.
22 is a circuit diagram schematically showing the configuration of the source driver 12 that can be combined with the pixel structure of Fig. 14 and the configuration of the switch array 40 in the display panel 10. Fig.
23 is a schematic circuit diagram for explaining display driving according to the pixel of Fig. 14 and the source driver of Fig.
FIG. 24 is a schematic waveform diagram for explaining the display driving of FIG. 23. FIG.
25 is a schematic circuit diagram for explaining sensing driving according to the pixel of Fig. 14 and the source driver of Fig.
26 is a schematic waveform diagram for explaining the sensing drive of Fig.
27 is a circuit diagram schematically illustrating an exemplary configuration of a gate driver capable of supplying the display driving and sensing driving control signals disclosed in Figs. 22 to 26. Fig.
28 to 30 are diagrams showing various implementations of the external compensation module.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but is capable of many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

An element or layer is referred to as being another element or layer "on ", including both intervening layers or other elements directly on or in between.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

The sizes and thicknesses of the individual components shown in the figures are shown for convenience of explanation and the present invention is not necessarily limited to the size and thickness of the components shown.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other partially or wholly and technically various interlocking and driving are possible and that the embodiments may be practiced independently of each other, It is possible.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically illustrating an organic light emitting display according to an embodiment of the present invention.

Hereinafter, an organic light emitting display according to an embodiment of the present invention will be described with reference to FIG.

The OLED display according to an exemplary embodiment of the present invention includes at least a display panel 10, a timing controller 11, a source driver 12, and a gate driver 13.

A plurality of pixels P, a plurality of data lines 14, a plurality of reference lines 15, and a plurality of gate line portions 16 are disposed in the display panel 10. [

The pixels P of the display panel 10 are arranged in a matrix form to constitute a pixel array. Each pixel P is connected to one of the data lines 14 to which the data voltage is supplied, to one of the reference lines 15 to which the reference voltage is supplied, and to one of the gate line portions 16 . Each pixel P is configured to receive a high potential driving power supply and a low potential driving power supply from a power generation unit. For example, the power generation section may supply the high potential driving power through the high potential drive power supply wiring or the pad part. And the low potential driving power can be supplied through the low potential driving power supply wiring or the pad portion.

In some embodiments, the OLED display includes at least one external compensation circuit. The external compensation circuit technology refers to a technique of sensing the electrical characteristics of the driving TFT provided in the pixels P and correcting the input video data DATA according to the sensed value. For example, the sensing section is configured to compensate for the luminance deviation between the pixel P and the threshold voltage of the driving TFT and the electron mobility of the driving TFT as the electrical characteristics of the driving TFT.

In some embodiments, the display panel 10 may be further configured to include a switch array 40. But is not limited thereto.

The source driver 12 is configured to include a data voltage supply unit 20 that supplies a data voltage to the display panel 10. [

The data voltage supply unit 20 of the source driver 12 includes a plurality of digital-to-analog converters (hereinafter, DAC). The data voltage supply unit 20 converts the digital data (DATA) of the corrected input image inputted from the timing controller 11 into a display data voltage through the DAC.

The data voltage supply unit 20 of the source driver 12 generates a sensing data voltage through the DAC under the control of the timing controller 11 during sensing operation. The sensing data voltage is a voltage applied to the gate electrode of the driving TFT provided in each pixel P during the sensing operation.

In some embodiments, the source driver 12 may be further configured to include the sensing section 30. [ But is not limited thereto.

The timing controller 11 receives timing signals such as video data (DATA), a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a dot clock signal (DCLK) and a data enable signal . But is not limited thereto.

The timing controller 11 generates a data control signal DDC for controlling the operation timing of the source driver 12 and a gate control signal GDC for controlling the operation timing of the gate driver 13 based on the inputted signals. ).

The data control signal DDC includes a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the data sampling start timing of the source driver 12. [ The source sampling clock is a clock signal that controls sampling timing of data based on the rising or falling edge. The source output enable signal controls the output timing of the source driver 12.

The gate control signal GDC includes a gate start pulse, a gate shift clock, and the like. The gate start pulse is applied to the gate stage of the gate driver 13 which generates the first output to control the gate stage. The gate shift clock is a clock signal commonly input to the gate stages, and is a clock signal for shifting the gate start pulse.

For example, the timing controller 11 may generate control signals (DDC, GDC) for driving the display and control signals (DDC, GDC) for sensing driving differently. But is not limited thereto.

The timing controller 11 is configured to control the sensing drive for sensing the electrical characteristics of the driving TFT of the pixel P and for updating the compensated value thereof and the display driving for displaying the input image reflecting the compensation value.

For example, the timing controller 11 can be configured to separate the sensing drive and the display drive according to a predetermined control sequence. But is not limited thereto.

For example, under the control of the timing controller 11, the sensing driving is performed in the vertical blank period during the display driving, or in the power-on sequence period before the display driving is started, or in the power- Can be performed in a sequence period. But the present invention is not limited thereto, and the sensing driving may be performed during the display driving.

The vertical blanking period is a period during which input image data (DATA) is not written, and is arranged between vertical active periods in which input image data (DATA) for one frame is written. The power-on sequence period means a transient period from when the driving power is turned on until the input image is displayed. The power-off sequence period means a transient period from the end of the display of the input image until the driving power is turned off. However, the sensing operation is not limited to the above-described periods.

For example, the timing controller 11 can detect a standby mode, a sleep mode, a low power mode, and the like according to a predetermined sensing process, and control all operations for sensing driving. That is, the sensing operation may be performed in a state where only the screen of the display device is turned off during the period in which the system power is being applied, for example, in a standby mode, a sleep mode, a low power mode, and the like. But is not limited thereto.

The timing controller 11 is configured to calculate a compensation parameter capable of compensating for a change in electrical characteristics of the driving TFT of the pixel P based on the digital sensing values input from the source driver 12 during sensing driving.

For example, the organic light emitting display device is configured to include or communicate with the storage memory 17. And the compensation parameters can be stored in the storage memory 17. The compensation parameter stored in the storage memory 17 can be updated each time the sensing operation is performed, and thus the time-varying characteristic of the driving TFT can be easily compensated. But is not limited thereto.

The timing controller 11 reads the compensation parameter from the storage memory 17 during the display driving and corrects the digital data DATA of the input image based on the compensation parameter and supplies it to the source driver 12.

2 is a schematic circuit diagram of pixels P included in the display panel 10 of the OLED display according to an embodiment of the present invention.

Hereinafter, a pixel P of the OLED display device according to an embodiment of the present invention will be described with reference to FIG.

The pixel array of the display panel 10 is configured to include a first pixel, a second pixel, and a third pixel.

The pixel array of the display panel 10 includes a first data line 14R corresponding to the first pixel, a second data line 14G corresponding to the second pixel, a third data line 14B corresponding to the third pixel, And at least one reference line (15).

The pixel array of the display panel 10 includes a plurality of first gate lines 16a to which a first scan control signal SC1 is supplied and a plurality of second gate lines 16b to which a second scan control signal SC2 is supplied And a plurality of third gate lines 16c to which the emission control signals EM are supplied. In other words, the first gate line 16a, the second gate line 16b, and the third gate line 16c may be referred to as the gate line portion 16 shown in FIG.

Each of the first to third pixels of the pixel array includes the OLED, the driving TFT DT, the first switch TFT ST1, the second switch TFT ST2, the emission control TFT ST3, and the storage capacitor Cst .

The first to third pixels differ only in the detailed configuration of the OLED, and the rest are substantially the same. The OLED is a light emitting element connected between the source node Ns connected to the source electrode of the driving TFT DT and the low potential driving power supply VSS and emitting light in accordance with the driving current. The OLED of the first pixel is an R OLED configured to display red. The OLED of the second pixel is a G OLED configured to display green. The OLED of the third pixel is a B OLED configured to display a blue color.

The driving TFT DT includes a gate electrode connected to the gate node Ng, a drain electrode connected to the drain node Nd, and a source electrode connected to the source node Ns. The driving TFT DT is a driving element for controlling the magnitude of the driving current in accordance with the gate-source-node voltage Vgs.

The first switch TFT ST1 includes a gate electrode connected to the first gate line 16a, a drain electrode connected to the corresponding data line 14R / 14G / 14B, and a gate electrode connected to the gate node Ng Source electrode. The first switch TFT ST1 is turned on in response to the first scan control signal SC1 from the first gate line 16a to turn on the gate line Ng ), Thereby applying the data voltage Vdata to the gate node Ng.

The second switch TFT ST2 includes a gate electrode connected to the second gate line 16b, a drain electrode connected to the reference line 15, and a source electrode connected to the source node Ns. The second switch TFT ST2 is turned on in response to the second scan control signal SC2 from the second gate line 16b to electrically connect the reference line 15 and the source node Ns, And applies the reference voltage Vref to the source node Ns.

The storage capacitor Cst is connected between the gate node Ng and the source node Ns to maintain the gate node-source node voltage Vgs of the drive TFT DT constant during the light emission period.

The emission control TFT ST3 includes a gate electrode connected to the third gate line 16c, a drain electrode connected to the high potential driving power supply VDD, and a source electrode connected to the drain node Nd. The emission control TFT ST3 is turned on in response to the emission control signal EM from the third gate line 16c to apply the high potential drive power supply VDD to the drain node Nd.

The first to third pixels are configured to be connected to at least one reference line (15). For example, as shown in FIG. 2, the first pixel, the second pixel, and the third pixel may be configured to share one reference line 15. According to the above-described configuration, since the number of reference lines can be reduced, there is an advantage that the aperture ratio of the pixel array can be increased. That is, since the number of reference lines is reduced, more pixels can be arranged within the same area. Therefore, there is an advantage that the resolution can be increased. However, the number of reference lines and the number and types of shared pixels may be variously modified.

According to the above-described configuration, the pixel array of the organic light emitting diode display according to the embodiment of the present invention includes a circuit capable of compensating the luminance uniformity between pixels.

FIG. 3 is a graph showing the relationship between the difference (Vgs) between the gate node and the source node voltage Vgs of the driving TFT according to the data voltage in the pixels of the display panel 10 of the organic light emitting diode display according to the embodiment of the present invention shown in FIG. FIG.

Hereinafter, the gate node-source node voltage Vgs set in the pixel P of the organic light emitting diode display according to the embodiment of the present invention will be described with reference to FIG.

Each pixel P of the pixel array of the display panel 10 shown in FIG. 2 receives a different data voltage Vdata and is a positive gamma gradation representation in which the luminance is increased in proportion to the magnitude of the data voltage Vdata Lt; / RTI > The positive gamma gradation expression scheme is configured to control the data voltage Vdata applied to the gate node Ng within a higher voltage range than the fixed reference voltage Vref applied to the source node Ns . In the positive gamma gradation representation method, since the gate node-source node voltage Vgs programmed in the driving TFT DT becomes larger as the data voltage Vdata is increased, the driving current and the amount of OLED light emission are increased.

For example, a case where three different data voltages Vdata are applied to one arbitrary pixel P will be described. When the lowest data voltage Vdata is applied, the gate node-source node voltage Vgs of the pixel P becomes the first gate node-source node voltage Vgs1 shown on the left side in Fig. When the intermediate data voltage Vdata is applied, the gate node-source node voltage Vgs of the pixel P becomes the second gate node-source node voltage Vgs2 shown at the center in FIG. When the highest data voltage Vdata is applied, the gate node-source node voltage Vgs of the pixel P becomes the third gate node-source node voltage Vgs3 shown on the right side in FIG.

4 is a schematic circuit diagram of pixels P included in the display panel 10 of the OLED display according to another embodiment of the present invention.

Hereinafter, a pixel P of the OLED display according to another embodiment of the present invention will be described with reference to FIG.

The OLED display according to another embodiment of the present invention is different from the OLED display according to an embodiment of the present invention in that the source electrode of the first switch TFT ST1 is not connected to the gate node Ng The source electrode of the second switch TFT ST2 is connected to the source node Ns and the source electrode of the second switch TFT ST2 is connected to the gate node Ng without being connected to the source node Ns. Therefore, the overlapping contents of the organic light emitting display according to one embodiment of the present invention and the organic light emitting display according to another embodiment of the present invention will be omitted for convenience of explanation.

Hereinafter, differences between the OLED display according to another embodiment of the present invention and the OLED display according to an embodiment of the present invention will be described.

The first switch TFT ST1 includes a gate electrode connected to the first gate line 16a and a drain electrode connected to the corresponding data line 14R / 14G / 14B, and a drain electrode connected to the source node Ns Source electrode. The first switch TFT ST1 is turned on in response to the first scan control signal SC1 from the first gate line 16a and is turned on in response to the first scan signal SC1 from the data line 14R / 14G / 14B and the source node Ns ) To the source node Ns by applying the data voltage Vdata to the source node Ns.

The second switch TFT (ST2) includes a gate electrode connected to the second gate line 16b, a drain electrode connected to the reference line 15, and a source electrode connected to the gate node Ng. The second switch TFT ST2 is turned on in response to the second scan control signal SC2 from the second gate line 16b to electrically connect the reference line 15 and the gate node Ng, And applies the reference voltage Vref to the gate node Ng.

According to the above-described configuration, the pixel array of the OLED display according to another embodiment of the present invention includes a circuit capable of compensating for the luminance uniformity between pixels.

5 is a graph showing the relationship between the gate node and source node voltage Vgs of the driving TFT according to the data voltage in the pixels P of the display panel 10 of the organic light emitting diode display according to another embodiment of the present invention shown in Fig. ) In the first embodiment.

Hereinafter, the gate node-source node voltage Vgs set in the pixel P of the OLED display according to another embodiment of the present invention will be described with reference to FIG.

The pixels P of the pixel array of the display panel 10 shown in FIG. 4 are supplied with different data voltages Vdata and are subjected to inverse gamma gradation expression . The inverse gamma gradation representation method controls the data voltage Vdata applied to the source node Ns within a voltage range lower than the fixed reference voltage Vref applied to the gate node Ng . In the inverse gamma-gradation representation method, since the gate-source-node voltage Vgs programmed in the driving TFT DT becomes smaller as the data voltage Vdata is increased, the driving current and the OLED emission amount are reduced.

For example, a case where three different data voltages Vdata are applied to one arbitrary pixel P will be described. When the highest data voltage Vdata is applied, the gate node-source node voltage Vgs of the pixel P becomes the first gate node-source node voltage Vgs1 shown on the left side in FIG. When the intermediate data voltage Vdata is applied, the gate node-source node voltage Vgs of the pixel P becomes the second gate node-source node voltage Vgs2 shown at the center in FIG. When the lowest data voltage Vdata is applied, the gate node-source node voltage Vgs of the pixel P becomes the third gate node-source node voltage Vgs3 shown on the right side in FIG.

Meanwhile, the TFTs included in the pixels of FIGS. 2 and 4 are all implemented in N-type, but the technical idea of the present invention is not limited thereto. The TFTs constituting the pixels may be of a P-type, or may be of a hybrid type in which N-type and P-type are mixed. For example, an oxide semiconductor layer TFT composed of an N-type and a hybrid TFT composed of a polysilicon TFT composed of a P-type.

To be more specific, the semiconductor layers of the TFTs constituting the pixel may be uniformly composed of amorphous silicon, uniformly composed of polysilicon, or uniformly composed of oxide. The semiconductor layer of the TFTs constituting the pixel may include at least one of amorphous silicon, polysilicon, and oxide. Further, in one pixel, some of the TFTs may include a polysilicon semiconductor layer, and the remaining TFTs may include an oxide semiconductor layer. The oxide TFT having an oxide semiconductor layer has good off current characteristics. Good off-current characteristics mean that the leakage current is low in the off state. Therefore, it is preferable that the oxide TFT is applied to the TFT, that is, the first and second switch TFTs, which are turned on only for a short time in one frame and then remain in the off state continuously. A poly TFT having a polysilicon semiconductor layer has a high electron mobility. High electron mobility means good current carrying capacity for a unit of time. Therefore, it is preferable that the poly TFT is applied to a driving TFT functioning as a driving element, and a light emission control TFT applying power directly to the driving TFT.

Fig. 6 is a schematic diagram for explaining an embodiment of a driving method for adjusting on-duty of the emission control TFT in the light emission period of the pixels of Figs. 2 and 4. Fig.

Hereinafter, an embodiment of the driving method of the present invention will be described with reference to FIG.

Referring to FIG. 6, the length of the emission period in one frame can be adjusted by adjusting the on-duty of the emission control signal EM as shown in FIG.

"Te1" shown in FIG. 6 is a light emission period when the on-duty of the emission control signal EM is relatively long, "Te2" is the emission period when the on-duty of the emission control signal EM is relatively short The light emission period is schematically shown.

The light emission control TFT ST3 provided in the pixels of Figs. 2 and 4 can perform pulse duty driving by the emission control signal EM.

It is possible to control the on-time of the emission control TFT (ST3), that is, the light emission period, in one frame through the pulse duty drive to provide various additional functions.

For example, in the case of expressing the grayscale by only N-bit video data, only the N-th grayscale of 2 can be expressed, whereas when the grayscale is expressed by using the N-bit video data and the pulse duty, There is an advantage that more gradations can be expressed. That is, there is an advantage that a more precise gradation can be expressed. However, the organic light emitting display according to embodiments of the present invention is not limited thereto.

For example, the emission control signal EM can be transited a plurality of times in one frame. That is, the emission control signals EM of the emission periods "Te1 " and" Te2 " shown in Fig. 6 may be in the form of a pulse in which the ON / OFF is repeated plural times. According to the above-described configuration, there is an advantage that flicker can be reduced in implementing on-duty. However, the organic light emitting display according to embodiments of the present invention is not limited thereto.

For example, there is an advantage that the maximum luminance of the organic light emitting display can be adjusted through pulse duty driving. That is, there is an advantage that the light emission period can be adjusted in consideration of the brightness or power consumption of the external light. Further, an illuminance sensor for measuring external light may be further added, and an algorithm for measuring power consumption may be further added. However, the organic light emitting display according to embodiments of the present invention is not limited thereto.

For example, the light emission period of each third gate line 16c of the organic light emitting display can be adjusted through pulse duty driving. That is, one third gate line 16c can simultaneously control the light emission period of the corresponding pixels. Therefore, the emission period of one third gate line 16c and the emission period of another third gate line 16c adjacent to each other can be controlled differently, and the emission period can be adjusted for each frame. According to the above-described configuration, there is an advantage that precise gradation representation and / or power consumption reduction can be individually achieved for each third gate line 16c in one frame. However, the organic light emitting display according to embodiments of the present invention is not limited thereto.

For example, by applying the pulse duty driving principle, the emission control signal EM can be configured to include at least a specific off period (i.e., a reset period). According to the above-described configuration, even when the pulse duty drive is not used for a long time, the emission control signal EM can be transitioned to the off level for a specific period in one frame, There is an advantage that the problem of the positive bias stress deterioration of the emission control TFT ST3 can be reduced. That is, the bias stress applied to the emission control TFT ST3 can be reduced by using the off period of the emission control signal EM (i.e., the reset period of the emission control signal EM). However, the organic light emitting display according to embodiments of the present invention is not limited thereto.

Hereinafter, embodiments of the present invention will be described and described as being configured to apply at least one of the pulse duty driving methods described above.

Fig. 7 is a waveform diagram for driving the pixel array of Fig. 2 as an undesirable comparative example.

Fig. 8 is a schematic equivalent circuit diagram corresponding to Fig. 7, which is an undesirable comparative example.

According to an undesirable comparative example, there is a problem that luminance distortion occurs due to the kickback effect when the switch TFT is turned off in the light emitting period.

Specifically, the principle that luminance distortion occurs when a conventional driving waveform as shown in FIG. 7 is applied to the pixel P shown in FIG. 2 will be described.

This will be described below with reference to Figs. 7 and 8. Fig. One frame period in the display driving is divided into a programming period Tp for setting the gate node-source node voltage Vgs of the driving TFT DT and a driving period Tp for driving according to the programmed gate node-source node voltage Vgs And a light emission period Te for causing the OLED to emit light.

During the programming period Tp, the first switch TFT ST1 is turned on in response to the first scan control signal SC1 of the ON level Lon to cause the gate node Ng to be turned on by the data voltage Vdata "Da" And the second switch TFT ST2 is turned on in accordance with the second scan control signal SC2 at the on level Lon to apply the reference voltage Vref to the source node Ns, DT) is programmed to "Vdata-Vref ". During the programming period Tp, the emission control TFT ST3 is turned off according to the emission control signal EM of the off level Loff to float the drain node Nd, thereby driving the drive TFT DT Lt; / RTI >

The display first and second scan control signals SC1 and SC2 are transitioned from the on level Lon to the off level Loff at the time t1 of the light emission period Te. Accordingly, the first switch TFT (ST1) and the second switch TFT (ST2) are turned off at time t1, and the turn-off state is maintained for the light emission period Te. the emission control signal EM is transitioned from the off level Loff to the on level Lon at the time t2 of the light emission period Te later than the time t1 so as to turn on the light emission control TFT ST3.

Since the emission control signal EM has an off level Loff at the time point t1 of the emission period Te, the drain node Nd is floated by the emission control TFT ST3 turned off at the time t1, State. Therefore, the parasitic capacitance Cp between the gate electrode of the first switch TFT ST1 and the drain node Nd allows the drain node Nd to be turned on when the first switch TFT ST1 is turned off at time t1 It is affected by kick back. That is, the potential of the drain node Nd is lowered by DELTA a at the high potential driving power supply VDD in synchronization with the polling of the first scan control signal SC1 at the time t1. Then, the potential of the drain node Nd reversely rises by DELTA a when the emission control TFT ST3 is turned on at time t2, and is turned to the high potential driving power supply VDD.

On the other hand, since the parasitic capacitance Cgd exists also between the gate node Ng and the drain node Nd of the driving TFT DT and the gate node Ng is in the floating state at the time t2, The potential of the gate node Ng also increases by approximately? A. That is, in the light emission period Te, the potential of the gate node Ng changes to a voltage level (Vdata +? A) which is higher by about? A than the data voltage Vdata.

When the potential of the gate node Ng of the driving TFT DT set in the programming period Tp changes in the light emission period Te, the gate node-source node voltage Vgs is turned off, which is recognized as a luminance change . If the driving TFT DT is in a floating state without being connected to the high potential driving power supply VDD when the first switch TFT ST1 is turned off in the light emission period Te, the influence of the kick back due to the parasitic capacitance There is a problem that luminance distortion may be caused.

9 is a waveform diagram schematically illustrating a method of driving an organic light emitting display according to an embodiment of the present invention.

10 is a circuit diagram schematically illustrating the pixel array driving of FIG. 2 according to the driving method of FIG.

Hereinafter, a driving method of an OLED display according to an embodiment of the present invention will be described with reference to FIGS. 9 and 10. FIG.

During the programming period Tp, the first switch TFT ST1 is turned on in response to the first scan control signal SC1 of the ON level Lon to cause the gate node Ng to be turned on by the data voltage Vdata "Da" And the second switch TFT ST2 is turned on in accordance with the second scan control signal SC2 at the on level Lon to apply the reference voltage Vref to the source node Ns, DT) is programmed to "Vdata-Vref ".

During the programming period Tp, the emission control TFT ST3 is turned on according to the emission control signal EM of the on level Lon to prevent floating of the drain node Nd, and the drain node Nd, To the high potential driving power supply (VDD).

According to the above-described configuration, since the drain node Nd is not in the floating state, there is an advantage that the kickback problem according to the driving method described with reference to FIGS. 7 and 8 may not occur. However, during the programming period Tp, the high potential driving power supply VDD is applied to the drain node Nd through the light emission control TFT ST3. That is, since the drain electrode of the driving TFT DT is connected to the high potential driving power supply VDD, a transient current can flow through the driving TFT DT during the programming period Tp. That is, the transient current is a phenomenon that can occur when the light emission control TFT ST3 is turned on during the programming period Tp in order to compensate the kickback phenomenon.

Therefore, the organic light emitting diode display according to the embodiment of the present invention is electrically connected to the source node Ns so as to compensate for the kickback phenomenon and at the same time compensate the false emission (wrong operation) of the OLED due to the transient current The OLED is configured to receive a reference voltage (Vref) that is at least less than the operating point voltage (threshold voltage) of the OLED. That is, the reference voltage Vref is configured to be smaller than the operating point voltage. Further, the minimum data voltage Vdata is configured to be larger than the reference voltage Vref.

In addition, as described above, the pixel array of FIG. 10, which illustrates the organic light emitting display according to the embodiment of the present invention, uses the positive gamma gradation representation of FIG.

According to the above-described configuration, there is an advantage that a transient current can be sinked to the reference line 15 without being applied to the OLED. That is, the reference voltage Vref may be referred to as a bypass voltage for transient current. An undesired transient current due to the transient current bypassing voltage can flow to the reference line 15 through the second switch TFT ST2 without flowing to the anode electrode of the OLED.

Further, the data voltage Vdata is configured to correspond to the transient current bypass voltage. More specifically, the reference voltage Vref is set to a value capable of blocking the transient current that can flow to the OLED. In this case, since the gate node-source node voltage Vgs of the drive TFT DT is "Vdata-Vref ", the data voltage Vdata is set so that the gate node-source node voltage Vgs can be set, And is set in correspondence with the transient current bypassing voltage. According to the above-described configuration, the data voltage (Vdata) has an advantage that the desired luminance can be displayed on the organic light emitting display device in correspondence with the transient current bypass voltage.

At the time t1 of the light emission period Te, the first and second scan control signals SC1 and SC2 are transitioned from the on level (Lon) to the off level (Loff). Accordingly, the first switch TFT (ST1) and the second switch TFT (ST2) are turned off at time t1, and the turn-off state is maintained for the light emission period Te. At the time t1, the emission control signal EM is maintained at the on level (Lon), and the emission control TFT ST3 is turned on subsequently.

Since the emission control signal EM has the on level Lon at the time t1 of the emission period Te, the electrical connection between the drain node Nd and the high potential driving power supply VDD is maintained. Therefore, even if the first switch TFT (ST1) is turned off at the time t1, the drain node Nd is not affected by kick back. That is, the potential of the drain node Nd maintains the level of the high potential driving power supply (VDD) even when the first scan control signal SC1 is polled at time t1. Since the potential of the drain node Nd does not change at the time t1, the potential of the gate node Ng does not change, and the programmed data voltage Vdata can be maintained. When the first switch TFT ST1 is turned off in the light emission period Te and the electrical connection between the high potential drive power supply VDD and the drive TFT DT is maintained, the kickback effect due to the parasitic capacitance is reduced or suppressed And the luminance distortion can be compensated or prevented.

That is, in the organic light emitting diode display according to the embodiment of the present invention, the emission control signal EM is maintained at the on level (Lon) for a specific time from the time t1 when the first switch TFT (ST1) . For example, the emission control signal EM is delayed to an on-level state for a specific time after the time point t1, and is then turned off.

For example, the delay period may be equal to or longer than one horizontal period (1H). One horizontal period means a dot clock, i.e., one clock period, which is the driving frequency of the driver for driving the emission control signal of the organic light emitting display. But is not limited thereto.

According to the above-described configuration, since the light emission control TFT ST3 can be kept in the turn-on state at the time t1 when the first switch TFT ST1 is turned off, the kickback effect as described above can be effectively reduced Or suppression of the disease.

Therefore, after a certain time from the time t1, the emission control signal EM can be turned off (Loff). More specifically, after a specific time at the time t1, the emission control signal EM is configured to have a specific duty according to the pulse duty drive described above with reference to FIG.

According to the above-described configuration, it is possible to reduce the influence of the kick back due to the parasitic capacitance, compensate for the luminance distortion, and perform pulse duty driving at the same time.

Fig. 11 is a waveform diagram for driving the pixel array of Fig. 4 as an undesirable comparative example.

Fig. 12 is a schematic circuit diagram corresponding to Fig. 11 as an undesirable comparative example.

According to an undesirable comparative example, there is a problem that luminance distortion is generated due to the kick back effect when the switch TFT is turned on in the light emission period.

Specifically, the principle that luminance distortion occurs when a conventional driving waveform as shown in FIG. 11 is applied to the pixel P shown in FIG. 4 will be described.

This will be described below with reference to Figs. 11 and 12. Fig. One frame period in the display driving is divided into a programming period Tp for setting the gate node-source node voltage Vgs of the driving TFT DT and a driving period Tp for driving according to the programmed gate node-source node voltage Vgs And a light emission period Te for causing the OLED to emit light.

During the programming period Tp, the second switch TFT ST2 is turned on according to the second scan control signal SC2 of the on level Lon to apply the reference voltage Vref to the gate node Ng, The first switch TFT ST2 is turned on in accordance with the first scan control signal SC1 of the ON level Lon to apply the data voltage Vdata of "Da" to the source node Ns, DT) is programmed to "Vref-Vdata ". During the programming period Tp, the emission control TFT ST3 is turned off according to the emission control signal EM of the off level Loff to float the drain node Nd, thereby driving the drive TFT DT Lt; / RTI >

The display first and second scan control signals SC1 and SC2 are transitioned from the on level Lon to the off level Loff at the time t1 of the light emission period Te. Accordingly, the first switch TFT (ST1) and the second switch TFT (ST2) are turned off at time t1, and the turn-off state is maintained for the light emission period Te. the emission control signal EM is transitioned from the off level Loff to the on level Lon at the time t2 of the light emission period Te later than the time t1 so as to turn on the light emission control TFT ST3.

Since the emission control signal EM has an off level Loff at the time point t1 of the emission period Te, the drain node Nd is floated by the emission control TFT ST3 turned off at the time t1, State. Therefore, the parasitic capacitance Cp between the gate electrode of the second switch TFT ST2 and the drain node Nd allows the drain node Nd to be turned on when the second switch TFT ST2 is turned off at time t1 It is affected by kick back. That is, the potential of the drain node Nd is lowered by? B from the high potential driving power supply VDD in synchronization with the polling of the second scan control signal SC2 at the time t1. Then, the potential of the drain node Nd reversely rises by? B when the emission control TFT ST3 is turned on at time t2, and is turned to the high potential driving power supply VDD.

On the other hand, since the parasitic capacitance Cgd exists also between the gate node Ng and the drain node Nd of the driving TFT DT and the gate node Ng is in the floating state at the time t2, The potential of the gate node Ng also increases by approximately? B. That is, the potential of the gate node Ng also changes to a voltage level (Vref +? B) which is higher by about? B than the reference voltage Vref in the light emission period Te.

When the potential of the gate node Ng of the driving TFT DT set in the programming period Tp changes in the light emission period Te, the gate node-source node voltage Vgs is turned off, which is recognized as a luminance change . If the driving TFT DT is in a floating state without being connected to the high potential driving power supply VDD during the turn-off of the second switch TFT ST2 in the light emission period Te, a kickback effect due to parasitic capacitance There is a problem that luminance distortion may be caused.

13 is a waveform diagram schematically illustrating a method of driving an organic light emitting display according to another embodiment of the present invention.

FIG. 14 is a circuit diagram schematically illustrating the pixel array driving of FIG. 4 according to the driving method of FIG.

Hereinafter, a driving method of an OLED display according to another embodiment of the present invention will be described with reference to FIGS. 13 and 14. FIG.

During the programming period Tp, the first switch TFT ST1 is turned on in response to the first scan control signal SC1 of the ON level Lon, and the data voltage Vdata, "Da," And the second switch TFT ST2 is turned on in accordance with the second scan control signal SC2 of the on level Lon to apply the reference voltage Vref to the gate node Ng to apply the reference voltage Vref to the drive TFT DT) is programmed to "Vref-Vdata ".

During the programming period Tp, the emission control TFT ST3 is turned on according to the emission control signal EM of the on level Lon to prevent floating of the drain node Nd, and the drain node Nd, To the high potential driving power supply (VDD).

According to the above-described configuration, since the drain node Nd is not in a floating state, there is an advantage that a kick back problem according to the driving method described with reference to FIGS. 11 and 12 can be avoided. However, during the programming period Tp, since the high potential driving power supply VDD is connected to the drain node Nd through the light emission control TFT ST3, the driving TFT DT is supplied with the transient current Transient current can flow. That is, the transient current is a phenomenon that can occur when the light emission control TFT ST3 is turned on during the programming period Tp in order to compensate the kickback phenomenon.

Therefore, the organic light emitting diode display according to another embodiment of the present invention is electrically connected to the source node Ns so as to compensate for the kickback phenomenon and at the same time compensate for the false emission (wrong operation) of the OLED due to the transient current The OLED is configured to receive at least a data voltage (Vdata) less than the operating point voltage (threshold voltage) of the OLED. That is, the maximum data voltage Vdata is configured to be smaller than the operating point voltage. The reference voltage Vref is configured to be larger than the maximum data voltage Vdata.

In addition, as described above, the pixel array of FIG. 14, which illustrates the organic light emitting display according to another embodiment of the present invention, uses the inverse gamma gradation representation of FIG.

According to the above-described configuration, there is an advantage that a transient current can be sinked into the data line 14 without being applied to the OLED. That is, the data voltage Vdata may be referred to as a bypass voltage for transient current. An undesired transient current due to the transient current bypassing voltage can flow to the data line 14 through the first switch TFT ST2 without flowing to the anode electrode of the OLED.

Further, the reference voltage Vref is configured to correspond to the transient current bypassing voltage. More specifically, the data voltage Vdata is set to a value capable of interrupting the transient current that may flow to the OLED. In this case, the reference voltage Vref is set so that the gate node-source node voltage Vgs can be set, since the gate node-source node voltage Vgs of the drive TFT DT is "Vref-Vdata & And is set in correspondence with the transient current bypassing voltage. According to the above-described configuration, the reference voltage Vref is advantageous in that a desired luminance can be displayed on the organic light emitting display device in correspondence with the transient current bypassing voltage.

The first and second scan control signals SC1 and SC2 are transited from the ON level Lon to the OFF level Loff at the time t1 of the light emission period Te. Accordingly, the first switch TFT (ST1) and the second switch TFT (ST2) are turned off at time t1, and the turn-off state is maintained for the light emission period Te. At the time t1, the emission control signal EM is maintained at the on level (Lon), and the emission control TFT ST3 is turned on subsequently.

Since the emission control signal EM has the on level Lon at the time t1 of the emission period Te, the electrical connection between the drain node Nd and the high potential driving power supply VDD is maintained. Therefore, even if the second switch TFT (ST2) is turned off at time t1, the drain node Nd is not affected by kick back. That is, the potential of the drain node Nd maintains the level of the high potential driving power supply (VDD) even if the second scan control signal SC2 is polled at the time t1. Since the potential of the drain node Nd does not change at the time t1, the potential of the gate node Ng does not change and the programmed reference voltage Vref can be maintained. When the electrical connection between the high potential driving power supply VDD and the driving TFT DT is maintained when the second switch TFT ST2 is turned off in the light emission period Te, the kickback effect due to the parasitic capacitance is reduced or suppressed And the luminance distortion can be compensated or prevented.

That is, in the OLED display according to another embodiment of the present invention, the emission control signal EM is maintained at the on level (Lon) for a specific time from the time t1 when the second switch TFT (ST2) is turned off . For example, the light emission control signal EM is delayed to the ON level state for a specific time after the time point t1.

For example, the delay time may be one horizontal period (1H) or more. But is not limited thereto.

In other words, the time t1 when the signal is turned off, for example, when the first switch TFT (ST1) is turned off, is referred to as a transition time of the one scan control signal SC1 . For example, the time t1 at which the second switch TFT (ST2) is turned off can be described as the transition time of the two-scan control signal SC2. The emission control signal EM maintains the emission control signal EM at the on level Lon at the transition time of the first scan control signal SC1 and the transition time of the second scan control signal SC1 do.

According to the above-described configuration, since the emission control TFT ST3 can be kept in the turn-on state at the time t1 when the second switch TFT ST2 is turned off, the drain node Nd is in the floating state I will not. Therefore, there is an advantage that the kickback effect as described above can be effectively reduced or suppressed.

Therefore, after a certain time from the time t1, the emission control signal EM can be turned off (Loff). More specifically, after a specific time at the time t1, the emission control signal EM is configured to have a specific duty according to the pulse duty drive described above with reference to FIG.

According to the above-described configuration, it is possible to reduce the influence of the kick back due to the parasitic capacitance, compensate for the luminance distortion, and perform pulse duty driving at the same time.

In some embodiments, the reference voltage Vref is set in consideration of the contrast ratio. For example, in the reverse gamma gradation method, the minimum data voltage Vdata that the source driver 12 can output must be smaller than the reference voltage. In this case, when the reference voltage Vref is lowered, since the gate node-source node voltage Vgs of the driving TFT DT is "Vref-Vdata", the gradation range, for example, The range of the gate node-source node voltage (Vgs) can be reduced. Therefore, if the maximum reference voltage Vref is too low, the gradation can not be expressed completely or the maximum luminance may be lowered. That is, since the contrast ratio may be lowered, the reference voltage Vref may be set in consideration of the minimum data voltage Vdata. But is not limited thereto. According to the above-described configuration, it is possible to simultaneously compensate for a decrease in contrast ratio and a kickback phenomenon.

In some embodiments, a delay circuit may be configured at the output of the emission driver to delay the emission control signal EM as desired. The scheme can be implemented in a simple manner without redesigning the emission driver. In particular, the delay circuit can be applied to all embodiments.

15A is a conceptual diagram schematically illustrating how luminance distortion is generated by a kickback phenomenon when external compensation is applied to undesirable comparative examples.

Referring to FIG. 15A, the X-axis denotes a data voltage (Vdata). The data voltage Vdata is configured to correspond to the gradation. The Y-axis corresponds to the luminance of the OLED corresponding to the input data voltage Vdata.

Driving is a graph showing an erroneous phenomenon caused by a kickback phenomenon when external compensation is applied to undesirable comparative examples. The dotted line (Fitting) is a graph showing the case where the external compensation is ideally compensated. When external compensation is applied when the above-described undesirable comparative examples (see FIGS. 7, 8, 11 and 12) are subjected to a kickback effect, undercompensation is performed according to a data interval as shown in FIG. Or overcompensation may be performed to increase the luminance distortion. For example, there is a non-linear interval between the deficit compensation and the over compensation. Particularly, the corresponding period can be generated when the voltage of the data voltage (Vdata) is close to the threshold voltage of the driving TFT.

FIG. 15B is a graph showing that the hump of the luminance-gradation curve is reduced or suppressed when the driving waveform of FIG. 9 or the driving waveform of FIG. 13 according to another embodiment of the present invention is applied according to an embodiment of the present invention. Fig.

Referring to FIG. 15B, the X-axis means gray level. The Y-axis means the log scale. The luminance-gradation curve can be referred to as a gamma curve.

The "before improvement" gamma curve includes a hump generated in a specific gradation period when the above-described undesirable comparative examples (see FIGS. 7, 8, 11 and 12) do. For example, the hump can be generated in a gradation of a period in which the magnitude of the data voltage (Vdata) is similar to the threshold voltage of the driving TFT.

The "after improvement" gamma curve has been removed from the luminance hump section appearing on the gamma curve by the embodiments of the present invention described above (see Figs. 9, 10, 13 and 14). Therefore, the problem that the luminance is distorted can be improved.

That is, one embodiment and another embodiment of the present invention can be described once again as follows.

In the programming period of the organic light emitting display device including the programming period and the light emission period according to the embodiment of the present invention, the data voltage is supplied to the gate node, which is arranged between the gate node and the data line of the driving TFT, 1 switch TFT, a second switch TFT arranged between the source node and the reference line, the first switch TFT being configured so that the transient current supplied through the drive TFT can bypass the reference line, between the drain node of the drive TFT and the high potential drive power supply line A storage capacitor arranged to supply a high potential driving power to the drain node; a light emitting control TFT disposed between the gate node and the source node, the storage capacitor being configured to charge the gate node to source node voltage of the driving TFT; And the organic light emitting diode is configured to operate so as to maintain the non-emission state The.

A first gate line configured to supply a first scan control signal to the gate electrode of the first switch TFT, a second gate line configured to supply a second scan control signal to the gate electrode of the second switch TFT, And a third gate line configured to supply a light emission control signal to the electrode.

When the first scan control signal, the second scan control signal, and the emission control signals are simultaneously turned on, the data voltage is applied to one electrode of the storage capacitor corresponding to the gate node, And the transient current is bypassed to the reference line by a reference voltage lower than the operating point voltage of the organic light emitting diode.

The light emission control TFT is turned on during the programming period and the light emission control TFT is turned off after the specific time in the light emission period.

The drain node is not in a floating state in a programming period, and is not in a floating state for at least a specific time in a light emitting period, so that a kickback can be reduced.

In the light emission period, the light emission control TFT maintains the turn-off state after a specific time, and is turned on after a predetermined time.

In the light emission period, the light emission control TFT is characterized in that it is turned on and off at least once.

In the light emission period, the light emission control TFT operates as a pulse duty drive capable of variable duty adjustment.

Further comprising a plurality of pixel lines including a driving TFT, a first switch TFT, a second switch TFT, a light emission control TFT, a storage capacitor, and an organic light emitting diode, wherein the duty of the pulse duty drive of each pixel line is adjustable .

The pulse duty driving is characterized by being capable of performing at least one of gray level representation, flicker reduction, maximum luminance adjustment, and stress reduction of the emission control TFT over N-bit video data.

Wherein the reference voltage is an overcurrent bypass voltage and the data voltage is a voltage set corresponding to the transient bypass voltage.

And the voltage between the gate node and the source node of the driving TFT is configured to operate in the positive gamma gradation method.

The first switching TFT is configured to include an oxide semiconductor layer, and the second switching TFT is configured to include an oxide semiconductor layer.

The first switching TFT is configured to further include one semiconductor layer of amorphous silicon and polysilicon and the second switching TFT is configured to further include one semiconductor layer of amorphous silicon or polysilicon.

In a programming period of an organic light emitting display including a programming period and a light emission period according to another embodiment of the present invention, A first switch TFT, a second switch TFT, and a driving TFT, which are disposed between the source node and the data line of the driving TFT and configured so that a transient current supplied from the driving TFT can be diverted to the data line while supplying the data voltage to the source node An emission control TFT disposed between the drain node and the high potential drive power supply line and configured to supply a high potential drive power to the drain node, A storage capacitor coupled to the source node and configured to operate in a non-light emitting state; , And an organic light emitting diode.

A first gate line configured to supply a first scan control signal to the gate electrode of the first switch TFT, a second gate line configured to supply a second scan control signal to the gate electrode of the second switch TFT, And a third gate line configured to supply a light emission control signal to the electrode.

When the first scan control signal, the second scan control signal, and the emission control signals are simultaneously turned on, the reference voltage is applied to one electrode of the storage capacitor corresponding to the gate node, and the data voltage is applied to the storage Is applied to the other electrode of the capacitor, and the transient current is bypassed to the reference line by a data voltage lower than the operating point voltage of the organic light emitting diode.

The light emission control TFT is turned on during the programming period and the light emission control TFT is turned off after the specific time in the light emission period.

The drain node is not in a floating state in a programming period, and is not in a floating state for at least a specific time in a light emitting period, so that a kickback can be reduced.

In the light emission period, the light emission control TFT maintains the turn-off state after a specific time, and is turned on after a predetermined time.

In the light emission period, the light emission control TFT is characterized in that it is turned on and off at least once.

In the light emission period, the light emission control TFT operates as a pulse duty drive capable of variable duty adjustment.

Further comprising a plurality of pixel lines including a driving TFT, a first switch TFT, a second switch TFT, a light emission control TFT, a storage capacitor, and an organic light emitting diode, wherein the duty of the pulse duty drive of each pixel line is adjustable .

The pulse duty driving is characterized by being capable of performing at least one of gray level representation, flicker reduction, maximum luminance adjustment, and stress reduction of the emission control TFT over N-bit video data.

The reference voltage is characterized in that the voltage is higher than the contrast-lowering voltage which can lower the contrast ratio of the organic light emitting display device.

The data voltage is an overcurrent bypass voltage and the reference voltage is a voltage set corresponding to the transient bypass voltage.

And the gate-source node voltage of the driving TFT is configured to operate in an inverse gamma-gradation manner.

The organic light emitting display according to embodiments of the present invention includes: A driving TFT which adjusts an amount of current supplied to the organic light emitting diode by a potential difference between voltages applied to the first electrode and the second electrode of the storage capacitor, a first switch TFT which inputs a first voltage to the first electrode, And a light emitting control TFT for inputting a second voltage to the electrode, the second switch TFT and the high potential driving power supply being supplied to the driving TFT, and adjusting the light emitting duty of the organic light emitting diode.

 The light emission control TFT is configured to maintain the turn-on state for a predetermined time after the first switch TFT and the second switch TFT turn off from the turn-on state to compensate the kickback.

 The organic light emitting display device is characterized by being composed of a positive gamma gradation method or an inverse gamma gradation method.

16 is a circuit diagram schematically showing the configuration of the source driver 12 that can be combined with the pixel of Fig. 10 and the configuration of the switch array 40 in the display panel 10. Fig.

16, the source driver 12 and the switch array 40 of the display panel 10 according to still another embodiment of the present invention will be described.

The OLED display according to another embodiment of the present invention is configured to include a source driver 12 further including a display panel 10 and a sensing unit 30 further including a switch array 40. [ In addition, the OLED display according to another exemplary embodiment of the present invention is configured to selectively perform display driving and sensing driving.

The source driver 12 includes a data voltage supply unit 20 for supplying the data voltage Vdata to the display panel 10 and a sensing unit 30 for sensing the pixels P of the display panel 10 . However, the present invention is not limited thereto, and the data voltage supply unit 20 and the sensing unit 30 may be physically separated from each other.

The data voltage supply unit 20 is configured to include a plurality of DACs (RDAC, GDAC, and BDAC) and first mux switches SA1 to SA6. The data voltage supplier 20 generates a data voltage for display and supplies the display data voltage to the output channels CH1 to CH3 during the driving of the display and generates a sensing data voltage at the sensing driving to output the data voltages to the output channels CH1 to CH3 Supply.

The first mux switches SA1 to SA6 are switched according to the first mux control signals SOE1 and SOE2 to thereby connect the DACs (RDAC, GDAC and BDAC) to the output channels CH1 to CH3.

Specifically, the odd-numbered switches SA1, SA3, and SA5 among the first mux switches SA1 to SA6 are simultaneously turned on in response to the first-mux control signal SOE1 to turn the RDAC on the first output channel CH1 and connects the BDAC to the second output channel CH2 and connects the GDAC to the third output channel CH3. The even switches SA2, SA4 and SA6 among the first mux switches SA1 to SA6 are simultaneously turned on in accordance with the first-second mux control signal SOE2 to turn on the GDAC to the first output channel CH1 At the same time as connecting, the RDAC is connected to the second output channel (CH2) and the BDAC is connected to the third output channel (CH3). In other words, "BUF" shown in the figure is a buffer for stabilizing the data voltage. But is not limited thereto.

That is, the plurality of DACs (RDAC, GDAC, and BDAC) connected to the output channels CH1 to CH3 are switched according to the first mux control signals SOE1 and SOE2. Therefore, each of the output channels CH1 to CH3 can selectively output different video signals, thereby reducing the number of output channels.

The sensing unit 30 includes second mux switches SS1 to SS6, a plurality of sensing units SU1 and SU2 that operate according to the second mux control signals SMUX-R, SMUX-G, and SMUX- And a plurality of ADCs (ADC1, ADC2).

For example, the sensing unit 30 is operated only at the time of sensing driving, and its operation can be stopped at the time of driving the display. In detail, the sensing unit 30 may include sensing switches SW-SEN for controlling sensing driving, and the sensing unit 30 may include sensing switches SW-SEN on / off Can be controlled according to the state. The output channels CH1 to CH3 can be connected to the second mux switches SS1 to SS6 of the sensing unit 30 by the sensing switches SW-SEN. But is not limited thereto.

It is possible to sense the source electrode voltage of the driving TFT through the reference lines 15 of the display panel 10 during sensing driving or to control the driving current of the driving TFT through the reference lines 15 of the display panel 10 Can be directly sensed. The sensing unit 30 further includes sensing switches SW-SEN that are turned on only during sensing operation and connect the second mux switches SS1 to SS6 to the output channels CH1 to CH3.

The second mux switches SS1 to SS6 are switched in accordance with the second mux control signals SMUX-R, SMUX-G and SMUX-B, and thus are supplied through the three output channels CH1 to CH3. The sensing inputs may be time-divided and sequentially applied to the two sensing units SU1 and SU2.

SS1 and SS4 among the second mux switches SS1 to SS6 are simultaneously turned on in accordance with the second-1 mux control signal SMUX-R to output the first output channel CH1 to the first sensing unit SU1 And simultaneously connects the second output channel (CH2) to the second sensing unit (SU2). SS2 and SS5 among the second mux switches SS1 to SS6 are simultaneously turned on in accordance with the second-2 mux control signal SMUX-G to simultaneously output the first output channel CH1 to the first sensing unit SU1 And connects the third output channel CH3 to the second sensing unit SU2. Among the second mux switches SS1 to SS6, SS3 and SS6 are simultaneously turned on in accordance with the second-order mux control signal SMUX-B to output the second output channel CH2 to the first sensing unit SU1 And connects the third output channel CH3 to the second sensing unit SU2.

For example, the sensing units SU1 and SU2 may be configured as a voltage sensing type. Therefore, the sensing unit 30 may be configured to sense the source electrode voltage of the driving TFT through the reference lines 15 of the display panel 10 during sensing driving. The voltage sensing type sensing unit includes a sample-and-hold circuit and senses a source electrode voltage of the driving TFT corresponding to the driving current of the driving TFT, that is, a source electrode voltage of the driving TFT stored in the line capacitor of the sensing line. But is not limited thereto.

For example, the sensing units SU1 and SU2 may be configured as a current sensing type. Therefore, the sensing unit 30 may be configured to directly sense the driving current of the driving TFT through the reference lines 15 of the display panel 10 during sensing driving. The current sensing type sensing unit further includes a current integrator at the front end of the sample and hold circuit to directly sense the driving current of the driving TFT flowing through the sensing line. But is not limited thereto.

The ADCs ADC1 and ADC2 convert the sampled analog sensing values in the sensing units SU1 and SU2 into digital sensing values.

The switch array 40 is configured to include the third mux switches SD1 through SD6, the fourth mux positions SX1 through SX6, and the reference voltage supply switches SR1 and SR2. The switch array 40 may be configured in a bezel area outside the pixel array in the display panel 10. [ The bezel region may refer to an area other than the pixel array of the display panel 10. [ That is, the bezel region may be referred to as a non-pixel region.

The third mux switches SD1 to SD6 are involved in outputting the data voltages generated in the DACs to the data lines 14 during the display driving and the sensing driving together with the first mux switches SA1 to SA6 .

The third mux switches SD1 to SD6 are switched in accordance with the third mux control signals DMUX1 and DMUX2 so that one output channel CH1 or CH2 or CH3 of the data voltage supply unit 20 is divided into two data In a time-division manner, to the lines 14R and 14G, or 14B and 14R, or 14G and 14B. The odd-numbered switches SD1, SD3 and SD5 among the third mux switches SD1 to SD6 are turned on simultaneously according to the third-order mux control signal DMUX1 to be output to the output channels of the data voltage supply unit 20 (CH1, CH2, CH3) to the odd-numbered data lines 14R, 14B, 14G, respectively. The odd-numbered switches SD2, SD4 and SD6 among the third mux switches SD1 to SD6 are simultaneously turned on in accordance with the third-order mux control signal DMUX2 to output the output of the data voltage supply unit 20 Channels CH1, CH2, and CH3 to the even data lines 14G, 14R, and 14B, respectively.

The fourth mux positions SX1 to SX6 together with the second mux switches SS1 to SS6 transmit the sensing inputs from the reference lines 15 to the sensing units SU1 and SU2 . Accordingly, the fourth mux positions SX1 to SX6 can be turned on / off at a timing similar to that of the second mux switches SS1 to SS6.

The fourth mux positions SX1 to SX6 are switched according to the fourth mux control signals SSEN-R, SSEN-G and SSEN-B, Divides the inputs into three output channels (CH1 to CH3). For this, SX1 and SX4 among the fourth mux positions SX1 to SX6 are simultaneously turned on in accordance with the 4-1 mux control signal SSEN-R to output the reference lines 15 to the first and second outputs Connect to channels (CH1, CH2). Among the second mux positions SX1 to SX6, SX2 and SX5 are simultaneously turned on in accordance with the 4-2 mux control signal SSEN-G to turn the reference lines 15 to the first and third output channels (CH1, CH3). Among the second mux positions SX1 to SX6, SX3 and SX6 are simultaneously turned on in accordance with the 4-3 mux control signal SSEN-B to turn the reference lines 15 to the second and third output channels (CH2, CH3).

The reference voltage supply switches SR1 and SR2 are simultaneously switched according to the reference voltage control signal SREF during the driving of the display and the driving of the sensing so as to output the reference voltage Vref to the reference lines 15. [ Since the reference voltage supply switches SR1 and SR2 and the fourth mux positions SX1 to SX6 are connected to the reference lines 15 in common, they are turned on at different timings. In the display panel 10, a reference power supply line connected to the reference power supply VREF is provided in a bezel area outside the pixel array. The reference voltage supply switches SR1 and SR2 are connected to the reference power supply line (VREF) and the reference lines (15).

According to the above-described configuration, there is an advantage that the number of the sensing units SU1 and SU2 and the ADCs ADC1 and ADC2 can be reduced. Specifically, the number of sensing units SU1 and SU2 is advantageously less than the number of output channels of the source driver 12. Also, the number of ADCs (ADC1, ADC2) is advantageously less than the number of output channels of the source driver 12. In addition, the switch array 40 has an advantage that the number of output channels of the data voltage supply unit 20 can be reduced. Furthermore, it becomes possible to simplify the sensing section 30 in the source driver 12 corresponding to the display device of the high resolution model.

Particularly, the present invention can cope with a high-resolution model without increasing the size of the source driver 12 through the third mux switches SD1 to SD6 and the first mux switches SA1 to SA6, Since the sensing unit 30 can be simplified, it is advantageous in that it can be more effective for a model having a high resolution and a small size such as a mobile.

The source driver 12 has a predetermined size, so that the size of the source driver 12 can not be infinitely increased in accordance with the increase in resolution. Further, since the source driver 12 corresponds to a relatively expensive component in the display device, increasing the number of output channels of the source driver 12 to increase the size is disadvantageous in terms of cost competitiveness.

In some embodiments, the third mux switches SD1 to SD6 of the switch array 40 are connected to the output channel of the data voltage supply unit 20 and the data line 14 at a ratio of 1: N (where N is a positive integer of 2 or more) Lt; / RTI > Accordingly, there is an advantage that it is possible to cope with a high-resolution model without increasing the size of the data voltage supply unit 20. [ But is not limited thereto.

In some embodiments, it is also possible for the organic light emitting display to be configured to exclude the switch array 40. For example, the organic light emitting display device in which the switch array 40 is excluded may be configured such that the first and second multiplexing switches SA1 to SA6 and the third multiplexing switches SD1 to SD6 are excluded. And that the sensing units, ADCs, DACs, buffers, and output channels can be adjusted and the sensing speed can be accelerated. But is not limited thereto.

In some embodiments, it is also possible that the organic light emitting display device is configured to exclude the sensing portion 30. [ For example, the organic light emitting display in which the sensing unit 30 is excluded is configured such that the second mux switches, the sensing units, the ADCs, the reference voltage supply switches, the sensing switches and the fourth mux switches are excluded . Therefore, the switch array 40 is advantageous in that the number of output channels of the source driver 12 can be reduced by the configuration of only the first mux switches SA1 to SA6 and the third mux switches SD1 to SD6 . But is not limited thereto.

In some embodiments, the organic light emitting display may be configured to include at least one of the sensing portion 30 and the switch array 40.

17 is a schematic circuit diagram for explaining display driving according to the pixel of Fig. 10 and the source driver of Fig. 16;

18 is a schematic waveform diagram for explaining the display driving of Fig.

Hereinafter, display driving of the OLED display according to another embodiment of the present invention will be described with reference to FIGS. 17 and 18. FIG.

The organic light emitting display according to another embodiment of the present invention is configured to control a light emitting operation in units of two neighboring pixel lines in a display driving operation.

The operation of the first mux switches SA1 to SA6 according to the first mux control signals SOE1 and SOE2 and the operation of the third mux switches according to the third mux control signals DMUX1 and DMUX2 The display data voltages to be input to the nth pixel line Ln and the display data voltages to be input to the (n + 1) th pixel line Ln + 1 are time-divided by the operation of the data lines 14R , 14G, and 14B.

The reference voltage supply switches SR1 and SR2 are turned on according to the reference voltage control signal SREF so that the reference voltage Vref is supplied to the reference lines 15. [ At this time, the fourth mux switches SX1 to SX6 are maintained in the turn-off state by the fourth mux control signals SSEN-R, SSEN-G, and SSEN-B. Also, the sensing switches SW-SEN are turned off when the reference voltage control signal SREF is turned on by the sensing driving control signal SSEN.

However, the present invention is not limited thereto, and it is also possible that various control signals are applied to various lines and set to enable display driving.

When driving the display, the emission control signal EM is simultaneously applied to the neighboring two pixel lines, the reference voltage Vref is simultaneously applied to the neighboring two pixel lines, and the data voltage Vdata is applied to each pixel line Respectively. That is, the emission driver 13C is configured to supply a light emission control signal EM simultaneously applied to two neighboring pixel lines.

The display driving will be described as an example of the neighboring nth pixel line Ln and the (n + 1) th pixel line Ln + 1.

SC1 (n + 1), which is the first scan control signal, is applied to the (n + 1) th pixel line Ln + Is applied. The second scan control signal SC2 (n + n + 1) is commonly applied to the nth and (n + 1) th pixel lines Ln and Ln + ) Are commonly applied.

On period of the first scan control signal SC1 (n) applied to the nth pixel line Ln in the programming period Tp and the second scan control signal SC2 (n + n + 1) On period of the first scan control signal SC1 (n + 1) applied to one pixel line Ln + 1 and is turned on. That is, the second scan driver 13B controls the turn-on period of the first scan control signal SC1 (n) applied to the nth pixel line Ln and the turn-on period of the (n + 1) N + 1) which is turned on during a turn-on period of a first scan control signal SC1 (n + 1) applied to the first scan control signal SC1 (n + 1).

In other words, the end of the programming period Tp of the OLED display according to another embodiment of the present invention can be defined as a time point at which the second scan control signal n & n + 1 is turned off have. Therefore, the start time of the light emission period Te may be defined after the second scan control signal n & n + 1 is turned off.

The light emission control signal EM (n + n + 1) is turned on during a specific time after the second scan control signal SC2 (n + n + 1) And is turned off. At this time, the specific time may be preset or adjusted. That is, in the display driving, the emission driver 13C maintains the on level (Lon) for a specific time after the second scan control signal SC2 (n + n + 1) (N ≤ n + 1) to be supplied to the light emitting element.

(N + 1) th pixel line Ln + 1 is turned on during the programming period Tp after the nth pixel line Ln is programmed by SC1 (n) and SC2 (n & 1) and SC2 (n & n + 1).

In the light emitting period Te, the nth and (n + 1) th pixel lines Ln and Ln + 1 are simultaneously reset by EM (n + n + 1) and then emit light simultaneously. Further, since the emission period of EM (n & n + 1) has an adjustable characteristic, the duty can be varied.

According to the above-described configuration, the kickback phenomenon can be reduced. In addition, the off-level (Loff) period of the light emission control signal EM (n & n + 1) described above is variably controlled to enable pulse duty driving.

For example, the light emission control signal EM outputted from one stage of the emission driver 13C of the gate driver 13 may be configured to simultaneously emit a two-line pixel group arranged in two neighboring pixel lines have. For example, the reference voltage Vref may be simultaneously supplied according to the second scan control signal SC2 output from one stage of the second scan driver of the gate driver 13. [ For example, each pixel line is connected to each stage of the first scan driver 13A on a one-to-one basis, and receives the first scan control signal SC1 in a line sequential manner.

19 is a schematic circuit diagram for explaining sensing driving according to the pixel of Fig. 10 and the source driver of Fig. 16;

20 is a schematic waveform diagram for explaining the sensing drive of Fig.

Hereinafter, the sensing operation of the OLED display according to another embodiment of the present invention will be described with reference to FIGS. 19 and 20. FIG.

According to the sensing operation of the OLED display according to another embodiment of the present invention, the data voltage supplier 20 generates a sensing data voltage through the DAC under the control of the timing controller 11 during sensing driving And supplies them to the output channels CH1 to CH3 through the first mux switches SA1 to SA6. The sensing data voltage is a voltage applied to the gate electrode of the driving TFT provided in each pixel during the sensing operation.

The sensing data voltage is applied to the first pixel including the red OLED as a first value, to the second pixels including the green OLED as the second value, and to the third pixels including the blue OLED as the third value Can be predetermined. Here, the first to third values may be equal to each other or may be different from each other.

For example, the one-sensing driving may be performed by driving a first pixel including a red (R) OLED, a second pixel including a green (G) OLED, and a third pixel including a blue (B) The sensing timing for the first to third pixels is temporally separated. For example, the pixel array is sequentially sensed in units of one pixel line to complete sensing for all the first pixels, and sequentially sensing one pixel line sequentially to complete sensing for all the second pixels, It is possible to sequentially sense all the third pixels by sequentially sensing line by line. However, the sensing order is not limited to this and can be implemented in various ways.

The sensing driving will be described below as an example of the nth pixel line Ln.

The sensing operation includes a first period T1 for initializing the pixels and a second period T2 for sensing the electrical characteristics of the pixels.

During the first period T1, the pixels to be sensed and the pixels to be non-sensed in the nth pixel line Ln may be programmed differently. Here, the non-sensing target pixel refers to a pixel that shares the reference line 15 with the sensing target pixel. During the first period T1, an on-level sensing data voltage is applied to the pixel to be sensed, and the pixel to be sensed is programmed so that the driving current flows. On the other hand, during the first period T1, an off-level sensing data voltage is applied to the non-sensing target pixel so that the non-sensing pixel is programmed so that the driving current does not flow.

To this end, during the first period T1, the operation of the first mux switches SA1 to SA6 according to the first mux control signals SOE1 and SOE2 and the operation of the third mux control signals DMUX1 and DMUX2 The sensing data voltage of the ON level and the sensing data voltage of the OFF level to be selectively input to the pixels of the nth pixel line Ln are applied to the data lines SL1 through SD6, (14R, 14G, 14B). During the first period T1, the reference voltage Vref is supplied to the reference lines 15 through the reference voltage supply switches SR1 and SR2. During the first period T1, an on-level sensing data voltage is applied to the pixels to be sensed in the n-th pixel line Ln according to the sensing first scan control signal SC1 (n) The sensing data voltage is applied to the pixels to be non-sensing of the nth pixel line Ln. During the first period T1, the reference voltage Vref is commonly applied to all the pixels of the n-th pixel line Ln in accordance with the second scan control signal SC2 (n) for sensing.

During the second period T2, the first scan control signal SC1 for sensing is turned off and the second scan control signal SC2 (n) for sensing is maintained in the turn-on state, The potential of each reference line 15 rises by the driving current flowing through the pixels to be sensed in the nth pixel line Ln. At this time, the present invention selectively turns on the fourth mux switches SX1 to SX6 and the second mux switches SS1 to SS6 corresponding to the pixels to be sensed, and changes the potential of the reference line 15 2 times sampling (V1 at t1, V2 at t2). The two sampling values V1 and V2 for the pixel to be sensed are used in the timing controller 11 to calculate the threshold voltage change and the electron mobility change of the pixel.

21 is a circuit diagram schematically illustrating an exemplary configuration of a gate driver capable of supplying the display driving and sensing driving control signals disclosed in Figs. 16 to 20. Fig.

Hereinafter, a gate driver of an OLED display according to another embodiment of the present invention will be described with reference to FIG.

The gate driver 13 according to another embodiment of the present invention includes a first scan driver 13A for generating a first scan control signal SC1 to be supplied to the first gate lines 16a, A second scan driver 13B for generating a second scan control signal SC2 to be supplied to the lines 16b and a second scan driver 13B for generating an emission control signal EM to be supplied to the third gate lines 16c, And a driver 13C.

Specifically, the gate driver 13 includes a first scan driver 13A having stages (SC1-STG1 to SC1-STG2100) as the pixel lines (L1 to L2100) of the pixel array, A second scan driver 13B having half the stages SC2-STG1 to SC1-STG1050 of the pixel lines L1 to L2100 and a second scan driver 13B having half the stages EM-STG1 to EM1- And an emission driver 13C having an STG 1050.

In other words, SC1-DUM, SC2-DUM, EM-DUM, SC1-MNT, SC2-MNT and EM-MNT mean dummy stages. L Dummy indicates a dummy pixel line. VGH, VEH and VGL applied to the stages indicate the driving power. But is not limited thereto, and the dummy stage may optionally be included or excluded.

The first scan driver 13A generates a first scan control signal SC1 in response to a gate control signal GDC during display driving and generates a first scan control signal for sensing SC1). ≪ / RTI > The first scan control signal SC1 for driving the display and the first scan control signal SC1 for sensing may be different.

For example, each of the stages SC1 to STG1 to SC1 to STG2100 constituting the first scan driver 13A may be individually connected to one pixel line. Each of the stages SC2-STG1 to SC1-STG1050 constituting the second scan driver 13B may be individually connected to two pixel lines. Each of the stages EM-STG1 to EM-STG1050 constituting the emission driver 13C may be individually connected to two pixel lines. That is, by reducing the number of stages of the second scan driver 13B and the emission driver 13C, the narrow bezel can be realized.

The stages SC1 to STG1 to SC1 to STG2100 of the first scan driver 13A sequentially shift the first start pulse G1Vst according to the first gate clock group G1CLK1 to G1CLK4, (SC1) or a first scan control signal for sensing (SC1).

The second scan driver 13B generates a second scan control signal SC2 in response to the gate control signal GDC during the display driving and generates a second scan control signal for sensing according to the gate control signal GDC SC2. ≪ / RTI > The second scan control signal SC2 for driving the display and the second scan control signal SC2 for sensing may be different.

For example, the stages SC2-STG1 to SC2-STG1050 of the second scan driver 13B sequentially shift the second start pulse G2Vst in accordance with the second gate clock group G2CLK1 to G2CLK4, 2 scan control signal SC2 or a first scan control signal SC2 for sensing.

The emission driver 13C generates the emission control signal EM in accordance with the gate control signal GDC in the display driving and generates the emission control signal EM for sensing in accordance with the gate control signal GDC in the sensing operation Can be implemented as a shift register. The emission control signal EM for the display drive and the emission control signal EM for sensing may be different.

For example, the stages EM-STG1 to EM-STG1050 of the emission driver 13C sequentially shift the third start pulse EVst in accordance with the third gate clock group ECLK1 to ECLK2, And generates a signal EM or a light emission control signal EM for sensing.

The number of stages constituting the second scan driver 13B as well as the stages constituting the emission driver 13C is reduced to half of the vertical resolution of each stage so that the width of the gate driver 13 There is an advantage that it can be reduced. In addition, it achieves Narrow bezel while at the same time it can improve the hump by reducing the kickback, and it also has the advantage of pulse duty drive.

In some embodiments, the gate driver 13 is formed in the left and right bezel regions with the pixel array interposed therebetween. But are not limited thereto.

In some embodiments, the gate driver 13 is formed only in the left bezel region of the pixel array or only in the right bezel region of the pixel array. But is not limited thereto.

In some embodiments, the shifter resistors constituting the gate driver 13 are formed directly in the bezel region of the display panel 10 through a TFT process of a gate driver in panel (GIP) method in order to reduce the process steps and the manufacturing cost . But is not limited thereto.

22 is a circuit diagram schematically showing the configuration of the source driver 12 that can be combined with the pixel structure of Fig. 14 and the configuration of the switch array 40 in the display panel 10. Fig.

22, the source driver 12 and the switch array 40 of the display panel 10 according to still another embodiment of the present invention will be described.

The OLED display according to another embodiment of the present invention is configured to include a source driver 12 further including a display panel 10 and a sensing unit 30 further including a switch array 40. [ In addition, the OLED display according to another exemplary embodiment of the present invention is configured to selectively perform display driving and sensing driving.

Since the source driver 12 shown in Fig. 22 is substantially the same as the source driver 12 shown in Fig. 16, a duplicate description will be omitted below.

The switch array 40 of the display panel 10 shown in Fig. 22 is structurally different from the switch array 40 shown in Fig. Hereinafter, the overlapping description of the switch array 40 shown in FIG. 22 and the switch array 40 shown in FIG. 16 will be omitted, and the differences will be described in detail.

The third mux switches SD1 to SD6 shown in Fig. 22 are substantially the same as the third mux switches SD1 to SD6 shown in Fig. Therefore, redundant description will be omitted.

However, since the switch array 40 shown in FIG. 22 targets pixels that use the data lines as sensing lines, the fourth mux switches SX1 to SX6 of the switch array 40 shown in FIG. 16 and the reference Voltage supply switches SR1 and SR2 are unnecessary. The reference voltage source VREF is connected to the reference lines 15 at all times.

To be more specific, the switch array 40 shown in Fig. 22 corresponds to the pixels and the driving method shown in Figs. 13 and 14. Therefore, it operates in an inverse gamma-gradation representation manner.

It is possible to eliminate the fourth mux switches SX1 to SX6 and the reference voltage supply switches SR1 and SR2 so that the bezel of the display panel 10 corresponding to the source driver 12 side There is an advantage in that the width of the light guide plate can be reduced. It also has the advantage that the advantages described in FIG. 16 can be taken in the same way.

23 is a schematic circuit diagram for explaining display driving according to the pixel of Fig. 14 and the source driver of Fig.

FIG. 24 is a schematic waveform diagram for explaining the display driving of FIG. 23. FIG.

Hereinafter, display driving of the OLED display according to another embodiment of the present invention will be described with reference to FIGS. 23 and 24. FIG.

The organic light emitting display according to another embodiment of the present invention is configured to control a light emitting operation in units of two neighboring pixel lines in a display driving operation.

24, since the first mux control signals SOE1 and SOE2 shown in Fig. 24 are substantially the same as the first mux control signals SOE1 and SOE2 shown in Fig. 18, a duplicate description will be omitted below . The third mux control signals DMUX1 and DMUX2 shown in Fig. 24 are substantially the same as the third mux control signals DMUX1 and DMUX2 shown in Fig.

The switch array 40 is configured not to include the reference voltage supply switches SR1 and SR2 and the fourth mux switches SX1 to SX6. At this time, the reference line 15 is configured to be able to supply the reference voltage Vref.

During the display driving, the emission control signals EM are simultaneously applied to the two neighboring pixel lines, and the data voltage Vdata and the reference voltage Vref are sequentially applied to the respective pixel lines. That is, the emission driver 13C is configured to supply a light emission control signal EM simultaneously applied to two neighboring pixel lines.

Since the pixel of the organic light emitting display according to another embodiment of the present invention is configured by the inverse gamma gradation representation method, the data voltage (Vdata) is applied to the source node of the driving TFT. Then, the reference voltage Vref is applied to the gate node of the driving TFT.

And the supply timing of the reference voltage and the data voltage for programming may be configured to be performed separately on a pixel line basis.

For example, each pixel line is connected to each stage of the first scan driver 13A in a one-to-one manner, and a first scan control signal SC1 is sequentially applied to each pixel line, One-to-one connection to each stage of the driver 13B and sequentially apply a second scan control signal SC2 to each pixel line.

The display driving will be described as an example of the neighboring nth pixel line Ln and the (n + 1) th pixel line Ln + 1.

The scan control signal SC1 (n) and the scan control signal SC2 (n) are applied to the n-th pixel line Ln and the (n + 1) th pixel line Ln + 1 The first scan control signal SC1 (n + 1) and the second scan control signal SC2 (n + 1) are applied. The emission control signal EM (n + n + 1) is commonly applied to the nth and (n + 1) th pixel lines Ln and Ln + 1. Since the emission control signal EM (n & n + 1) shown in Fig. 24 is substantially the same as the emission control signal EM (n & n + 1) shown in Fig. 18, duplicate explanation will be omitted below.

When the display is driven, the reference line (Vref) is continuously supplied to the reference lines (15).

The n + 1 th pixel line Ln + 1 is divided into SC1 (n + 1) and SC2 (n) after the nth pixel line Ln is programmed by SC1 (n + 1).

In the light emitting period Te, the nth and (n + 1) th pixel lines Ln and Ln + 1 are simultaneously reset by EM (n + n + 1) and then emit light simultaneously.

According to the above-described configuration, the kickback phenomenon can be reduced. In addition, the off-level (Loff) period of the light emission control signal EM (n & n + 1) described above is variably controlled to enable pulse duty driving.

25 is a schematic circuit diagram for explaining sensing driving according to the pixel of Fig. 14 and the source driver of Fig.

26 is a schematic waveform diagram for explaining the sensing drive of Fig.

Hereinafter, sensing operation of the OLED display according to another embodiment of the present invention will be described with reference to FIGS. 25 and 26. FIG.

According to the sensing operation of the organic light emitting diode display according to another embodiment of the present invention, since the data lines 14R, 14G, and 14B are used as the sensing lines, There is an advantage that is easier than this. In the sensing operation of the present invention, the reference voltage (Vref) is always supplied to the reference line (15). Hereinafter, the duplicated contents among the contents described in FIG. 19 and FIG. 20 will be partially explained.

The sensing driving will be described below as an example of the nth pixel line Ln.

The sensing operation includes a first period T1 for initializing the pixels and a second period T2 for sensing the electrical characteristics of the pixels.

During the first period T1, an on-level sensing data voltage is simultaneously applied to the odd-numbered pixels of the n-th pixel line Ln, and then the odd-numbered pixels of the n-th pixel line Ln are simultaneously turned on The sensing data voltage is applied. Accordingly, all the pixels of the n pixel line Ln in the first period T1 are programmed so that the driving current flows.

To this end, during the first period T1, by the operation of the third mux switches SD1 to SD6 according to the third mux control signals DMUX1 and DMUX2, the pixels of the nth pixel line Ln An on-level sensing data voltage to be input is supplied to the data lines 14R, 14G, 14B in a time-division manner. During the first period T1, an on-level sensing data voltage is applied to the odd-numbered pixels of the n-th pixel line Ln according to the sensing first scan control signal SC1 (n) Th pixels. During the first period T1, the reference voltage Vref is simultaneously applied to all the pixels in accordance with the second scan control signal SC2 (n) for sensing.

During the second period T2, the second scan control signal SC2 (n) for sensing is turned off and the first scan control signal SC1 (n) for sensing is maintained in the turn- Since the supply of the data voltage is cut off (i.e., the electrical connection between the output channels and the DACs is released in the source driver 12, and the output channels and the sensing units SU are electrically connected) The potentials of the data lines 14R, 14G, and 14B rise due to the driving current flowing through the pixels of the data lines Ln and Ln. At this time, the present invention can sample the potential change twice (V1 at t1 and V2 at t2) for each of the data lines 14R, 14G, and 14B. The two sampling values (V1, V2) for each pixel are used in the timing controller to calculate the threshold voltage change and the electron mobility change of the pixel.

27 is a circuit diagram schematically illustrating an exemplary configuration of a gate driver capable of supplying the display driving and sensing driving control signals disclosed in Figs. 22 to 26. Fig.

Hereinafter, a gate driver of an organic light emitting display according to another embodiment of the present invention will be described with reference to FIG.

Since the first scan driver 13A shown in FIG. 27 is substantially the same as the first scan driver 13A shown in FIG. 21, a duplicate description will be omitted. Since the emissive driver 13C shown in Fig. 27 is substantially the same as the emissive driver 13C shown in Fig. 21, a duplicate description will be omitted below.

The gate driver 13 according to another embodiment of the present invention includes a first scan driver 13A having stages (SC1-STG1 to SC1-STG2100) as pixel lines (L1 to L2100) A second scan driver 13B having stages SC2-STG1 to SC1-STG2100 as many as the pixel lines L1 to L2100 and a second scan driver 13B having as many stages as the pixel lines L1 to L2100, STG1 to EM-STG1050).

Each of the stages SC2-STG1 to SC1-STG2100 constituting the second scan driver 13B may be individually connected to one pixel line.

The stages SC2-STG1 to SC2-STG2100 of the second scan driver 13B sequentially shift the second start pulse G2Vst according to the second gate clock group G2CLK1 to G2CLK4, (SC2) or a first scan control signal for sensing (SC2).

According to the above-described configuration, the number of stages constituting the emission driver 13C can be reduced to half the vertical resolution (i.e., the pixel lines of the display panel), and one stage can drive two pixel lines . Therefore, there is an advantage that the bezel area can be reduced.

That is, another embodiment of the present invention can be described again as follows. An organic light emitting display according to another embodiment of the present invention includes a driving TFT, a first switch TFT, a second switch TFT, and a light emission control TFT, and the light emitting period capable of driving during the programming period and pulse duty is sequentially operated A plurality of pixels configured to include at least an n-th pixel line and an (n + 1) th pixel line; And a gate driver configured to include a first scan driver configured to control the first switch TFT, a second scan driver configured to control the second switch TFT, and a third scan driver configured to control the light emission control TFT, The third scan driver is configured to control the plurality of emission control TFTs corresponding to the n-th pixel line and the (n + 1) th pixel line to be turned on during the programming period, and in the light emission period immediately after the programming period, On state, and to control the turn-on period according to the adjustable turn-off period after a certain period of time.

In the programming period, the first scan driver may be configured to supply the turn-on periods of the respective first scan control signals supplied to the n-th pixel line and the (n + 1) th pixel line different from each other.

The first scan driver is configured to control the plurality of first switch TFTs corresponding to the n-th pixel line and the (n + 1) th pixel line to be sequentially turned on for each pixel line in the programming period, , The n-th pixel line, and the (n + 1) th pixel line.

The first scan driver may be configured to include a plurality of stages corresponding to the respective pixel lines.

One stage of the third scan driver and one stage of the second scan driver may be configured to correspond to two stages of the first scan driver so as to drive one pixel line while reducing kick back.

One stage of the third scan driver and one stage of the second scan driver may be configured to correspond to two stages of the first scan driver so as to drive one pixel line while reducing kick back.

The data voltage applied to the gate node of the driving TFT may be configured to have a higher voltage range than the reference voltage applied to the source node of the driving TFT.

The gate-source voltage of the driving TFT can be configured to operate in a positive gamma gradation manner.

In the programming period, the turn-on period of the second scan control signal simultaneously supplied from the second scan driver to the n-th pixel line and the (n + 1) th pixel line is set to the n-th pixel line and the And may be equal to the sum of the turn-on intervals of the respective first scan control signals supplied.

The second scan driver is configured to turn on all of the plurality of second switch TFTs corresponding to the n-th pixel line and the (n + 1) th pixel line in the programming period, and turn off all of the plurality of second switch TFTs corresponding to the (n + 1) th pixel line.

The second scan driver may be configured to include a plurality of stages corresponding to a pair of adjacent pixel lines.

The number of stages of the first scan driver may be greater than the number of stages of the second scan driver.

The data voltage applied to the source node of the driving TFT can be configured in a voltage range lower than the reference voltage applied to the gate node of the driving TFT.

The gate-source voltage of the driving TFT may be configured to operate in an inverse gamma gradation manner.

In the programming period, the turn-on period of the second scan control signal supplied from the second scan driver to the nth pixel line is the turn-on period of the first scan control signal supplied from the first scan driver to the nth pixel line, And the turn-on period of the second scan control signal supplied from the second scan driver to the (n + 1) th pixel line is the turn-on period of the first scan control signal supplied from the first scan driver to the (n + The ON period may be the same as the ON period.

The second scan driver is configured to control the plurality of second switch TFTs corresponding to the n-th pixel line and the (n + 1) th pixel line to be sequentially turned on for each pixel line in the programming period, , The n-th pixel line, and the (n + 1) th pixel line.

The second scan driver may be configured to include a plurality of stages corresponding to the respective pixel lines.

Each pixel line may have a stage of each first scan driver equal to the number of stages of the second scan driver.

28 to 30 are diagrams showing various implementations of the external compensation module.

28, the organic light emitting diode display of the present invention includes a driver IC (DIC) mounted on a chip on film (COF), a flexible printed circuit board , A storage memory and a power IC (PIC) mounted on a flexible printed circuit board (FPCB), and a host system mounted on a system printed circuit board (SPCB).

The driver IC (DIC) includes the sensing unit, the control unit, the compensation unit, and the compensation memory, which are the above-described source driver 12 and the timing controller 11, which are formed as a single chip. The sensing unit includes a plurality of sensing units SU1 and SU2, a plurality of ADCs ADC1 and ADC2, and the like, as described above. The control unit calculates a compensation parameter that can compensate for a change in the electrical characteristics of the driving TFT based on the digital sensing values input from the sensing unit during the sensing operation, and stores the compensation parameter in the storage memory. The control unit generates various control signals necessary for the operation of the gate driver. The compensation unit reads the compensation parameter from the storage memory at the time of driving the display, stores it in the compensation memory, and corrects the digital data of the input image based on the compensation parameter. The control unit and the compensation unit correspond to the timing controller 11 described above. The storage memory is implemented as a ROM (Read Only Memory), and may be, for example, a flash memory. The compensation memory may be implemented as a random access memory (RAM), for example, a DDR SDRAM (Double Date Rate Synchronous Dynamic RAM).

The power IC (PIC) generates various driving power required for operating the module.

The host system outputs the digital data of the input image to the driver IC (DIC) together with the timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the dot clock signal DCLK, and the data enable signal DE, Lt; / RTI >

29, the organic light emitting diode display of the present invention includes a driver IC (DIC) mounted on a chip-on-film (COF), a storage memory mounted on a flexible printed circuit board (FPCB) A power supply IC (PIC), and a host system mounted on a system print substrate (SPCB). The external compensation module of FIG. 29 is different from FIG. 28 in that the compensation unit and the compensation memory are mounted on the host system without being mounted on the driver IC (DIC). The external compensation module of FIG. 29 is meaningful in that the structure of the driver IC (DIC) is simplified.

Referring to FIG. 30, the organic light emitting diode display of the present invention includes a source IC (SIC) mounted on a chip on film (COF), a storage memory mounted on a flexible printed circuit (FPCB) A compensation IC, a compensation memory and a power IC (PIC), and a host system mounted on a system printed substrate (SPCB). The external compensation module of Fig. 29 implements only the sensing part in the source IC (SIC) to further simplify its configuration, and implements the control part and the compensation part in a compensation IC manufactured separately. The compensation IC, the storage memory, and the compensation memory are mounted together on the flexible printed circuit board (FPCB) to facilitate the up-loading and down-loading operations of the compensation parameter.

INDUSTRIAL APPLICABILITY As described above, the present invention can reduce or suppress the kickback effect within the light emission period for image display, compensate or prevent the luminance distortion, and enhance the image quality.

The present invention can reduce the manufacturing cost and flexibly cope with a high-resolution model by reducing the area occupied by all the circuits for sensing the electrical characteristics of the driving TFT in the source driver.

By reducing the size of the gate driver formed directly on the display panel, it is possible to minimize the left and right edge portions of the display surface from which no image is output.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: Source driver 13: Gate driver
20: Data voltage supply unit 30:
40: Switch array

Claims (30)

In the programming period of the organic light emitting display including the programming period and the light emitting period,
A first switch TFT arranged between the gate node and the data line of the driving TFT and configured to supply a data voltage to the gate node;
A second switch TFT disposed between a source node of the drive TFT and a reference line, and configured such that a transient current supplied through the drive TFT can bypass the reference line;
A light emitting control TFT arranged between the drain node of the driving TFT and the high potential driving power supply line and configured to supply a high potential driving power to the drain node;
A storage capacitor disposed between the gate node and the source node, the storage capacitor configured to charge the gate node to source node voltage of the drive TFT; And
And an organic light emitting diode (OLED) connected to the source node and configured to operate in a non-emission state. The method according to claim 1,
A first gate line configured to supply a first scan control signal to a gate electrode of the first switch TFT, a second gate line configured to supply a second scan control signal to a gate electrode of the second switch TFT, And a third gate line configured to supply a light emission control signal to the gate electrode of the TFT. 3. The method of claim 2,
When the first scan control signal, the second scan control signal, and the emission control signals are simultaneously turned on, the data voltage is applied to one electrode of the storage capacitor corresponding to the gate node, The reference voltage is applied to the other electrode of the storage capacitor corresponding to the source node through the reference line, and the transient current is bypassed to the reference line by the reference voltage lower than the operating point voltage of the organic light emitting diode And the organic light emitting display device. The method according to claim 1,
Wherein the light emitting control TFT is turned on during the programming period, and in the light emitting period, the light emitting control TFT is turned off after a specific time. 5. The method of claim 4,
Wherein the drain node is not in a floating state in the programming period and is not in a floating state for at least the specific time in the light emission period so that kickback can be reduced. 5. The method of claim 4,
Wherein in the light emission period, the light emission control TFT maintains the turn-off state after the predetermined time, and is turned on after a predetermined time. The method according to claim 6,
And the emission control TFT is turned on and off at least one time in the light emission period. 8. The method of claim 7,
Wherein in the light emission period, the light emission control TFT operates as pulse duty drive capable of variable duty adjustment. 9. The method of claim 8,
Further comprising a plurality of pixel lines including the driving TFT, the first switch TFT, the second switch TFT, the light emission control TFT, the storage capacitor and the organic light emitting diode, and the duty of the pulse duty drive of each pixel line is Wherein the organic electroluminescent display device is capable of being adjusted. 10. The method of claim 9,
Wherein the pulse duty driving is capable of performing at least one of gray level representation, flicker reduction, maximum luminance adjustment, and stress reduction of the emission control TFT over N-bit video data. The method of claim 3,
Wherein the reference voltage is a transient current bypass voltage and the data voltage is a voltage set corresponding to the transient current bypass voltage. The method according to claim 1,
And the gate-source node voltage of the driving TFT is configured to operate in a positive gamma gradation manner. The method according to claim 1,
Wherein the first switching TFT is configured to include an oxide semiconductor layer, and the second switching TFT is configured to include an oxide semiconductor layer. 14. The method of claim 13,
Wherein the first switching TFT is configured to further include one semiconductor layer of amorphous silicon and polysilicon and the second switching TFT is configured to further include one of amorphous silicon and polysilicon. Emitting display device. In the programming period of the organic light emitting display including the programming period and the light emitting period,
A second switch TFT arranged between the gate node of the driving TFT and the reference line and configured to supply a reference voltage to the gate node;
A first switch TFT disposed between a source node and a data line of the driving TFT and configured to supply a data voltage to the source node while allowing a transient current supplied from the driving TFT to bypass the data line;
A light emitting control TFT arranged between the drain node of the driving TFT and the high potential driving power supply line and configured to supply a high potential driving power to the drain node;
A storage capacitor disposed between the gate node and the source node, the storage capacitor configured to charge the gate node to source node voltage of the drive TFT; And
And an organic light emitting diode (OLED) connected to the source node and configured to operate in a non-emission state. 16. The method of claim 15,
A first gate line configured to supply a first scan control signal to a gate electrode of the first switch TFT, a second gate line configured to supply a second scan control signal to a gate electrode of the second switch TFT, And a third gate line configured to supply a light emission control signal to the gate electrode of the TFT. 17. The method of claim 16,
When the first scan control signal, the second scan control signal, and the emission control signals are simultaneously turned on, the reference voltage is applied to one electrode of the storage capacitor corresponding to the gate node, Is applied to the other electrode of the storage capacitor corresponding to the source node, and the transient current is bypassed to the reference line by the data voltage lower than the operating point voltage of the organic light emitting diode. Display device. 16. The method of claim 15,
Wherein the light emitting control TFT is turned on during the programming period, and in the light emitting period, the light emitting control TFT is turned off after a specific time. 19. The method of claim 18,
Wherein the drain node is not in a floating state in the programming period and is not in a floating state for at least the specific time in the light emission period so that kickback can be reduced. 19. The method of claim 18,
Wherein in the light emission period, the light emission control TFT maintains the turn-off state after the predetermined time, and is turned on after a predetermined time. 21. The method of claim 20,
And the emission control TFT is turned on and off at least one time in the light emission period. 22. The method of claim 21,
Wherein in the light emission period, the light emission control TFT operates as pulse duty drive capable of variable duty adjustment. 23. The method of claim 22,
Further comprising a plurality of pixel lines including the driving TFT, the first switch TFT, the second switch TFT, the light emission control TFT, the storage capacitor and the organic light emitting diode, and the duty of the pulse duty drive of each pixel line is Wherein the organic electroluminescent display device is capable of being adjusted. 24. The method of claim 23,
Wherein the pulse duty driving is capable of performing at least one of gray level representation, flicker reduction, maximum luminance adjustment, and stress reduction of the emission control TFT over N-bit video data. 16. The method of claim 15,
Wherein the reference voltage is higher than a contrast-lowering voltage, which is capable of lowering the contrast ratio of the OLED display. 18. The method of claim 17,
Wherein the data voltage is a transient current bypass voltage and the reference voltage is a voltage set corresponding to the transient current bypass voltage. 16. The method of claim 15,
And the gate-source voltage of the driving TFT is configured to operate in an inverse gamma-gradation manner. A driving TFT for adjusting an amount of current supplied to the organic light emitting diode by a potential difference between voltages applied to the first electrode and the second electrode of the storage capacitor;
A first switch TFT for inputting a first voltage to the first electrode;
A second switch TFT for inputting a second voltage to the second electrode; And
And an emission control TFT which controls a light emission duty of the organic light emitting diode while supplying a high potential drive power to the drive TFT. 29. The method of claim 28,
Wherein the light emission control TFT is configured to maintain a turn-on state for a predetermined time after the first switch TFT and the second switch TFT are turned off from the turn-on state to compensate the kickback. Organic light emitting display. 30. The method of claim 29,
Wherein the organic light emitting display comprises a positive gamma gradation method or an inverse gamma gradation method.

Images