KR20180057285A - Driver Integrated Circuit For External Compensation And Display Device Including The Same And Data Calibration Method of The Display Device - Google Patents

Abstract

The present invention provides a driver integrated circuit for external compensation which increases sensing performance and compensation performance with respect to electrical properties of pixels by compensating a property deviation between analog to digital converters (ADC), a display device including the same, and a data correction method of the display device. The driver integrated circuit for external compensation according to the present invention comprises: a data voltage generating part generating data voltage for sensing and data voltage for calibration; a sensor sampling a signal input from the pixel in a sensing mode for sensing the electrical properties of the pixel, and sampling the data voltage for calibration in a calibration mode for sensing output properties of the ADC; the ADC converting the analog signal sampled by the sensor into a digital signal; and a switching part connected to the sensor with the data voltage generating part, and connected to the pixel through a channel terminal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an external compensation driver integrated circuit, a display device including the same, and a data correction method for the display device.

The present invention relates to a driver integrated circuit for external compensation, a display device including the same, and a data correction method for the display device.

Various flat panel display devices are being developed and sold. Among them, an electroluminescent display device is divided into an inorganic light emitting display device and an organic light emitting display device depending on the material of the light emitting layer. Particularly, an active matrix type organic light emitting display device includes an organic light emitting diode (OLED) which emits light by itself, has a high response speed, and has a light emitting efficiency, a luminance and a viewing angle This is a great advantage.

The OLED, which is a self-luminous element, includes an anode electrode, a cathode electrode, and an organic compound layer formed therebetween. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer layer, EIL). When a power source voltage is applied to the anode electrode and the cathode electrode, holes passing through the HTL and electrons passing through the ETL are transferred to the EML to form excitons. As a result, the light emitting layer (EML) Thereby generating visible light.

The organic light emitting display device arranges pixels each including an OLED and a driving TFT (Thin Film Transistor) in a matrix form, and adjusts the brightness of an image implemented in pixels according to gray levels of image data. The driving TFT controls a driving current flowing in the OLED according to a voltage (hereinafter referred to as "gate-source voltage") applied between the gate electrode and the source electrode of the driving TFT. The light emission amount of the OLED is determined according to the driving current, and the brightness of the image is determined according to the amount of light emitted from the OLED.

In general, when the driving TFT operates in the saturation region, the driving current Ids flowing between the drain and the source of the driving TFT is expressed by the following equation (1).

In the equation (1), μ represents the electron mobility, C represents the capacitance of the gate insulating film, W represents the channel width of the driving TFT, and L represents the channel length of the driving TFT. Vgs represents the gate-source voltage of the driving TFT, and Vth represents the threshold voltage (or threshold voltage) of the driving TFT. According to the pixel structure, the gate-source voltage (Vgs) of the driving TFT can be the difference voltage between the data voltage and the reference voltage. Since the data voltage is an analog voltage corresponding to the gradation of the image data and the reference voltage is a fixed voltage, the gate-source voltage Vgs of the driving TFT is programmed (or set) according to the data voltage. Then, the drive current Ids is determined according to the programmed gate-source voltage Vgs.

The electrical characteristics of the pixel such as the threshold voltage Vth of the driving TFT, the electron mobility of the driving TFT, and the threshold voltage of the OLED are factors for determining the driving current Ids, Should be. However, electrical characteristics between the pixels may be varied due to various causes such as process characteristics, time-varying characteristics, and the like. Such electric characteristic deviations lead to a luminance deviation, which is a limitation in realizing a desired image.

In order to compensate for the luminance deviation between pixels, an external compensation technique for sensing the electrical characteristics of pixels and correcting the digital data of the input image based on the sensing result is known. In order for the luminance deviation to be compensated, a current change by? Y must be ensured when the data voltage applied to the pixel is changed by? X. Therefore, the external compensation technique is to realize the same brightness by calculating Δx for each pixel and applying the same driving current to the OLED. That is, the external compensation technique adjusts the gray level value to compensate for the brightness of each pixel.

In order to realize the external compensation technique, a sensor for sensing electrical characteristics of pixels and an analog-to-digital converter (ADC) for converting analog sensing data input from the sensor into digital sensing data are required .

The digital sensing data output by the ADC can be distorted for various reasons. Among them, the distortion caused by the characteristic deviation between the ADCs is particularly problematic. If the sensing data is distorted, the luminance deviation due to the difference in electrical characteristics of the pixels can not be compensated properly.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a driver IC for external compensation that can compensate for a characteristic deviation between ADCs and improve the sensing performance and compensation performance of electrical characteristics of pixels, a display device including the driver IC, .

According to an aspect of the present invention, there is provided a driver IC for external compensation, comprising: a data voltage generator for generating a sensing data voltage and a calibration data voltage; A sensor for sampling the signal input from the pixel and sampling the calibration data voltage in a calibration mode for sensing an output characteristic of the analog-to-digital converter; An analog-to-digital converter, and a switching unit connected to the data voltage generating unit and the sensor, and connected to the pixel through a channel terminal.

The present invention can improve the sensing performance and the compensation performance of the electrical characteristics of the pixels by compensating the characteristic deviation between the ADCs.

1 is a block diagram illustrating an EL display device for external compensation according to an embodiment of the present invention.
2 is a schematic view showing a connection configuration of a driver integrated circuit for external compensation and a pixel according to an embodiment of the present invention.
3 is an equivalent circuit diagram showing a pixel according to an embodiment of the present invention.
Fig. 4 is a timing chart of operation for the pixel of Fig. 3; Fig.
5 is a flowchart illustrating an external compensation method according to an embodiment of the present invention.
FIG. 6A is a diagram showing deriving a reference curve equation in the external compensation method of FIG. 5; FIG.
FIG. 6B is a diagram showing the average IV curve of the display panel and the IV curve of the compensation target pixel in the external compensation method of FIG. 5; FIG.
FIG. 6C is a graph showing the IV curve of the display panel, the IV curve of the compensation target pixel, and the IV curve of the compensated pixel in the external compensation method of FIG.
FIGS. 7 to 9 are views showing various implementations of the external compensation module.
10A to 10D are diagrams showing various implementations of the driver IC for external compensation.
11 is a diagram illustrating a configuration of an external compensation driver integrated circuit including a switching unit according to an embodiment of the present invention.
12 is a diagram showing a signal flow for a display mode, a calibration mode, and a sensing mode in the driver IC for external compensation of Fig.
13 is a diagram showing the operation states of the switching unit for the display mode, the calibration mode, and the sensing mode in the driver IC for external compensation of Fig.
FIG. 14 is a diagram illustrating a configuration of an external compensation driver integrated circuit including a switching unit according to another embodiment of the present invention.
FIG. 15 is a diagram showing a signal flow for a display mode, a calibration mode, and a sensing mode in the driver IC for external compensation of FIG. 14; FIG.
FIG. 16 is a diagram showing the operation states of the switching unit for the display mode, the calibration mode, and the sensing mode in the driver IC for external compensation of FIG. 14;
17 is a view showing output data of the ADC corresponding to AVC points in the calibration mode.
18 is a flowchart showing a data compensation method of a display apparatus according to an embodiment of the present invention.
Figs. 19A, 19B and 19C are diagrams showing the operation of the display device corresponding to S10, S20 and S30 of Fig. 18, respectively.
FIG. 20 shows the offset and gain of the ADC before and after compensation for the output characteristics of the ADC.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but is capable of many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other partially or wholly and technically various interlocking and driving are possible and that the embodiments may be practiced independently of each other, It is possible.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the following embodiments, an electroluminescent display device will be described mainly with respect to an organic light emitting display device including an organic light emitting material. However, it should be noted that the technical idea of the present invention is not limited to the organic light emitting display, but can be applied to an inorganic light emitting display device including an inorganic light emitting material. It should be noted that the technical idea of the present invention can be applied not only to an electroluminescent display device but also to various display devices such as a flexible display device and a wearable display device.

1 is a block diagram illustrating an EL display device for external compensation according to an embodiment of the present invention. 2 is a schematic view showing a connection configuration of a driver integrated circuit for external compensation and a pixel according to an embodiment of the present invention. 3 is an equivalent circuit diagram showing a pixel according to an embodiment of the present invention. Fig. 4 is a timing chart of operation for the pixel of Fig. 3; Fig. 5 is a flowchart illustrating an external compensation method according to an embodiment of the present invention. FIG. 6A is a diagram showing deriving a reference curve equation in the external compensation method of FIG. 5; FIG. FIG. 6B is a graph showing the average I-V curve of the display panel and the I-V curve of the compensation target pixel in the external compensation method of FIG. And FIG. 6C is a graph showing an I-V curve of the display panel and an I-V curve of the compensated pixel and an I-V curve of the compensated pixel in the external compensation method of FIG.

1 to 4, an electroluminescent display device according to an embodiment of the present invention includes a display panel 10, a driver IC (D-IC) 20, a compensation IC 30, a host system 40, And a storage memory 50, as shown in FIG.

The display panel 10 is provided with a plurality of pixels PXL and a plurality of signal lines. The signal lines may include data lines 140 for supplying analog data voltages to the pixels PXL and gate lines 150 for supplying gate signals to the pixels PXL.

The gate signal may include a plurality of gate signals SCAN1 and SCAN1. In this case, each of the gate lines 150 may include a first gate line SCAN1 for supplying a first gate signal SCAN1, And a second gate line 150B for supplying a first gate signal 150A and a second gate signal SCAN2. However, the gate signal may be a single number depending on the circuit configuration of the pixel PXL. In this case, each of the gate lines 150 may be a single number. The technical idea of the present invention is not limited to the example configuration of the gate signal and the gate line 150. [

The electrical characteristics of the pixels PXL may be sensed through the data line 140. [ In the following description, it is described that the electrical characteristics of the pixels PXL are sensed through the data line 140 for convenience, but the technical idea of the present invention is not limited thereto. The technical idea of the present invention can be applied to the case of sensing the electrical characteristics of the pixels PXL through a separate signal line other than the data line 140. [

The pixels PXL of the display panel 10 are arranged in a matrix form to constitute a pixel array. Each pixel PXL may be connected to any one of the data lines 140 and to at least one of the gate lines 150. [ Each pixel PXL is configured to receive a high potential driving power supply VDD and a low potential driving power supply VSS from a power generation unit. To this end, the power generator may supply the high-potential driving power source (VDD) to the pixel via the high-potential pixel power supply wiring or the pad portion. The power generation section can supply the low potential driving power supply (VSS) to the pixel through the low potential pixel power supply line or the pad section.

The gate driver 15 can generate a gate signal for display necessary for display driving and a sensing gate signal necessary for sensing driving. The display gate signal and the sensing gate signal may include a first gate signal SCAN1 and a second gate signal SCAN2, respectively.

The gate driver 15 generates a first gate signal SCAN1 for display in driving the display and supplies the generated first gate signal SCAN1 to the first gate line 150A to generate a second gate signal SCAN2 for display, . The display first gate signal SCAN1 and the second gate signal SCAN2 are signals synchronized with the writing timing of the display data voltage Vdata-DIS.

The gate driver 15 generates a first gate signal SCAN1 for sensing during sensing driving and supplies the generated first gate signal SCAN1 to the first gate line 150A to generate a second gate signal SCAN2 for sensing, . The sensing first gate signal SCAN1 is a signal synchronized with the writing timing of the sensing data voltage Vdata-SEN. The sensing second gate signal SCAN2 is a signal synchronized with the writing timing and the sensing timing of the sensing data voltage Vdata-SEN.

The gate driver 15 may be formed directly on the lower substrate of the display panel 10 by a gate-driver In Panel (GIP) method. The gate driver 15 is formed in a non-display area (i.e., a bezel area) outside the pixel array in the display panel 10, and can be formed in the same TFT process as the pixel array.

The driver IC (D-IC) 20 is connected to the data line 140 of the display panel 10 through the channel terminal CH. The driver IC (D-IC) 20 includes a timing control section 26 and a data driving section 25.

The timing control unit 26 refers to the timing signals input from the host system 40 such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE It is possible to generate a gate timing control signal GDC for controlling the operation timing of the gate driving unit 15 and a data timing control signal DDC for controlling the operation timing of the data driving unit 25. [

The data timing control signal DDC may include, but is not limited to, a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the data sampling start timing of the data driver 25. The source sampling clock is a clock signal that controls sampling timing of data based on the rising or falling edge. The source output enable signal controls the output timing of the data driver 25.

The gate timing control signal GDC may include, but is not limited to, a gate start pulse, a gate shift clock, and the like. The gate start pulse is applied to the stage that produces the first output to activate the operation of the stage. The gate shift clock is a clock signal commonly inputted to the stages, and is a clock signal for shifting the gate start pulse.

The timing controller 26 can control a calibration mode for calibration driving, a sensing mode for sensing driving, and a display mode for driving the display according to a predetermined control sequence.

In the calibration mode, the first characteristic data (C-DATA) indicating the output characteristic of the ADC is obtained. In the sensing mode, the second characteristic data (S-DATA) indicating the electrical characteristics of the pixel PXL is obtained. In the display mode, the input image data to be written to the pixels PXL is corrected based on the first characteristic data (C-DATA) acquired through the calibration mode and the second characteristic data (S-DATA) acquired through the sensing mode And converts the corrected image data into a display data voltage Vdata-DIS to apply it to the pixels PXL.

The timing controller 26 may generate timing control signals for driving the display, timing control signals for sensing driving, and timing control signals for calibration driving. But is not limited thereto. Under the control of the timing control unit 26, the sensing drive is performed in the vertical blank period during the display drive, or in the power-on sequence period before the display drive is started, or in the power-off sequence period after the display drive is finished . But the present invention is not limited thereto, and the sensing driving can be performed in the vertical active period during the display driving. On the other hand, the calibration driving may be performed in the vertical blank period during the display driving, or in the power-on sequence period before the display driving is started, or in the power-off sequence period after the display driving is finished. But is not limited thereto.

The vertical blanking period is a period in which input image data is not written, and is arranged between vertical active periods in which input image data for one frame is written. The power-on sequence period means a transient period from when the driving power is turned on until the input image is displayed. The power-off sequence period means a transient period from the end of the display of the input image until the driving power is turned off.

The timing controller 26 can control all operations for sensing driving according to a predetermined sensing process. That is, the sensing operation may be performed in a state where only the screen of the display device is turned off during the period in which the system power is being applied, for example, in a standby mode, a sleep mode, a low power mode, and the like. But is not limited thereto.

The timing controller 26 can control all operations for driving the calibration in accordance with a predetermined calibration process. Since the characteristic change of the ADC progresses relatively slowly compared with the change of the electrical characteristic of the pixel PXL, the calibration drive can be performed once every plural sensing runs.

The AVC (ADC Variation Compensation) data obtained in the calibration mode, that is, the first characteristic data (C-DATA) is reflected in the compensation value for compensating for the change in electrical characteristics of the pixel PXL, Degradation of performance and compensation performance can be prevented.

The data driver 25 includes a sensing unit 22, a data voltage generator 23, and a switching unit (SWC).

The data voltage generator 23 may include a digital-to-analog converter (DAC) and an output buffer (not shown) for converting a digital signal into an analog signal. The DAC generates a display data voltage (Vdata-DIS) or a sensing data voltage (Vdata-SEN) or a calibration data voltage (Vdata-CAL).

The data voltage generator 23 converts the corrected video data V-DATA into an analog gamma voltage using the DAC and outputs the result of the conversion to the data lines Vdata-DIS as display data voltages Vdata- 140. The display data voltage Vdata-DIS supplied to the data lines 140 is applied to the pixels PXL in synchronization with the turn-on timing of the first and second gate signals (not shown) do. Source voltage of the drive TFT included in the pixels PXL is programmed by the display data voltage Vdata-DIS, and the drive current flowing to the drive TFT is determined according to the gate-source voltage of the drive TFT .

The data voltage generator 23 generates a predetermined sensing data voltage Vdata-SEN using the DAC and supplies the sensing data voltage Vdata-SEN to the data lines 140 during sensing operation. The sensing data voltage Vdata-SEN supplied to the data lines 140 is applied to the pixels PXL in synchronization with the turn-on timing of the first and second gate signals SCAN1 and SCAN2 for sensing . Source voltage of the driving TFT included in the pixels PXL is programmed by the sensing data voltage Vdata-SEN, and the driving current flowing to the driving TFT is determined according to the gate-source voltage of the driving TFT .

The data voltage generator 23 generates a preset calibration data voltage Vdata-CAL using the DAC and supplies the data voltage Vdata-CAL to the sensing unit 22 via the switching unit SWC. If the calibration data voltage (Vdata-CAL) is generated by using the DAC inside the driver IC 20, it is possible to reduce the signal multiplier, circuit area, and the like compared with the case where the calibration data voltage Vdata-CAL is supplied to the driver IC 20 from a separate external voltage source . In addition, since the signal delay is greatly reduced, there is an advantage that the output characteristic of the ADC can be accurately sensed. The data voltage for calibration (Vdata-CAL) may be implemented with voltages of a plurality of gradations corresponding to predetermined representative gradations.

The pixels PXL may be implemented as shown in FIG. Referring to FIG. 3, each of the pixels PXL constituting the pixel array includes an OLED, a driving TFT (Thin Film Transistor) DT, a storage capacitor Cst, a first switch TFT ST1, And a TFT (ST2). The TFTs may be implemented as a PMOS. However, the pixel configuration in Fig. 3 is merely an example, and the technical idea of the present invention is not limited to the pixel structure.

3, the first gate signal SCAN1 may be a first gate signal for sensing or a first gate signal for display and the second gate signal SCAN2 may be a second gate signal for sensing or a second gate signal for display . The data voltage Vdata supplied from the data voltage generator 23 to the data line 140 may be a sensing data voltage Vdata-SEN or a display data voltage Vdata-DIS.

The OLED is a light emitting element that emits light in accordance with a driving current input from the driving TFT DT. The OLED includes an anode electrode, a cathode electrode, and an organic compound layer positioned between the anode electrode and the cathode electrode. The anode electrode is connected to the second node N2 which is the drain electrode of the driving TFT DT. And the cathode electrode is connected to the input terminal of the low potential driving voltage VSS. The gradation value of the image displayed on the pixel PXL is determined according to the amount of light emitted by the OLED.

The driving TFT DT is a driving element for controlling the driving current input to the OLED according to the gate-source voltage Vgs. The driving TFT DT has a gate electrode connected to the first node N1, a source electrode connected to the input terminal of the high potential driving voltage VDD, and a drain electrode connected to the second node N2. The gate-source voltage Vgs of the driving TFT DT is a difference voltage between the high potential driving voltage VDD and the first node N1 voltage.

The storage capacitor Cst is connected between the high potential driving voltage VDD and the first node N1. The storage capacitor Cst holds the gate-source voltage Vgs of the driving TFT DT for a predetermined time.

The first switch TFT ST1 applies the data voltage Vdata on the data line 140 to the first node N1 in response to the first gate signal SCAN1. The first switch TFT ST1 has a gate electrode connected to the first gate line 150A, a source electrode connected to the data line 140, and a drain electrode connected to the first node N1.

The second switch TFT (ST2) switches the current flow between the second node (N2) and the data line (140) in response to the second gate signal (SCAN2). The second switch TFT ST2 has a gate electrode connected to the second gate line 150B, a drain electrode connected to the data line 140, and a source electrode connected to the second node N2. When the second switch TFT (ST2) is turned on, the second node (N2) and the sensor (21) are electrically connected.

The sensing operation may include a programming period Tp and a sensing period Ts as shown in FIG. The data voltage Vdata is applied to the first node N1 of the pixel PXL in synchronization with the turn-on timing of the first gate signal SCAN1 and the turn-off timing of the second gate signal SCAN2 during the programming period Tp . At this time, since the gate-source voltage Vgs of the driving TFT DT is higher than the threshold voltage, the driving TFT DT is turned on and a driving current flows. The drive current flowing in the drive TFT DT is applied to the second switch TFT ST2 in synchronization with the turn-off timing of the first gate signal SCAN1 and the turn- The data line 140, and the switching unit SWC.

The sensing unit 22 includes a sensor 21 and an ADC that operate in a sensing mode and a calibration mode.

The sensor 21 is turned on when the sensing operation is performed and the electric characteristics of the pixels PXL such as the pixels PXL and the pixels PXL are controlled in synchronization with the turn- The driving characteristics of the driving TFT and / or the OLED included in the driving signal lines PXL and / or PXL may be sensed through the data lines 140 and the switching unit SWC. On the other hand, the sensor 21 can receive the calibration data voltage (Vdata-CAL) input from the DAC through the switching unit (SWC) and sample it when the calibration is driven.

Such a sensor 21 may include a sensing unit SUT and a sample and hold unit SHA for sampling the output of the sensing unit SUT, as shown in Fig. The sensing unit SUT may be implemented as a voltage sensing type.

The sensing unit SUT senses the voltage charged in the channel terminal CH by the driving current flowing to the driving TFT of the pixel PXL during sensing driving and senses the calibration data voltage Vdata-CAL during the calibration driving have. The sample and hold unit (SHA) samples the output of the sensing unit (SUT) and supplies the sampled result to the ADC.

The ADC converts the analog sampling signal input from the sample-and-hold unit (SHA) into a digital signal and outputs first characteristic data (C-DATA) representing the output characteristic of the ADC. The ADC converts the analog sampling signal input from the sample-and-hold unit (SHA) into a digital signal and outputs second characteristic data (S-DATA) representing the electrical characteristics of the pixel (P).

The ADC can be implemented as a flash-type ADC, an ADC using a tracking technique, or an ADC with a successive approximation register type. The ADC supplies the first characteristic data (C-DATA) obtained at the time of the calibration operation to the storage memory (50). The ADC supplies the second characteristic data (S-DATA) obtained at the sensing operation to the storage memory (50).

The switching unit SWC operates differently in the calibration mode, the sensing mode and the display mode and is connected to the data voltage generator 23 and the sensor 21 and to the pixel PXL through the channel terminal CH . The specific configuration and operation of the switching unit (SWC) will be described in detail with reference to Figs. 11 to 16. Fig.

The storage memory 50 stores the first characteristic data C-DATA and the second characteristic data S-DATA. The storage memory 50 may be implemented as a flash memory, but is not limited thereto.

The compensation IC 30 generates an offset and a gain for each pixel based on the first characteristic data C-DATA and the second characteristic data S-DATA read from the storage memory 50, (Or corrects) the digital image data to be input to the pixels PXL according to the calculated offset and gain, and outputs the modulated digital image data V-DATA to the driver IC 20 Supply. To this end, the compensation IC 30 may include a compensation unit 31 and a compensation memory 32. [

The compensation memory 32 transfers the first characteristic data (C-DATA) and the second characteristic data (S-DATA) read from the storage memory 50 to the compensation section 31. The compensation memory 32 may be a RAM (Random Access Memory), for example, a DDR SDRAM (Double Data Rate Synchronous Dynamic RAM), but is not limited thereto.

5 to 6C, the compensating unit 31 obtains one average current (I) -voltage (V) curve through a plurality of sensing operations and compensates the IV curve of the pixel so that it corresponds to the average IV curve Algorithm.

5 and FIG. 6A, the compensating unit 31 performs a known least squares method (least squares method) after sensing a plurality of gradations (for example, 7 grades including A to F) The following equation (2) corresponding to the average IV curve is derived (S1).

In Equation 2, "a" is the electron mobility of the driving TFT, "b" is the threshold voltage of the driving TFT, and "c" indicates the physical property value of the driving TFT.

The compensating unit 31 compares the current values I1 and I2 measured at two points and the gradation values (X and Y gradations) (i.e., the data voltage values (Vdata1 and Vdata2)) as shown in Figs. 5 and 6B A 'value and a b' value, which are parameter values of the pixel PXL, are calculated (S2).

The compensating unit 31 may calculate the a 'value and the b' value, which are parameter values of the pixel PXL, using the quadratic equation in Equation (3).

The compensating unit 31 may calculate an offset and a gain to make the I-V curve of the corresponding pixel coincide with the average I-V curve as shown in FIGS. 5 and 6C (S3). The offset (Offset) and gain (gain) after the compensation is completed are shown in Equation (4). In Equation (4), "Vcomp" indicates a compensation voltage at a digital level.

The compensation unit 31 corrects the digital image data to be input to the pixel PXL so as to correspond to the compensation voltage Vcomp (S4).

The host system 40 can supply digital image data to be inputted to the pixels PXL of the display panel 10 to the compensation IC 30. [ The host system 40 can further supply the user input information such as the digital brightness information to the compensation IC 30. [ The host system 40 may be implemented as an application processor.

FIGS. 7 to 9 are views showing various implementations of the external compensation module.

Referring to FIG. 7, the electroluminescent display device of the present invention includes a driver IC (D-IC) 20 mounted on a chip on film (COF) A storage memory 50 and a power supply IC (P-IC) 60 mounted on a flexible printed circuit board (FPCB), and a host system 40 mounted on a system printed circuit board (SPCB) can do.

The driver IC (D-IC) 20 may further include a compensation unit 32 and a compensation memory 32 in addition to the timing control unit 26, the sensing unit 22, and the data voltage generation unit 23. [ This external compensation module is a driver IC (D-IC) 20 and a compensation IC ('30' in FIG. The power IC (P-IC) 60 generates various driving power sources necessary for operating the external compensation module.

8, the OLED display of the present invention includes a driver IC (D-IC) 20 mounted on a chip-on-film (COF) and a flexible printed circuit board (FPCB) A storage memory 50 and a power source IC (P-IC) 60, and a host system 40 mounted on a system print substrate (SPCB).

The external compensation module in Fig. 8 is different from Fig. 7 in that the compensation unit 31 and the compensation memory 32 are mounted on the host system 40 without being mounted on the driver IC (D-IC) 8 is meaningful in that the compensation IC ('30' in FIG. 1) is integrated in the host system 40 and can simplify the configuration of the driver IC (D-IC) 20 have.

9, the organic light emitting diode display of the present invention includes a driver IC (D-IC) 20 mounted on a chip-on-film (COF) and a flexible printed circuit board (FPCB) (Not shown) can be provided that includes a mounted storage memory 50, a compensation IC 30, a compensation memory 32 and a power IC (P-IC) 60 and a host system 40 mounted on a system printed circuit board (SPCB) have.

The external compensation module of Fig. 9 further simplifies the structure of the driver IC 20 by mounting only the voltage generator 23 and the sensor 21 to the driver IC 20, and the timing controller 31 and the compensator 32 Is mounted on the compensation IC 30 manufactured separately. The compensation IC 30, the storage memory 50, and the compensation memory 32 are mounted on the flexible printed circuit board (FPCB) to facilitate the up-loading and down-loading of the compensation value.

10A to 10D are diagrams showing various implementations of the driver IC for external compensation.

One or a plurality of ADCs may be mounted in the driver IC 20. [ In other words, as shown in Figs. 10A to 10D, at least one sensor 21 may be connected to the ADC. For example, eight sensors 21 may be connected to each ADC as shown in FIG. 10A, four sensors 21 may be connected to each ADC as shown in FIG. 10B, and sensors 21 may be connected to each ADC as shown in FIG. And two sensors 21 may be connected to each ADC, as shown in FIG. 10D. 10A to 10C, a mux switch (not shown) is further connected between the plurality of sensors 21 and the ADC so that signals input from the sensor 21 can be sequentially supplied to the ADC.

The sampling rate of the ADC and the accuracy of the sensing are in a trade-off relationship. As the number of ADCs mounted in the driver IC 20 increases, the number of sensing data to be processed by one ADC is reduced, so that the sampling rate of the ADC can be reduced and the accuracy of sensing can be increased accordingly. However, as the number of ADCs increases, the area occupied by the ADC in the driver IC 20 may increase. The number of ADCs can be appropriately designed according to the model and specification of the display device and the like.

10A to 10D, at least one sensor 21 may be electrically connected to each of the channel terminals CH. Although the sensors 21 are shown as being connected to each channel terminal CH, a plurality of sensors 21 may be connected to each channel terminal CH. The number of channel terminals CH of the driver IC 20 can be reduced when a plurality of sensors 21 are connected to each channel terminal CH so that the circuit configuration of the driver IC 20 can be simplified . On the other hand, a switching unit is connected between the channel terminal CH and the sensor 21, but is not shown in Figs. 10A to 10D.

11 is a diagram illustrating a configuration of an external compensation driver integrated circuit including a switching unit according to an embodiment of the present invention. 12 is a diagram showing a signal flow for a display mode, a calibration mode, and a sensing mode in the driver IC for external compensation of Fig. 13 is a diagram showing the operation states of the switching unit for the display mode, the calibration mode, and the sensing mode in the driver IC for external compensation of Fig.

11 to 13, the switching unit SWC is connected to the sensor 21 and the data voltage generating unit 23 and is connected to the pixel PXL through the channel terminal CH and the data line 140, Lt; / RTI > The switching unit SWC includes a first switch SW1 connected between the data voltage generating unit 23 and the channel terminal CH and a second switch SW2 connected between the sensor 21 and the channel terminal CH .

11 to 13, in the calibration mode, the first switch SW1 and the second switch SW2 are turned on. Thus, the switching unit SWC can supply the sensor 21 with the calibration data voltage Vdata-CAL input from the data voltage generation unit 23 in the calibration mode.

On the other hand, in the sensing mode, the first switch SW1 is turned on during the programming period (Tp in Fig. 4), turned off during the sensing period (Ts in Fig. 4) And is turned on during the sensing period. The switching unit SWC switches the sensing data voltage Vdata-SEN input from the data voltage generation unit 23 during the programming period (Tp in FIG. 4) to the pixel The signal input from the pixel PXL can be supplied to the sensor 21 during the sensing period (Ts in Fig. 4). Since the first switch SW1 is turned off during the sensing period (Ts in Fig. 4), the output of the data voltage generation section 23 during the sensing period (Ts in Fig. 4) is mixed into the signal input from the pixel PXL Can be effectively prevented.

On the other hand, in the display mode, the first switch SW1 is turned on and the second switch SW2 is turned off. Accordingly, the switching unit SWC can supply the display data voltage Vdata-DIS input from the data voltage generating unit 23 to the pixel PXL through the channel terminal CH in the display mode.

FIG. 14 is a diagram illustrating a configuration of an external compensation driver integrated circuit including a switching unit according to another embodiment of the present invention. FIG. 15 is a diagram showing a signal flow for a display mode, a calibration mode, and a sensing mode in the driver IC for external compensation of FIG. 14; FIG. FIG. 16 is a diagram showing the operation states of the switching unit for the display mode, the calibration mode, and the sensing mode in the driver IC for external compensation of FIG. 14;

14 to 16, the switching unit SWC is connected to the sensor 21 and the data voltage generating unit 23, and is connected to the pixel PXL through the channel terminal CH and the data line 140, Lt; / RTI > The switching unit SWC includes a first switch SW1 connected between the data voltage generating unit 23 and the channel terminal CH and a second switch SW2 connected between the data voltage generating unit 23 and the sensor 21. [ (SW2).

Referring to Figs. 14 to 16, in the calibration mode, the first switch SW1 is turned off, and the second switch SW2 is turned on. Thus, the switching unit SWC can supply the sensor 21 with the calibration data voltage Vdata-CAL input from the data voltage generation unit 23 in the calibration mode. Since the first switch SW1 is turned off in the calibration mode as compared with the switching unit SWC in Fig. 14, the switching unit SWC in Fig. 14 effectively prevents the panel noise from flowing into the sensor 21 at the time of the calibration operation can do.

In the sensing mode, the first switch SW1 is turned off during the programming period (Tp in FIG. 4), turned off during the sensing period (Ts in FIG. 4) Is turned off during the programming period and turned on during the sensing period. The switching unit SWC switches the sensing data voltage Vdata-SEN input from the data voltage generation unit 23 during the programming period (Tp in FIG. 4) to the pixel The signal input from the pixel PXL can be supplied to the sensor 21 during the sensing period (Ts in Fig. 4). Since the first switch SW1 is also turned on during the sensing period (Ts in Fig. 4), the driving power of the buffer BUF during the sensing period (Ts in Fig. 4) May be disabled to block the input from the signal input from the pixel PXL.

On the other hand, in the display mode, the operation and effects of the first and second switches SW1 and SW2 in Figs. 14 to 16 are substantially the same as those described in Figs. 11 to 13. Fig.

17 is a view showing output data of the ADC corresponding to AVC points in the calibration mode.

Referring to Fig. 17, the driver IC 20 can generate the data voltage for calibration (Vdata-CAL) using the internal DAC in the calibration mode. This data voltage for calibration (Vdata-CAL) is implemented by voltages of a plurality of predetermined gradation levels, and the voltages P1 to Pk of the plural gradations become AVC (ADC Variation Compensation) points. The number of AVC points can be appropriately selected in consideration of a tact time for driving the calibration. In Fig. 17, the ADC output data is the first characteristic data indicating the output characteristic of the ADC.

18 is a flowchart showing a data compensation method of a display apparatus according to an embodiment of the present invention. Figs. 19A, 19B and 19C are diagrams showing the operation of the display device corresponding to S10, S20 and S30 of Fig. 18, respectively. 20 is a graph showing the offset and gain of the ADC before and after compensation for the output characteristics of the ADC.

Referring to FIG. 18, a data compensation method of a display apparatus according to an exemplary embodiment of the present invention includes a step S10 of measuring an ADC output characteristic, a step S20 of measuring an electrical characteristic of a pixel, (S30).

The step S10 of measuring the ADC output characteristic is a step of acquiring the first characteristic data in the calibration mode. That is, step (S10) of measuring the ADC output characteristic samples the data voltage for calibration generated internally in the calibration mode through the first and second switches SW1 and SW2 and the sensor 21 as shown in FIG. 19A, And converting the sampled signal from the ADC to a digital signal to obtain first characteristic data (ADC characteristic data) indicative of an output characteristic of the ADC.

The step S20 of measuring the electrical characteristic of the pixel is a step of acquiring the second characteristic data in the sensing mode. That is, the step S20 of measuring the electrical characteristics of the pixel samples the signal input from the pixels of the display panel through the second switch SW2 and the sensor 21 in the sensing mode as shown in Fig. 19B, (Panel characteristic data) representing the electrical characteristics of the pixel by converting the analog signal into the digital signal by the ADC.

The step of correcting the input image data (S30) corrects the input image data to be written to the pixel based on the first characteristic data and the second characteristic data in the display mode as shown in Fig. 19C, A data voltage for display is internally generated and supplied to the pixel through the first switch SW1.

As shown in FIG. 20, the ADC output characteristics, offset and gain, may be different between neighboring ADCs (ADC connected to channel N and ADC connected to channel N + 1) (A). This characteristic deviation is contained in the first characteristic data. Therefore, if the input image data to be written to the pixel is corrected based on the first characteristic data, deterioration of the sensing performance and the compensation performance due to the ADC output deviation can be prevented. The process of correcting the input image data based on the first characteristic data is a process of correcting the offset of the ADC to 0 and correcting the gain of the ADC to 1 (B).

As described above, the present invention can improve the sensing performance and the compensation performance of the electrical characteristics of the pixels by compensating the characteristic deviation between the ADCs.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 20: Driver IC
15: Gate driver 21: Timing controller
22: sensor 23: data voltage generator
30: Compensation IC 40: Host system
50: Storage memory

Claims (18)

A data voltage generator for generating a sensing data voltage, and a data voltage for calibration;
A sensor that samples the signal input from the pixel in a sensing mode for sensing the electrical characteristics of the pixel and samples the data voltage for calibration in a calibration mode for sensing an output characteristic of the analog-to-digital converter;
The analog-to-digital converter converting an analog signal sampled by the sensor into a digital signal; And
And a switching unit connected to the data voltage generating unit and the sensor and connected to the pixel through a channel terminal. The method according to claim 1,
The switching unit includes:
Wherein the sensing data voltage is supplied to the pixel through the channel terminal in the sensing mode, and then a signal input from the pixel is supplied to the sensor, and in the calibration mode, Compensating driver integrated circuit. 3. The method of claim 2,
Wherein the data voltage generator further generates a display data voltage,
Wherein the switching unit supplies the display data voltage to the pixel through the channel terminal in a display mode for displaying an input image. The method of claim 3,
The switching unit includes:
A first switch connected between the data voltage generator and the channel terminal; And
And a second switch connected between the sensor and the channel terminal. 5. The method of claim 4,
Wherein the first switch and the second switch are turned on in the calibration mode. The method of claim 3,
The switching unit includes:
A first switch connected between the data voltage generator and the channel terminal; And
And a second switch connected between the data voltage generator and the sensor. The method according to claim 6,
And the second switch is turned on in the calibration mode. The method according to claim 6,
Wherein the first switch is turned off to block the noise of the display panel from entering the sensor in the calibration mode. 5. The method of claim 4,
In the sensing mode,
Wherein the first switch is turned on during a programming period to set a gate-to-source voltage of the pixel, and is turned off during a sensing period subsequent to the programming period,
And the second switch is turned off during the programming period and turned on during the sensing period. The method according to claim 6,
In the sensing mode,
The first switch is turned on during a programming period to set a gate-to-source voltage of the pixel, is turned on during a sensing period subsequent to the programming period,
And the second switch is turned off during the programming period and is turned on during the sensing period. The method according to claim 4 or 6,
Wherein the first switch is turned on and the second switch is turned off in the display mode. The method according to claim 1,
Wherein at least one of the sensors is connected to the analog-to-digital converter. The method according to claim 1,
And each of the channel terminals is electrically connected to at least one of the sensors. A display panel having a plurality of pixels and data lines connected to the pixels; And
And a driver integrated circuit for external compensation according to any one of claims 1 to 10, which is connected to the data line through a channel terminal. 15. The method of claim 14,
And a compensation unit electrically connected to the analog-to-digital converter for receiving first characteristic data representing an output characteristic of the analog-to-digital converter and second characteristic data representing an electrical characteristic of the pixel from the analog-to-digital converter, Display device. 16. The method of claim 15,
And the compensating unit corrects the input image data based on the first characteristic data and the second characteristic data. In the calibration mode, a data voltage for calibration generated internally is sampled through a switching unit and a sensor, and the sampled signal is converted into a digital signal by an analog-to-digital converter to generate first characteristic data representing an output characteristic of the analog- ;
A signal input from the pixels of the display panel is sampled through the switching unit and the sensor in the sensing mode, and the sampled signal is converted into a digital signal by the analog-to-digital converter to generate second characteristic data representing the electrical characteristics of the pixel Obtaining; And
And correcting the input image data to be written to the pixel based on the first characteristic data and the second characteristic data 18. The method of claim 17,
Generating a display data voltage corresponding to the input image data in the display mode and supplying the generated data voltage to the pixel through the switching unit.

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