KR20170111516A - Magnetic sensor apparatus - Google Patents

Abstract

A hall sensor device according to the present invention includes a pair of first and third terminals facing each other and a pair of second and fourth terminals facing each other, A Hall element for detecting the magnetic field as a voltage signal; And first to fourth switches respectively connected to the first to fourth terminals, wherein the first voltage signal and the third voltage signal respectively detected at the first terminal and the third terminal, A switch circuit for selectively switching between a second voltage signal and a fourth voltage signal respectively detected by the first voltage signal and the second voltage signal; A first switching module and a second switching module connected in parallel to a first common output terminal of the first switch and the second switch and a third switching module connected in parallel to a second common output terminal of the third switch and the fourth switch, And a fourth switching module for selectively switching the first output signal output from the first common output terminal and the second output signal output from the second common output terminal and outputting the digital output signal as digital data through delta sigma modulation, A conversion unit; And a switching control unit for controlling switching of the first to fourth switches of the switch circuit unit and the first to fourth switching modules of the delta sigma conversion unit.

Description

[0001]

[0001] The present invention relates to a Hall sensor device, and more particularly, to a Hall sensor device which eliminates an offset voltage signal and a noise signal through a delta-sigma converter ([Delta] [Sigma] ADC) And more particularly,

A Hall sensor is a type of magnetic sensor that senses a change in an external magnetic field by using a Hall effect and outputs it as an electric signal.

Such a Hall sensor is a sensor that uses a current and a potential difference generated in a direction perpendicular to the magnetic field, that is, a Hall voltage, when a current is applied to a semiconductor substrate and a magnetic field is applied in a direction perpendicular to the current flow. Resistance.

The conventional Hall sensor outputs a constant offset voltage whose detection voltage is not 0 even when the magnetic field is zero, that is, even when the Hall sensor is in the non-magnetic state. Since the offset voltage generates an error in the measured value of the Hall sensor, there is a method of driving the Hall sensor to which the spinning current method is applied to remove the offset voltage.

However, in such a conventional Hall sensor, since the Hall voltage signal has a low frequency, there is a problem that the operating speed of the Hall sensor device is slow.

Korean Patent Publication No. 0676212 Korean Patent Publication No. 1519320 U.S. Published Patent Application No. 2010/0052665 Japanese Patent Application Laid-Open No. 2015-508168

It is an object of the present invention to provide a Hall sensor device for eliminating an offset voltage signal included in a voltage signal output from a Hall element and outputting only a voltage signal.

The present invention also provides a method of driving a Hall element, which receives analog voltage signals output from respective terminals of a Hall element by alternately inputting them to a delta-sigma converter (? ADC) to remove an offset voltage signal and a noise signal, A sensor device is provided.

A hall sensor device according to an embodiment of the present invention includes a pair of first and third terminals facing each other, and a pair of second and fourth terminals facing each other include a plurality A Hall element for detecting the magnetic field as a voltage signal in accordance with the detection direction of the Hall element; And first to fourth switches respectively connected to the first to fourth terminals, wherein the first voltage signal and the third voltage signal respectively detected at the first terminal and the third terminal, A switch circuit for selectively switching between a second voltage signal and a fourth voltage signal respectively detected by the first voltage signal and the second voltage signal; A first switching module and a second switching module connected in parallel to a first common output terminal of the first switch and the second switch and a third switching module connected in parallel to a second common output terminal of the third switch and the fourth switch, And a fourth switching module for selectively switching the first output signal output from the first common output terminal and the second output signal output from the second common output terminal and outputting the digital output signal as digital data through delta sigma modulation, A conversion unit; And a switching control unit for controlling switching of the first to fourth switches of the switch circuit unit and the first to fourth switching modules of the delta sigma conversion unit.

In the present invention, the output terminals of the first switch and the second switch are common to the first common output terminal, and the output terminals of the third and fourth switches are common to the second common output terminal do.

In the present invention, the switching control unit outputs the same first clock signal to the first switch and the third switch, and outputs the same second clock signal to the second switch and the fourth switch.

In the present invention, the first clock signal and the second clock signal have the same frequency and have opposite phases to each other.

According to another aspect of the present invention, there is provided a Hall sensor device including a pair of first and third terminals facing each other, and a pair of second and fourth terminals facing each other, A Hall element for detecting a magnetic field as a voltage signal in accordance with a plurality of detection directions set; And first to fourth switching modules respectively connected to the first to fourth terminals, wherein the first voltage signal and the third voltage signal respectively detected at the first terminal and the third terminal, A delta sigma converter for selectively switching the second voltage signal and the fourth voltage signal detected by the delta sigma conversion unit and outputting the digital data through delta sigma modulation; And a switching control unit for controlling switching of the first to fourth switching modules of the delta sigma conversion unit.

In the present invention, the first to fourth switching modules each have first and second switching elements connected in series, and a first capacitor is connected in series between the first and second switching elements.

In the present invention, the switching controller outputs the same third clock signal to each of the two switch elements included respectively in the first and fourth switching modules, and the second switching module and the third switching module And outputs the same fourth clock signal to each of the two switch elements.

In the present invention, the third clock signal and the fourth clock signal have the same frequency and have opposite phases to each other.

In the present invention, the outputs of the first and second switching modules are common to the third common output terminal, and the output terminals of the third and fourth switching modules are common to each other. 4 common output stage.

In the present invention, the delta sigma converter includes an amplifier for amplifying the output signal of the third common output terminal and the output signal of the fourth common output terminal.

In the present invention, the delta sigma conversion unit may include: a fifth switching module for switching the output signal of the third common output terminal between the third common output terminal and the output terminal of the amplification unit; And a sixth switching module for switching an output signal of the fourth common output terminal between the fourth common output terminal and the output terminal of the amplification section.

The fifth switching module may include a third switch element and a fourth switch element connected in series between the third common output terminal and one output terminal of the amplification section, and a third switch element and a fourth switch element serially connected between the third and fourth switch elements, 2 capacitor, a fifth switch element having one end connected to the fourth common output terminal and the other end connected to the neutral point of the third switch element and the second capacitor, and a fifth switch element having one end connected to the neutral point of the second capacitor and the fourth switch element And a sixth switching element connected at the other end to the other output terminal of the amplifying part, wherein the sixth switching module includes a seventh switching element and an eighth switch connected in series between the fourth common output terminal and the other output terminal of the amplifying part, A third capacitor connected in series between the seventh and eighth switch elements, one end connected to the third common output terminal, and the other end connected to the seventh switch element and the third capacitor, And a tenth switch element having one end connected to the neutral point of the third capacitor and the eighth switch element and the other end connected to one output terminal of the amplification section.

In the present invention, the switching control unit outputs a third click signal to the fifth switch element and the sixth switch element, and the ninth switch element and the tenth switch element, and the third switch element and the fourth switch element, And outputs a fourth clock signal to the seventh switch element and the eighth switch element.

According to the present invention, since the offset voltage signal is relatively removed from the output signal of the Hall element, the detection sensitivity of the Hall sensor device is improved.

In addition, according to the present invention, the structure is simple and the frequency required for implementation can be minimized compared with the prior art, which is excellent in both size and power consumption.

1 is a diagram illustrating a configuration of a Hall element according to an embodiment of the present invention.
2 is a configuration diagram of a Hall sensor device according to an embodiment of the present invention.
3 is a diagram illustrating an example of a clock signal of the switch circuit according to an exemplary embodiment of the present invention.
4 is an exemplary diagram illustrating a clock signal of a delta sigma conversion unit according to an embodiment of the present invention.
5 is a configuration diagram of a Hall sensor device according to another embodiment of the present invention.
6 and 7 are diagrams for explaining a signal flow according to a clock signal in the delta sigma conversion unit according to the embodiment of the present invention.
8 is a time chart showing the sampling and voltage output according to the clock signal in the delta sigma converter according to the embodiment of the present invention.
9 is a signal waveform diagram according to frequency modulation of a voltage signal in the Hall sensor device according to the embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. It should be noted that, in adding reference numerals to the constituent elements of the drawings, the same constituent elements are denoted by the same reference numerals whenever possible, even if they are shown in different drawings. In the following description of the embodiments of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the difference that the embodiments of the present invention are not conclusive.

In describing the components of the embodiment of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the constituent elements from other constituent elements, and the terms do not limit the nature, order or order of the constituent elements. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; may be "connected," "coupled," or "connected. &Quot;

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating an example of modeling an algebra according to an embodiment of the present invention; FIG.

Referring to FIG. 1, a Hall element 110 according to the present invention includes four resistors R1, R2, R3, and R4 connected in the form of a bridge, and each of the resistors R1, R2, R3, R4 may be modeled so that four terminals 111, 112, 113, 114 are formed at respective neutral points. In this case, as shown in the figure, the Hall element 110 includes first to fourth terminals 111 to 114, and detects a magnetic field in accordance with a plurality of preset detection directions through these terminals, And outputs the voltage signal corresponding to the magnetic field detected by the magnetic field detection unit.

The driving power is supplied to a pair of terminals facing each other among the four terminals 111 to 114, and a detection voltage is output to the other pair of terminals facing each other. The power supply and the output of the detection voltage are alternately repeated. For example, the driving power is supplied to the first and third terminals 111 and 113, and the second and fourth terminals 112 and 114 output the detection voltage. Then, driving power is supplied to the second and fourth terminals 112 and 114 at a predetermined time interval according to the detection direction, and the detection voltage is outputted from the first and third terminals 111 and 113. This process is continuously repeated in the magnetic field detection process in the Hall element 110.

At this time, the output voltage is determined by the difference of the voltage signals output from the two opposing terminals. For example, the first terminal 111 is V _{out +} voltage signal is output to the third terminal 113 is V _{out -} the output voltage V _out in the case where the voltage signal is output Hall element 110 is V _{out +} - V _{out -} . At this time, the output voltage V _out of the Hall element 110 is the sum of the Hall voltage V _hall and the offset voltage V _offset .

FIG. 2 is a configuration diagram of a Hall sensor device according to an embodiment of the present invention, FIG. 3 is an exemplary view of a clock signal of a switch circuit according to an embodiment of the present invention, and FIG. Fig. 4 is a diagram illustrating a clock signal of a delta-sigma conversion unit according to an embodiment of the present invention;

2, the Hall sensor device 100 according to the present invention includes a Hall element 110, a switch circuit 120, a delta sigma converter (ADC) 130, and a switching controller 140 .

The Hall element 110 has a pair of first and third terminals facing each other as described above, and a pair of second and fourth terminals facing each other include a plurality of detections And detects the magnetic field as a voltage signal according to the direction.

The switch circuit unit 120 includes first to fourth switches 121, 122, 123, and 124 connected to the first to fourth terminals 111, 112, 113, and 114 of the Hall element 110, respectively. The output terminals of the first switch 121 and the second switch 122 are common to form the first common output terminal 125 and the output terminals of the third switch 123 and the fourth switch 124 are common Thereby forming a second common output terminal 126.

The first through fourth switches 121, 122, 123, and 124 configured as described above are respectively connected to the first voltage signal S1 and the third voltage signal S3 detected at the first terminal 111 and the third terminal 113, 112 and the fourth terminal 114, respectively, of the second voltage signal S2 and the fourth voltage signal S4, respectively. Specifically, the first switch 121 switches the first voltage signal S1 output from the first terminal 111 and the second switch 122 switches the second voltage signal S1 output from the second terminal 112, The third switch 123 switches the third voltage signal S3 outputted from the third terminal 113 and the fourth switch 124 switches the second voltage signal S2 outputted from the fourth terminal 114 And switches the fourth voltage signal S4.

)를 출력하고 제2스위치(122) 및 제4스위치(124)로 동일한 제2클럭신호(

)를 출력한다. Here, in this embodiment, the first switch 121 and the third switch 123 are interlocked and switched, and the second switch 122 and the fourth switch 124 are interlocked and switched. For this switching, the switching controller 140 controls the first switch 121 and the third switch 123 to output the same first clock signal

) To the second switch 122 and the fourth switch 124 to the same second clock signal (

).

)와 제2클럭신호(

)는 도 3에 도시된 바와 같이 동일한 주파수를 가지며 서로 반대 위상을 갖는다. 도 3을 참조하면 제1클럭신호(

)가 제1스위치(121)와 제3스위치(123)로 출력되는 동안에는 제2클럭신호(

)가 제2스위치(122)와 제4스위치(124)로 출력된다. 반대로 제2클럭신호(

)가 제2스위치(122)와 제4스위치(124)로 출력되는 동안에는 제1클럭신호(

)가 제1스위치(121)와 제3스위치(123)로 출력된다.Here, the first clock signal (

And a second clock signal < RTI ID = 0.0 >

Have the same frequency as shown in Fig. 3 and have opposite phases to each other. Referring to FIG. 3, a first clock signal (

Is output to the first switch 121 and the third switch 123, the second clock signal (

Is output to the second switch 122 and the fourth switch 124. [ Conversely, the second clock signal

Is output to the second switch 122 and the fourth switch 124, the first clock signal (

Is output to the first switch 121 and the third switch 123. [

As described above, the first switch 121 and the third switch 123 are interlocked and switched, and the second switch 122 and the fourth switch 124 are interlocked and switched. A first voltage signal S1 and a third voltage signal S3 are output from the first common output terminal 125 and the second common output terminal 126 in a specific clock signal, The second voltage signal S2 and the fourth voltage signal S4 are output.

As described above, in the Hall sensor device 100 according to the present invention, the switch circuit 120 sequentially samples the voltage signal input from the Hall element 110 continuously in accordance with a clock signal of a predetermined frequency. Thus, the number of voltage signals sampled according to the frequency of the clock signal can be adjusted.

The delta sigma conversion unit 130 includes a first switching module 131 and a second switching module 132 connected in parallel to each other at a first common output terminal 125 of the first switch 121 and the second switch 122, And a third switching module 133 and a fourth switching module 134 connected in parallel to each other at a second common output terminal 125 of the third switch 123 and the fourth switch 124. The input and output terminals of the first switching module 131 and the second switching module 132 are common to each other and the input and output terminals of the third and fourth switching modules 133 and 134 are common do. The delta-sigma conversion unit 130 selectively switches the first output signal output from the first common output terminal 125 and the second output signal output from the second common output terminal 126 and outputs the delta-sigma sigma- And outputs it as data. Here, the first output signal is a voltage signal of either the first voltage signal S1 or the second voltage signal S2, and the second output signal is the third voltage signal S3 or the fourth voltage signal S4 The voltage signal becomes a voltage signal.

Specifically, the first to fourth switching modules 131, 132, 133, and 134 configured as described above selectively output the first output signal output from the first common output terminal 125 and the second output signal output from the second common output terminal 126 Lt; / RTI > That is, the first switching module 131 and the second switching module 132 switch the first output signal, and the third switching module 133 and the fourth switching module 134 switch the second output signal.

) 및 제4클럭신호(

)를 선택적으로 반복해서 출력한다.In this embodiment, the first switching module 131 and the fourth switching module 134 are interlocked and switched, and the second switching module 132 and the third switching module 133 are interlocked and switched. For this switching, the switching controller 140 controls the first to fourth switching modules 131 to 134 to output the third clock signal

And the fourth clock signal (

) To be output repeatedly.

)와 제4클럭신호(

)는 도 4에 도시된 바와 같이 동일한 주파수를 가지며 서로 반대 위상을 갖는다. 도 4를 참조하면 제3클럭신호(

)가 제1스위칭모듈(131)과 제4스위칭모듈(134)로 출력되는 동안에는 제4클럭신호(

)가 제2스위칭모듈(132)와 제3스위칭모듈(133)로 출력되고, 이와 반대로 제4클럭신호(

)가 제1스위칭모듈(131)과 제4스위칭모듈(134)로 출력되는 동안에는 제3클럭신호(

)가 제2스위칭모듈(132)와 제3스위칭모듈(133)로 출력된다.Specifically, the third clock signal (

And a fourth clock signal (

Have the same frequency as shown in Fig. 4 and have opposite phases to each other. Referring to FIG. 4, the third clock signal (

Is output to the first switching module 131 and the fourth switching module 134, the fourth clock signal (

Is output to the second switching module 132 and the third switching module 133, and conversely, the fourth clock signal

Is output to the first switching module 131 and the fourth switching module 134, the third clock signal (

Is output to the second switching module 132 and the third switching module 133.

As described above, the first switching module 131 and the fourth switching module 134 are interlocked and switched, the second switching module 132 and the third switching module 133 are interlocked and switched, and the two pairs of switching modules The third common output 135 of the first switching module 131 and the second switching module 132 and the third switching module 133 and the fourth switching module 134 of the first switching module 131 and the second switching module 132, A fourth output terminal 136 of the second differential amplifier 130 receives a first output signal of one of the first voltage signal S1 or the second voltage signal S2 and a third output signal of the third voltage signal S3 or the fourth voltage signal S2, (S4), and a voltage signal different from the previously output voltage signal is output from the next clock signal, respectively.

At this time, in the hall sensor device 100 according to the present invention, the delta sigma converter 130 sequentially and secondarily samples the voltage signal according to a clock signal of a predetermined frequency. Thus, the number of voltage signals sampled according to the frequency of the clock signal can be adjusted. Here, the frequencies of the first and second clock signals and the third and fourth clock signals are adjustable. Preferably, the first to fourth clock signals may have the same frequency, but may vary depending on the number of voltage signals to be sampled.

In the embodiment of the present invention, the first to fourth switching modules 131 to 134 each have two switch elements, that is, first and second switch elements 137 and 138 connected in series, And a capacitor 139 is connected in series between the two switch elements 137 and 138, respectively. Each of the capacitors 139 stores (charges) the detected voltage or outputs (discharges) the stored voltage in accordance with the switching of the first and second switch elements 137 and 138. Here, in the configuration in which two first and second switch elements 137 and 138 and one capacitor 139 are connected in series to one switching module as described above, each of the first and second switch elements 137 and 138 has It is preferable that clock signals of opposite phases of the same frequency are applied respectively. This is to apply a clock signal of opposite phase to the two switch elements 137 and 138 so that charging and discharging in the capacitor 139 alternately occur. This will be described in detail below.

The switching controller 140 controls the first to fourth switches 121 to 124 of the switch circuit 120 and the first to fourth switching modules 131 to 134 of the delta sigma converter 130, And controls the switching of the two switching elements 137 and 138 included in the switching elements 131 to 134, respectively. For this switching control, the switching controller 140 outputs the first to fourth clock signals to corresponding first to fourth switches 121 and two switch elements 137 and 138, respectively.

5 is a configuration diagram of a Hall sensor device according to another embodiment of the present invention.

=

인 경우에 가능하다. 여기서, 도 5에 도시된 홀소자(110), 델타 시그마 변환부(130) 및 스위칭제어부(140)의 구성은 도 1에 도시된 구성과 비교할 때 기본적으로 동일한 동작을 수행한다. 다만, 도 5에서는 홀소자(110)와 델타시그마 변환부(130)의 직접 결합에 따라 결합되는 구성연결과 델타시그마 변환부(130)의 제1 내지 제4 스위칭모듈(131~134)의 스위칭동작에서 일부 차이가 있다. 이하에서는 차이가 있는 부분을 중심으로 구체적으로 설명한다.5, the Hall sensor device according to another embodiment of the present invention is different from the Hall sensor device according to the embodiment shown in FIG. 1 in that the switch circuit part 120 is omitted and the Hall device 110 and the delta sigma And the conversion unit 130 are directly coupled. In this case, the direct coupling between the Hall element 110 and the delta-sigma converter 130 is performed when the first and second clock signals and the third and fourth clock signals have the same frequency,

=

. Here, the configuration of the Hall element 110, the delta sigma conversion unit 130, and the switching control unit 140 shown in FIG. 5 basically performs the same operation as compared with the configuration shown in FIG. 5, the configuration of the Hall element 110 and the delta sigma conversion unit 130 are combined according to the direct coupling and the switching of the first to fourth switching modules 131 to 134 of the delta sigma conversion unit 130 is performed. There are some differences in behavior. Hereinafter, the description will be made mainly with respect to the differences.

The first through fourth switching modules 131, 132, 133 and 134 of the delta sigma conversion unit 130 are connected to the first through fourth terminals 111, 112, 113 and 114 of the Hall element 110, respectively. The first to fourth switching modules 131 to 132 are connected to the first to fourth voltage signals S1 to S4 detected by the first terminal 111 to the fourth terminal 114 of the Hall element 110, And outputs it as digital data through delta sigma modulation.

More specifically, the first switching module 131 switches the first voltage signal S1 output from the first terminal 111, and the second switching module 132 switches the first voltage signal S1 output from the second terminal 112, 2 voltage signal S2 while the third switching module 133 switches the fourth voltage signal S4 output from the fourth terminal 114 and the fourth switching module 134 switches the fourth voltage signal S4 output from the third terminal And the third voltage signal S3 output from the second switch 113 is switched.

) 및 제4클럭신호(

)를 선택적으로 반복해서 출력한다. In this embodiment, the first switching module 131 and the third switching module 133 are interlocked and switched, and the second switching module 132 and the fourth switching module 134 are interlocked and switched. For this switching, the switching controller 140 controls the first to fourth switching modules 131 to 134 to output the third clock signal

And the fourth clock signal (

) To be output repeatedly.

)와 제4클럭신호(

)는 도 4에 도시된 바와 같이 동일한 주파수를 가지며 서로 반대 위상을 갖는다. 도 4를 참조하면 제3클럭신호(

)가 제1스위칭모듈(131)와 제4스위칭모듈(134)로 출력되는 동안에는 제4클럭신호(

)가 제2스위칭모듈(132)와 제3스위칭모듈(133)로 출력된다. 이와 반대로 제4클럭신호(

)가 제2스위칭모듈(132)와 제3스위칭모듈(133)로 출력되는 동안에는 제3클럭신호(

)가 제1스위칭모듈(131)와 제4스위칭모듈(134)로 출력된다.Specifically, the third clock signal (

And a fourth clock signal (

Have the same frequency as shown in Fig. 4 and have opposite phases to each other. Referring to FIG. 4, the third clock signal (

Is output to the first switching module 131 and the fourth switching module 134, the fourth clock signal (

Is output to the second switching module 132 and the third switching module 133. In contrast, the fourth clock signal (

Is output to the second switching module 132 and the third switching module 133, the third clock signal

Are output to the first switching module 131 and the fourth switching module 134. [

As described above, the first switching module 131 and the fourth switching module 134 are interlocked and switched, and the second switching module 132 and the third switching module 133 are interlocked and switched. The first voltage signal S1 and the third voltage signal S3 are output to the third common output terminal 135 and the fourth common output terminal 136 in a specific clock signal, And the second voltage signal S2 and the fourth voltage signal S4 are output at the next clock signal.

As described above, in the Hall sensor device 100 according to another embodiment of the present invention, the delta sigma converter 130 continuously samples the voltage signal input from the Hall element 110 according to a clock signal of a preset frequency . Thus, the number of voltage signals sampled according to the frequency of the clock signal can be adjusted.

For this, the switching controller 140 controls the switching of the first to fourth switching modules 131 to 134 of the delta sigma converter 130.

As described above, in the switching modules 131 to 134 of the delta sigma conversion unit 130 shown in FIGS. 1 and 5, two switch devices 137 and 138 and a capacitor 139 are connected in series. These two switch elements 137 and 138 are connected in series to the two sides of the capacitor 139 via the capacitor 139, respectively. At this time, clock signals having opposite phases of the same frequency are applied to the two switch elements 137 and 138 from the switching controller 140, respectively. Will be described in detail with reference to Figs. 6 and 7. Fig.

6 and 7 are diagrams for explaining a signal flow in a delta sigma converter by a clock signal according to an embodiment of the present invention, FIG. 6 shows a flow of a voltage signal in a first phase , And Fig. 7 shows the flow of the voltage signal in the second phase.

)가 ON이고 제4클럭신호(

)가 OFF인 일례가 도시된다. 이 경우 제1스위칭모듈(131)의 전단 스위치소자(137a)는 턴온되고 후단 스위치소자(138a)는 턴오프되어 전압신호는 제1스위칭모듈(131)의 출력단으로 출력되지 않고 커패시터(139a)에 충전되며, 제2스위칭모듈(132)의 전단 스위치소자(137b)는 턴오프되고 후단 스위치소자(137b)는 턴온되어 커패시터(139b)에 충전된 전압이 제2스위칭모듈(132)의 출력단으로 출력된다. 이와 동일하게, 제4스위칭모듈(134)의 커패시터(139d)에 충전되고 제3스위칭모듈(133)의 커패시터(139c)에 충전된 전압이 제3스위칭모듈(133)의 출력단으로 출력된다. 이와 반대로, 도 7에서는 제4클럭신호(

)가 ON이고 제3클럭신호(

)가 OFF인 일례가 도시되며, 이러한 경우에는 도 6a와 반대로 제1스위칭모듈(131) 및 제4스위칭모듈(134)의 각 출력단으로 전압이 출력된다.Referring to FIG. 6, in the first phase, the third clock signal (

) Is ON and the fourth clock signal (

) Is OFF is shown. In this case, the front-stage switching element 137a of the first switching module 131 is turned on and the rear-stage switching element 138a is turned off so that the voltage signal is not outputted to the output terminal of the first switching module 131, The switch 137b of the second switching module 132 is turned off and the switch 137b of the second switch module 137b is turned on so that the voltage charged in the capacitor 139b is output to the output terminal of the second switching module 132, do. The voltage charged in the capacitor 139d of the fourth switching module 134 and charged in the capacitor 139c of the third switching module 133 is outputted to the output terminal of the third switching module 133. [ In contrast, in FIG. 7, the fourth clock signal (

) Is ON and the third clock signal (

In this case, a voltage is output to each output terminal of the first switching module 131 and the fourth switching module 134, as opposed to FIG. 6A.

In the delta sigma conversion unit 130, the signals sampled and output from the first through fourth switching modules 131 through 134 are different depending on whether the third clock signal and the fourth clock signal are turned on or off.

8 is a time chart showing sampling and voltage output processes in the delta sigma converter according to the third and fourth clock signals according to the embodiment of the present invention.

Referring to FIG. 8, when the third clock signal is ON and the fourth clock signal is OFF in the initial T1 period, the capacitors of the first and third switching modules 131 and 134 are charged to 1 (Sample 1). Thereafter, when the third clock signal is turned OFF and the fourth clock signal is turned ON in the T2 period, the voltages charged in the capacitors of the first switching module 131 and the fourth switching module 134 are outputted (output 1), the capacitors of the second switching module 132 and the third switching module 133 are charged with a voltage to perform a second sampling (sample 2). Thus, the sampling and the voltage output are repeated by repeating ON and OFF of the third clock signal and the fourth clock signal. At this time, by changing the magnitude of the clock frequency of the third clock signal and the fourth clock signal, sampling and voltage output times can be adjusted. In this case, the third clock signal may be OFF and the fourth clock signal may be ON in the initial T1 interval. In this case, sampling and voltage output may be different depending on the order of the respective switching modules. Occurs.

Here, FIGS. 8A and 8B explain which clock signal the sampling and the voltage output are performed. 8A shows a case where the first switching module 131 and the fourth switching module 134 sample a signal when the third clock signal is ON and the signals are sampled by the second switching module 132 and the third switching module 133 Voltage output. 8B shows a case where a signal is sampled by the second and third switching modules 132 and 133 and the first and third switching modules 131 and 134 when the fourth clock signal is ON. Is an example of performing the voltage output at the output terminal.

In the present invention, the delta sigma conversion unit 130 includes an amplification unit 1310 for amplifying the output signal of the third common output stage 135 and the output signal of the fourth common output stage 136. The delta sigma conversion unit 130 of the present invention includes a third common output terminal 135 between the third common output terminal 135 and the fourth common output terminal 136 and the two output terminals of the amplification unit 1310, And a fourth common output terminal 136. The fifth switching module 150 and the sixth switching module 160 switch the output signals output from the fourth common output terminal 136 and the fourth common output terminal 136, respectively.

The fifth switching module 150 has a third switch element 151 and a fourth switch element 152 connected in series between the third common output terminal 135 and one output terminal of the amplification part 1310, A capacitor 153 is connected in series between the elements 151 and 152. The fifth switching module 150 includes a fifth switch element 154 having one end connected to the fourth common output terminal 136 and the other end connected to the neutral point of the third switch element 151 and the capacitor 153, And a sixth switch element 155 having one end connected to the neutral point of the capacitor 153 and the fourth switch element 152 and the other end connected to the other output terminal of the amplifier 1310.

The seventh switching device 160 and the eighth switching device 162 are connected in series between the fourth common output terminal 136 and the other output terminal of the amplifying part 1310, A capacitor 163 is connected in series between the elements 161 and 162. The sixth switching module 160 includes a ninth switching device 164 having one end connected to the third common output terminal 135 and the other end connected to the neutral point of the seventh switching device 161 and the capacitor 163, And a tenth switching element 165 having one end connected to the neutral point of the capacitor 163 and the eighth switching element 162 and the other end connected to one output terminal of the amplifying part 1310.

)를 출력하고, 제3스위치소자(151)와 제4스위치소자(152), 그리고 제7스위치소자(161)와 제8스위치소자(162)에는 제4클럭신호(

)를 출력한다. 이로써 상기한 제3공통출력단(135) 및 제4공통출력단(136)에서 출력되는 출력신호는 제3 내지 제10 스위치소자의 스위칭에 의해 샘플링 및 전압출력이 이루어지게 된다. 이러한 샘플링 및 전압출력은 제3클럭신호 및 제4클럭신호의 샘플링 주파수에 의해 결정된다.The switching controller 140 controls the fifth switch element 154 and the sixth switch element 155 and the ninth switch element 164 and the tenth switch element 165 to generate a third click signal

The third switch element 151 and the fourth switch element 152 and the seventh switch element 161 and the eighth switch element 162 output the fourth clock signal

). As a result, the output signals output from the third common output terminal 135 and the fourth common output terminal 136 are sampled and voltage output by the switching of the third to tenth switch elements. This sampling and voltage output is determined by the sampling frequency of the third clock signal and the fourth clock signal.

As shown in FIG. 9, in the Hall sensor device 100 of the present invention configured as described above, the voltage signal, which is a low frequency signal among the voltage signal and the offset voltage signal included in the output signal output from the hall sensor device 100, Frequency signal so that the Hall sensor device 100 can operate at a high frequency and a delta-sigma converter (?? ADC) is applied in the form of a high-pass filter to eliminate an offset voltage signal as a relatively low frequency signal So that only the voltage signal is output. In addition, since the present invention adopts a delta sigma converter (? ADC), it modulates a high frequency voltage signal as shown in FIG. 9, so that a relatively low frequency noise signal can be separated. Through this process, the detection sensitivity and the detection accuracy of the hall sensor device 100 according to the present invention are improved.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. That is, within the scope of the present invention, all of the components may be selectively coupled to one or more of them. Furthermore, the terms "comprises", "comprising", or "having" described above mean that a component can be implanted unless otherwise specifically stated, But should be construed as including other elements. All terms, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. Commonly used terms, such as predefined terms, should be interpreted to be consistent with the contextual meanings of the related art, and are not to be construed as ideal or overly formal, unless expressly defined to the contrary.

The foregoing description is merely illustrative of the technical idea of the present invention, and various changes and modifications may be made by those skilled in the art without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

110: Hall elements 111, 112, 113, 114: First to fourth terminals
120: Switch circuit parts 121, 122, 123, and 124: First to fourth switches
130: delta sigma conversion unit 131, 132, 133, 134: first to fourth switching modules
140: switching control unit 1310:

Claims (13)

A pair of first and third terminals facing each other and a pair of second and fourth terminals facing each other include terminals for detecting a magnetic field as a voltage signal in accordance with a plurality of preset detection directions, device;
And first to fourth switches respectively connected to the first to fourth terminals, wherein the first voltage signal and the third voltage signal respectively detected at the first terminal and the third terminal, A switch circuit for selectively switching between a second voltage signal and a fourth voltage signal respectively detected by the first voltage signal and the second voltage signal;
A first switching module and a second switching module connected in parallel to a first common output terminal of the first switch and the second switch and a third switching module connected in parallel to a second common output terminal of the third switch and the fourth switch, And a fourth switching module for selectively switching the first output signal output from the first common output terminal and the second output signal output from the second common output terminal and outputting the digital output signal as digital data through delta sigma modulation, A conversion unit; And
And a switching control section for controlling switching of the first to fourth switches of the switch circuit section and the first to fourth switching modules of the delta sigma conversion section. The method according to claim 1,
Wherein the output terminal of the first switch and the output terminal of the second switch are set to a first common output terminal and the output terminals of the third switch and the fourth switch are common to be set to a second common output terminal, . 3. The method of claim 2,
The switching control unit alternately and repeatedly outputs the first clock signal and the second clock signal to the first switch to the fourth switch, while the first control unit outputs the first clock signal to the first switch and the third switch, And outputs a first clock signal to the second switch and the fourth switch while outputting a second clock signal to the first switch and the third switch, . The method of claim 3,
Wherein the first clock signal and the second clock signal have the same frequency and have opposite phases to each other. A pair of first and third terminals facing each other and a pair of second and fourth terminals facing each other include terminals for detecting a magnetic field as a voltage signal in accordance with a plurality of preset detection directions, device;
And first to fourth switching modules respectively connected to the first to fourth terminals, wherein the first voltage signal and the third voltage signal respectively detected at the first terminal and the third terminal, A delta sigma converter for selectively switching the second voltage signal and the fourth voltage signal detected by the delta sigma conversion unit and outputting the digital data through delta sigma modulation; And
And a switching control unit for controlling switching of the first to fourth switching modules of the delta sigma conversion unit. 6. The method according to claim 1 or 5,
Wherein the first to fourth switching modules each have first and second switch elements connected in series and a first capacitor is connected in series between the first and second switch elements. The method according to claim 6,
Wherein the switching controller alternately and repeatedly outputs the third clock signal and the fourth clock signal to the first switching module to the fourth switching module, And outputs a fourth clock signal to each of the two switch elements included in the second and third switching modules while outputting the third clock signal to the first and fourth switching modules, And outputs a third clock signal to each of the two switch elements included in the second switching module and the third switching module while outputting the fourth clock signal to the two respective switch elements included. 8. The method of claim 7,
Wherein the third clock signal and the fourth clock signal have the same frequency and have opposite phases to each other. 3. The method according to claim 1 or 2,
The delta sigma converter outputs the outputs of the first and second switching modules to a third common output terminal and the output terminals of the third and fourth switching modules are common to the fourth common output terminal The Hall sensor device being set. 10. The method of claim 9,
Wherein the delta sigma converter includes an amplifier for amplifying an output signal of the third common output terminal and an output signal of the fourth common output terminal. 11. The apparatus of claim 10, wherein the delta-
A fifth switching module for switching the output signal of the third common output terminal between the third common output terminal and the output terminal of the amplifying part; And
And a sixth switching module for switching the output signal of the fourth common output terminal between the fourth common output terminal and the output terminal of the amplifying section. 12. The method of claim 11,
The fifth switching module includes a third switching device and a fourth switching device connected in series between the third common output terminal and one output terminal of the amplifying unit, a second capacitor connected in series between the third and fourth switching devices, A fifth switch element having one end connected to the fourth common output terminal and the other end connected to the neutral point of the third switch element and the second capacitor, and a fifth switch element having one end connected to the neutral point of the second capacitor and the fourth switch element, And a sixth switch element connected to the other output terminal of the amplifying part,
The sixth switching module includes a seventh switching element and an eighth switching element connected in series between the fourth common output terminal and the other output terminal of the amplifying part, a third capacitor connected in series between the seventh and eighth switching elements, A third capacitor having one end connected to the third common output terminal and the other end connected to the neutral point of the seventh switching element and the third capacitor; and a seventh switching element having one end connected to the neutral point of the third capacitor and the eighth switching element, And a tenth switching element connected to one output terminal of the amplifying part. 13. The method of claim 12,
Wherein the switching control section outputs a third click signal to the fifth switch element and the sixth switch element, and the third switch element and the fourth switch element to the ninth switch element and the tenth switch element, And outputs a fourth clock signal to the switch element and the eighth switch element.

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