KR20170106031A - Semiconductor device and fabrication method thereof - Google Patents

Abstract

Provided are a semiconductor device for adjusting threshold voltage of a plurality of transistors, and a manufacturing method thereof. The semiconductor device comprises: a substrate including a first area; a first dielectric film arranged on the substrate of the first area, and including a first porosity area and a second porosity area having a porosity different from that of the first porosity area; and a first gate stack arranged on the first dielectric film.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device,

The present invention relates to a semiconductor device and a method of manufacturing the same.

The semiconductor device may include transistors having different threshold voltages. Examples of transistors having different threshold voltages include a logic transistor and a combination of a static random access memory (SRAM) or a dynamic random access memory (DRAM) transistor.

Meanwhile, various methods for controlling the threshold voltage of the transistors included in the semiconductor device have been studied.

A problem to be solved by the present invention is to provide a semiconductor device in which the threshold voltages of a plurality of transistors are adjusted.

A problem to be solved by the present invention is to provide a semiconductor device whose threshold voltage is adjusted.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device manufacturing method capable of providing a semiconductor device in which threshold voltages of a plurality of transistors are adjusted.

The technical objects of the present invention are not limited to the technical matters mentioned above, and other technical subjects not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a substrate including a first region; a second region disposed on the substrate of the first region and having a first porosity region and a first porosity region, A first dielectric layer including a second porosity region having a different porosity and a first gate stack disposed on the first dielectric layer.

In some embodiments of the present invention, the second porosity region has a porosity higher than the first porosity region, the second porosity region is disposed adjacent the first gate stack, And may be spaced apart from the first gate stack.

In some embodiments of the present invention, the thickness of the second porosity region may be less than the thickness of the first porosity region.

In some embodiments of the present invention, the first porosity region and the second porosity region may be formed through oxygen vacancies.

In some embodiments of the present invention, the substrate further comprises a second region different from the first region, a second dielectric layer disposed on the substrate of the second region, an oxide layer disposed on the second dielectric layer, And a second gate stack disposed on the oxide layer.

In some embodiments of the present invention, the first gate stack comprises a sequentially stacked first work function tuning film, a first barrier film and a first metal film, and the second gate stack comprises a sequentially deposited second Wherein the first work function control film and the first dielectric film are in contact with each other, the second work function control film is in contact with the oxide layer, the first work function adjusting film is in contact with the second work function adjusting film, The control film may be thicker than the second work function control film.

In some embodiments of the present invention, the upper surface of the first work function adjusting film and the upper surface of the second work function adjusting film may be disposed on the same plane.

In some embodiments of the present invention, the oxide layer may comprise an oxide of a material that the second dielectric layer comprises.

In some embodiments of the present invention, the first and second gate stacks form first and second transistors, respectively, and the threshold voltages of the first and second transistors may be different from each other.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a substrate including a first region and a second region; a second region disposed on the substrate of the first region, A second dielectric layer disposed on the substrate of the second region and having a first porosity, a first dielectric layer disposed on the first dielectric layer, the second dielectric layer having a porosity greater than the first porosity region, And a second gate stack disposed on the second dielectric layer, wherein the first dielectric layer may be thicker than the second dielectric layer.

In some embodiments of the present invention, the second porosity region is disposed adjacent to the first gate stack, and the first porosity region may be spaced apart from the first gate stack.

In some embodiments of the present invention, the thickness of the second porosity region may be less than the thickness of the first porosity region.

And an oxide layer between the second dielectric layer and the second gate stack, wherein the oxide layer may include an oxide of a material included in the second dielectric layer. In some embodiments of the present invention, the first gate stack comprises a sequentially stacked first work function tuning film, a first barrier film and a first metal film, and the second gate stack comprises a sequentially deposited second Wherein the first work function control film and the first dielectric film are in contact with each other, the second work function control film is in contact with the oxide layer, the first work function adjusting film is in contact with the second work function adjusting film, The upper surface of the regulating film may be disposed on the same plane as the upper surface of the second work function regulating film.

In some embodiments of the present invention, the first work function control film may be thicker than the second work function control film.

According to an aspect of the present invention, there is provided a semiconductor device including a substrate including a first region and a second region, a first dielectric layer disposed on the substrate of the first region, A first gate stack disposed on the first dielectric layer and in contact with the first dielectric layer, an oxide layer disposed on the second dielectric layer and in contact with the second dielectric layer, A second gate stack disposed on the oxide layer and in contact with the oxide layer, the oxide layer comprising an oxide of a material that the second dielectric layer comprises. In some embodiments of the present invention, the first dielectric layer may be thicker than the second dielectric layer.

In some embodiments of the present invention, the first dielectric layer includes a first porosity region and a second porosity region having a porosity higher than the first porosity region, and the second porosity region comprises a first porosity region, And the first porosity region may be spaced apart from the first gate stack.

In some embodiments of the present invention, the thickness of the second porosity region may be less than the thickness of the first porosity region.

In some embodiments of the present invention, the first porosity region and the second porosity region may be formed through the pores of oxygen contained in the first dielectric layer.

According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising: forming a first dielectric layer on a substrate; forming a first conductive layer on the first dielectric layer; Annealing is performed to remove the first barrier layer and the first conductive layer to expose the first dielectric layer and to bake the first dielectric layer to form a first dielectric layer in the first dielectric layer, Forming a first porosity region and a second porosity region having a porosity higher than the first porosity region and forming a first gate stack on the first dielectric layer.

In some embodiments of the present invention, baking the first dielectric layer includes baking the first dielectric layer such that the second porosity region is formed in an area adjacent to the first gate stack of the first dielectric layer. can do.

In some embodiments of the present invention, baking the first dielectric layer may include baking the first dielectric layer such that the second porosity region has a thickness that is less than the first porosity region.

In some embodiments of the present invention, baking the first dielectric layer may include removing oxygen contained in the first dielectric layer to form the second porosity region.

According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising: forming a first dielectric layer on a substrate; forming a first conductive layer on the first dielectric layer; Annealing is performed to remove the first blocking film to expose the first conductive film and baking the first conductive film to form a first conductive film on the first conductive film and between the first conductive film and the first dielectric film, And removing the first conductive layer to expose the oxide layer and form a first gate stack on the oxide layer.

In some embodiments of the present invention, forming the oxide layer may include forming a portion of the first dielectric layer to oxidize the first dielectric layer.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming first and second dielectric layers on a substrate including a first region and a second region, Forming first and second conductive films on the first and second conductive films, annealing the first and second conductive films, respectively, after forming the first and second conductive films on the first and second conductive films, The first dielectric layer and the second conductive layer are removed, and the first dielectric layer is baked to remove the first dielectric layer and the second dielectric layer from the first porosity region and the first porosity region Forming a second porosity region having a high porosity and baking the second conductive film to form an oxide layer between the second conductive film and the second dielectric film and removing the second conductive film to expose the oxide layer , The first dielectric Forming a first gate stack on, and may include forming a second gate stack on said oxide layer.

In some embodiments of the present invention, baking the first dielectric layer and baking the second conductive layer may be performed through the same baking process.

In some embodiments of the present invention, baking the first dielectric layer includes baking the first dielectric layer such that the second porosity region is formed in an area adjacent to the first gate stack of the first dielectric layer. can do.

In some embodiments of the present invention, baking the first dielectric layer may include baking the first dielectric layer such that the second porosity region has a thickness that is less than the first porosity region.

In some embodiments of the present invention, baking the first dielectric layer may include removing oxygen contained in the first dielectric layer to form the second porosity region.

In some embodiments of the present invention, the first gate stack comprises a sequentially stacked first work function tuning film, a first barrier film and a first metal film, and the second gate stack comprises a sequentially deposited second Wherein the first work function control film and the first dielectric film are in contact with each other, the second work function control film is in contact with the oxide layer, the first work function adjusting film is in contact with the second work function adjusting film, The control film may be thicker than the second work function control film.

In some embodiments of the present invention, the upper surface of the first work function adjusting film and the upper surface of the second work function adjusting film may be disposed on the same plane.

In some embodiments of the present invention, the first and second gate stacks form first and second transistors, respectively, and the threshold voltages of the first and second transistors may be different from each other.

Other specific details of the invention are included in the detailed description and drawings.

FIGS. 1 to 13 are diagrams showing intermediate steps for explaining a method of manufacturing a semiconductor device according to some embodiments of the present invention.
14 to 16 are perspective and sectional views for explaining a semiconductor device according to some embodiments of the present invention.
17 to 20 are diagrams showing intermediate steps for explaining a method of manufacturing a semiconductor device according to some embodiments of the present invention.
21 to 23 are perspective and sectional views for explaining a semiconductor device according to some embodiments of the present invention.
24 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention.
FIGS. 25 to 41 are views of an intermediate step for explaining a method of manufacturing a semiconductor device according to some embodiments of the present invention.
42 to 44 are a perspective view and a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention.
45 is a block diagram of an electronic system including a semiconductor device manufactured in accordance with some embodiments of the present invention.
Figure 46 is an exemplary semiconductor system to which a semiconductor device fabricated in accordance with some embodiments of the present invention may be applied

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

One element is referred to as being "connected to " or" coupled to "another element, either directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

In the drawings relating to the semiconductor device according to some embodiments of the present invention, a pinned transistor (FinFET) including a channel region of a pin-shaped pattern shape is exemplarily shown, but the present invention is not limited thereto. The semiconductor device according to some embodiments of the present invention may include a tunneling FET, a transistor including a nanowire, a transistor including a nanosheet, or a three-dimensional (3D) transistor . Further, the semiconductor device according to some embodiments of the present invention may include a bipolar junction transistor, a lateral double diffusion transistor (LDMOS), and the like.

Next, a method of manufacturing a semiconductor device according to some embodiments of the present invention and a semiconductor device manufactured thereby will be described with reference to FIGS. 1 to 16. FIG.

FIGS. 1 to 13 are diagrams showing intermediate steps for explaining a method of manufacturing a semiconductor device according to some embodiments of the present invention. 1 to 3 are perspective views, and Figs. 4 to 13 are sectional views. 4 is a cross-sectional view taken along the line A-A in Fig. FIGS. 14 to 16 are a perspective view and a sectional view for explaining a semiconductor device according to some embodiments of the present invention, FIG. 15 is a sectional view taken along line A1-A1 of FIG. 14, Fig.

First, referring to FIG. 1, a first fin F1 is formed on a substrate 101, respectively. The first pin F1 may protrude in the third direction Z1. The first pin F1 may extend along the second direction Y1 which is the longitudinal direction and may have the long side of the second direction Y1 and the short side of the first direction X1. However, the present invention is not limited thereto. For example, the long side direction may be the first direction X1 and the short side direction may be the second direction Y1.

The first fin F1 may be part of the substrate 101 and may include an epitaxial layer grown from the substrate 101. [ For example, Si or SiGe.

The field insulating film 110 is formed on the substrate 101 so as to cover the side wall of the first fin F1. The field insulating film 110 may be formed of a material including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

Referring to FIG. 2, an upper portion of the field insulating film 110 is recessed to expose an upper portion of the first fin F1. The recess process may include an optional etch process.

On the other hand, a part of the first fin F1 protruding above the field insulating film 110 may be formed by an epitaxial process. For example, after the field insulating film 110 is formed, a part of the first fin F1 is formed by an epitaxial process in which the upper surface of the first fin F1 exposed by the field insulating film 110 is seeded, Can be formed.

Further, doping for threshold voltage adjustment can be performed on the exposed first fin F1. For example, the first fin F1 of the first region I may be doped with boron (B) as an impurity and doped with phosphorus (P) or arsenic (As).

Then, a first dummy gate structure 111 is formed on the first fin F1 to cross the first fin F1. 2, the first dummy gate structure 111 is shown as crossing the first fin F1 at a right angle, that is, in the first direction X1, but the present invention is not limited thereto, The first pin 111 may intersect the first pin F1 at an acute angle and / or an obtuse angle with the first direction X1.

The first dummy gate structure 111 may include a dummy gate insulating film 113 and a dummy gate electrode 115. The dummy gate insulating film 113 and the dummy gate electrode 115 may be sequentially stacked.

The dummy gate insulating film 113 may be formed in conformity with the upper surface and the upper surface of the sidewall of the exposed first fin F1 without being covered by the field insulating film 110. [ The dummy gate insulating film 113 may be disposed between the dummy gate electrode 115 and the field insulating film 110.

The dummy gate electrode 115 may be formed on the dummy gate insulating film 113.

For example, the dummy gate electrode 115 may include silicon oxide, and the dummy gate insulating film 113 may include polysilicon.

The dummy hard mask film 117 may be formed on the first dummy gate structure 111. The dummy hard mask film 117 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

Referring to FIGS. 3 and 4, spacers 121 are formed on both side walls of the first dummy gate structure 111. The spacer 121 can expose the upper surface of the hard mask film 117.

The spacer 121 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO _2), silicon nitride pellets (SiOCN) and at least one of a combination of the two.

Although the spacer 121 is shown as being a single membrane, it is for convenience of illustration only, and is not limited thereto. If the spacers 121 are a plurality of films, at least one of the films included in the spacers 121 may include a low dielectric constant material such as silicon oxynitride (SiOCN).

When the spacer 121 is a plurality of films, at least one of the films included in the spacer 121 may have an L-shaped or I-shaped shape.

In some cases, the spacer 121 may serve as a guide for forming a Self Aligned Contact. Thus, the spacer 121 may include a material having an etch selectivity to the first interlayer insulating film 130.

Then, the first dummy gate structure 111 is not covered, and the exposed first fin F1 is etched. The first fin F1 can be etched using the spacer 121 and the first dummy gate structure 111 as an etching mask.

Then, a first source / drain region 123 is formed in the etched portion of the first fin F1. The first source / drain region 123 can be formed in the first fin F1. The first source / drain region 123 may be an elevated source / drain region. 4, the upper surface of the first source / drain region 123 may be higher than the upper surface of the first fin F1.

The first source / drain region 123 of the first region I may comprise a tensile stress material. The first source / drain region 123 may be the same material as the substrate 101 or a tensile stress material. For example, when the substrate 101 is Si, the first source / drain region 123 may be Si or a material having a smaller lattice constant than Si (e.g., SiC, SiP).

Also, the first source / drain region 123 of the first region I may comprise a compressive stress material. For example, the compressive stress material may be a material having a larger lattice constant than Si, and may be, for example, SiGe. The first source / drain region 123 can be formed by epitaxial growth.

3, the first source / drain region 123 is a pentagon, but the present invention is not limited thereto. For example, the first source / drain region 123 may have a rectangular shape, a circular shape, or a hexagonal shape. Shape.

Referring to FIG. 5, a first interlayer insulating film 130 covering the first source / drain region 123 is formed. The first interlayer insulating film 130 may cover the side wall of the spacer 121 and expose the upper surface of the hard mask film 117. The first interlayer insulating film 130 may include, for example, silicon oxide.

Referring to FIG. 6, a first trench 135 exposing the top of the first fin F1 is formed. First, the hard mask film 117 is removed. The hard mask film 117 may be formed through a planarization process or the like, and if the planarization process is performed, the first interlayer insulating film 130 may also be partially etched.

Then, the first dummy gate structure 111 is removed. The dummy gate electrode 115 and the dummy gate insulating film 113 are removed to expose the first fin F1. The first trench 135 is formed in the place where the first dummy gate structure 111 was located. The sidewalls of the spacers 121 can be exposed by the first trenches 135.

Referring to FIG. 7, a first interface film 141 is formed in the first trench 135. The first interface film 141 may be formed along the upper surface of the first fin F1 and the upper portion of the sidewall.

The first interface film 141 may be formed by oxidizing the exposed first pin F1 in the first trench 135, but is not limited thereto. The first interface film 141 may be formed along the bottom surface of the first trench 135. The first interface film 141 may prevent a poor interface between the first fin F1 and the first dielectric layer 143a. The first interface film 141 may be formed of a low dielectric material layer having a dielectric constant k of 9 or less such as a silicon oxide film (k is about 4) or a silicon oxynitride film (k is about 4 - 8). Alternatively, the first interface film 141 may be made of a silicate or a combination of the above-exemplified membranes.

Then, a first dielectric layer 143a is formed in the first trench 135. Then, Specifically, the first dielectric layer 143a may be conformally formed along the sidewalls and the bottom surface of the first trench 135, and may include a field insulating layer 110, It can be formed into a foam. Also, the first dielectric layer 143a may be formed on the first interlayer insulating layer 130 as well.

The first dielectric layer 143a may include a dielectric material having a higher dielectric constant than the silicon oxide layer. For example, the first dielectric layer (143a) _{is, HfSiON, HfO 2, ZrO 2} , Ta 2 O 5, TiO 2, SrTiO 3 , or may comprise a material selected from the group consisting of such as (Ba, Sr) TiO ₃ have. The first dielectric layer 143a may have an appropriate thickness depending on the type of device to be formed.

Referring to FIG. 8, a first conductive layer 145 and a first blocking layer 147 are sequentially formed. A first conductive layer 145 is formed in the first trench 135. The first conductive layer 145 may be conformally formed along the sidewalls and the bottom surface of the first trench 135. Further, it may be formed along the upper surface and the upper surface of the side wall of the first fin F1. The first conductive layer 145 may include, but is not limited to, TiN.

Next, a first blocking layer 147 is formed on the first conductive layer 145. The first blocking layer 147 may fill the first trench 135 and may cover the first conductive layer 145 so that the first conductive layer 145 is not exposed to the outside. The first blocking layer 147 may include, for example, Si.

Annealing 150 is then performed. The first dielectric layer 143a contains oxygen atoms. The oxygen atoms are bonded to other materials (for example, Hf, Zr, Ta, Ti, etc.) in the first dielectric layer 143a, some of which may be broken. If the coupling is broken, a leak current or the like may be generated and the performance of the transistor may deteriorate. To prevent this problem, annealing 150 is performed to bond the oxygen atoms to the broken part of the bond. When the annealing 150 is performed, the oxygen atoms contained in the first conductive layer 145 are respectively provided to the first dielectric layer 143a.

On the other hand, if the first conductive layer 145 is exposed during the annealing 150, oxygen atoms outside the first conductive layer 145 may penetrate into the first conductive layer 145 The number of moving oxygen atoms increases. If oxygen atoms are supplied in excess of the number of oxygen atoms required by the first dielectric layer 143a, an excess of oxygen atoms may react with the first fin (F1) in the first trench 135. As a result, the thickness of the first interface film 141 becomes thick, and the performance of the transistor may deteriorate. Accordingly, the first blocking layer 147 may be formed on the first conductive layer 145 to shield the first conductive layer 145 from the outside during the annealing 150, so that the supply amount of oxygen atoms can be appropriately controlled.

The annealing 150 may be performed at a temperature of 500 ° C to 1500 ° C.

The thickness of the first conductive layer 145 may vary depending on the number of oxygen atoms to be supplied.

Referring to FIG. 9, the first blocking layer 147 and the first conductive layer 145 are sequentially removed. Accordingly, the first dielectric layer 143a can be exposed again.

Next, referring to FIG. 10, a baking step (H) may be performed. Accordingly, the first dielectric layer 143a may include a first porosity region HR and a second porosity region LR. The porosity of the second porosity region LR may be higher than that of the first porosity region HR. The porosity of the first porosity region HR and the second porosity region LR may be formed through oxygen vacancies formed by removing the oxygen contained in the first dielectric layer 143a.

That is, in this embodiment, oxygen contained in the material of the surface of the first dielectric layer 143a may be removed through heat applied during the baking step (H) to form oxygen vacancies, Such a region may have a relatively high porosity as compared with the region in contact with the spacer 121 and the first interface film 141 of the first dielectric layer 143a. Therefore, in the present invention, a region having a relatively high porosity is referred to as a second porosity region (LR), and a region having a relatively low porosity is referred to as a first porosity region (HR). Although the first porosity region HR and the second porosity region LR are shown as having a clear boundary, the technical idea of the present invention is not limited thereto. The porosity of the second porosity region LR can vary continuously. That is, the porosity of the second porosity region LR can be reduced as it moves from the upper surface of the first dielectric layer 143a to the first interface film 141 within the second porosity region LR.

The region adjacent to the first interface 141 or the first spacer 121 in the first dielectric layer 143a can have the same porosity before and after the baking process H as compared with the surface of the first dielectric layer 143a have. Therefore, in the present embodiment, a region having the same porosity before and after the baking step H in the first dielectric film 143a can be referred to as a first porosity region HR, and a porosity before and after the baking step (H) This changed region can be referred to as a second porosity region LR.

The thickness H1 of the second porosity region LR may be less than half of the thickness H1 of the first dielectric layer 143a. That is, the thickness H2 of the second porosity region LR may be thinner than the thickness H1-H2 of the first porosity region HR. However, the technical idea of the present invention is not limited thereto, and the thicknesses of the first and second porosity regions LR and HR may be variously changed according to the necessity of the invention.

 The process time and the process temperature of the baking process (H) may be determined in consideration of the thickness and the porosity of the desired second porosity region (LR).

In this embodiment, since the oxygen porosity in the second porosity region LR of the first dielectric film 143a changes before and after the baking step H, the threshold voltage of the semiconductor device can be adjusted.

Next, referring to FIG. 11, a first conductive layer 151a is formed on the first dielectric layer 143a. The first conductive film 151a may include TiN. The first conductive layer 151a may be conformally formed along the sidewalls and the bottom surface of the first trench 135. A first work function adjusting film 163a is formed on the first conductive film 151a. The first work function regulating film 163a may comprise, for example, TiAlC. The first work function regulating film 163a may be formed conformally along the side wall and the bottom surface of the first trench 135. [ A first barrier film 165a is formed on the first work function regulating film 163a. The first barrier layer 165a may be formed along the sidewalls and the bottom surface of the first trench 135. [ The first barrier film 165a may be formed conformally along the upper and upper surfaces of the sidewall of the first fin F1. The first barrier layer 165a may comprise, for example, TiN

A first metal film 167a is formed on the first barrier film 165a. The first metal film 167a may fill the remaining portion of the first trench 135. [ The first metal film 167a may include, for example, Al, W, and the like.

Referring to FIG. 12, a first gate stack 170 is formed. 11, when the planarization process is performed to expose the first interlayer insulating layer 130, the first interface layer 141, the first dielectric layer 143, the first conductive layer 151, A first gate stack 170 including a film 163, a first barrier film 165, and a first metal film 167 may be formed. The first dielectric layer 143, the first conductive layer 151, the first work function control layer 163, and the first barrier layer 165 may have a concave shape in the first trench 135.

Referring to FIG. 13, a first capping layer 180 is formed on the first gate stack 170, respectively. Specifically, the first capping layer 180 may be formed on the first gate stack 170 and cover the first trench 135. The first capping layer 180 may comprise a nitride (e.g., at least one of SiN, SiON, SiCON) or an oxide. The first capping layer 180 may block the first gate stack 170 from the outside to prevent a change in the performance of the first gate stack 170. For example, oxygen atoms may penetrate into the first gate stack 170, in which case the threshold voltage of the first gate stack 170 may be varied. Accordingly, the first capping layer 180 may be formed to keep the threshold voltage of the first gate stack 170 constant. The thickness of the first capping layer 180 may range from 5 to 500 Å.

Before forming the first capping layer 180, the first gate stack 170 may be partially removed for height adjustment of the first gate stack 170. The first dielectric film 143, the first conductive film 151, the first work function control film 163, the first barrier film 165, and the first metal film 167 in the first trench 135 Some can be removed. In this case, the sidewalls of the first capping layer 180 may be in contact with the sidewalls of the first spacers 121. In addition, the upper surface of the first capping layer 180 may be disposed on the same plane as the first interlayer insulating layer 130. The threshold voltage of the first gate stack 170 can be adjusted by adjusting the height of the first gate stack 170.

Next, referring to FIGS. 14 to 16, a second interlayer insulating film 132 is formed on the first interlayer insulating film 130. The second interlayer insulating film 132 may cover the first capping layer 180. The second interlayer insulating film 132 may include the same material as the first interlayer insulating film 130 and may include, for example, silicon oxide.

A first silicide film 191 is formed on the first source / drain region 123 and a first interlayer insulating film 130 and a second interlayer insulating film 132 are formed on the first source / The first contact 193 may be formed to form the semiconductor device according to the present embodiment. The first silicide layer 191 may reduce the surface resistance and the contact resistance of the first source / drain region 123 and may include, for example, Pt, Ni, Co, or the like. The first contact 193 may include, for example, W, Al Cu, or the like.

Next, with reference to FIGS. 17 to 23, a method of manufacturing a semiconductor device according to some embodiments of the present invention and a semiconductor device manufactured thereby will be described.

17 to 20 are diagrams showing intermediate steps for explaining a method of manufacturing a semiconductor device according to some embodiments of the present invention. 17 to 20 are sectional views. 21 to 23 are perspective and sectional views for explaining a semiconductor device according to some embodiments of the present invention. 21 is a perspective view for explaining the semiconductor device. Fig. 22 is a sectional view taken along line A-A in Fig. 21, and Fig. 23 is a sectional view taken along line C-C in Fig.

The semiconductor device according to this embodiment is substantially the same as the semiconductor device manufacturing method and the semiconductor device described with reference to Figs. 1 to 16, except that it includes an oxide layer instead of the conductive film. Accordingly, like reference numerals refer to like elements and repeated descriptions may be omitted.

The intermediate step of FIG. 17 may be the next step of the intermediate step of FIG. 8 in the previous embodiment. Referring to FIG. 17, after the annealing 150 is performed, the first blocking layer 147 is removed to expose the first conductive layer 145. The baking step (H) may be performed on the exposed first conductive film 145. [

When the baking step (H) is performed on the first conductive layer 145, the oxidized layer 144 may be formed between the first conductive layer 145 and the first dielectric layer 143a. Although the first conductive layer 145, the first dielectric layer 143a and the oxidant layer 144 are shown to have similar thicknesses, the present invention is not limited thereto. The thickness of each of the first conductive layer 145, the first dielectric layer 143a, and the oxidized layer 144 can be controlled differently.

At the baking step (H), the oxygen atoms contained in the first dielectric layer 143a can not escape to the outside due to the first conductive layer 145. Accordingly, an oxide layer 144 may be formed between the first conductive layer 145 and the first dielectric layer 143a. The oxide layer 144 may include a material in which the substance contained in the first dielectric layer 143a is oxidized. In addition, the oxide layer 144 may include a substance in which the substance contained in the first conductive film 145 is oxidized. However, the present invention is not limited thereto.

In this embodiment, since the oxide layer 144 is formed on the dielectric layer 143a, the threshold voltage of the transistor formed of the semiconductor device including the oxide layer 144 can be controlled.

Next, referring to FIG. 18, an oxide layer 144 is formed on the first dielectric layer 143a. And a first work function regulating film 163a is formed on the oxide layer 144. [ The first work function regulating film 163a may comprise, for example, TiAlC. The first work function regulating film 163a may be formed conformally along the side wall and the bottom surface of the first trench 135. [ A first barrier film 165a is formed on the first work function regulating film 163a. The first barrier layer 165a may be formed along the sidewalls and the bottom surface of the first trench 135. [ The first barrier film 165a may be formed conformally along the upper and upper surfaces of the sidewall of the first fin F1. The first barrier layer 165a may comprise, for example, TiN

A first metal film 167a is formed on the first barrier film 165a. The first metal film 167a may fill the remaining portion of the first trench 135. [ The first metal film 167a may include, for example, Al, W, and the like.

Referring to FIG. 19, a first gate stack 170 is formed. 18, the first interface film 141, the first dielectric layer 143, the oxide layer 144, the first work function control film 163 A first dielectric layer 143, an oxide layer 144, a first work function control layer (not shown), a second dielectric layer 145, The first barrier layer 163 and the first barrier layer 165 may have a concave shape in the first trench 135.

Referring to FIG. 20, a first capping layer 180 is formed on the first gate stack 170, respectively. Specifically, the first capping layer 180 may be formed on the first gate stack 170 and cover the first trench 135. The first capping layer 180 may comprise a nitride (e.g., at least one of SiN, SiON, SiCON) or an oxide. The first capping layer 180 may block the first gate stack 170 from the outside to prevent a change in the performance of the first gate stack 170.

Before forming the first capping layer 180, the first gate stack 170 may be partially removed for height adjustment of the first gate stack 170. Therefore, the first dielectric layer 143, the oxide layer 144, the first work function control film 163, the first barrier film 165, and the first metal film 167 can be partially removed. In this case, the sidewalls of the first capping layer 180 may be in contact with the sidewalls of the first spacers 121. In addition, the upper surface of the first capping layer 180 may be disposed on the same plane as the first interlayer insulating layer 130. The threshold voltage of the first gate stack 170 can be adjusted by adjusting the height of the first gate stack 170.

Next, referring to FIGS. 21 to 23, a semiconductor device including the oxide layer 144 disposed between the first dielectric layer 143 and the first work function control film 163 can be manufactured.

In this embodiment, the oxide layer 144 may be formed between the first dielectric layer 143 and the first conductive layer 145 through the baking step (H). Therefore, the semiconductor device according to the present embodiment can have a different threshold voltage as compared with the semiconductor device including the oxide layer 144. [

Next, a semiconductor device according to some embodiments of the present invention will be described with reference to FIG.

24 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present invention. The semiconductor device according to this embodiment can correspond to Fig. 23 of the above-described semiconductor device. Therefore, the semiconductor device according to the present embodiment is substantially the same as the embodiment of FIG. 23 except that it further includes a second field insulating film between the fin and the field insulating film. Accordingly, like reference numerals refer to like elements and repeated descriptions may be omitted.

Referring to FIG. 24, a second field insulating layer 105 may be further formed between the first fin F1 and the field insulating layer 110. Referring to FIG. Specifically, the second field insulating film 105 may cover the upper surface of the substrate 101 and the sidewalls of the first fin F1. The second field insulating film 105 may be conformally formed along the sidewalls of the upper surface and the first fin F1.

Next, with reference to FIGS. 25 to 44, a method of manufacturing a semiconductor device according to some embodiments of the present invention and a semiconductor device manufactured thereby will be described.

FIGS. 25 to 41 are views of an intermediate step for explaining a method of manufacturing a semiconductor device according to some embodiments of the present invention. 25 to 28 are perspective views, and Figs. 29 to 41 are sectional views. 29 is a cross-sectional view taken along the line A-A and B-B in Fig. 42 to 44 are a perspective view and a cross-sectional view for explaining a semiconductor device according to some embodiments of the present invention. Fig. 42 is a perspective view, Fig. 43 is a sectional view taken along the line A-A and B-B in Fig. 42, and Fig. 44 is a sectional view taken along the line C-C and D-D in Fig.

Referring to FIG. 25, a first fin F1 and a second fin F2 are formed on a substrate 101, respectively. The first region I and the second region II may be defined on the substrate 101. [ The first region (I) and the second region (II) may be attached to each other or may be separated from each other.

The first pin F1 may be formed in the first region I and the second pin F2 may be formed in the second region II. The first and second pins F1 and F2 may protrude in the third direction Z1. The first and second pins F1 and F2 may extend along the second longitudinal direction Y1 and may have a long side of the second direction Y1 and a short side of the first direction X1 . However, the present invention is not limited thereto. For example, the long side direction may be the first direction X1 and the short side direction may be the second direction Y1.

The first and second pins F1 and F2 may be part of the substrate 101 and may include an epitaxial layer grown from the substrate 101. [ For example, Si or SiGe.

Referring to FIG. 26, a field insulating layer 110 is formed on the substrate 101 so as to cover sidewalls of the first and second fins F1 and F2. The field insulating film 110 may be formed of a material including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

27, the upper portion of the field insulating film 110 is recessed to expose the upper portions of the first and second pins F1 and F2. The recess process may include an optional etch process.

On the other hand, a part of the first and second pins F1 and F2 protruding above the field insulating film 110 may be formed by an epitaxial process. For example, after the formation of the field insulating film 110, the first and second fins F1 and F2 exposed by the field insulating film 110 without a recess process are epitaxially grown on the upper surfaces of the first and second fins F1 and F2. A part of the second pins F1 and F2 may be formed.

Also, doping for threshold voltage adjustment can be performed on the exposed first and second fins F1 and F2. For example, the first fin F1 of the first region I may be doped with boron (B) as an impurity, and the second fin F2 of the second region II may be doped with impurities P) or arsenic (As). However, the present invention is not limited thereto, and the first and second fins F1 and F2 may be doped with the same kind of impurity.

Next, first and second dummy gate structures 111 and 211 are formed on the first and second fins F1 and F2, respectively, which intersect the first and second fins F1 and F2. 27, the first and second dummy gate structures 111 and 211 are illustrated as intersecting the first and second pins F1 and F2 at right angles, that is, in the first direction X1. However, And the first and second dummy gate structures 111 and 211 may intersect the first and second pins F1 and F2 at an acute angle and / or an obtuse angle with the first direction X1, respectively .

The first and second dummy gate structures 111 and 211 may include dummy gate insulating films 113 and 213 and dummy gate electrodes 115 and 215, respectively. The dummy gate insulating films 113 and 213 and the dummy gate electrodes 115 and 215 may be sequentially stacked.

The dummy gate insulating films 113 and 213 may be conformally formed on the upper and upper surfaces of the sidewalls of the exposed first and second fins F1 and F2 without being covered by the field insulating film 110. [ The dummy gate insulating films 113 and 213 may be disposed between the dummy gate electrodes 115 and 215 and the field insulating film 110.

The dummy gate electrodes 115 and 215 may be formed on the dummy gate insulating films 113 and 213.

For example, the dummy gate electrodes 115 and 215 may include silicon oxide, and the dummy gate insulating films 113 and 213 may include polysilicon.

Each of the dummy hard mask films 117 and 217 may be formed on the first and second dummy gate structures 111 and 211. The dummy hard mask films 117 and 217 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

Referring to FIGS. 28 and 28, first and second spacers 121 and 221 are formed on both side walls of the first and second dummy gate structures 111 and 211. The first and second spacers 121 and 221 may expose the upper surfaces of the hard mask films 117 and 217.

Each of the first and second spacers (121, 221) are, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO _2), silicon shot nitride (SiOCN) and at least one of a combination of One can be included.

Although each of the first and second spacers 121 and 221 is shown as a single film, it is for convenience of explanation, but is not limited thereto. When the first and second spacers 121 and 221 are a plurality of films, at least one of the films included in each of the first and second spacers 121 and 221 has a low dielectric constant material such as silicon oxynitride (SiOCN) . ≪ / RTI >

When the first and second spacers 121 and 221 are a plurality of films, at least one of the films included in the first and second spacers 121 and 221 may have an L shape or an I shape Lt; / RTI >

In some cases, the first and second spacers 121 and 221 may serve as guides for forming Self Aligned Contacts. Accordingly, the first and second spacers 121 and 221 may include a material having an etch selectivity to the interlayer insulating layer 130.

Then, the first and second fins F1 and F2 are etched without exposing the first and second dummy gate structures 111 and 211, respectively. The first and second fins F1 and F2 can be etched using the first and second spacers 121 and 221 and the first and second dummy gate structures 111 and 211 as an etching mask.

Then, first and second source / drain regions 123 and 223 are formed in the etched portions of the first and second fins F1 and F2. The first source / drain region 123 can be formed in the first fin F1 and the second source / drain region 223 can be formed in the second fin F2. The first and second source / drain regions 123 and 223 may be elevated source / drain regions. Therefore, as shown in FIG. 20, the upper surfaces of the first and second source / drain regions 123 and 223 may be higher than the upper surfaces of the first and second pins F1 and F2.

The first source / drain region 123 and / or the second source / drain region 223 may comprise a tensile stress material. The first source / drain region 123 and / or the second source / drain region 223 may be the same material as the substrate 101 or a tensile stress material. For example, when the substrate 101 is Si, the first source / drain region 123 and / or the second source / drain region 223 may be Si or a material having a smaller lattice constant than Si (e.g., SiC, SiP).

However, the first source / drain region 123 and / or the second source / drain region 223 may include a compressive stress material. For example, the compressive stress material may be a material having a larger lattice constant than Si, and may be, for example, SiGe. The first and second source / drain regions 123 and 223 can be formed by epitaxial growth.

Although the first and second source / drain regions 123 and 223 are shown as being pentagonal in FIG. 28, the present invention is not limited thereto. For example, the first and second source / 223 may have a shape such as a rectangle, a circle, or a hexagon.

Referring to FIG. 30, an interlayer insulating film 130 covering the first and second source / drain regions 123 and 223 is formed. The interlayer insulating film 130 may cover the sidewalls of the first and second spacers 121 and 221 and expose the upper surfaces of the hard mask films 117 and 217. The interlayer insulating film 130 may include, for example, silicon oxide.

Referring to FIG. 31, first and second trenches 135 and 235 are formed to expose the upper portions of the first and second pins F1 and F2. First, the hard mask films 117 and 217 are removed. The hard mask films 117 and 217 can be removed through a planarization process or the like, and if the planarization process is performed, the interlayer insulating film 130 can also be partially etched.

Then, the first and second dummy gate structures 111 and 211 are removed. The dummy gate electrodes 115 and 215 and the dummy gate insulating films 113 and 213 are removed to expose the first and second pins F1 and F2. The first trench 135 is formed at a position where the first dummy gate structure 111 was present and the second trench 235 is formed at a place where the second dummy gate structure 211 was located. The sidewalls of the first and second spacers 121 and 221 can be exposed by the first and second trenches 135 and 235.

Referring to FIG. 32, first and second interface films 141 and 241 are formed in first and second trenches 135 and 235, respectively. The first and second interface films 141 and 241 may be formed along the upper surface of the first and second pins F1 and F2 and the upper surface of the sidewall.

The first and second interface films 141 and 241 may be formed by oxidizing the exposed first and second fins F1 and F2 in the first and second trenches 135 and 235 . The first and second interface films 141 and 241 may be formed along the bottom surfaces of the first and second trenches 135 and 235, respectively.

A first dielectric layer 143a is formed in the first trench 135 and a second dielectric layer 243a is formed in the second trench 235. Next, Specifically, the first dielectric layer 143a may be conformally formed along the sidewalls and the bottom surface of the first trench 135, and may include a field insulating layer 110, It can be formed into a foam. The second dielectric layer 243a may be conformally formed along the sidewalls and the bottom surface of the second trench 235 and may conform to the top surface and top surface of the sidewall of the field insulating layer 210, . Also, the first and second dielectric layers 143a and 243a may be formed on the dielectric interlayer 130 as well.

The first and second dielectric layers 143a and 243a may include a dielectric material having a higher dielectric constant than the silicon oxide layer. For example, the first and the second dielectric layer (143a, 243a) is, HfSiON, HfO _2, ZrO _2, Ta ₂ O _5, TiO _2, SrTiO _3, or selected from the group consisting of such as (Ba, Sr) TiO ₃ ≪ / RTI > The first and second dielectric layers 143a and 243a may be formed to have an appropriate thickness depending on the type of device to be formed.

Referring to FIG. 33, the first and second conductive films 145 and 245 and the first and second blocking films 147 and 247 are sequentially formed. A first diffusion film 147 is formed in the first trench 135 and a second diffusion film 247 is formed in the second trench 235. The first and second conductive films 145 and 245 may be conformally formed along the sidewalls and bottom surfaces of the first and second trenches 135 and 235, respectively. Further, it may be formed along the upper and upper surfaces of the side walls of the first and second pins F1 and F2. The first and second conductive films 145 and 245 may include, but are not limited to, TiN.

Next, first and second blocking films 147 and 247 are formed on the first and second conductive films 145 and 245, respectively. The first and second blocking films 147 and 247 may fill the first and second trenches 135 and 235 and may cover the first and second conductive films 145 and 245 so that the first and second conductive films 145 and 245 are not exposed to the outside . The first and second blocking films 147 and 247 may include, for example, Si.

Annealing 150 is then performed. The first and second dielectric layers 143a and 243a contain oxygen atoms. The oxygen atoms are bonded to other materials (for example, Hf, Zr, Ta, Ti, etc.) in the first and second dielectric layers 143a and 243a. If the coupling is broken, a leak current or the like may be generated and the performance of the transistor may deteriorate. To prevent this problem, annealing 150 is performed to bond the oxygen atoms to the broken part of the bond. When the annealing 150 is performed, oxygen atoms contained in the first diffusion layer 147 can be provided to the first dielectric layer 143a. In addition, the oxygen atoms contained in the second diffusion film 247 and / or the second lanthanum film 245a may be provided to the second dielectric film 243a.

On the other hand, if the first and second conductive films 145 and 245 are exposed during the annealing 150, oxygen atoms outside the first and second conductive films 145 and 245 penetrate into the first and second conductive films 145 and 245 during the annealing 150 The number of oxygen atoms moving to the bottom of the first and second conductive films 145 and 245 increases. When oxygen atoms are supplied in excess of the required number of oxygen atoms of the first and second dielectric layers 143a and 243a, excess oxygen atoms are supplied to the first and second pins 135 and 235 in the first and second trenches 135 and 235 F1, < / RTI > F2). As a result, the thickness of the first and second interface films 141 and 241 becomes thick, and the performance of the transistor may deteriorate. The first and second blocking films 147 and 247 are formed on the first and second conductive films 145 and 245 so that the first and second conductive films 145 and 245 are exposed to the outside The supply amount of oxygen atoms can be appropriately adjusted by blocking.

The annealing 150 may be performed at a temperature of 500 ° C to 1500 ° C.

The thickness of the first and second conductive films 145 and 245 may vary depending on the number of oxygen atoms to be supplied.

Referring to FIG. 34, the first and second blocking films 147 and 247 are removed to expose the first and second conductive films 145 and 245.

35, a mask pattern 1001 covering the second region II is formed, and the first conductive film 145 disposed in the region I is removed. More specifically, after forming a mask layer covering the first and second regions I and II, the mask layer is patterned by the mask pattern 1001 through a patterning process. Then, the exposed first conductive film 145 is removed through an etching process. Accordingly, the first dielectric layer 143a can be exposed.

Referring to FIG. 36, the mask pattern 1001 disposed in the second region II is removed, and a baking step (H) is performed. Accordingly, a first porosity region HR and a second porosity region LR may be formed in the first dielectric layer 143a disposed in the first region I. In the second region II, an oxide layer 244 may be formed between the second dielectric layer 243a and the second conductive layer 245.

The porosity of the second porosity region LR may be higher than that of the first porosity region HR. The porosity of the first porosity region HR and the second porosity region LR may be formed through oxygen vacancies formed by removing the oxygen contained in the first dielectric layer 143a.

That is, in this embodiment, oxygen contained in the material of the surface of the first dielectric layer 143a may be removed through heat applied during the baking step (H) to form oxygen vacancies, The area of the exposed surface of the dielectric layer 143a may have a relatively high porosity as compared to the area of the first dielectric layer 143a in contact with the spacer 121 and the first interface layer 141. Therefore, in the present invention, a region having a relatively high porosity is referred to as a second porosity region (LR), and a region having a relatively low porosity is referred to as a first porosity region (HR). Although the first porosity region HR and the second porosity region LR are shown as having a clear boundary, the technical idea of the present invention is not limited thereto. The porosity of the second porosity region LR can vary continuously. That is, the porosity of the second porosity region LR can be reduced as it moves from the upper surface of the first dielectric layer 143a to the first interface film 141 within the second porosity region LR.

The region adjacent to the first interface 141 or the first spacer 121 in the first dielectric layer 143a can have the same porosity before and after the baking process H as compared with the surface of the first dielectric layer 143a have. Therefore, in the present embodiment, a region having the same porosity before and after the baking step H in the first dielectric film 143a can be referred to as a first porosity region HR, and a porosity before and after the baking step (H) This changed region can be referred to as a second porosity region LR.

The thickness H1 of the second porosity region LR may be less than half of the thickness H1 of the first dielectric layer 143a. That is, the thickness H2 of the second porosity region LR may be thinner than the thickness H1-H2 of the first porosity region HR. However, the technical idea of the present invention is not limited thereto, and the thicknesses of the first and second porosity regions LR and HR may be variously changed according to the necessity of the invention.

The oxygen porosity in the second porosity region LR of the first dielectric film 143a is changed before and after the baking step H in this embodiment so that the threshold voltage of the semiconductor device disposed in the first region I Lt; / RTI >

When the baking process (H) is performed on the second conductive film 245, an oxidizing charge 244 may be formed between the second conductive film 245 and the second dielectric film 243a. Although the second conductive layer 245, the second dielectric layer 243a and the oxidized layer 244 are shown to have similar thicknesses, the present invention is not limited thereto. The thickness of each of the second conductive layer 245, the second dielectric layer 243a, and the oxidation pad 244 can be controlled differently.

At the baking step (H), the oxygen atoms contained in the second dielectric film 243a can not escape to the outside due to the second conductive film 245. [ Accordingly, an oxide layer 244 may be formed between the second conductive layer 245 and the second dielectric layer 243a. The oxide layer 244 may include a substance in which the substance contained in the second dielectric film 243a is oxidized. In addition, the oxide layer 244 may include a substance in which the substance included in the second conductive film 245 is oxidized. However, the present invention is not limited thereto.

In this embodiment, since the oxide layer 244 is formed on the second dielectric film 243a, the threshold voltage of the semiconductor device disposed in the second region II including the oxide layer 244 can be controlled.

That is, in the present embodiment, the first dielectric layer 143a having a high porosity in the region including the surface can be formed in the first region I through the same baking step (H), and the second region The oxide layer 244 may be formed between the second conductive layer 245 and the second dielectric layer 243a. Thus, the semiconductor device can control the threshold voltages of the transistors included in the first region I and the transistors included in the second region II differently from each other.

Referring to FIG. 37, the second conductive film 245 disposed in the second region II is removed. The second dielectric layer 243a may be thinner than the first dielectric layer 143a because a part of the second dielectric layer 243a changes to the oxide layer 144. [ Therefore, the upper surfaces of the first dielectric layer 143a and the second dielectric layer 243a may not be disposed on the same plane. In this embodiment, the thickness including the oxide layer 244 and the second dielectric layer 243a is shown to be about twice the thickness of the first dielectric layer 143a, but this is for the purpose of illustrating the present invention, But is not limited thereto. Therefore, the thickness including the oxide layer 244 and the second dielectric layer 243a may be 1.1 times or less the thickness of the first dielectric layer 143a.

Referring to FIG. 38, first and second conductive films 151a and 261a are formed on the first dielectric layer 143a and the oxide layer 144, respectively. The first and second conductive films 151a and 261a may be conformally formed along the sidewalls and bottom surfaces of the first and second trenches 135 and 235, respectively. In addition, the first and second conductive films 151a and 261a may include, for example, TiN. First and second work function adjusting films 163a and 263a are formed on the first and second conductive films 151a and 261a, respectively. The first and second work function regulating films 163a and 263a may comprise, for example, TiAlC. The first and second work function regulating films 163a and 263a may be conformally formed along the sidewalls and bottom surfaces of the first and second trenches 135 and 235. The first and second work function regulating films First and second barrier films 165a and 265a are formed on the first and second barrier films 163a and 263a, respectively. Each of the first and second barrier films 165a and 265a may be formed along the sidewalls and the bottom surface of the first and second trenches 135 and 235. The first and second barrier films 165a and 265a may be formed conformally along the upper and upper surfaces of the sidewalls of the first and second pins F1 and F2, respectively. The first and second barrier films 165a and 265a may comprise, for example, TiN

First and second metal films 167a and 267a are formed on the first and second barrier films 165a and 265a, respectively. The first and second metal films 167a and 267a may fill the remaining portions of the first and second trenches 135 and 235. [ The first and second metal films 167a and 267a may include, for example, Al, W, and the like.

Referring to FIG. 39, first and second gate stacks 170 and 270 are formed. 38, when the planarization process is performed so that the first interlayer insulating layer 130 is exposed, the first interface layer 141, the first dielectric layer 143, the first conductive layer 151, A first gate stack 170 including a film 163, a first barrier film 165, and a first metal film 167 may be formed. The first dielectric layer 143, the first conductive layer 151, the first work function regulating layer 163 and the first barrier layer 165 may have a concave shape in the first trench 135.

The second interface film 241, the second dielectric film 243, the oxide layer 244, the second conductive layer 261, the second work function control film 263, the second barrier film 265, A second gate stack 270 including a metal film 267 may be formed. The second dielectric film 243, the oxide layer 244, the second conductive layer 261, the second work function control film 263 and the second barrier film 265 have a concave shape in the second trench 235 .

Referring to FIG. 40, first and second capping films 180 and 280 are formed on first and second gate stacks 170 and 270, respectively. Specifically, each of the first and second capping films 180 and 280 may be formed on the first and second gate stacks 170 and 270 and cover the first and second trenches 135 and 235. The first and second capping films 180 and 280 may comprise a nitride (e.g., at least one of SiN, SiON, SiCON) or an oxide. Each of the first and second capping layers 180 and 280 may block the first and second gate stacks 170 and 270 from outside to prevent a change in performance of the first and second gate stacks 170 and 270 have.

Next, referring to FIG. 41, second interlayer insulating films 132 and 232 are formed on the interlayer insulating film 130. Next, as shown in FIG. The second interlayer insulating films 132 and 232 may cover the first and second capping films 180 and 280. The second interlayer insulating films 132 and 232 may include the same material as the interlayer insulating film 130, and may include, for example, silicon oxide.

42 to 44, first and second silicide films 191 and 291 are formed on the first and second source / drain regions 123 and 223, respectively, and first and second source / The first and second contacts 193 and 293 penetrating the interlayer insulating film 130 and the second interlayer insulating films 132 and 232 are formed on the regions 123 and 223 to form the semiconductor device according to this embodiment . However, the technical idea of the present invention is not limited thereto. The first and second silicide layers 191 and 291 may reduce the surface resistance and the contact resistance of the first and second source and drain regions 123 and 223. For example, , Co, and the like. The first and second contacts 193 and 293 may include, for example, W, Al Cu, and the like.

The semiconductor device according to the present embodiment may include the first and second transistors TR1 and TR2 in the first region I and the second region II, respectively. The threshold voltage of the first transistor TR1 may be adjusted by the first dielectric layer 143 and the threshold voltage of the second transistor TR2 may be adjusted by the oxide layer 244. [ Therefore, the first transistor TR1 and the second transistor TR2 can be controlled to have different threshold voltages.

45 is a block diagram of an electronic system including a semiconductor device according to some embodiments of the present invention.

45, an electronic system 11000 according to an embodiment of the present invention includes a controller 11100, an input / output (I / O) device 11200, a memory device 11300, an interface 11400, 11500, bus). The controller 11100, the input / output device 11200, the storage device 11300, and / or the interface 11400 may be coupled to each other via the bus 11500. [ Bus 11500 corresponds to a path through which data is moved.

The controller 11100 may include at least one of a microprocessor, a digital signal process, a microcontroller, and logic elements capable of performing similar functions. The input / output device 11200 may include a keypad, a keyboard, a display device, and the like. The storage device 11300 may store data and / or instructions and the like. The interface 11400 may perform functions to transmit data to or receive data from the communication network. Interface 11400 may be in wired or wireless form. For example, the interface 11400 may include an antenna or a wired or wireless transceiver. Although not shown, the electronic system 11000 is an operation memory for improving the operation of the controller 11100, and may further include a high-speed DRAM and / or an SRAM. The semiconductor devices 1-11 according to some embodiments of the present invention may be provided in the storage device 11300 or may be provided as a part of the controller 11100, the input / output device 11200, the I / O device, and the like.

The electronic system 11000 may be a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a smart phone, a mobile phone, ), A digital music player, a memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

46 is an exemplary semiconductor system to which a semiconductor device according to some embodiments of the present invention may be applied. 2 shows a tablet PC. The semiconductor device manufactured according to some embodiments of the present invention can be used for a tablet PC, a notebook computer, and the like. It will be apparent to those skilled in the art that semiconductor devices fabricated in accordance with some embodiments of the present invention may be applied to other integrated circuit devices not illustrated.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

101: substrate 110: field insulating film
130: interlayer insulating film 123, 223: source / drain region
121, 221: Spacer 135, 2355: Trench
141, 241: interface film 143, 243: dielectric film
163, 263: work function regulating film 165, 265: barrier film
167, 267: metal film 170, 270: gate stack

Claims (20)

A substrate comprising a first region
A first dielectric layer disposed on the substrate of the first region and including a first porosity region and a second porosity region having a porosity different from that of the first porosity region; And
And a first gate stack disposed on the first dielectric layer. The method of claim 1, wherein
Wherein the second porosity region has a porosity higher than the first porosity region and the second porosity region is disposed adjacent the first gate stack and the first porosity region is spaced apart from the first gate stack A semiconductor device. 3. The method of claim 2,
And the thickness of the second porosity region is thinner than the thickness of the first porosity region. The method according to claim 1,
Wherein the first porosity region and the second porosity region are formed through oxygen vacancies. The method according to claim 1,
Wherein the substrate further comprises a second region different from the first region,
A second dielectric layer disposed on the substrate of the second region;
An oxide layer disposed on the second dielectric layer; And
And a second gate stack disposed on the oxide layer. 6. The method of claim 5,
Wherein the first gate stack includes sequentially sequentially stacked first work function control films, a first barrier film, and a first metal film,
Wherein the second gate stack comprises a sequentially stacked second work function control film, a second barrier film and a second metal film,
The first work function control film and the first dielectric film are in contact with each other, the second work function control film is in contact with the oxide layer,
Wherein the first work function adjusting film is thicker than the second work function adjusting film. The method according to claim 6,
And the upper surface of the first work function control film and the upper surface of the second work function control film are disposed on the same plane. 6. The method of claim 5,
Wherein the oxide layer comprises an oxide of a substance contained in the second dielectric layer. 6. The method of claim 5,
Wherein the first and second gate stacks form first and second transistors, respectively, and the threshold voltages of the first and second transistors are different. A substrate comprising a first region and a second region;
A first dielectric layer disposed on the substrate of the first region and including a first porosity region and a second porosity region having a porosity higher than the first porosity region;
A second dielectric layer disposed on the substrate of the second region and having a first porosity;
A first gate stack disposed on the first dielectric layer; And
And a second gate stack disposed on the second dielectric layer,
Wherein the first dielectric layer is thicker than the second dielectric layer. 11. The method of claim 10,
Wherein the second porosity region is disposed adjacent to the first gate stack and the first porosity region is spaced apart from the first gate stack. 12. The method of claim 11,
And the thickness of the second porosity region is thinner than the thickness of the first porosity region. 11. The method of claim 10,
Further comprising an oxide layer between said second dielectric layer and said second gate stack, said oxide layer comprising an oxide of a material comprised by said second dielectric layer. 14. The method of claim 13,
Wherein the first gate stack includes sequentially sequentially stacked first work function control films, a first barrier film, and a first metal film,
Wherein the second gate stack comprises a sequentially stacked second work function control film, a second barrier film and a second metal film,
The first work function control film and the first dielectric film are in contact with each other, the second work function control film is in contact with the oxide layer,
And the upper surface of the first work function regulating film is disposed on the same plane as the upper surface of the second work function regulating film. 15. The method of claim 14,
Wherein the first work function adjusting film is thicker than the second work function adjusting film. A substrate comprising a first region and a second region;
A first dielectric layer disposed on the substrate of the first region;
A second dielectric layer disposed on the substrate of the second region;
A first gate stack disposed on the first dielectric layer and in contact with the first dielectric layer;
An oxide layer disposed on the second dielectric layer and in contact with the second dielectric layer; And
And a second gate stack disposed on the oxide layer and in contact with the oxide layer,
Wherein the oxide layer comprises an oxide of a substance contained in the second dielectric layer. 17. The method of claim 16,
Wherein the first dielectric layer is thicker than the second dielectric layer. 17. The method of claim 16,
Wherein the first dielectric layer comprises a first porosity region and a second porosity region having a porosity higher than the first porosity region,
Wherein the second porosity region is disposed adjacent to the first gate stack and the first porosity region is spaced apart from the first gate stack. 19. The method of claim 18,
And the thickness of the second porosity region is thinner than the thickness of the first porosity region. 19. The method of claim 18,
Wherein the first porosity region and the second porosity region are formed through a gap of oxygen included in the first dielectric layer.

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