KR20140146874A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

Provided are a semiconductor device and a method for fabricating the same. A semiconductor device includes an active pattern which is extended from a semiconductor substrate, includes a source and a drain region, and a channel region between them in a point of a horizontal view and a local insulating pattern locally formed between the channel region of the active pattern and the semiconductor substrate in a point of vertical view, a gate electrode which crosses the channel region of the active pattern and the sidewall of the local insulating pattern, a sidewall spacer of both sides of the gate electrode, and a protection spacer which is interposed between the both sidewalls of the gate electrode and the sidewall spacer and is made of a material which has etch selectivity to the sidewall spacer.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device and a manufacturing method thereof,

Field of the Invention [0002] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a fin field effect transistor and a manufacturing method thereof.

The semiconductor device includes an integrated circuit composed of MOS (Metal Oxide Semiconductor) FETs. As the size and design rules of semiconductor devices are gradually shrinking, the scale down of MOS field effect transistors is also accelerating. The size reduction of the MOS field effect transistors may cause a short channel effect and the like, which may degrade the operation characteristics of the semiconductor device. Accordingly, various methods for forming a semiconductor device with superior performance while overcoming the limitations of high integration of the semiconductor device have been researched.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device with improved electrical characteristics.

Another object of the present invention is to provide a method of manufacturing a semiconductor device having improved electrical characteristics.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided an active pattern extending from a semiconductor substrate, the active pattern including, in a horizontal view, source and drain regions and a channel region therebetween, A vertical insulated pattern locally formed between the channel region of the active pattern and the semiconductor substrate, a gate electrode across the sidewall of the localized insulated pattern and the channel region of the active pattern, A sidewall spacer on either side of the gate electrode and a protection spacer interposed between the sidewall spacers and the sidewall spacers of the gate electrode and formed of a material having etch selectivity to the sidewall spacers.

According to one embodiment, the protective spacers may be in direct contact with both sidewalls of the gate electrode.

According to one embodiment, the protective spacer may be made of a metal oxide.

According to one embodiment, the lowermost surface of the gate electrode may be located below the top surface of the localized insulation pattern.

According to one embodiment, the width of the localized insulation pattern may be substantially equal to or greater than the width of the active pattern.

According to one embodiment, the local insulation pattern may be disposed between the source and drain electrodes in a horizontal view.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: patterning a semiconductor substrate to form an active pattern; forming an anti-oxidation spacer covering an upper sidewall of the active pattern; Forming an active pattern and a dummy gate pattern across the antioxidant spacer; covering both sidewalls of the dummy gate pattern; forming protective spacers made of a material having etch selectivity for the antioxidant spacer Removing the dummy gate pattern to form a gate region between the protection spacers exposing a bottom sidewall of the active pattern; oxidizing the bottom sidewall of the active pattern exposed in the gate region, Forming a localized insulation pattern in the gate insulation layer, In the includes forming a gate electrode.

According to one embodiment, before forming the dummy gate pattern, forming a device isolation pattern that exposes a portion of a lower sidewall of the active pattern away from a bottom surface of the anti-oxidation spacer.

According to one embodiment, the dummy gate pattern may directly contact the active pattern between the device isolation pattern and the anti-oxidation spacer.

According to one embodiment, forming the active pattern may include forming a mask pattern defining the active pattern on the semiconductor substrate, etching the semiconductor substrate using the mask pattern as an etch mask to form trenches And forming an element isolation film exposing an upper sidewall of the active pattern in the trenches, wherein the anti-oxidation spacer can be formed on the element isolation film.

According to one embodiment, after forming the antioxidant spacer, the method further comprises forming an element isolation pattern that recesses an upper surface of the isolation layer to expose a lower sidewall of the active pattern.

According to one embodiment, the gate electrode may be in direct contact with the sidewalls of the localized insulation pattern.

According to one embodiment, forming the gate electrode comprises exposing an upper portion of the active pattern by removing the antioxidant spacer, and exposing an upper portion of the active pattern to the protective spacers And filling the conductive film in direct contact.

According to one embodiment, before forming the gate region, the method further comprises forming a sidewall spacer covering the sidewall of the protection spacer, wherein the sidewall spacer may be formed of an insulating material different from the protection spacer.

According to one embodiment, the active pattern includes a channel region below the dummy gate pattern and source and drain regions on either side of the channel region, wherein before forming the gate region, the source and drain regions To form an epitaxial layer.

The details of other embodiments are included in the detailed description and drawings.

According to embodiments of the present invention, in the process of manufacturing a fin field effect transistor having a local insulation pattern in a lower portion of a channel region, when the gate electrode is formed after the source and drain electrodes are formed, The width of the electrode can be prevented from varying.

Further, since the step of recessing the element isolation film is not performed after removing the dummy gate pattern, the step of recessing the element isolation film can prevent the height of the interlayer insulating film, which defines the height of the gate region, from being reduced. Therefore, the height of the gate electrode can be prevented from being reduced.

1 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
2A to 15A are perspective views illustrating a method of manufacturing a semiconductor device according to embodiments of the present invention.
FIGS. 2B to 15B are cross-sectional views for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention, and are taken along lines I-I ', II-II', and III-III ' Cut sections.
16 is a perspective view for explaining structural features of a semiconductor device according to embodiments of the present invention.
17 and 18 are block diagrams schematically illustrating electronic devices including a semiconductor device according to embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions.

In addition, the embodiments described herein will be described with reference to cross-sectional views and / or plan views, which are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. For example, the etched area shown at right angles may be rounded or may have a shape with a certain curvature. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

Hereinafter, a method of manufacturing a semiconductor device according to embodiments of the present invention and a semiconductor device formed thereby will be described in detail with reference to the drawings.

1 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention. 2A to 15A are perspective views illustrating a method of manufacturing a semiconductor device according to embodiments of the present invention. FIGS. 2B to 15B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to embodiments of the present invention. FIGS. 2B to 15B are cross-sectional views taken along lines I-I ', II-II', and III-III ' Cut sections.

Referring to FIGS. 1, 2A and 2B, the semiconductor substrate 100 is patterned to form trenches 103 defining active patterns 101 (S10).

The formation of the trenches 103 may include forming a mask pattern 110 that exposes certain regions of the semiconductor substrate 100 and anisotropically etching the mask pattern 110 as an etch mask .

According to one embodiment, The mask pattern 110 may be in the form of a line extending in a first direction (i.e., an x-axis direction) and includes an oxide film pattern 111 and a hard mask pattern 113 stacked in that order.

More specifically, the formation of the mask pattern 110 may be achieved by sequentially laminating a silicon oxide film and a hard mask film on the semiconductor substrate 100, a photoresist pattern (not shown) defining the active pattern 101 on the hard mask film And then anisotropically etching the hard mask film and the silicon oxide film in order to expose the upper surface of the semiconductor substrate 100 using a photoresist pattern (not shown) as an etch mask. Here, the photoresist pattern (not shown) may be a line shape extending in a first direction (i.e., x-axis direction). The silicon oxide film can be formed by thermal oxidation of the semiconductor substrate 100, and such a silicon oxide film can relieve the stress between the semiconductor substrate 100 and the hard mask film. The hard mask film may be formed of any one material selected from a silicon nitride film, a silicon oxynitride film, and a polysilicon film. The thickness of the hard mask layer may vary depending on the depth of the trenches 103 formed in the semiconductor substrate 100. Further, the hard mask film may be thicker than the silicon oxide film. According to one embodiment, after forming the mask pattern 110, the photoresist pattern (not shown) may be removed.

Subsequently, the semiconductor substrate 100 is anisotropically etched to a predetermined depth by using the mask pattern 110 as an etching mask. Accordingly, trenches defining the active pattern 101 can be formed in the semiconductor substrate 100. [ The trenches 103 may be in the form of a line extending in the first direction (i.e., the x-axis direction) and may be formed to have a lower width smaller than the top width by an anisotropic etching process. That is, the trenches 103 may have a sidewall profile that becomes narrower toward the bottom.

3A and 3B, an element isolation film 105 is formed to expose the upper sidewall of the active pattern 101 in the trenches 103. [ That is, the upper surface of the device isolation film 105 may be located below the upper surface of the active pattern 101.

According to one embodiment, forming the device isolation film 105 may be performed by forming an insulating film filling the trenches 103, planarizing the insulating film to expose the upper surface of the mask pattern 110, To expose the top sidewalls of the active pattern 101. [0034] Here, the insulating film filling the trenches 103 can be deposited using a deposition technique with excellent step coverage. The insulating layer may be formed of an insulating material having excellent gap fill characteristics. For example, a boron-phosphor silicate glass (BPSG) layer, a high density plasma (HDP) oxide layer, an undoped silicate glass TOSZ (Tonen SilaZene) material. In addition, an etch back method and / or a chemical mechanical polishing (CMP) method may be used as the planarization process for the insulating film. And, recessing the upper surface of the planarized insulating film may be selective etching of the planarized insulating film using the etching recipe having etching selectivity with respect to the active pattern 101. While the upper surface of the insulating film is thus recessed, the thickness of the mask pattern 110 may be reduced.

Referring to FIGS. 1, 4A, and 4B, an anti-oxidation spacer 117 covering an upper sidewall of the active pattern 101 is formed on the device isolation film 105 (S20). Further, the anti-oxidation spacer 117 may cover the side wall of the mask pattern 110. [

Formation of the anti-oxidation spacer 117 includes conformally depositing an anti-oxidation film along the surface of the active pattern 101 and the mask pattern 110, and anisotropically etching the anti-oxidation film. Here, the oxidation preventing film can be removed from the upper surface of the mask pattern 110 and the upper surface of the isolation film 105 by the front anisotropic etching process for the oxidation preventing film.

According to one embodiment, the anti-oxidation spacer 117 may be formed of a material having an etching selectivity to the silicon oxide film, and may be formed of, for example, a silicon nitride film or a silicon oxynitride film. In one embodiment, the anti-oxidation spacer 117 may be formed of the same material as the hard mask pattern 113 of the mask pattern 110.

On the other hand, before forming the oxidation preventing spacer 117, a sidewall oxide film 115 for protecting the upper sidewall of the active pattern 101 may be formed. The sidewall oxide film 115 can be formed by thermally oxidizing the upper sidewall of the active pattern 101.

5A and 5B, the upper surface of the device isolation film 105 is recessed to form a device isolation pattern 107 that exposes the lower sidewalls of the active pattern 101. As shown in FIG.

According to one embodiment, forming the element isolation pattern 107 is to selectively etch the element isolation film 105 using the anti-oxidation spacer 117 and the etch recipe having etch selectivity for the active pattern 101 . Here, in order to selectively etch the element isolation film 105, an isotropic dry or wet etching method may be used. The upper surface of the device isolation pattern 107 and the bottom surface of the anti-oxidation spacer 117 can be spaced apart from each other and the lower surface of the active pattern 101 between the device isolation pattern 107 and the anti- A portion of the sidewall may be exposed. That is, the active pattern 101 has a first portion 101a covered with a sidewall by the oxidation preventing spacer 117, a second portion 101b whose sidewall is covered by the device isolation pattern 107 and is connected to the semiconductor substrate 100, And a third portion 101c that is disposed between the first portion 101a and the second portion 101b and to which the sidewall is exposed.

6A and 6B, the dummy gate film 120 is formed on the entire surface of the semiconductor substrate 100 on which the element isolation patterns 107 are formed.

The dummy gate film 120 may be formed on the mask pattern 110 while filling the trenches 103 in which the element isolation patterns 107 are formed. The dummy gate film 120 filling the trenches 103 can directly contact the third portion 101c of the active pattern 101. [

The dummy gate film 120 may be formed of a material having etch selectivity with respect to the device isolation pattern 107, the anti-oxidation spacer 117, and the active pattern 101. [ For example, the dummy gate film 120 may be formed of an impurity doped polysilicon film, an undoped polysilicon film, a silicon germanium film, or a silicon carbide film.

The dummy gate film 120 may be formed by a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, or an atomic layer deposition (ALD) method . After forming the dummy gate film 120 using this deposition method, the upper surface of the dummy gate film 120 can be planarized.

1, 7A, and 7B, a dummy gate pattern 125 is formed across the active pattern 101 (S30).

The dummy gate pattern 125 is formed by forming the gate mask pattern 121 across the active pattern 101 on the dummy gate film 120 and forming the dummy gate pattern 121 by using the gate mask pattern 121. [ RTI ID = 0.0 > 120 < / RTI > Here, in the anisotropic etching process for the dummy gate film 120, the hard mask pattern 113 and the device isolation pattern 107 can be used as an etching stopper film.

The channel region CHR and the source and drain regions SDR may be defined in the first portion 101a of the active pattern 101 as the dummy gate pattern 125 is formed. Here, the channel region CHR is a portion of the active pattern 101 located under the dummy gate pattern 125, the source and drain regions SDR are located on both sides of the dummy gate pattern 125, CHR < / RTI >

8A and 8B, a part of the mask pattern 110 is anisotropically etched using the dummy gate pattern 125 as an etching mask. Accordingly, the oxide film pattern 111 covering the active pattern 101 of the source and drain regions SDR can be exposed. Also, The remaining hard mask pattern 114 and the anti-oxidation spacer 117 can be locally formed under the dummy gate pattern 125. [

Referring to FIGS. 1, 9A and 9B, protective spacers 131 and sidewall spacers 133 are sequentially formed on both side walls of the dummy gate pattern 125 (S40). The protective spacers 131 may be in direct contact with the sidewalls of the dummy gate pattern 125. [

The formation of the protective spacers 131 and the sidewall spacers 133 is accomplished by conformally depositing a protective spacer film and a sidewall spacer film on the semiconductor substrate 100 on which the dummy gate pattern 125 is formed, Anisotropically etching the spacer film.

According to one embodiment, the protective spacers 131 may be formed of a material having etch selectivity to the anti-oxidant spacers 117. For example, the protective spacers 131 may be formed of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, niobium oxide, cesium oxide, indium oxide, iridium oxide, barium strontium titanate (BST) lead zirconate titanate) film.

In addition, the sidewall spacers 133 may be formed of a material having an etch selectivity to the protective spacers 131. For example, the sidewall spacers 133 may be formed of a silicon nitride film or a silicon oxynitride film.

On the other hand, according to another embodiment, forming the sidewall spacer on the protection spacer 131 may be omitted, and in this case, the protection spacer 131 may be in direct contact with the interlayer insulating film 140.

Referring to FIGS. 1, 10A, and 10B, on both sides of the dummy gate pattern 125, Source and drain electrodes 135 are formed in the active pattern 101 (S50).

The source and drain electrodes 135 may be formed at the positions of the source / drain regions SDR of the active pattern 101. [ Accordingly, the channel region CHR of the active pattern 101 can be interposed between the source and drain electrodes 135. [

According to one embodiment, forming the source and drain electrodes 135 can include removing the active pattern 101 of the source / drain regions (SDR) and forming an epitaxial layer . If the semiconductor device is a CMOS structure, forming the epitaxial layer may be accomplished by forming a first epitaxial layer for the source / drain electrode of the NMOSFET and forming a second epitaxial layer for the source / drain electrode of the PMOSFET . According to some embodiments, the first epitaxial layer may be configured to cause a tensile strain, and the second epitaxial layer may be configured to cause a compressive strain. For example, the first epitaxial layer may be formed of silicon carbide (SiC) and the second epitaxial layer may be formed of silicon germanium (SiGe), but the embodiments of the present invention are not limited thereto. In addition, a silicide film (not shown) such as nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, niobium silicide, or tantalum silicide may be formed on the source and drain electrodes 135.

According to another embodiment, forming the source and drain electrodes 135 may be performed by using the dummy gate pattern 125 as an ion implantation mask to form an n-type or an n-type electrode in the active pattern 101 of the source / drain regions (SDR) and ion implantation of a p-type impurity.

Referring to FIGS. 11A and 11B, on the active pattern 101, The interlayer insulating film 140 exposing the upper surface of the pattern 125 is formed.

The formation of the interlayer insulating film 140 may include forming an insulating film covering the resultant formed with the source and drain electrodes 135 and then planarizing the insulating film so that the upper surface of the dummy gate pattern 125 is exposed. have. The interlayer insulating film 140 may include at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a low dielectric film.

Referring to FIGS. 12A and 12B, the dummy gate pattern 125 is removed to form the gate region 141 between the protection spacers 131. FIG.

Removing the dummy gate pattern 125 can be performed by a combination of dry and wet etching processes. In detail, the dummy gate pattern 125 can be wet-etched using the etch recipe having etch selectivity for the interlayer insulating film 140, the protective spacers 131, and the anti-oxidation spacer 117. In one embodiment, when the dummy gate pattern 125 is formed of silicon-germanium (SiGe), the dummy gate pattern 125 may be removed using an etchant mixed with ammonia water and hydrogen peroxide. In another embodiment, when the dummy gate pattern 125 is formed of polysilicon, the polysilicon may be wet etched using an etchant mixed with nitric acid, acetic acid, and hydrofluoric acid.

As described above, by removing the dummy gate pattern 125, a part of the lower side wall of the active pattern 101 in the gate region 141 can be exposed. In other words, the third portion 103c of the active pattern 101 can be exposed. The first portion 103a of the active pattern 101 may be covered with the anti-oxidation spacer 117 and the mask pattern 110. [

The upper surface of the interlayer insulating layer 140 is not exposed to the surface of the device isolation pattern 107 because the process of recessing the device isolation pattern 107 made of an insulating material is not performed when a portion of the lower side wall of the active pattern 101 is exposed. And can be prevented from being recessed from the upper surface of the separation pattern 107. Therefore, it is possible to prevent the thickness of the interlayer insulating film 140 from decreasing after the gate region 141 is formed. In other words, after the gate region 141 is formed, the height of the gate region 141 can be maintained.

Referring to FIGS. 1, 13A and 13B, a lower side wall of the active pattern 101 exposed in the gate region 141 is oxidized to form a local insulation pattern 151 in the channel region of the active pattern 101 (S60).

According to one embodiment, forming the localized insulating pattern 151 can be performed by an oxidation process that is heat-treated in a gas atmosphere containing oxygen atoms. For example, the oxidation process may be a thermal oxidation process or a radical oxidation process. The thermal oxidation process may be a dry oxidation process using oxygen, a steam oxidation process, ) May be used as a wet oxidation method. As the source gas in the oxidation step, O 2 gas, H 2 O (g) gas (that is, steam), a mixed gas of H 2 and O 2, or a mixed gas of H 2, Cl 2 and O 2 can be used.

Oxygen atoms react with the silicon atoms of the third portion 101c of the active pattern 101 exposed in the gate region 141 to form a silicon oxide film. The width of the local insulation pattern 151 thus formed may be substantially equal to or greater than the width of the active pattern 101. [ Since the local insulation pattern 151 is formed by oxidizing from both side walls of the active pattern 101, it may have a curved upper surface and a lower surface.

14A and 14B, after the formation of the local insulation pattern 151, the oxidation prevention spacer 117, the mask pattern 110, and the like are patterned so that the first portion 101a of the active pattern 101 can be exposed. And the sidewall oxide film 115 can be removed.

The anti-oxidation spacer 117, the mask pattern 110 and the sidewall oxide film 115 can be removed by performing etching processes using an etch recipe having an etch selectivity for the protective spacers 131. In one embodiment, when the anti-oxidation spacer 117 and the residual hard mask pattern 114 are formed of a silicon nitride film, the anti-oxidation spacer 117 and the residual hard mask pattern 114 are etched using an etchant containing phosphoric acid Lt; / RTI > The sidewall oxide film 115 and the oxide film pattern 111 may be removed by an etching process using an etchant containing HF.

According to one embodiment, the sidewall spacers 133 can be prevented from being lost by the protective spacers 131 while removing the anti-oxidation spacer 117, the mask pattern 110 and the sidewall oxide film 115. Therefore, the width of the gate region 141 can be kept substantially equal to the width of the dummy gate pattern 125. [

14A and 14B, a gate insulating film 153 which conformally covers the surface of the first portion 101a of the active pattern 101 is formed.

The gate insulating film 153 may be formed of a high-k film such as hafnium oxide, hafnium silicate, zirconium oxide, or zirconium silicate. This gate insulating film 153 can be conformally formed on the sidewalls and the upper surface of the active pattern 101 using an atomic layer deposition technique. The gate insulating film 153 may be formed by thermally oxidizing the surface of the first portion 101a of the active pattern 101 exposed in the gate region 141. [

Referring to FIGS. 1, 15A and 15B, a gate electrode 160 is formed in a gate region 141 in which a gate insulating film 153 is formed (S70).

According to one embodiment, the gate electrode 160 may extend in a direction transverse to the active pattern 101 (i.e., in the y-axis direction). The gate electrode 160 may be formed in contact with the sidewalls of the local insulation pattern 151. The gate electrode 160 may be formed thicker on the upper surface of the device isolation pattern 107 than on the upper surface of the active pattern 101. [ The gate electrode 160 may include a barrier metal pattern 161 and a metal pattern 163 which are sequentially formed.

The barrier metal pattern 161 may be in direct contact with the protective spacers 131. The barrier metal pattern 161 may be formed of a conductive material having a predetermined work function, and may contribute to adjusting a threshold voltage of the channel region CHR. According to embodiments, the barrier metal pattern 161 may be formed of one of the metal nitrides. For example, the barrier metal pattern 161 may be formed of a metal nitride film such as titanium nitride, tantalum nitride, tungsten nitride, hafnium nitride, and zirconium nitride.

The metal pattern 163 may be formed of one of materials having a lower specific resistance than the barrier metal pattern 161. [ For example, the metal pattern 163 can be formed of any one or a combination of tungsten, copper, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel and conductive metal nitrides have.

According to one embodiment, the gate electrode 160 is formed by sequentially depositing a barrier metal film and a metal film in the gate region 141 in which the gate insulating film 153 is formed, and depositing the barrier metal film and the metal film on the upper surface of the interlayer insulating film 140 And planarizing the metal film and the barrier metal film so as to be exposed.

Here, the barrier metal film and the metal film may be formed using a chemical vapor deposition technique, a physical vapor deposition technique, or an atomic layer deposition technique. The barrier metal film may be deposited to conformally cover the inner wall of the gate region 141. [ That is, the barrier metal film may be formed with a uniform thickness on the gate insulating film 153 exposed on the gate region 141 and on the protective spacer 131. In the planarization process for the barrier metal film and the metal film, the front anisotropic etching process and / or the CMP process may be used.

On the other hand, when the semiconductor device is a CMOS structure, forming the gate electrode 160 includes forming the gate electrode 160 of the NMOSFET and forming the gate electrode 160 of the PMOSFET independently performed thereon .

16 is a perspective view for explaining structural features of a semiconductor device according to embodiments of the present invention.

Referring to FIG. 16, a gate electrode 160 may be disposed across the active pattern 101 extending from the semiconductor substrate 100.

According to one embodiment, the semiconductor substrate 100 may be a bulk silicon wafer, and the active pattern 101 may have a bar shape extending in one direction (i.e., x-axis direction). The active pattern 101 may include source and drain regions on both sides of the channel region CHR and the channel region CHR below the gate electrode 160 from a horizontal viewpoint. The source and drain electrodes 135 may be disposed in the source and drain regions of the active pattern 101. [ According to one embodiment, the source and drain electrodes 135 may be formed of an epitaxial layer grown epitaxially from the active pattern 101.

According to one embodiment, in a vertical view, a local insulation pattern 151 locally formed between the channel region CHR of the active pattern 101 and the semiconductor substrate 101 is disposed. The local insulation pattern 151 can be disposed between the source and drain regions of the active pattern 101 from a horizontal viewpoint. The local insulation pattern 151 may be formed of a silicon oxide film and the width of the local insulation pattern 151 may be substantially equal to or greater than the width of the active pattern 101. [ Further, the upper surface of the localized insulation pattern 151 may be disposed above the upper surface of the element isolation pattern, and the sidewall of the localized insulation pattern 151 may be in contact with the gate electrode 160.

According to one embodiment, the gate electrode 160 may extend in a direction transverse to the active pattern 101 (i.e., in the y-axis direction). The gate electrode 160 may be formed thicker on the upper surface of the device isolation pattern 107 than on the upper surface of the active pattern 101. [ Since the gate electrode 160 covers the sidewall of the local insulation pattern 151, the lowermost surface of the gate electrode 160 may be located below the upper surface of the localized insulation pattern 151. In addition, the gate electrode 160 may include a barrier metal pattern 161 and a metal pattern 163 which are sequentially formed.

A gate insulating layer 153 may be interposed between the gate electrode 160 and the channel region CHR. In one embodiment, the gate insulating film 153 may be formed to surround the channel region CHR of the active pattern 101. [ The gate insulating film 153 may include at least one of the high-k films. For example, the gate insulating film 153 may be formed of at least one of hafnium oxide, hafnium silicate, zirconium oxide, or zirconium silicate.

According to one embodiment, a sidewall spacer 133 is disposed on both sidewalls of the gate electrode 160 and a protective spacer 131 may be interposed between the sidewall spacer 133 and the sidewalls of the gate electrode 160.

In detail, the sidewall spacers 133 may have a conical shape and may be formed of an insulating material. The protective spacers 131 may be formed of an insulating material having an etch selectivity to the sidewall spacers 133 and may have an L shape that covers the sidewalls of the gate electrode 160 and the bottom surface of the sidewall spacers 133 . For example, the sidewall spacers 133 may be formed of silicon nitride or silicon oxynitride, and the protective spacers 131 may be formed of a tantalum oxide film, a titanium oxide film, a hafnium oxide film, a zirconium oxide film, an aluminum oxide film, a yttrium oxide film, An oxide film, an indium oxide film, an iridium oxide film, a barium strontium titanate (BST) film, and a lead zirconate titanate (PZT) film.

17 and 18 are block diagrams schematically illustrating an example of electronic systems including a semiconductor device according to embodiments of the present invention.

Referring to FIG. 17, an electronic system including a semiconductor device according to embodiments of the present invention may be a personal digital assistant (PDA) portable computer, a web tablet, a wireless telephone phone, a mobile phone, a digital music player, a memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

The electronic system 1100 may include a controller 1110, an I / O device 1120, a memory device 1130, an interface 1140, and a bus 1150, bus. The controller 1110, the input / output device 1120, the storage device 1130, and / or the interface 1140 may be coupled to each other via a bus 1150. The bus 1150 corresponds to a path through which data is moved. The controller 1110, the input / output device 1120, the memory device 1130, and / or the interface 1140 may include a semiconductor device according to embodiments of the present invention.

The controller 1110 may include at least one of a microprocessor, a digital signal process, a microcontroller, and logic elements capable of performing similar functions. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The storage device 1130 may store data and / or instructions and the like. The interface 1140 may perform the function of transmitting data to or receiving data from the communication network. Interface 1140 may be in wired or wireless form. For example, the interface 1140 may include an antenna or a wired or wireless transceiver. Although not shown, the electronic system 1100 may further include a high-speed DRAM device and / or an SLAM device as an operation memory device for improving the operation of the controller 1110. [

Figure 18 illustrates a semiconductor device according to embodiments of the present invention may be used to implement a memory system. The memory system 1400 may include a memory device 1410 and a memory controller 1420 for storing large amounts of data. The memory controller 1420 controls the memory element 1410 to read or write the stored data from the memory element 1410 in response to a read / write request of the host 1430. The memory controller 1420 may configure an address mapping table for mapping an address provided by the host 1430, e.g., a mobile device or a computer system, to the physical address of the memory device 1410. The memory element 1410 may include a semiconductor device according to the above-described embodiments of the present invention.

The semiconductor devices disclosed in the above embodiments can be implemented in various types of semiconductor packages. For example, the semiconductor devices according to the embodiments of the present invention may be used in a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package Level Processed Stack Package (WSP) or the like. Furthermore, the package in which the semiconductor device according to the embodiments of the present invention is mounted may further include a controller and / or a logic element for controlling the semiconductor device.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

Claims (10)

An active pattern extending from a semiconductor substrate, said active pattern comprising, from a horizontal viewpoint, source and drain regions and a channel region therebetween;
A vertical insulated pattern locally formed between the channel region of the active pattern and the semiconductor substrate;
A gate electrode crossing a side wall of the localized insulation pattern and the channel region of the active pattern;
Side wall spacers on both sides of the gate electrode; And
And a protective spacer interposed between both sidewalls of the gate electrode and the sidewall spacers and formed of a material having etch selectivity with respect to the sidewall spacers. The method according to claim 1,
Wherein the protection spacer is in direct contact with both side walls of the gate electrode. The method according to claim 1,
Wherein the protection spacer is made of a metal oxide. The method according to claim 1,
And the lowermost surface of the gate electrode is located below the upper surface of the localized insulation pattern. Patterning a semiconductor substrate to form an active pattern;
Forming an anti-oxidation spacer over the top sidewall of the active pattern;
Forming a dummy gate pattern across the active pattern and the anti-oxidation spacer;
Forming protective spacers overlying the sidewalls of the dummy gate pattern, the protection spacers being made of a material having etch selectivity to the antioxidant spacers;
Removing the dummy gate pattern to form a gate region between the protection spacers to expose bottom sidewalls of the active pattern;
Oxidizing a lower sidewall of the active pattern exposed in the gate region to form a localized insulation pattern in the active pattern; And
And forming a gate electrode in the gate region. 6. The method of claim 5,
Before forming the dummy gate pattern,
Further comprising forming a device isolation pattern that is spaced apart from a bottom surface of the anti-oxidation spacer to expose a portion of a lower sidewall of the active pattern. The method according to claim 6,
Wherein the dummy gate pattern is in direct contact with the active pattern between the device isolation pattern and the anti-oxidation spacer. 6. The method of claim 5,
Wherein the gate electrode is in direct contact with a side wall of the localized insulation pattern. 6. The method of claim 5,
The reason why the gate electrode is formed is that,
Removing the anti-oxidation spacer to expose an upper portion of the active pattern; And
And filling the conductive film in direct contact with the protective spacers in the gate region in which the top of the active pattern is exposed. 6. The method of claim 5,
Further comprising forming a sidewall spacer that covers a sidewall of the protection spacer prior to forming the gate region, wherein the sidewall spacer is formed of an insulating material different from the protection spacers.

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