KR20170098370A - Semiconductor device and the method of manufacturing the same - Google Patents

Semiconductor device and the method of manufacturing the same Download PDF

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KR20170098370A
KR20170098370A KR1020160019789A KR20160019789A KR20170098370A KR 20170098370 A KR20170098370 A KR 20170098370A KR 1020160019789 A KR1020160019789 A KR 1020160019789A KR 20160019789 A KR20160019789 A KR 20160019789A KR 20170098370 A KR20170098370 A KR 20170098370A
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South Korea
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pattern
active
active pattern
element isolation
preliminary
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KR1020160019789A
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Korean (ko)
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김상관
박순병
김지영
이상호
정의식
조성학
조창현
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삼성전자주식회사
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Publication of KR20170098370A publication Critical patent/KR20170098370A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32138—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only pre- or post-treatments, e.g. anti-corrosion processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L27/10885—
    • H01L27/10891—

Abstract

A semiconductor device is provided on a substrate and includes a device isolation pattern defining an active pattern wherein the maximum width of the top portion of the active pattern is greater than the minimum width of the bottom portion of the active pattern, And a first bottom surface extending in a direction parallel to the upper surface of the substrate and in contact with the device isolation pattern.

Figure P1020160019789

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device,

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having improved anti-oxidation characteristics of an active pattern and a method of manufacturing the same.

The miniaturization, multifunctionality and / or low manufacturing cost characteristics make semiconductor devices an important element in the electronics industry. Semiconductor devices can be classified into a semiconductor storage device for storing logic data, a semiconductor logic device for computing and processing logic data, and a hybrid semiconductor device including a storage element and a logic element.

In recent years, with the increase in the speed of electronic devices and the reduction of power consumption, a semiconductor device embedded therein is also required to have a high operating speed and / or a low operating voltage. Semiconductor devices are becoming more highly integrated to meet these demanding characteristics. As the degree of integration of the semiconductor device increases, the reliability of the semiconductor device may deteriorate. However, as the electronics industry is highly developed, the demand for high reliability of semiconductor devices is increasing. Therefore, much research has been conducted to improve the reliability of the semiconductor device.

An object of the present invention is to provide a semiconductor device which prevents oxidation of an active pattern.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which prevents tilting of an active pattern.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of easily forming a desired structure on an active pattern.

However, the problem to be solved by the present invention is not limited to the above disclosure.

According to an aspect of the present invention, there is provided a semiconductor device including a device isolation pattern provided on a substrate and defining an active pattern, And the upper portion of the active pattern may include a first bottom surface extending in a direction parallel to the upper surface of the substrate from one side wall of the lower portion of the active pattern and in contact with the device isolation pattern .

In one embodiment, the upper portion of the active pattern extends in a direction parallel to the upper surface of the substrate from the other side wall of the lower portion opposite to the one side wall of the lower portion, and a second bottom surface .

In one embodiment, the top surface of the device isolation pattern may be coplanar with the top surface of the active pattern.

In one embodiment, the top surface of the device isolation pattern may be located at a level lower than the top surface of the active pattern from the top surface of the substrate.

In one embodiment, a word line is penetrated through the active pattern; A bit line electrically connected to the active pattern; And a data storage element electrically coupled to the active pattern.

In one embodiment, a gate insulating pattern interposed between the word line and the active pattern; And a first capping pattern provided on the word line, wherein the word line may be electrically isolated from the active pattern.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: etching a substrate to form active patterns; Forming a first preliminary element isolation pattern surrounding the lower portions of the active patterns; Forming an oxidation-preventive film conformally covering side walls and an upper surface of each of the active patterns on the first preliminary element isolation pattern; And forming a second preliminary element isolation layer on the oxidation prevention layer, wherein the first preliminary element isolation pattern and the second preliminary element isolation layer may include the same material.

In one embodiment, the oxidation-preventive film may be a polysilicon film.

In one embodiment, the method further comprises performing a heat treatment on the second preliminary element isolation layer, wherein after the heat treatment process, the oxidation barrier layer adjacent to the first preliminary element isolation pattern and the second preliminary element isolation layer includes a silicon oxide layer, The oxidation-preventive film adjacent to the active pattern may include a silicon film having the same crystal structure as the active pattern.

In one embodiment, the thickness of the oxidation-prevention film immediately adjacent to the first preliminary element isolation pattern may be thinner than the thickness of the oxidation-prevention film immediately adjacent to the respective side walls and the upper surface of the active patterns.

According to the concept of the present invention, the first preliminary element isolation pattern fills the bottom of the trench between the preliminary active patterns, and then the antioxidant film covers the preliminary active patterns. The first preliminary element isolation pattern can support the preliminary active patterns so as not to be tilted toward the sidewall. The oxidation-preventive film can prevent the oxidation of the preliminary active patterns.

According to the concept of the present invention, the top of the active pattern can protrude in the sidewall direction. From a planar viewpoint, the active pattern may have a larger area when the top of the active pattern protrudes than when it did not protrude.

1 is a plan view of a substrate structure according to an embodiment of the present invention.
2 is a cross-sectional view of a substrate structure according to an embodiment of the present invention, taken along line I-I 'and II-II' in FIG.
FIGS. 3 to 7 are sectional views for explaining a substrate structure according to an embodiment of the technical idea of the present invention, corresponding to lines I-I 'and II-II' of FIG.
8 is a plan view of a semiconductor device according to an embodiment of the present invention.
9 and 10 are cross-sectional views of a semiconductor device according to an embodiment of the present invention, taken along line III-III 'and line IV-IV' in FIG.

In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It will be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

In this specification, when an element is referred to as being on another element, it may be directly formed on another element, or a third element may be interposed therebetween. Further, in the drawings, the thickness of the components is exaggerated for an effective description of the technical content. The same reference numerals denote the same elements throughout the specification.

Embodiments described herein will be described with reference to cross-sectional views and / or plan views that are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention. Although the terms first, second, third, etc. in the various embodiments of the present disclosure are used to describe various components, these components should not be limited by these terms. These terms have only been used to distinguish one component from another. The embodiments described and exemplified herein also include their complementary embodiments.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. The terms "comprises" and / or "comprising" used in the specification do not exclude the presence or addition of one or more other elements.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a substrate structure according to an embodiment of the present invention. 2 is a cross-sectional view of a substrate structure according to an embodiment of the present invention, taken along line I-I 'and II-II' in FIG.

1 and 2, a substrate 100 may be provided. The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a compound semiconductor substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium substrate, or a gallium arsenide (GaAs) substrate.

The active pattern 200 may be provided on the substrate 100. The active pattern 200 may provide a region where electrical elements are formed. From a plan viewpoint, the active pattern 200 may have an island shape extending in a third direction D3 that intersects both the first direction D1 and the second direction D2. The first direction D1 to the third direction D3 may be directions parallel to the upper surface 102 of the substrate 100. The active pattern 200 may have a top surface 226 parallel to the top surface 102 of the substrate 100. The active pattern 200 may protrude from the top surface 102 of the substrate 100. For example, the active pattern 200 may protrude from the top surface 102 of the substrate 100 in a fourth direction D4 perpendicular to the top surface 102 of the substrate 100.

The active pattern 200 may include an upper portion 220 provided on a lower portion 210 and a lower portion 210 immediately adjacent to the substrate 100. The width of the lower portion 210 of the active pattern 200 may vary depending on the height. For example, the lower portion 210 of the active pattern 200 may have a decreasing width away from the substrate 100. The width may be defined as the distance along the direction parallel to the top surface 102 of the substrate 100 and the height may be defined as the distance along the direction D4 perpendicular to the top surface 102 of the substrate 100. The width of the lower portion 210 of the active pattern 200 may be the smallest at a portion farthest from the upper surface 102 of the substrate 100. The lower portion 210 of the active pattern 200 may include a pair of lower sidewalls 212 facing each other. The pair of lower sidewalls 212 may extend in a fourth direction D4 or may extend in a direction inclined in a fourth direction D4. For example, each of the pair of lower sidewalls 212 extends in a tilted direction in the fourth direction D4, so that the distance between the pair of lower sidewalls 212 along the first direction D1, The distance from the upper surface 102 of the substrate 100 can be narrowed. The distance between the pair of lower sidewalls 212 along the first direction D1 may be smallest at a portion farthest from the top surface 102 of the substrate 100. [

The width of the top portion 220 of the active pattern 200 may vary with height. For example, the upper portion 220 of the active pattern 200 may have a decreasing width away from the substrate 100. The width of the upper portion 220 of the active pattern 200 may be the largest at the portion closest to the upper surface 102 of the substrate 100. The maximum width of the top portion 220 of the active pattern 200 may be greater than the minimum width of the bottom portion 210 of the active pattern. The upper portion 220 of the active pattern 200 may have a pair of upper sidewalls 222 that are opposite to each other. The pair of upper sidewalls 222 may extend in the fourth direction D4 or may extend in the tilted direction in the fourth direction D4. For example, the pair of upper sidewalls 222 each extend in a tilted direction in the fourth direction D4, so that the distance between the pair of upper sidewalls 222 along the first direction D1, The distance from the upper surface 102 of the substrate 100 can be narrowed. The distance between the pair of upper sidewalls 222 along the first direction D1 may be the largest at the portion closest to the upper surface 102 of the substrate 100. [ Each of the pair of upper sidewalls 222 may be parallel to the immediately adjacent lower sidewall 212. The upper portion 220 of the active pattern 200 includes a first bottom surface 224a connecting one of the pair of upper sidewalls 222 and a lower sidewall 212 immediately adjacent thereto and a pair of upper sidewalls 222 And a second bottom surface 224b connecting the other of the first and second sidewalls 212 and 212 adjacent thereto. The bottom surface 224 of the top 220 of the active pattern 200 may be parallel to the top surface 102 of the substrate 100. The bottom surface 224 of the top 220 of the active pattern 200 may extend around the perimeter of the active pattern 200. For example, the bottom surface 224 of the top portion 220 of the active pattern 200 may have a ring shape surrounding the active pattern 200. The active pattern 200 may be provided in a plurality, and in a plan view, the plurality of active patterns 200 may be spaced apart from each other by the device isolation pattern 300.

A device isolation pattern 300 may be provided between a pair of active patterns 200 immediately adjacent to each other. The device isolation pattern 300 can electrically isolate the active patterns 200 from each other. The device isolation pattern 300 may fill between a pair of adjacent active patterns 200 immediately adjacent to each other. The device isolation pattern 300 may be in contact with the bottom surface 224 of the top portion 220 of the active pattern 200. The top surface of the element isolation pattern 300 may be substantially coplanar with the top surfaces 226 of the active patterns 200. [ The device isolation pattern 300 may surround the active patterns 200. The device isolation pattern 300 may include an insulating material. In one example, device isolation pattern 300 may comprise silicon oxide, silicon nitride, and / or silicon oxynitride. For example, the element separation pattern 300 may include SiO 2. The device isolation pattern 300 can electrically isolate the active patterns 200 from each other. The active pattern 200 may include an upper portion 220 that extends horizontally from a lower portion 210 thereof along a direction parallel to an upper surface 102 of the substrate 100. Thus, in plan view, the area of the active pattern 200 can be maximized.

Hereinafter, a manufacturing method will be described with reference to the drawings.

FIGS. 3 to 7 are sectional views for explaining a substrate structure according to an embodiment of the technical idea of the present invention, corresponding to lines I-I 'and II-II' of FIG.

Referring to FIGS. 1 and 3, preliminary active patterns 110 may be formed on a substrate 100. The preliminary active patterns 110 may be formed by etching the substrate 100 using an etch mask. For example, the etching process of the substrate 100 may be a dry etching process using an etching gas. Through the etching process of the substrate 100, the trenches 120 can be formed between the pair of preliminary active patterns 110 immediately adjacent to each other. The trench 120 may define the preliminary active patterns 110.

Referring to FIGS. 1 and 4, a first preliminary element isolation pattern 310 filling a portion of the trench 120 may be formed. The first preliminary element isolation pattern 310 may be formed by forming a first preliminary element isolation layer (not shown) on the substrate 100 and the preliminary active pattern 110 and then removing a part of the first preliminary element isolation layer have. In one example, a first preliminary device isolation layer may be deposited and formed on the substrate 100 and the preliminary active pattern 110. The deposition of the first preliminary element isolation layer may be performed using a chemical vapor deposition (CVD) method or a physical vapor deposition (PVD) method. For example, the deposition process of the first preliminary device isolation film can be performed using APCVD, LPCVD, PECVD, or HDPVD. The first preliminary device isolation layer may cover the preliminary active patterns 110 and fill the trenches 120. The first preliminary element isolation film may include an insulating material. In one example, the first preliminary element isolation film may comprise silicon oxide, silicon nitride, and / or silicon oxynitride. For example, the first preliminary element isolation film may be a SiO 2 film.

The first preliminary element isolation patterns 310 may be formed by etching the upper portions of the first preliminary element isolation layers. The etching process of the first preliminary device isolation film can be performed using wet etching or dry etching. For example, the etching of the first preliminary element isolation layer may be performed using a wet etching process using an etchant (for example, HF) for selectively etching the first preliminary element isolation layer. The first preliminary device isolation film may be etched to expose the top surfaces 116 and sidewalls 112 of the preliminary active patterns 110. [ Each top surface 316 of the first preliminary device isolation patterns 310 may be located at a lower level from the substrate 100 than the top surface 116 of each of the preliminary active patterns 110. [ Accordingly, the first preliminary element isolation patterns 310 can expose the sidewalls 112 on top of each of the preliminary active patterns 110. The sidewalls 312 of the first preliminary element isolation patterns 310 may be in direct contact with the sidewalls 112 of the active pattern 110. The sidewalls 312 of the first preliminary element isolation patterns 310 may be in direct contact with the upper surface 102 of the substrate 100.

Referring to FIGS. 1 and 5, an oxidation-preventive film 330 provided on the preliminary active pattern 110 and extending into the trench 120 may be formed. In one example, the oxidation preventing film 330 is formed on the upper surface 116 of the preliminary active pattern 110, a part of the side wall 112 of the preliminary active pattern 110, and the upper surface 316 of the first preliminary element isolation pattern 310 ) Can be conformally covered. The oxidation preventing film 330 may be formed on the preliminary active pattern 110 and the first preliminary element isolation pattern 310 by deposition. The deposition process of the oxidation preventing film 330 may be performed using CVD or PVD. The thickness t1 of one portion of the oxidation preventing film 330 contacting the top surface 316 of the first preliminary element isolation pattern 310 is greater than the thickness t1 of the one portion of the oxidation preventing film 330 contacting the preliminary active pattern 110. [ As shown in FIG. For example, the thickness t1 of a portion of the oxidation preventing film 330 contacting the top surface 316 of the first preliminary element isolation pattern 310 may be smaller than the thickness t1 of the oxidation preventive film 110 contacting the top surface 116 of the preliminary active pattern 110 0.0 > t2 < / RTI > A part of the oxidation preventing film 330 contacting the upper surface 316 of the first preliminary element isolation pattern 310 may be changed to an oxide film and the active pattern 110 may be removed, The oxidation preventing film 330 in contact with the active pattern 110 can be changed into a film having the same material and the same crystal structure as the active pattern 110. [ The oxidation preventing film 330 may be a silicon (Si) based film. For example, the oxidation preventing film 330 may be a polysilicon film. The oxidation prevention film 330 can prevent the preliminary activation pattern 110 from being oxidized.

Referring to FIGS. 1 and 6, a second preliminary isolation layer 350 may be formed on the anti-oxidation layer 330 to fill the remaining portion of the trench 120. The second preliminary element isolation layer 350 may cover the entire surface of the substrate 100. The second preliminary element isolation layer 350 may be formed by depositing on the oxidation prevention layer 330. The deposition process of the second preliminary device isolation film 350 may be performed using CVD or PVD. The second preliminary element isolation layer 350 may include an insulating material. In one example, the second preliminary element isolation film 350 may include silicon oxide, silicon nitride, and / or silicon oxynitride. For example, the second spare element isolation layer 350 may be formed of SiO 2 It can be a membrane.

In one embodiment, the oxidation-preventive film 330 is a film that is heat-treated in the deposition process of the second preliminary element isolation film 350 and contains substantially the same material and the same crystal structure as the film or pattern adjacent to the oxidation- Can change. For example, when the first preliminary element isolation pattern 310 is a silicon dioxide (SiO 2 ) pattern and the oxidation prevention layer 330 is a polysilicon layer, the oxidation barrier layer 330 ) Can be changed to a silicon dioxide (SiO 2 ) film. For example, in the case where the preliminary active pattern 110 is a single crystal silicon (Si) pattern and the oxidation preventing film 330 is a polysilicon (Si) film, a part of the oxidation preventing film 330 immediately adjacent to the preliminary activating pattern 110 May be changed to a single crystal silicon (Si) film. For example, in the case where the second spare element isolation layer 350 is a silicon dioxide (SiO 2 ) layer and the oxidation prevention layer 330 is a polysilicon layer, the oxidation resistance of the oxidation prevention layer 330 immediately adjacent to the second spare element isolation layer 350 One portion can be converted to a silicon dioxide (SiO 2 ) film. Thus, the boundary 358 between the single crystal silicon (Si) film and the silicon dioxide (SiO 2 ) film can be formed in the oxidation preventing film 330. The oxidation preventing film 330 may be changed to another film at about 890 캜. In one embodiment, the temperature in the chamber (not shown) in which the CVD process is performed can be increased to about 900 ° C., so that the oxidation-preventive film 330 is formed by the deposition process of the second preliminary isolation film 350, Can be changed to membranes containing substantially the same materials and structures.

Referring to FIGS. 1 and 7, active patterns 200 may be defined on a substrate 100 according to the process described with reference to FIG. Specifically, the active patterns 200 include a lower portion 210 and an upper portion 220, and the upper portion 220 of the active pattern 200 includes an oxidation prevention layer (not shown) having the same material and the same crystal structure as the preliminary active pattern 330). ≪ / RTI > A part of the oxidation preventing film may include a material substantially the same as the preliminary active pattern by the deposition process of the second preliminary separation layer 350 as described above. Each upper portion 220 of the active patterns 200 may have a width greater than the top of the pre-active pattern described with reference to Figures 3-6 along the first direction D1. Each of the top surfaces 226 of the active patterns 200 may be located at a higher level from the substrate 100 along the fourth direction D4 than the top surface of the spare active pattern described with reference to Figures 3-6 have.

Hereinafter, the element isolation layer 370 is formed by stacking a first preliminary element isolation pattern 310, a second preliminary element isolation layer 350, a first preliminary element isolation pattern 310 and a second preliminary element isolation layer 350, Lt; RTI ID = 0.0 > 330 < / RTI > At this time, the portions of the oxidation preventing layer 330 may include the same materials as the first preliminary element isolation patterns 310 and the second preliminary element isolation layers 350. The device isolation film 370 may cover the active patterns 200 and the substrate 100. The device isolation film 370 may include an insulating material. In one example, the device isolation film 370 may comprise silicon oxide, silicon nitride, and / or silicon oxynitride. For example, the device isolation film 370 may be formed of SiO 2 . ≪ / RTI >

Referring again to FIGS. 1 and 2, the device isolation pattern 300 may be formed by etching the device isolation film 370 described with reference to FIG. The etching process of the device isolation film 370 described with reference to FIG. 7 may be performed using wet etching or dry etching. For example, the etching process of the device isolation film 370 described with reference to FIG. 7 can be performed using a wet etching process using an etchant (for example, HF) that selectively etches the device isolation film 370 have. The upper surface 226 of each upper portion 220 of the active patterns 200 can be exposed by etching the element isolation film 370 described with reference to FIG.

In general, in the case where the first preliminary element isolation pattern is not formed, in the oxidation prevention film formation step described with reference to Fig. 5, the oxidation preventive film can conformally cover the upper surface and sidewalls of the preliminary active pattern, have. When the interval between the preliminary active patterns is narrow, in the deposition process of the oxidation preventing film, the preliminary active pattern may not be provided at the required position. For example, in the process of depositing the oxidation-preventive film, the preliminary active pattern may be inclined in a direction parallel to the upper surface of the substrate. According to the concept of the present invention, the first preliminary element isolation pattern is provided below the trench so that the preliminary active pattern may not be tilted. Thus, a method of manufacturing a substrate structure that prevents oxidation of an active pattern and inclination of an active pattern can be provided.

8 is a plan view of a semiconductor device according to an embodiment of the present invention. 9 and 10 are cross-sectional views of a semiconductor device according to an embodiment of the present invention, taken along line III-III 'and line IV-IV' in FIG. For brevity of description, substantially the same explanations as those described with reference to Figs. 1 and 2 are omitted.

8-10, a device isolation pattern 300 defining active patterns 200 on a substrate 100 may be provided. The substrate 100, the active patterns 200, and the device isolation pattern 300 may be substantially the same as those described with reference to FIGS.

The upper surface 302 of the element isolation pattern 300 is separated from the upper surface 202 of the active patterns 200 from the substrate 100 along the fourth direction D4 perpendicular to the upper surface of the substrate 100. In this case, Lt; RTI ID = 0.0 > level. ≪ / RTI > The upper portion of the active pattern 200 may protrude from the lower portion thereof in a direction parallel to the upper surface of the substrate 100. [ Thus, in plan view, the area of the active pattern 200 can be maximized.

Word lines WL extending in a first direction D1 parallel to the top surface of the substrate 100 may be provided. The word lines WL may penetrate the active patterns 200 and the device isolation pattern 300. The upper surfaces of the word lines WL are spaced apart from the uppermost surfaces of the active patterns 200 and the uppermost surface of the element isolation patterns 300 in the fourth direction D4 perpendicular to the upper surface of the substrate 100 It can therefore have a lower level. The word lines WL may be buried gate lines 420. Embedded gate lines 420 may be gates embedded within active patterns 200. In one example, a pair of buried gate lines 420 may be provided in one active pattern 200. Embedded gate lines 420 may comprise a conductive material. For example, the buried gate lines 420 may be formed of a doped semiconductor material (doped silicon, doped germanium, etc.), a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal (tungsten, titanium, tantalum, etc.) And a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.).

A gate insulation pattern 410 may be interposed between each of the buried gate lines 420 and each of the active patterns 200 immediately adjacent thereto. The gate insulator pattern 410 may cover the bottom surface of the buried gate line and extend over the sidewalls. The gate insulating pattern 410 may electrically isolate the buried gate line 420 and the active pattern 200 from each other. In one example, the gate insulator pattern 410 may comprise an oxide, a nitride, and / or an oxynitride.

In one embodiment, the gate insulator pattern 410 may conformally cover the top surface 302 of the device isolation pattern 300 and the top surface 202 of the active patterns 200. A buried gate line 420 may be provided on the gate insulator pattern 410 to cover the gate insulator pattern 410. The upper surface of the embedding gate line 420 may be parallel to the upper surface of the substrate 100. A first capping pattern 430 may be provided on each of the buried gate lines 420. The first capping pattern 430 may cover the top surface of the buried gate line 420. For example, the first capping pattern 430 may be in contact with the top surface of the buried gate line 420. The sidewalls of the first capping pattern 430 may contact the inner walls of the active pattern 200. The top surface of the first capping pattern 430 may be substantially coplanar with the top surface of the active pattern 200 and the top surface of the device isolation pattern 300. The first capping pattern 430 may electrically isolate the embedded gate line 420 and the elements provided on the active pattern 200 and protect the embedded gate line 420. In one example, the first capping pattern 430 may comprise silicon oxide, silicon nitride, and / or silicon oxynitride.

The first and second source / drain regions SD1 and SD2 may be provided in the active pattern 200 immediately adjacent to the sidewalls of the pair of buried gate lines 420 provided in the active pattern 200 . The first and second source / drain regions SD1 and SD2 may be formed by implanting impurities. The first source / drain region SD1 may be provided between a pair of buried gate lines 420 provided in the active pattern 200. [ The second source / drain regions SD2 may be located opposite the first source / drain regions SD1 with the buried gate line 420 therebetween. The first and second source / drain regions SD1 and SD2 may have the same conductivity type. For example, the first and second source / drain regions SD1 and SD2 may all be n-type or all p-type. In one example, the first and second source / drain regions SD1 and SD2 may have a conductivity type opposite that of the active pattern 200. [ For example, when the active pattern 200 is an n-type, the first and second source / drain regions SD1 and SD2 may be p-type. The first source / drain region SD1 and the second source / drain region SD2 may have opposite functions. For example, when the first source / drain region SD1 is the source region, the second source / drain regions SD2 may be the drain regions. Conversely, when the first source / drain region SD1 is a drain region, the second source / drain regions SD2 may be source regions. The substrate 100, the active pattern 200, the device isolation pattern 300, the embedded gate line 420, the gate insulation pattern 410, the first capping pattern 430, and the first and second source / (SD1, SD2) may be defined as the substrate structure 1000.

A first pad 510 may be provided on the first source / drain region SD1 and a second pad 520 may be provided on each of the second source / drain regions SD2. The first and second pads 510 and 520 may cover the first and second source / drain regions SD1 and SD2, respectively. The first and second pads 510 may be electrically connected to the first and second source / drain regions SD1 and SD2, respectively. From a plan viewpoint, the first and second pads 510, 520 may have substantially the same area or larger area than the first and second source / drain regions SD1, SD2, respectively. Accordingly, the first and second pads 510 and 520 may cover all of the first and second source / drain regions SD1 and SD2, respectively. The first and second pads 510 and 520 may comprise a conductive material. For example, the first and second pads 510 and 520 may comprise a doped semiconductor material (e.g., doped polysilicon) or a metal.

A first interlayer insulating film 530, a second interlayer insulating film 580, and a protective film 590 stacked in this order on the first and second pads 510 and 520 may be provided. The first interlayer insulating film 530 may cover the substrate structure 1000 and the first and second pads 510 and 520. The second interlayer insulating film 580 may cover the first interlayer insulating film 530. The protective film 590 may cover the second interlayer insulating film 580. The first and second interlayer insulating films 530 and 580 and the protective film 590 may include an insulating material. For example, the first and second interlayer insulating films 530 and 580 and the protective film 590 may include silicon oxide, silicon nitride, and / or silicon oxide. The upper surfaces of the first and second interlayer insulating films 530 and 580 and the protective film 590 may be parallel to the upper surface of the substrate structure 1000.

The bit lines BL may be provided on the first interlayer insulating film 530 through the second interlayer insulating film 580. [ Each of the bit lines BL may extend in a second direction D2 parallel to the top surface of the substrate structure 1000 and intersecting the first direction D1. For example, each of the bit lines BL may be parallel to the top surface of the substrate structure 1000 and extend in a direction perpendicular to the first direction D1. The bit lines BL may comprise a conductive material. For example, the bit lines BL may be formed of a doped semiconductor material (doped silicon, doped germanium, etc.), a conductive metal nitride (such as titanium nitride or tantalum nitride), a metal (tungsten, titanium, tantalum, - a semiconductor compound (tungsten suicide, cobalt suicide, titanium suicide, etc.).

A second capping pattern 570 may be provided on each of the bit lines BL. The second capping pattern 570 may electrically isolate the bit line BL from other components and protect the bit line BL. Insulating spacers 560 may be provided on both sidewalls of bit line BL, respectively. Each of the insulating spacers 560 may cover the immediately adjacent sidewall of the bit line BL and may extend on the immediately adjacent sidewalls of the second capping pattern 570. [ Insulation spacers 560 may electrically isolate bit line BL from other components. The second capping pattern 570 and the insulating spacers 560 may comprise an insulating material. For example, the second capping pattern 570 and the insulating spacers 560 may comprise silicon oxide, silicon nitride, and / or silicon oxynitride.

A first contact 540 may be provided between each of the bit lines BL and the first pad 510. The first contact 540 may electrically connect the bit line BL and the first pad 510. The first contact 540 may comprise a conductive material. For example, the first contact 540 may be formed of a material selected from the group consisting of a doped semiconductor material (doped silicon, doped germanium, etc.), a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal (tungsten, titanium, tantalum, - a semiconductor compound (tungsten suicide, cobalt suicide, titanium suicide, etc.).

A data storage element 600 may be provided on the protective film 590. The data storage element 600 may be implemented in various forms. In one example, the data storage element 600 may be a capacitor (not shown). The capacitor may include a lower electrode, a dielectric layer, and an upper electrode. In one example, the data storage element 600 may include a variable resistor (not shown). For example, the variable resistor may include a phase change material. The phase change material may include at least one selected from the group consisting of tellurium (Te) and selenium (Se), which are chalcogenide elements. The phase change material may be selected from the group consisting of germanium (Ge), antimony (Sb), bismuth (Bi), lead (Pb), tin (Sn), silver (Ag), arsenic (As) , Oxygen (O), and nitrogen (N). For example, the phase-change material may be selected from the group consisting of Ge-Sb-Te, As-Sb-Te, As-Ge-Sb-Te, Sn-Sb- At least one element selected from the group consisting of element-Sb-Te, Group 6A element -Sb-Te, Group 5A element -Sb-Se and Group 6A element -Sb-Se. For example, the variable resistor may be a magnetic tunnel junction (MTJ) pattern (not shown). The magnetic tunnel junction (MTJ) pattern may include a free layer, a reference layer, and a tunnel barrier layer disposed between the free layer and the reference layer. The magnetization direction of the free layer can be changed. The reference layer may have a fixed magnetization direction.

A second contact 550 may be provided between each of the data storage elements 600 and each of the second pads 510. [ The second contact 550 may electrically couple the data storage elements 600 to the second pads 550. The second contact 550 may comprise a conductive material. For example, the second contact 550 may be formed from a doped semiconductor material (doped silicon, doped germanium, etc.), a conductive metal nitride (such as titanium nitride or tantalum nitride), a metal (such as tungsten, titanium, or tantalum) - a semiconductor compound (tungsten suicide, cobalt suicide, titanium suicide, etc.).

The foregoing description of embodiments of the present invention provides illustrative examples for the description of the present invention. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the appended claims. It is clear.

100: substrate
110: preliminary active pattern
200: active pattern
212: Lower side wall
222: upper side wall
224a, 224b: a first bottom surface, a second bottom surface
300: Device isolation pattern
310, 350: a first preliminary element isolation pattern, a second preliminary element isolation film
330: oxidation prevention film
370: Element isolation film

Claims (10)

A device isolation pattern provided on the substrate, the device isolation pattern defining an active pattern,
Wherein the maximum width of the upper portion of the active pattern is larger than the minimum width of the lower portion of the active pattern,
Wherein the upper portion of the active pattern comprises a first bottom surface extending in a direction parallel to an upper surface of the substrate from one side wall of the lower portion of the active pattern and in contact with the device isolation pattern. The method according to claim 1,
And the upper portion of the active pattern includes a second bottom surface extending in a direction parallel to the upper surface of the substrate from the other side wall of the lower portion opposite to the one side wall of the lower portion and in contact with the device isolation pattern. The method according to claim 1,
Wherein an upper surface of the element isolation pattern is coplanar with an upper surface of the active pattern. The method according to claim 1,
And the upper surface of the element isolation pattern is located at a lower level than the upper surface of the active pattern from the upper surface of the substrate. The method according to claim 1,
A word line passing through the active pattern;
A bit line electrically connected to the active pattern; And
And a data storage element electrically connected to the active pattern. 6. The method of claim 5,
A gate insulating pattern interposed between the word line and the active pattern; And
Further comprising a first capping pattern provided on the word line,
Wherein the word line is electrically separated from the active pattern. Etching the substrate to form active patterns;
Forming a first preliminary element isolation pattern surrounding the lower portions of the active patterns;
Forming an oxidation-preventive film conformally covering side walls and an upper surface of each of the active patterns on the first preliminary element isolation pattern; And
And forming a second preliminary element isolation layer on the oxidation prevention layer,
Wherein the first preliminary element isolation pattern and the second preliminary element isolation film comprise the same material. 8. The method of claim 7,
Wherein the oxidation preventing film is a polysilicon film. 8. The method of claim 7,
Further comprising annealing the oxidation preventing film,
After the heat treatment process, the oxidation preventing layer adjacent to the first preliminary element isolation pattern and the second preliminary element isolation layer includes a silicon oxide layer,
Wherein the oxidation prevention film adjacent to the active pattern comprises a silicon film having the same crystal structure as the active pattern. 8. The method of claim 7,
Wherein the thickness of the oxidation preventing layer immediately adjacent to the first preliminary element isolation pattern is thinner than the thickness of the oxidation preventing layer immediately adjacent to the side walls and the upper surface of each of the active patterns.
KR1020160019789A 2016-02-19 2016-02-19 Semiconductor device and the method of manufacturing the same KR20170098370A (en)

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