KR20170097322A - Semiconductor device - Google Patents

Abstract

Provided is a semiconductor device capable of improving a performance of the device by variously controlling a threshold voltage of a transistor having a gate all-around structure. The semiconductor device comprises: a substrate including first and second areas; a first wire pattern on the substrate of the first area, staying away from the substrate; a second wire pattern on the substrate of the second area, staying away from the substrate and the first wire pattern; a first gate electrode crossing with the first wire pattern, and overlapped with the first wire pattern as much as a first width; and a second gate electrode crossing with the second wire pattern, and overlapped with the second wire pattern as much as a second width different from the first width.

Description

[0001]

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a gate all around structure.

As one of scaling techniques for increasing the density of semiconductor devices, a gate allround structure has been proposed in which a silicon body in the shape of a nanowire is formed on a substrate and a gate is formed to surround the silicon body .

Since the gate all-around structure uses a three-dimensional channel, scaling is easy. Also, the current control capability can be improved without increasing the length of the gate. In addition, the short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device capable of improving the device performance by variously adjusting the threshold voltage of a transistor having a gate all around structure.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a substrate including a first region and a second region; A first wire pattern spaced apart from the substrate on the substrate in the first region; A second wire pattern spaced apart from the substrate and the first wire pattern on the substrate of the second region; A first gate electrode crossing the first wire pattern and overlapping the first wire pattern by a first width; And a second gate electrode crossing the second wire pattern and overlapping the second wire pattern by a second width different from the first width.

In some embodiments of the present invention, the first width is a width in which the first gate electrode and the first wire pattern overlap with each other between the first wire pattern and the substrate, And the width of the second gate electrode and the second wire pattern overlap with each other.

In some embodiments of the present invention, a first gate spacer positioned at both ends of the first wire pattern, a second gate spacer positioned at both ends of the second wire pattern, and a second gate spacer disposed on both sides of the first wire pattern And a second epitaxial pattern disposed on both sides of the second wire pattern, wherein the first gate electrode is disposed between the first gate spacers, and the second gate electrode is disposed between the first gate electrode and the second gate electrode, And is disposed between the second gate spacers.

In some embodiments of the present invention, the width of the first gate spacer interposed between the first epitaxial pattern and the first gate electrode, between the substrate and the first wire pattern, And the width of the second gate spacer between the second epitaxial pattern and the second gate electrode between the patterns.

In some embodiments of the present invention, the device further comprises a first gate insulating film between the first gate spacer and the first gate electrode, and a second gate insulating film between the second gate spacer and the second gate electrode, The thickness of the first gate insulating film is different from the thickness of the second gate insulating film.

In some embodiments of the present invention, the first gate spacer comprises an inner spacer located between the first wire pattern and the substrate, and an outer spacer located on the first wire pattern, Outer spacers and other materials.

In some embodiments of the present invention, the first gate spacer defines a first trench, the second gate spacer defines a second trench, and along a sidewall of the first trench and a periphery of the first wire pattern And a second gate insulating film extending along the sidewalls of the second trench and around the second wire pattern.

In some embodiments of the present invention, on the first wire pattern of the first region, a third wire pattern intersecting the first gate electrode, and on the second wire pattern of the second region, And a fourth wire pattern intersecting the two gate electrodes.

In some embodiments of the present invention, the width at which the first gate electrode and the first wire pattern overlap between the first wire pattern and the substrate is smaller than the width of the first wire pattern, 1 gate electrode and the first wire pattern are overlapped with each other, and a width at which the second gate electrode and the second wire pattern overlap each other between the second wire pattern and the substrate, Pattern is substantially the same as the width at which the second gate electrode and the second wire pattern overlap between the pattern and the fourth wire pattern.

In some embodiments of the present invention, the width at which the first gate electrode and the first wire pattern overlap between the first wire pattern and the substrate is smaller than the width of the first wire pattern, 1 gate electrode and the first wire pattern are overlapped with each other, and a width at which the second gate electrode and the second wire pattern overlap each other between the second wire pattern and the substrate, And the width of the fourth wire pattern is larger than the width of the second gate electrode and the second wire pattern overlapping each other.

In some embodiments of the present invention, the height of the first gate electrode between the first wire pattern and the substrate is substantially equal to the height of the first gate electrode between the first wire pattern and the third wire pattern And the height of the second gate electrode between the second wire pattern and the substrate is substantially equal to the height of the second gate electrode between the second wire pattern and the fourth wire pattern.

In some embodiments of the present invention, the height of the first gate electrode between the first wire pattern and the substrate is greater than the height of the first gate electrode between the first wire pattern and the third wire pattern, The height of the second gate electrode between the second wire pattern and the substrate is larger than the height of the second gate electrode between the second wire pattern and the fourth wire pattern.

In some embodiments of the present invention, an interlayer insulating film is further formed on the substrate of the first region and the second region, and the upper surface of the interlayer insulating film in the first region is flush with the upper surface of the first gate electrode And the upper surface of the interlayer insulating film in the second region lies on the same plane as the upper surface of the second gate electrode.

In some embodiments of the present invention, the substrate includes a semiconductor substrate and an insulating film substrate formed on the semiconductor substrate.

In some embodiments of the present invention, the apparatus further comprises a first pin-shaped protrusion and a second pin-shaped protrusion protruding from an upper surface of the substrate and spaced apart from each other, the first wire pattern being vertically overlapped with the first pin- , And the second wire pattern vertically overlaps with the second pin-shaped protrusion.

In some embodiments of the present invention, in the longitudinal section of the first wire pattern, the thickness of the first wire pattern is constant along the distance from the first gate spacer.

In some embodiments of the present invention, in the longitudinal section of the first wire pattern, the thickness of the first wire pattern decreases with distance from the first gate spacer.

In some embodiments of the present invention, in the longitudinal section of the first wire pattern, the first wire pattern includes a first portion having a first thickness and a second portion having a second thickness less than the first thickness, , The first portion of the first wire pattern is disposed on both sides of the second portion of the first wire pattern.

In some embodiments of the present invention, the cross section of the first wire pattern is one of a figure composed of a combination of straight lines, a figure composed of a combination of straight lines and curves, and a figure composed of a combination of curves.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a substrate including a first region and a second region; A first wire pattern spaced apart from the substrate on the substrate in the first region; A second wire pattern spaced apart from the first wire pattern on the first wire pattern; A third wire pattern spaced apart from the substrate on the substrate in the second region; A fourth wire pattern spaced apart from the third wire pattern on the third wire pattern; A first gate spacer positioned at both ends of the first wire pattern and the second wire pattern; A second gate spacer located at both ends of the third wire pattern and the fourth wire pattern, the distance between the third wire pattern and the fourth wire pattern being spaced apart from the second gate pattern, A second gate spacer between the second wire patterns, the first gate spacer being smaller than the spaced distance; A first gate electrode intersecting the first wire pattern and the second wire pattern between the first gate spacers; And a second gate electrode intersecting the third wire pattern and the fourth wire pattern, between the second gate spacer.

In some embodiments of the present invention, the semiconductor device further includes a first epitaxial pattern disposed on both sides of the first gate electrode and a second epitaxial pattern disposed on both sides of the second gate electrode, And the width of the first gate spacer interposed between the first epitaxial pattern and the first gate electrode between the second wire pattern is larger than the width of the second epitaxial pattern between the third wire pattern and the fourth wire pattern, Is smaller than the width of the second gate spacer interposed between the first gate electrode and the second gate electrode.

In some embodiments of the present invention, the width of the first gate spacer interposed between the first epitaxial pattern and the first gate electrode between the first wire pattern and the substrate is greater than the width of the third wire pattern, And the width of the second gate spacer sandwiched between the second epitaxial pattern and the second gate electrode is smaller than that of the second gate spacer sandwiched between the second epitaxial pattern and the second gate electrode.

In some embodiments of the present invention, the width of the first gate electrode between the first wire pattern and the second wire pattern is greater than the width of the second gate electrode between the third wire pattern and the fourth wire pattern Lt; / RTI >

In some embodiments of the present invention, the width of the first gate electrode between the first wire pattern and the second wire pattern is substantially equal to the width of the first gate electrode between the first wire pattern and the substrate And the width of the second gate electrode between the third wire pattern and the fourth wire pattern is substantially equal to the width of the second gate electrode between the third wire pattern and the substrate.

In some embodiments of the present invention, the width of the first gate electrode between the first wire pattern and the second wire pattern is smaller than the width of the first gate electrode between the first wire pattern and the substrate, The width of the second gate electrode between the third wire pattern and the fourth wire pattern is smaller than the width of the second gate electrode between the third wire pattern and the substrate.

In some embodiments of the present invention, the height of the first gate electrode between the first wire pattern and the substrate is substantially equal to the height of the first gate electrode between the first wire pattern and the second wire pattern And the height of the second gate electrode between the third wire pattern and the substrate is substantially equal to the height of the second gate electrode between the third wire pattern and the fourth wire pattern.

In some embodiments of the present invention, the height of the first gate electrode between the first wire pattern and the substrate is greater than the height of the first gate electrode between the first wire pattern and the second wire pattern, The height of the second gate electrode between the third wire pattern and the substrate is greater than the height of the second gate electrode between the third wire pattern and the fourth wire pattern.

In some embodiments of the present invention, the first gate electrode between the first wire pattern and the substrate includes a first electrode layer and a second electrode layer that are sequentially stacked on the first wire pattern, and the first wire The first gate electrode between the pattern and the second wire pattern includes the first electrode layer on the first wire pattern and does not include the second electrode layer.

In some embodiments of the present invention, the first gate electrode between the first wire pattern and the second wire pattern includes an air gap, and the first gate electrode between the first wire pattern and the substrate is an air Lt; / RTI >

In some embodiments of the present invention, there is provided a semiconductor device comprising: a first gate insulating film extending along a sidewall of the first gate spacer, a periphery of the first wire pattern and a periphery of the second wire pattern; And a second gate insulating film extending around the periphery of the third wire pattern and around the fourth wire pattern.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a substrate including a first region and a second region; A first wire pattern spaced apart from the substrate on the substrate in the first region; A second wire pattern spaced apart from the substrate on the substrate in the second region; A first gate spacer positioned at both ends of the first wire pattern; A second gate spacer positioned at both ends of the second wire pattern; A first gate electrode intersecting the first wire pattern, between the first gate spacers; A second gate electrode between the second gate spacers, the second gate electrode intersecting the second wire pattern; A first epitaxial pattern disposed on both sides of the first gate electrode and connected to the first wire pattern; And a second epitaxial pattern disposed on both sides of the second gate electrode and connected to the second wire pattern, wherein between the first wire pattern and the substrate, the first epitaxial pattern and the first gate The width of the first gate spacer interposed between the electrodes is different from the width of the second gate spacer interposed between the second epitaxial pattern and the second gate electrode between the second wire pattern and the substrate.

In some embodiments of the present invention, the width of the first gate electrode between the first wire pattern and the substrate is different from the width of the second gate electrode between the second wire pattern and the substrate.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a substrate including a first region and a second region; A first wire pattern spaced apart from the substrate on the substrate in the first region; A second wire pattern spaced apart from the substrate on the substrate in the second region; A first gate spacer positioned at both ends of the first wire pattern; A second gate spacer positioned at both ends of the second wire pattern; A first gate electrode intersecting the first wire pattern, between the first gate spacers; And a second gate electrode intersecting the second wire pattern between the first gate pattern and the second gate spacing, wherein a height of the first gate spacer between the first wire pattern and the substrate is greater than a height of the second wire pattern, Is greater than the height of the second gate spacer between the substrates.

In some embodiments of the present invention, the height of the first gate electrode between the first wire pattern and the substrate is greater than the height of the second gate electrode between the second wire pattern and the substrate.

In some embodiments of the present invention, the first gate electrode includes a first metal layer and a second metal layer that are sequentially stacked, and the second gate electrode includes a third metal layer and a fourth metal layer which are sequentially stacked.

In some embodiments of the present invention, the first gate electrode between the first wire pattern and the substrate includes the first metal layer and the second metal layer, and the first wire pattern between the second wire pattern and the substrate The gate electrode includes the third metal layer, and the fourth metal layer is not included.

In some embodiments of the present invention, the second gate electrode between the substrate and the second wire pattern includes an air gap, and the first gate electrode between the substrate and the first wire pattern has an air gap .

In some embodiments of the present invention, on the first wire pattern of the first region, a third wire pattern intersecting the first gate electrode, and on the second wire pattern of the second region, And a fourth wire pattern intersecting the two gate electrodes.

In some embodiments of the present invention, a first epitaxial pattern disposed on both sides of the first gate electrode and connected to the first wire pattern, and a second epitaxial pattern disposed on both sides of the second gate electrode, And a first air gap is formed between the first epitaxial pattern and the first gate spacer.

In some embodiments of the present invention, a second air gap is formed between the second epitaxial pattern and the second gate spacer.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a substrate including a first region and a second region; A first wire pattern spaced apart from the substrate on the substrate in the first region; A second wire pattern spaced apart from the substrate on the substrate in the second region; A first gate spacer positioned at both ends of the first wire pattern; A second gate spacer positioned at both ends of the second wire pattern; A first gate electrode intersecting the first wire pattern, between the first gate spacers; And a second gate electrode intersecting the second wire pattern between the second gate spacer and the thickness of the first wire pattern as the first gate spacer is away from the longitudinal face of the first wire pattern, Wherein the first wire pattern comprises a first portion having a first thickness and a second portion having a second thickness less than the first thickness, A first portion of the pattern is disposed on both sides of the second portion of the first wire pattern.

In some embodiments of the present invention, the height of the first gate electrode between the first wire pattern and the substrate is less than the height of the second gate electrode between the second wire pattern and the substrate.

In some embodiments of the present invention, the height of the first gate spacer between the first wire pattern and the substrate is substantially equal to the height of the second gate spacer between the second wire pattern and the substrate.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a substrate including a first region and a second region; A first wire pattern spaced apart from the substrate on the substrate in the first region; A second wire pattern spaced apart from the substrate on the substrate in the second region; A first gate spacer positioned at both ends of the first wire pattern; A second gate spacer positioned at both ends of the second wire pattern; A first gate insulating film extending along the sidewall of the first gate spacer and around the first wire pattern; A second gate insulating film which is formed on the sidewall of the second gate spacer and extends along the periphery of the second wire pattern, the thickness of the second gate insulating film being different from the thickness of the first gate insulating film; A first gate electrode crossing the first wire pattern on the first gate insulating film; And a second gate electrode crossing the second wire pattern on the second gate insulating film.

In some embodiments of the present invention, the height of the first gate electrode between the first wire pattern and the substrate is different from the height of the second gate electrode between the second wire pattern and the substrate.

In some embodiments of the present invention, the height of the first gate spacer between the first wire pattern and the substrate is substantially equal to the height of the second gate spacer between the second wire pattern and the substrate.

Other specific details of the invention are included in the detailed description and drawings.

1 is a schematic plan view for explaining a semiconductor device according to some embodiments of the present invention.
Fig. 2 is a cross-sectional view taken along line A-A and D-D in Fig. 1;
3 is a cross-sectional view taken along line B-B and E-E in Fig.
4 is a cross-sectional view taken along line C-C and F-F in Fig.
Figs. 5A to 5E are various cross-sectional views of the first wire pattern of Fig. 1 cut along B-B. Fig.
Figs. 6A to 6C are various cross-sectional views of the first wire pattern of Fig. 1 cut along the line A-A.
7 is a view for explaining a semiconductor device according to some embodiments of the present invention.
8 is a view for explaining a semiconductor device according to some embodiments of the present invention.
9 is a view for explaining a semiconductor device according to some embodiments of the present invention.
10 is a view for explaining a semiconductor device according to some embodiments of the present invention.
Figs. 11A and 11B are illustrative drawings for explaining the first wire pattern of Fig.
12 is a view for explaining a semiconductor device according to some embodiments of the present invention.
13 is an illustrative drawing for explaining the first wire pattern of Fig.
14 and 15 are views for explaining a semiconductor device according to some embodiments of the present invention.
16 and 17 are views for explaining a semiconductor device according to some embodiments of the present invention.
18 is a view for explaining a semiconductor device according to some embodiments of the present invention.
19 is a view for explaining a semiconductor device according to some embodiments of the present invention.
20 is a view for explaining a semiconductor device according to some embodiments of the present invention.
21 is a view for explaining a semiconductor device according to some embodiments of the present invention.
22 is a view for explaining a semiconductor device according to some embodiments of the present invention.
23 is a view for explaining a semiconductor device according to some embodiments of the present invention.
24 is a view for explaining a semiconductor device according to some embodiments of the present invention.
25 is a schematic plan view for explaining a semiconductor device according to some embodiments of the present invention.
26 is a cross-sectional view taken along line A-A and D-D in Fig.
27A and 27B are cross-sectional views taken along B-B and E-E in Fig. 25. Fig.
28 is a view for explaining a semiconductor device according to some embodiments of the present invention.
29 is a view for explaining a semiconductor device according to some embodiments of the present invention.
30 is a view for explaining a semiconductor device according to some embodiments of the present invention.
31 is a view for explaining a semiconductor device according to some embodiments of the present invention.
32 is a view for explaining a semiconductor device according to some embodiments of the present invention.
33 is a view for explaining a semiconductor device according to some embodiments of the present invention.
34 is a view for explaining a semiconductor device according to some embodiments of the present invention.
35 is a view for explaining a semiconductor device according to some embodiments of the present invention.
36 to 46 are intermediate-level diagrams for explaining a semiconductor device manufacturing method according to some embodiments of the present invention.
47 is a block diagram of a SoC system including a semiconductor device according to embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The relative sizes of layers and regions in the figures may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout the specification.

One element is referred to as being "connected to " or" coupled to "another element, either directly connected or coupled to another element, One case. On the other hand, when one element is referred to as being "directly connected to" or "directly coupled to " another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above" indicates that no other device or layer is interposed in between.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

In the drawings relating to the semiconductor device according to some embodiments of the present invention, a gate allround transistor (GAA FET) including a channel region in the form of a nanowire or a nanosheet is illustratively shown, but the present invention is not limited thereto. A semiconductor device according to some embodiments of the present invention may include a tunneling FET, a bipolar junction transistor, a lateral double diffusion transistor (LDMOS), and the like.

1 to 6C, a semiconductor device according to some embodiments of the present invention will be described.

1 is a schematic plan view for explaining a semiconductor device according to some embodiments of the present invention. Fig. 2 is a cross-sectional view taken along line A-A and D-D in Fig. 1; 3 is a cross-sectional view taken along line B-B and E-E in Fig. Fig. 4 is a cross-sectional view taken along line C-C and F-F in Fig. 1; Figs. 5A to 5E are various cross-sectional views of the first wire pattern of Fig. 1 cut along B-B. Fig. Figs. 6A to 6C are various cross-sectional views of the first wire pattern of Fig. 1 cut along the line A-A. For convenience of explanation, the interlayer insulating film 190 and the like are not shown in Fig.

1 to 4, a semiconductor device according to some embodiments of the present invention includes a substrate 100, a first wire pattern 110, a second wire pattern 210, a first gate insulating film 130 A second gate insulating film 230, a first gate electrode 120, and a second gate electrode 220.

The substrate 100 may include a first region I and a second region II. The first region I and the second region II may be spaced apart from each other or may be connected to each other. In the first region I and the second region II, transistors of different types may be formed, or transistors of the same type may be formed.

In addition, the first area and the second area II may each be, for example, one of a logic area, an SRAM area, and an input / output (IO) area. That is, the first region I and the second region II may be regions having the same function or regions having different functions.

In addition, although the first gate electrode 120 and the second gate electrode 220 are shown as different gate electrodes in FIG. 1, the present invention is not limited thereto.

When the first wire pattern 110 and the second wire pattern 210 are adjacent to each other and the first region I and the second region II are connected to each other and the first wire pattern 110 and the second wire pattern 210 are adjacent to each other, The first gate electrode 120 and the second gate electrode 220 intersecting the second wire pattern 210 may be the same gate electrode.

The substrate 100 may be a silicon substrate or may include other materials, such as silicon germanium, indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate 100 may have an epilayer formed on the base substrate.

The first pin-shaped protrusion 100P may be formed in the first region I, and the second pin-shaped protrusion 200P may be formed in the second region II. The first pin-shaped protrusion 100P and the second pin-shaped protrusion 200P may protrude from the upper surface of the substrate 100.

The field insulating film 105 may cover at least a part of the side wall of the first pin-shaped protrusion 100P and at least a part of the side wall of the second pin-shaped protrusion 200P. The first pin-shaped protrusion 100P and the second pin-shaped protrusion 200P can be defined by the field insulating film 105. [

The field insulating film 105 may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof.

3, the sidewalls of the first fin-shaped protrusion 100P and the second fin-shaped protrusion 200P are shown as being surrounded by the field insulating film 105 as a whole, but the present invention is not limited thereto.

The first pin-shaped protrusion 100P may be elongated in the first direction X1 and the second pin-shaped protrusion 200P may be elongated in the second direction X2.

The first pin-shaped protrusion 100P and the second pin-shaped protrusion 200P may be formed by etching a portion of the substrate 100 and may include an epitaxial layer grown from the substrate 100, respectively.

The first fin-shaped protrusion 100P and the second fin-shaped protrusion 200P may each include silicon or germanium, which is an element semiconductor material. Further, the first pin-shaped protrusion 100P and the second pin-shaped protrusion 200P may each include a compound semiconductor, for example, a compound semiconductor of Group IV-IV or a group III-V compound semiconductor.

IV-IV compound semiconductors may be binary compounds including at least two of carbon (C), silicon (Si), germanium (Ge), tin (Sn), ternary compounds compound, or a compound doped with a Group IV element thereon.

Group III-V compound semiconductors are, for example, Group III elements which include at least one of aluminum (Al), gallium (Ga) and indium (In) and at least one element of group V (P), arsenic (As) Sb) may be bonded to form a binary compound, a ternary compound, or a siliceous compound.

The first wire pattern 110 may be formed on the substrate 100 of the first region I. The second wire pattern 210 may be formed on the substrate 100 of the second region II. The first wire pattern 110 and the second wire pattern 210 may be spaced apart from the substrate 100, respectively.

The first wire pattern 110 may extend in the first direction X1 like the first pin-shaped protrusion 100P. The second wire pattern 210 may extend in the second direction X2 like the second pin-shaped protrusion 200P.

The first wire pattern 110 may be formed on the first pin-shaped protrusion 100P and spaced apart from the first pin-shaped protrusion 100P. The first wire pattern 110 may be vertically overlapped with the first pin-shaped protrusion 100P. The first wire pattern 110 is not formed on the field insulating film 105 but may be formed on the first pin-shaped protrusion 100P.

The second wire pattern 210 may be formed on the second pin-shaped protrusion 200P and spaced apart from the second pin-shaped protrusion 200P. The second wire pattern 210 may be vertically overlapped with the second fin-shaped protrusion 200P. The second wire pattern 210 is not formed on the field insulating film 105 but may be formed on the second pin-shaped protrusion 200P.

The first wire pattern 110 and the second wire pattern 210 may include silicon or germanium, which are element semiconductor materials, respectively. The first wire pattern 110 and the second wire pattern 210 may each include a compound semiconductor, for example, a compound semiconductor of Group IV-IV or a group III-V compound semiconductor.

The first wire pattern 110 and the second wire pattern 210 may be used as a channel region of a transistor, respectively.

The first wire pattern 110 and the second wire pattern 210 include the same material depending on whether the semiconductor device including the first wire pattern 110 and the second wire pattern 210 is a PMOS or an NMOS Or may contain different materials.

The first wire pattern 110 and the second wire pattern 210 may be formed of the same material as the semiconductor device including the first wire pattern 110 and the second wire pattern 210, Or may include different materials.

In addition, the first wire pattern 110 may include the same material as the first pin-shaped protrusion 100P, and may include a material different from the first pin-shaped protrusion 100P. Similarly, the second wire pattern 210 may include the same material as the second fin-shaped protrusion 200P, and may include a material different from the second fin-shaped protrusion 200P.

The first gate spacer 140 may extend in the third direction Y1. The first gate spacer 140 may intersect the first wire pattern 110.

The first gate spacers 140 may be located at both ends of the first wire pattern 110 extending in the first direction X1. The first gate spacers 140 may be formed on opposite sides of the first wire pattern 110, facing each other. The first gate spacer 140 may include a penetration through which the first wire pattern 110 passes.

The first wire pattern 110 may pass through the first gate spacer 140. The first gate spacer 140 may be in full contact with the periphery of the termination of the first wire pattern 110.

The first gate spacer 140 may include a first outer spacer 141 and a first inner spacer 142. The first inner spacer 142 may be disposed between the first pin protrusion 100P and the first wire pattern 110.

3 and 4, the first inner spacer 142 may be formed at a position vertically overlapping the first wire pattern 110 and / or the first pin-shaped protrusion 100P. The first inner spacers 142 may not be formed on the field insulating film 105 that does not overlap with the first wire pattern 110 and / or the first fin-shaped protrusion 100P. That is, the first outer spacers 141 may be formed on the upper surface of the field insulating film 105. The first outer spacers 141 may be located on the first wire pattern 110.

The first gate spacer 140 may define a first trench 140t that intersects the first wire pattern 110. [

The second gate spacer 240 may extend in the fourth direction Y2. The second gate spacers 240 may intersect the second wire pattern 210.

The second gate spacers 240 may be located at both ends of the second wire pattern 210 extending in the second direction X2. The second gate spacers 240 may be formed on opposite sides of the second wire pattern 210, facing each other. The second gate spacer 240 may include a penetration through which the second wire pattern 110 passes.

The second wire pattern 210 may pass through the second gate spacer 240. The second gate spacers 240 may be in full contact with the perimeter of the termination of the second wire pattern 210.

The second gate spacer 240 may include a second outer spacer 241 and a second inner spacer 242. The second inner spacer 242 may be disposed between the second pin protrusion 200P and the second wire pattern 210.

3 and 4, the second inner spacer 242 may be formed at a position vertically overlapping the second wire pattern 210 and / or the second pin-shaped protrusion 200P. The second inner spacers 242 may not be formed on the field insulating film 105 that does not overlap with the second wire pattern 210 and / or the second fin-shaped protrusions 200P. That is, the second outer spacers 241 may be formed on the upper surface of the field insulating film 105. A second outer spacer 241 may be positioned on the second wire pattern 210.

The second gate spacers 240 may define a second trench 240t that intersects the second wire pattern 210. [

A first outer spacer 141 and a second outer spacer 241 are each, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO _2), silicon shot nitride (SiOCN) and their And combinations thereof.

First inner spacer 142 and a second inner spacer 242 are each, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO _2), silicon shot nitride (SiOCN) and their And combinations thereof.

In FIG. 2, the first outer spacer 141 and the first inner spacer 142 may be the same material as one another, and the second outer spacer 241 and the second inner spacer 242 may be the same material.

The first gate insulating layer 130 may be formed around the first wire pattern 110. That is, the first gate insulating layer 130 may cover the first wire pattern 110.

Also, the first gate insulating film 130 may be formed on the upper surface of the field insulating film 105 and on the first fin-shaped protrusion 100P. The first gate insulating film 130 may extend along the inner wall of the first gate spacer 140.

In other words, the first gate insulating film 130 may extend along the circumference of the first wire pattern 110 and the sidewalls and the bottom surface of the first trench 140t.

Although not shown, an interface film may be formed between the first gate insulating film 130 and the first wire pattern 110, and between the first gate insulating film 130 and the first pinned protrusion 100P. In addition, depending on the method of forming the interface film, the interface film may be formed in the same manner as the profile of the first gate insulating film 130.

The second gate insulating layer 230 may be formed around the second wire pattern 210. That is, the second gate insulating layer 230 may cover the second wire pattern 210.

Also, the second gate insulating film 230 may be formed on the upper surface of the field insulating film 105 and on the second fin-shaped protrusion 200P. The second gate insulating film 230 may extend along the inner wall of the second gate spacer 240.

In other words, the second gate insulating film 230 may extend along the circumference of the second wire pattern 210 and the side wall and the bottom surface of the second trench 240t.

Although not shown, an interfacial film may be formed between the second gate insulating film 230 and the second wire pattern 210, and between the second gate insulating film 230 and the second fin-shaped protrusion 200P. In addition, depending on the method of forming the interface film, the interface film may be formed in the same manner as the profile of the second gate insulating film 230.

The first gate insulating layer 130 and the second gate insulating layer 230 may each include at least one of silicon oxide, silicon oxynitride, silicon nitride, and high permittivity material having a dielectric constant larger than that of silicon oxide.

The high-permittivity material may be, for example, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, oxide or zirconium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate. . ≪ / RTI >

In addition, although the above-described high dielectric constant insulating film has been described mainly with respect to oxides, it is not limited thereto. Unlike the above, the high-k insulating film may include at least one of a nitride of a metallic material (e.g., hafnium nitride) or an oxynitride (e.g., hafnium oxynitride) It is not.

The first gate insulating film 130 and the second gate insulating film 230 may include the same material or may include different materials.

2 to 4, the thickness of the first gate insulating film 130 and the thickness of the second gate insulating film 230 may be the same.

The first gate electrode 120 may intersect the first wire pattern 110 formed apart from the substrate 100 and the first fin-shaped protrusion 100P. The first gate electrode 120 may be formed to surround the first wire pattern 110.

The first gate electrode 120 may also be formed in a spaced space between the first wire pattern 110 and the first pinned protrusion 100P.

The first gate electrode 120 may be disposed between the first gate spacers 140. The first gate electrode 120 may be formed on the first gate insulating layer 130. The first gate electrode 120 may fill the first trench 140t.

The first gate electrode 120 may include M metal layers. Here, M may be a natural number greater than two. In FIGS. 2 through 4, the first gate electrode 120 may include a first lower metal layer 122 and a first upper metal layer 124, but is not limited thereto.

The first lower metal layer 122 may be formed on the first gate insulating layer 130. The first lower metal layer 122 may be formed along the profile of the first gate insulating layer 130.

The first lower metal layer 122 may be formed around the first wire pattern 110. The first lower metal layer 122 may cover the first gate insulating layer 130.

Also, the first lower metal layer 122 may be formed on the upper surface of the field insulating film 105 and on the first pin-shaped protrusion 100P. The first bottom metal layer 122 may extend along the inner wall of the first gate spacer 140.

In other words, the first lower metal layer 122 may extend along the circumference of the first wire pattern 110, with the sidewalls and the bottom surface of the first trench 140t.

The first upper metal layer 124 may be formed on the first lower metal layer 122. The first upper metal layer 124 may fill the first trench 140t with the first lower metal layer 122 formed thereon.

The second gate electrode 220 may intersect the second wire pattern 210 spaced apart from the substrate 100 and the second fin-shaped protrusion 200P. The second gate electrode 220 may be formed to surround the second wire pattern 210.

The second gate electrode 220 may also be formed in a spaced space between the second wire pattern 210 and the second fin-shaped protrusion 200P.

The second gate electrode 220 may be disposed between the second gate spacers 240. The second gate electrode 220 may be formed on the second gate insulating film 230. The second gate electrode 220 may fill the second trench 240t.

The second gate electrode 220 may include N metal layers. Where N may be a natural number greater than two. 2 through 4, the second gate electrode 220 may include a second lower metal layer 222 and a second upper metal layer 224, but is not limited thereto.

The second lower metal layer 222 may be formed on the second gate insulating layer 230. The second lower metal layer 222 may be formed along the profile of the second gate insulating layer 230.

The second lower metal layer 222 may be formed around the second wire pattern 210. The second lower metal layer 222 may cover the second gate insulating layer 230.

Also, the second lower metal layer 222 may be formed on the upper surface of the field insulating film 105 and on the second fin-shaped protrusion 200P. The second bottom metal layer 222 may extend along the inner wall of the second gate spacer 240.

In other words, the second lower metal layer 222 may extend along the circumference of the second wire pattern 110, with the sidewalls and the bottom surface of the second trench 240t.

The second upper metal layer 224 may be formed on the second lower metal layer 222. The second upper metal layer 224 may fill the second trench 240t with the second lower metal layer 222 formed thereon.

The first lower metal layer 122 and the second lower metal layer 222 are each formed of a material selected from the group consisting of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), tantalum carbonitride (TaCN), titanium silicon nitride (TiAl), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum (TiAlN), tantalum silicon nitride (TaSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride And may include at least one of carbide (TiAlC), titanium aluminum carbonitride (TiAlC-N), titanium carbide (TiC), and combinations thereof.

In addition, the first lower metal layer 122 and the second lower metal layer 222 may each include an oxidized form of the above-described material.

Although the first lower metal layer 122 and the second lower metal layer 222 are shown as a single film, they are for convenience of explanation, but are not limited thereto.

The first upper metal layer 124 and the second upper metal layer 224 may be formed of a material selected from the group consisting of tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti) ), Tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), poly-Si, SiGe or a metal alloy.

The first lower metal layer 122 and the second lower metal layer 222 may or may not have the same material. 2 to 4, the first lower metal layer 122 and the second lower metal layer 222 may have a laminated structure including the same number of metal layers.

In addition, the first upper metal layer 124 and the second upper metal layer 224 may or may not contain the same material.

The first epitaxial pattern 150 may be formed on both sides of the first gate electrode 120. The first epitaxial pattern 150 may be disposed on both sides of the first wire pattern 110 and may be connected to the first wire pattern 110. The first epitaxial pattern 150 may be formed on the first fin-shaped protrusion 100P.

The second epitaxial pattern 250 may be formed on both sides of the second gate electrode 220. The second epitaxial pattern 250 may be disposed on both sides of the second wire pattern 210 and may be connected to the second wire pattern 210. The second epitaxial pattern 250 may be formed on the second fin-shaped protrusion 200P.

The first epitaxial pattern 150 and the second epitaxial pattern 250 may be included in the source / drain regions, respectively.

2, the relationship between the first inner spacer 142 and the second inner spacer 242 will be described.

The width of the first gate electrode 120 formed between the first inner spacers 142 according to the relationship between the first inner spacers 142 and the second inner spacers 242 and the width of the second inner spacers 242, A change in the width of the second gate electrode 220 formed between the first gate electrode 220 and the second gate electrode 220 will be described.

The distance between the outer walls of the first gate spacer 140 facing the first epitaxial pattern 150 is greater than the distance between the outer walls of the second gate spacer 240 facing the second epitaxial pattern 250, Can be substantially the same as the distance.

The width SW11 of the first inner spacer 142 interposed between the first gate electrode 120 and the first epitaxial pattern 150 between the first wire pattern 110 and the substrate 100 is larger than the width May be different from the width SW21 of the second inner spacer 242 interposed between the second gate electrode 220 and the second epitaxial pattern 250 between the wire pattern 210 and the substrate 100. [

2, the width SW11 of the first inner spacer 142 between the first wire pattern 110 and the substrate 100 is larger than the width SW11 between the second wire pattern 210 and the substrate 100 May be smaller than the width SW21 of the second inner spacer 242.

The distance G11 between the first wire pattern 110 and the substrate 100 at which the first gate spacer 140 is spaced apart is smaller than the distance G11 between the second wire pattern 210 and the substrate 100. In other words, The spacers 240 may be different from the spaced distance G21.

A distance G11 between the first wire pattern 110 and the substrate 100 that is spaced apart from the first inner spacer 142 is greater than a distance G11 between the second wire pattern 210 and the substrate 100. [ The inner spacers 242 may be different from the spaced distance G21.

2, the distance G11 between the first wire pattern 110 and the substrate 100 at which the first gate spacers 140 are spaced apart is smaller than the distance G11 between the second wire pattern 210 and the substrate 100. [ The second gate spacer 240 may be greater than the spaced distance G21.

The height SH11 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 is greater than the height SH11 of the second gate spacer 240 between the second wire pattern 210 and the substrate 100. [ (SH21).

In other words, the height SH11 of the first inner spacer 142 between the first wire pattern 110 and the substrate 100 is greater than the height SH11 between the second wire pattern 210 and the substrate 100, May be substantially the same as the height SH21 of the protrusion 242.

Since the distance G11 between the first inner spacers 142 and the second inner spacers 242 is different from the distance G21 between the first inner spacers 142 and the second inner spacers 242, The width W11 of the electrode 120 may be different from the width W21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100. [

Since the distance G11 between the first inner spacers 142 and the second inner spacers 242 is greater than the distance G21 between the second inner spacers 242, The width W11 of the electrode 120 may be larger than the width W21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100. [

The width W11 of the first gate electrode 120 and the first wire pattern 110 overlapping the first wire pattern 110 and the substrate 100 is greater than the width W11 of the second wire pattern 210, The width W21 of the second gate electrode 220 and the second wire pattern 210 overlapping the substrate 100 may be different.

The width W11 of the first wire pattern 110 and the first wire pattern 110 overlapping the first gate electrode 120 and the first wire pattern 110 is greater than the width W11 of the second wire pattern 210, The width W21 of the second gate electrode 220 and the second wire pattern 210 overlapping the substrate 100 may be larger than the width W21.

2, the first wire pattern 110 may include first and second sides facing each other. The first side of the first wire pattern 110 may be closer to the substrate 100 than the second side of the first wire pattern 110.

The width W11 of the first wire pattern 110 and the first gate electrode 120 overlap with each other when the second side of the first wire pattern 110 and the first gate electrode 120 overlap each other Width W12.

2, the second wire pattern 210 may include a third side and a fourth side opposite to each other. The third side of the second wire pattern 210 may be closer to the substrate 100 than the fourth side of the second wire pattern 210.

The width W21 of the third wire 210 of the second wire pattern 210 and the second gate electrode 220 is set such that the fourth side of the second wire pattern 210 overlaps the second gate electrode 220 Width W22, but it is not limited thereto.

The width W11 of the first gate electrode 120 and the first wire pattern 110 overlapping the first wire pattern 110 and the substrate 100 is larger than the width W11 of the second wire pattern 210 and the substrate 100, The threshold voltage of the transistor of the first region I is different from the width W21 of the overlap of the second gate electrode 220 and the second wire pattern 210 between the threshold of the transistor of the second region II It may be different from the voltage.

Thus, by fabricating a semiconductor device having various threshold voltages, the device performance of the semiconductor device can be improved.

An interlayer insulating film 190 may be formed on the substrate 100. The interlayer insulating film 190 may surround the outer wall of the first gate spacer 140 defining the first trench 140t and the outer wall of the second gate spacer 240 defining the second trench 240t.

The interlayer insulating film 190 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. Low dielectric constant materials include, for example, FOX (Flowable Oxide), TONZ Silicon (TOSZ), Undoped Silica Glass (USG), Borosilica Glass (BSG), PhosphoSilica Glass (PSG), Borophosphosilicate Glass (BPSG), Plasma Enhanced Tetra Ethyl Ortho Silicate, Fluoride Silicate Glass, CDO, Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG, Parylene, Bis-benzocyclobutenes, material, or a combination thereof.

2, the upper surface of the interlayer insulating film 190 in the first region I is flush with the upper surface of the first gate electrode 120, and the upper surface of the interlayer insulating film 190 in the second region II The first gate electrode 220 and the second gate electrode 220 are formed on the same plane. However, the present invention is not limited thereto.

2, a capping pattern may be formed on the upper surfaces of the first gate electrode 120 and the second gate electrode 220, respectively. When the capping pattern is formed, the top surface of the capping pattern on the first gate electrode 120 may be flush with the top surface of the interlayer insulating layer 190 of the first region I. Likewise, the top surface of the capping pattern on the second gate electrode 220 may be flush with the top surface of the interlayer insulating layer 190 in the second region II.

5A to 5E, the cross section of the first wire pattern 110 will be described. It goes without saying that the description of the first wire pattern 110 may be applied to the second wire pattern 210 as well.

In Fig. 5A, the cross-section 110s of the first wire pattern 110 may be a figure composed of a combination of straight lines 110m. The cross-section 110s of the first wire pattern 110 may be, for example, a square. The width L1 of the first wire pattern 110 and the height L2 of the first wire pattern 110 may be equal to each other on the cross section 110s of the first wire pattern 110. [ More specifically, the cross-section 110s of the first wire pattern 110 may be square, but is not limited thereto.

5B, in the transverse section 110s of the first wire pattern 110, the width L1 of the first wire pattern 110 and the height L2 of the first wire pattern 110 are different from each other . More specifically, the cross-section 110s of the first wire pattern 110 may be rectangular, but is not limited thereto.

5C, in the transverse section 110s of the first wire pattern 110, the width L11 of one side of the first wire pattern 110 facing each other and the width L11 of one side of the first wire pattern 110 The width L12 may be different from each other. More specifically, the cross-section 110s of the first wire pattern 110 may be trapezoidal, but is not limited thereto.

5D, the cross-section 110s of the first wire pattern 110 may be a figure composed of a combination of a straight line 110m and a curve 110n. The cross-section 110s of the first wire pattern 110 may be, for example, a square with rounded corners.

5E, the cross-section 110s of the first wire pattern 110 may be a figure composed of a combination of the curve 110n.

5A to 5E, the cross section 110s of the first wire pattern 110 may be one of a figure composed of a combination of straight lines, a figure composed of a combination of straight lines and curves, and a figure composed of a combination of curves.

6A to 6C, a longitudinal section of the first wire pattern 110 will be described. It goes without saying that the description of the first wire pattern 110 may be applied to the second wire pattern 210 as well.

In FIG. 6A, as the first epitaxial pattern 150 and the first gate spacer 140 move away from each other, the thickness of the first wire pattern 110 may be substantially the same. For example, the thickness t1_a of the end portion of the first wire pattern 110 adjacent to the first epitaxial pattern 150 is substantially equal to the thickness t1_b of the center portion of the first wire pattern 110 .

In Fig. 6B, as the distance from the first epitaxial pattern 150 and the first gate spacer 140 increases, the thickness of the first wire pattern 110 may decrease. For example, the thickness t1_a of the end portion of the first wire pattern 110 adjacent to the first epitaxial pattern 150 may be greater than the thickness t1_b of the center portion of the first wire pattern 110.

In FIG. 6C, as the distance from the first epitaxial pattern 150 and the first gate spacer 140 increases, the thickness of the first wire pattern 110 may increase. For example, the thickness t1_a of the end portion of the first wire pattern 110 adjacent to the first epitaxial pattern 150 may be thinner than the thickness t1_b of the center portion of the first wire pattern 110. [

6B and 6C, as the distance from the first epitaxial pattern 150 and the first gate spacer 140 increases, the thickness of the first wire pattern 110 can be continuously varied.

7 is a view for explaining a semiconductor device according to some embodiments of the present invention. 8 is a view for explaining a semiconductor device according to some embodiments of the present invention. 9 is a view for explaining a semiconductor device according to some embodiments of the present invention. For the sake of convenience of explanation, the differences from those described with reference to Figs. 1 to 6C will be mainly described.

7, in the semiconductor device according to some embodiments of the present invention, a first inner spacer 142 is further formed on the first wire pattern 110, and a second inner spacer 142 is formed on the second wire pattern 210, An inner spacer 242 may be further formed.

For example, the width of the first inner spacer 142 on the first wire pattern 110 may be equal to the width of the first inner spacer 142 between the first wire pattern 110 and the substrate 100 have.

The width of the second inner spacer 242 on the second wire pattern 210 may be the same as the width of the second inner spacer 242 between the second wire pattern 210 and the substrate 100.

The first wire pattern 110 may include a first side and a second side facing each other. The first side of the first wire pattern 110 may be closer to the substrate 100 than the second side of the first wire pattern 110.

7, the width W11 of the first wire pattern 110 and the first gate electrode 120 overlap each other, and the width W11 of the first wire pattern 110 and the first gate electrode 120 May be substantially the same as the overlap width W12.

If the width of the first inner spacer 142 on the first wire pattern 110 is different from the width of the first inner spacer 142 between the first wire pattern 110 and the substrate 100, The width W11 of the first pattern of the wire pattern 110 and the first gate electrode 120 overlaps the width W2 of the first wire pattern 110 and the first gate electrode 120 W12).

Referring to FIG. 8, in a semiconductor device according to some embodiments of the present invention, the first inner spacer 142 may include a material different from the first outer spacer 141. Also, the second inner spacer 242 may comprise a different material than the second outer spacer 241. [

A first outer spacer 141 and a second outer spacer 241 are each, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO _2), silicon shot nitride (SiOCN) and their And combinations thereof.

The first inner spacer 142 and the second inner spacer 242 are each formed of a low dielectric constant material such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO ₂ ), silicon oxynitride (SiOCN) Nitride (SiBN), silicon boron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. The low dielectric constant material may be a material having a lower dielectric constant than, for example, silicon oxide.

Alternatively, the first inner spacer 142 and the second inner spacer 242 may include at least one element selected from the group consisting of carbon (C), nitrogen (N), oxygen (O), and hydrogen (H) Si). ≪ / RTI >

In one example, when the permittivity of the material contained in the first outer spacer 141 is a first permittivity and the permittivity of the material contained in the first inner spacer 142 is a second permittivity, the first permittivity and the second permittivity May be different.

For example, the first dielectric constant of the material contained in the first outer spacer 141 may be greater than the second dielectric constant of the material contained in the first inner spacer 142. The second dielectric constant may be smaller than the first dielectric constant to reduce the fringing capacitance between the first gate electrode 120 and the first epitaxial pattern 150.

9, in the semiconductor device according to some embodiments of the present invention, the first outer spacer 141 includes the first spacer film 141a and the second spacer film 141b, and the second outer spacer 141 241 may include a third spacer film 241a and a fourth spacer film 241b.

However, the first inner spacer 142 and the second inner spacer 242 may each be a single film.

For example, the first spacer film 141a and the third spacer film 241a may each be L-shaped. That is, at least one of the first outer spacer 141 and the second outer spacer 241 made of a multilayer film may have an L shape.

At least one of the first outer spacers 141 and the second outer spacers 241 made of a multilayer film may include a silicon oxynitride film (SiOCN).

9, the first inner spacer 142 and the second inner spacer 242 may be multilayer films, respectively. At this time, the number of the films constituting the first outer spacers 141 and the number of the films constituting the first inner spacers 142 may be different. In addition, the number of the films constituting the second outer spacers 241 may be different from the number of the films constituting the second inner spacers 242.

10 is a view for explaining a semiconductor device according to some embodiments of the present invention. Figs. 11A and 11B are illustrative drawings for explaining the first wire pattern of Fig. 12 is a view for explaining a semiconductor device according to some embodiments of the present invention. 13 is an illustrative drawing for explaining the first wire pattern of Fig.

For reference, FIGS. 11A, 11B, and 13 are longitudinal sectional views taken along line A-A in FIG.

10 to 11B, in the semiconductor device according to some embodiments of the present invention, the first wire pattern 110 and the second wire pattern 210 may each be a wire pattern that is trimming.

10, the first wire pattern 110 may include a first side and a second side facing each other. The first side of the first wire pattern 110 may be closer to the substrate 100 than the second side of the first wire pattern 110. The width of the first gate spacer 140 located between the first side of the first wire pattern 110 and the substrate 100 is equal to the width of the first gate spacer 140 on the second side of the first wire pattern 110 140).

For example, the first wire pattern 110 may include a first portion 110a, a second portion 110b, and a third portion 110c.

The second portion 110b of the first wire pattern may be disposed on both sides of the first portion 110a of the first wire pattern. The third portion 110c of the first wire pattern may be disposed on both sides of the first portion 110a of the first wire pattern. The third portion 110c of the first wire pattern may be disposed between the first portion 110a of the first wire pattern and the second portion 110b of the first wire pattern.

The thickness t13 of the third portion 110c of the first wire pattern is larger than the thickness t11 of the first portion 110a of the first wire pattern and is greater than the thickness t11 of the second portion 110b of the first wire pattern t12.

FIG. 11B shows that the connecting portion of the third portion 110c of the first wire pattern and the second portion 110b of the first wire pattern is rounded, and the third portion 110c of the first wire pattern and the first wire pattern Lt; RTI ID = 0.0 > 110a < / RTI >

11A and 11B, the width of the first portion 110a of the first wire pattern is shown to be constant irrespective of the position, but this is for convenience of description, and is not limited thereto. That is, the width of the first portion 110a of the first wire pattern may be changed as shown in FIG. 6B or FIG. 6C.

10 and 12, the shape of the second wire pattern 210 trimmed according to the width of the second gate spacer 240 in which the second wire pattern 210 is positioned at the upper and lower portions is similar to that of FIGS. 11A and 11B Or may be similar to FIG. 13 to be described later.

12 and 13, in the semiconductor device according to some embodiments of the present invention, the first wire pattern 110 and the second wire pattern 210 may each be a wire pattern that is trimmed.

Also, in Fig. 12, the first wire pattern 110 may include a first side and a second side facing each other. The first side of the first wire pattern 110 may be closer to the substrate 100 than the second side of the first wire pattern 110. The width of the first gate spacer 140 located between the first side of the first wire pattern 110 and the substrate 100 is equal to the width of the first gate spacer 140 on the second side of the first wire pattern 110 140). ≪ / RTI >

The second portion 110b of the first wire pattern may be disposed on both sides of the first portion 110a of the first wire pattern.

The thickness t12 of the second portion 110b of the first wire pattern is larger than the thickness t11 of the first portion 110a of the first wire pattern.

It is a matter of course that the connection portion of the second portion 110b of the first wire pattern and the first portion 110a of the first wire pattern may be rounded unlike that shown in Fig.

In FIG. 13, the width of the first portion 110a of the first wire pattern is shown to be constant irrespective of the position. However, the width is not limited thereto. That is, the width of the first portion 110a of the first wire pattern may be changed as shown in FIG. 6B or FIG. 6C.

14 and 15 are views for explaining a semiconductor device according to some embodiments of the present invention. For convenience of explanation, a description will be given centering on differences from those described with reference to Figs. 1 to 6C.

14 is a sectional view taken along line A - A and D - D in Fig. 1, and Fig. 15 is a sectional view taken along line B - B and E - E in Fig.

14 and 15, a semiconductor device according to some embodiments of the present invention includes a first insulation pattern 100pi formed on a first fin-shaped protrusion 100P, a second insulation pattern 100P formed on a second fin- 2 insulation pattern (200 pi).

The first insulation pattern 100pi may be formed on the upper surface of the first fin-shaped protrusion 100P. The first insulation pattern 100pi can be in contact with the first fin-shaped protrusion 100P. The first insulation pattern 100pi may not be formed on the upper surface of the field insulating film 105. [

The width of the first insulation pattern 100pi may correspond to the width of the first fin-shaped protrusion 100P under the first insulation pattern 100pi.

The second insulation pattern 200pi may be formed on the upper surface of the second fin-shaped protrusion 200P. The second insulation pattern 200pi can be in contact with the second fin-shaped protrusion 200P. The second insulating pattern 200pi may not be formed on the upper surface of the field insulating film 105. [

The width of the second insulation pattern 200pi may correspond to the width of the second fin-shaped protrusion 200P under the second insulation pattern 200pi.

The first insulating pattern 100pi and the second insulating pattern 200pi may include an insulating material.

Although the upper surface of the first insulating pattern 100pi and the second insulating pattern 200pi are shown as being flush with the upper surface of the field insulating film 105 in FIG. 15, the present invention is not limited thereto. no.

15, the first insulation pattern 100pi is formed entirely along the upper surface of the first pin-shaped protrusion 100P and the second insulation pattern 200pi is formed entirely along the upper surface of the second pin-shaped protrusion 200P However, the present invention is not limited thereto.

For example, the first insulation pattern 100pi may be formed at a portion overlapping the first gate electrode 120, and may not be formed at a portion overlapping the first source / drain region 150. Conversely, the first insulation pattern 100pi may not be formed in a portion overlapping the first gate electrode 120, but may be formed in a portion overlapping the first source / drain region 150. [

In other words, the first insulation pattern 100pi may be formed on a part of the upper surface of the first pin-shaped protrusion 100P, but not the rest.

The description of the second insulation pattern (200pi) is substantially similar to the description of the first insulation pattern (100pi), and therefore is omitted.

16 and 17 are views for explaining a semiconductor device according to some embodiments of the present invention. For convenience of explanation, a description will be given centering on differences from those described with reference to Figs. 1 to 6C.

16 is a cross-sectional view taken along line A-A and D-D in Fig. 1, and Fig. 17 is a cross-sectional view taken along line B-B and E-E in Fig.

16 and 17, in a semiconductor device according to some embodiments of the present invention, a substrate 100 includes a lower substrate 101 and an upper substrate 103 formed on one surface of the lower substrate 101 .

For example, the lower substrate 101 may be a semiconductor substrate, and the upper substrate 103 may be an insulating film substrate.

The substrate 100 may include a semiconductor substrate and an insulating film substrate formed on one side of the semiconductor substrate and may be, for example, a silicon on insulator (SOI), a silicon-germanium on insulator (SGOI) It is not.

18 is a view for explaining a semiconductor device according to some embodiments of the present invention. 19 is a view for explaining a semiconductor device according to some embodiments of the present invention. For convenience of explanation, a description will be given centering on differences from those described with reference to Figs. 1 to 6C.

For reference, Figs. 18 and 19 are cross-sectional views taken along the line A-A and D-D in Fig.

18, the thickness ti1 of the first gate insulating film 130 may be different from the thickness ti2 of the second gate insulating film 230 in the semiconductor device according to some embodiments of the present invention.

For example, the thickness ti1 of the first gate insulating film 130 may be smaller than the thickness ti2 of the second gate insulating film 230.

The height SH11 of the first inner spacer 142 between the first wire pattern 110 and the substrate 100 is greater than the height SH11 of the second inner spacer 242 between the second wire pattern 210 and the substrate 100. [ May be substantially the same as the height SH21.

The first gate electrode 120 and the first gate insulating film 130 are formed between the first wire pattern 110 and the substrate 100 and the second gate electrode 220 and the second gate insulating film 230 are formed between the first wire pattern 110 and the substrate 100, And may be formed between the two-wire pattern 210 and the substrate 100.

The first gate insulating film 130 is formed between the first wire pattern 110 and the first gate electrode 120 and between the first wire pattern 110 and the substrate 100 and between the first wire pattern 110 and the substrate 100. In more detail, And the first gate electrode (120).

Between the second wire pattern 210 and the substrate 100 the second gate insulating film 230 is formed between the second wire pattern 210 and the second gate electrode 220 and between the substrate 100 and the second gate electrode 220. [ (Not shown).

The height SH11 of the first inner spacer 142 is substantially equal to the height SH21 of the second inner spacer 242 and the thickness ti1 of the first gate insulating film 130 is substantially equal to the height SH11 of the second inner insulating spacer 230 The height h11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is different from the thickness ti2 of the second wire pattern 210 between the second wire pattern 210 and the substrate 100 May be different from the height h21 of the second gate electrode 220 of FIG.

When the thickness ti1 of the first gate insulating film 130 is smaller than the thickness ti2 of the second gate insulating film 230, the first gate electrode 120 between the first wire pattern 110 and the substrate 100, May be larger than the second gate electrode (h21) between the second wire pattern (210) and the substrate (100).

The width SW11 of the first inner spacer 142 between the first wire pattern 110 and the substrate 100 is larger than the width SW11 of the second inner spacer 242 between the second wire pattern 210 and the substrate 100. [ May be substantially the same as the width SW21.

A first gate insulating film 130 is formed between the first gate spacer 140 and the first gate electrode 120 between the first wire pattern 110 and the substrate 100. [ Between the second wire pattern 210 and the substrate 100, a second gate insulating film 230 is formed between the second gate spacer 240 and the second gate electrode 220.

Since the thickness ti1 of the first gate insulating film 130 is different from the thickness ti2 of the second gate insulating film 230 at this time, The width W11 of the second gate electrode 120 may be different from the width W21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100. [

The width W11 of the first gate electrode 120 and the first wire pattern 110 overlapping the first wire pattern 110 and the substrate 100 is greater than the width W11 of the second wire pattern 210, The width W21 of the second gate electrode 220 and the second wire pattern 210 overlapping the substrate 100 may be different.

When the thickness ti1 of the first gate insulating film 130 is smaller than the thickness ti2 of the second gate insulating film 230, the first gate electrode 120 between the first wire pattern 110 and the substrate 100, The width W11 of the second gate electrode 220 may be greater than the width W21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100. [

The width SW11 of the first inner spacer 142 between the first wire pattern 110 and the substrate 100 is larger than the width of the second inner spacer 142 between the second wire pattern 210 and the substrate 100, The first wire pattern 110 and the second gate insulating film 230 are formed in accordance with the relationship between the thickness ti1 of the first gate insulating film 130 and the thickness ti2 of the second gate insulating film 230, The width W11 of the first gate electrode 120 between the first wire pattern 210 and the substrate 100 may be different from the width W21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100 , And may be the same.

19, in a semiconductor device according to some embodiments of the present invention, the first wire pattern 110 may be a trimmed wire pattern, and the second wire pattern 210 may be a wire pattern that is not trimmed.

11A, 11B and 13, the trimmed first wire pattern 110 includes a first portion 110a of a first wire pattern having a different thickness and a second portion 110b of the first wire pattern . The second portion 110b of the first wire pattern may be disposed on both sides of the first portion 110a of the first wire pattern.

On the other hand, since the second wire pattern 210 is not trimmed, the thickness of the second wire pattern 210 may be constant as the distance from the second gate spacer 240 increases.

The height SH11 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 is greater than the height SH11 of the second gate spacer 240 between the second wire pattern 210 and the substrate 100. [ May be substantially the same as the height SH21. That is, the height SH11 of the first inner spacer 142 between the first wire pattern 110 and the substrate 100 is greater than the height SH11 between the second wire pattern 210 and the substrate 100 by the second inner spacers 242 (SH21).

On the other hand, since the first wire pattern 110 is trimmed and the second wire pattern 210 is not trimmed, the first wire pattern 110 formed between the first gate electrode 120 and the substrate 100 The space may be larger than the space between the substrate 210 and the second wire pattern 210 where the second gate electrode 220 is formed.

The height h11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is greater than the height h11 of the second gate electrode h21 between the second wire pattern 210 and the substrate 100 ).

20 is a view for explaining a semiconductor device according to some embodiments of the present invention. For the sake of convenience of explanation, the differences from those described with reference to Figs. 1 to 6C will be mainly described.

20, in a semiconductor device according to some embodiments of the present invention, the height SH11 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 is larger than the height SH11 of the second wire pattern 110, (SH21) of the second gate spacer 240 between the first gate spacer 210 and the substrate 100.

In other words, the height SH11 of the first inner spacer 142 between the first wire pattern 110 and the substrate 100 is greater than the height SH11 between the second wire pattern 210 and the substrate 100, May be different from the height (SH21) of the protrusion (242).

20, the height SH11 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 is greater than the height SH11 between the second wire pattern 210 and the substrate 100 May be greater than the height SH21 of the second gate spacer 240. [

That is, a space where the first gate electrode 120 is formed between the first wire pattern 110 and the substrate 100 is formed between the second wire pattern 210 and the substrate 100 by the second gate electrode 220, May be different.

The height SH11 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 is greater than the height SH11 of the second gate spacer 240 between the second wire pattern 210 and the substrate 100. [ The height h11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is different from the height h21 between the second wire pattern 210 and the substrate 100, And the height h21 of the second gate electrode 220 may be different.

When the height SH11 of the first inner spacer 142 is greater than the height SH21 of the second inner spacer 242, the first gate electrode 120 between the first wire pattern 110 and the substrate 100, The height h11 of the second gate electrode 220 may be greater than the height h21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100. [

The first gate electrode 120 includes a first lower metal layer 122 and a first upper metal layer 124 and a second gate electrode 220 includes a second lower metal layer 222 and a second upper metal layer 224. The first gate electrode 120 includes a first lower metal layer 122 and a first upper metal layer 124, . ≪ / RTI >

The first gate electrode 120 between the substrate 100 and the first wire pattern 110 may include a first bottom metal layer 122 and a first top metal layer 124.

20, the space between the second wire pattern 210 and the substrate 100 may be smaller than the space between the first wire pattern 110 and the substrate 100. However, the space between the substrate 100 and the second wire pattern 210 210 may include a second lower metal layer 222 and a second upper metal layer 224.

20, the first inner spacers 142 are spaced apart from each other between the first wire pattern 110 and the substrate 100 by the second inner spacers 242 between the second wire pattern 210 and the substrate 100, Are shown to be substantially the same as the spaced distances, but are not limited thereto.

21 is a view for explaining a semiconductor device according to some embodiments of the present invention. 22 is a view for explaining a semiconductor device according to some embodiments of the present invention. 23 is a view for explaining a semiconductor device according to some embodiments of the present invention. 24 is a view for explaining a semiconductor device according to some embodiments of the present invention. For convenience of description, differences from those described with reference to Fig. 20 will be mainly described.

Referring to FIG. 21, in the semiconductor device according to some embodiments of the present invention, the number of metal layers included in the second gate electrode 220 may be different, centering on the second wire pattern 210.

More specifically, the second gate electrode 220 may include a second lower metal layer 222 and a second upper metal layer 224. However, the second gate electrode 220 between the second wire pattern 210 and the substrate 100 includes the second lower metal layer 222, but may not include the second upper metal layer 224.

That is, only the second lower metal layer 222 may be formed between the second wire pattern 210 and the substrate 100 without forming the second upper metal layer 224.

3, the second upper metal layer 224 is not formed between the second wire pattern 210 and the second pin-shaped protrusion 200P, but may be formed on the field insulating film 105. [

Meanwhile, the first gate electrode 120 may include a first lower metal layer 122 and a first upper metal layer 124. The first gate electrode 120 between the first wire pattern 110 and the substrate 100 may also include a first lower metal layer 122 and a first upper metal layer 124.

22, in a semiconductor device according to some embodiments of the present invention, the first gate electrode 120 does not include an air gap, the second gate electrode 220 includes a second gate electrode air gap 220g, . ≪ / RTI >

More specifically, the first gate electrode 120 between the first wire pattern 110 and the substrate 100 may not include an air gap. On the other hand, the second gate electrode air gap 220g may be formed between the second wire pattern 210 and the substrate 100.

The second gate electrode air gap 220g may be formed by not forming the second upper metal layer 224 between the second wire pattern 210 and the substrate 100. However, It is not.

3, the second gate electrode air gap 220g may be formed between the second wire pattern 210 and the second fin-shaped protrusion 200P.

Referring to FIG. 23, in a semiconductor device according to some embodiments of the present invention, a first source / drain air gap 150g may be formed between the first epitaxial pattern 150 and the first gate spacer 140 have.

However, an air gap may not be formed between the second epitaxial pattern 250 and the second gate spacer 240.

A first source / drain air gap 150g may be formed between the first inner spacers 142 and the first epitaxial pattern 150.

Referring to FIG. 24, in a semiconductor device according to some embodiments of the present invention, a first source / drain air gap 150g may be formed between the first epitaxial pattern 150 and the first gate spacer 140 have.

Also, a second source / drain air gap 250g may be formed between the second epitaxial pattern 250 and the second gate spacer 240.

The first source / drain air gap 150g is formed between the first inner spacer 142 and the first epitaxial pattern 150 and the second source / drain air gap 250g is formed between the second inner spacer 242 and the second source / And the second epitaxial pattern 250, as shown in FIG.

The size of the first source / drain air gap 150g is influenced by the height of the first inner spacer 142 and the size of the second source / drain air gap 250g is larger than the height of the second inner spacer 242 It can be affected.

The size of the first source / drain air gap 150g is affected by which material the first epitaxial pattern 150 contains and the size of the second source / drain air gap 250g is larger than the size of the second epitaxial pattern 150. [ It can be influenced by which material the tax pattern 250 contains.

25 is a schematic plan view for explaining a semiconductor device according to some embodiments of the present invention. 26 is a cross-sectional view taken along line A-A and D-D in Fig. 27A and 27B are cross-sectional views taken along B-B and E-E in Fig. 25. Fig. 1 to Fig. 6C will be mainly described.

25 to 27B, a semiconductor device according to some embodiments of the present invention includes a third wire pattern 310 formed in a first region I and a fourth wire pattern 310 formed in a second region II 410).

The third wire pattern 310 may be formed on the first wire pattern 110. The third wire pattern 310 may be spaced apart from the first wire pattern 110. The third wire pattern 310 may extend in the first direction X1. The third wire pattern 310 may be vertically overlapped with the first wire pattern 110.

The fourth wire pattern 410 may be formed on the second wire pattern 210. The fourth wire pattern 410 may be spaced apart from the second wire pattern 210. The fourth wire pattern 410 may extend in the second direction X2. The fourth wire pattern 410 may be vertically overlapped with the second wire pattern 210.

27B, the width of the first wire pattern 110 in the third direction Y1 may be different from the width of the third wire pattern 310 in the third direction Y1.

Similarly, the width of the second wire pattern 210 in the fourth direction Y2 may be different from the width of the fourth wire pattern 410 in the fourth direction Y2.

In the semiconductor device according to some embodiments of the present invention, when the wire pattern includes upper and lower surfaces parallel to the upper surface of the substrate 100, the width of the wire pattern means the width of the lower surface of the wire pattern.

For example, the width of the first wire pattern 110 in the third direction Y1 may be greater than the width of the third wire pattern 310 in the third direction Y1. The width of the second wire pattern 210 in the fourth direction Y2 may be greater than the width of the fourth wire pattern 410 in the fourth direction Y2.

In other words, as the distance from the upper surface of the substrate 100 increases, the width of the wire pattern may decrease.

26 to 27B, two wire patterns are successively formed on the substrate 100 in the thickness direction of the substrate 100 in the first region I and two wire patterns are formed in the second region II Are sequentially formed on the substrate 100 in the thickness direction of the substrate 100. However, the present invention is not limited thereto.

Three or more wire patterns may be sequentially formed in the thickness direction of the substrate 100 on the substrate 100 of the first region I and three or more wire patterns may be sequentially formed on the substrate 100 of the second region II It is needless to say that more than one wire pattern may be sequentially formed in the thickness direction of the substrate 100. [

The first gate spacer 140 defining the first trench 140t may be formed at both ends of the first wire pattern 110 and the third wire pattern 310. [ The first wire pattern 110 and the third wire pattern 310 may pass through the first gate spacer 140. The first gate spacer 140 may be in contact with the end of the first wire pattern 110 and the end of the third wire pattern 310 as a whole.

The first inner spacer 142 may be disposed between the first pin protrusion 100P and the first wire pattern 110 and between the first wire pattern 110 and the third wire pattern 310.

A second gate spacer 240 defining a second trench 240t may be formed at both ends of the second wire pattern 210 and the fourth wire pattern 410. [ The second wire pattern 210 and the fourth wire pattern 410 may pass through the second gate spacer 240. The second gate spacer 240 may be in contact with the end of the second wire pattern 210 and the end of the fourth wire pattern 410 as a whole.

The second inner spacer 242 may be disposed between the second pin protrusion 200P and the second wire pattern 210 and between the second wire pattern 210 and the fourth wire pattern 410.

The first gate insulating layer 130 may be formed around the periphery of the first wire pattern 110 and the third wire pattern 310. The first gate insulating layer 130 may cover the first wire pattern 110 and the third wire pattern 310, respectively.

That is, the portions of the first gate insulating layer 130 formed along the periphery of the first wire pattern 110 and the portions of the first gate insulating layer 130 formed around the periphery of the third wire pattern 310 may be vertically spaced from each other have.

The first gate insulating layer 130 may extend around the sidewalls and the bottom surface of the first trench 140t and the periphery of the first wire pattern 110 and around the third wire pattern 310. [

The second gate insulating layer 230 may be formed around the second wire pattern 210 and around the fourth wire pattern 410. The second gate insulating layer 230 may cover the second wire pattern 210 and the fourth wire pattern 410, respectively.

That is, the portion of the second gate insulating layer 230 formed along the periphery of the second wire pattern 210 and the portion of the second gate insulating layer 230 formed along the periphery of the fourth wire pattern 410 may be vertically spaced from each other have.

The second gate insulating layer 230 may extend around the sidewalls and the bottom surface of the second trench 240t, the second wire pattern 210, and the fourth wire pattern 410.

The first gate electrode 120 may be formed on the first gate insulating layer 130. The first gate electrode 120 may cover the first wire pattern 110 and the third wire pattern 310. The first gate electrode 120 may intersect the first wire pattern 110 and the third wire pattern 310.

The first lower metal layer 122 may be formed on the first gate insulating layer 130. The first lower metal layer 122 may be formed along the profile of the first gate insulating layer 130.

The first lower metal layer 122 may be formed around the circumference of the first wire pattern 110 and the third wire pattern 310. The first lower metal layer 122 may cover the first gate insulating layer 130 formed along the outer surfaces of the first wire pattern 110 and the third wire pattern 310.

26 to 27B, the first lower metal layer 122 surrounding the first wire pattern 110 and the first lower metal layer 122 surrounding the third wire pattern 310 may be spaced apart from each other.

The first upper metal layer 124 may be formed on the first lower metal layer 122. The first upper metal layer 124 may fill the first trench 140t with the first lower metal layer 122 formed thereon.

The first upper metal layer 124 may be interposed between the first wire pattern 110 and the third wire pattern 310. The first upper metal layer 124 may be interposed between the first wire pattern 110 and the first pinned protrusion 100P, i.e., between the first wire pattern 110 and the substrate 100.

That is, the first gate insulating layer 130 and the first lower metal layer 122 may be sequentially disposed around the first wire pattern 110 and the third wire pattern 310, respectively. The first upper metal layer 124 is formed to cover the first wire pattern 110 and the third wire pattern 310 in which the first gate insulating layer 130 and the first lower metal layer 122 are sequentially disposed, .

The second gate electrode 220 may be formed on the second gate insulating film 230. The second gate electrode 220 may cover the second wire pattern 210 and the fourth wire pattern 410. The second gate electrode 220 may intersect the second wire pattern 210 and the fourth wire pattern 410.

The second lower metal layer 222 may be formed on the second gate insulating layer 230. The second lower metal layer 222 may be formed along the profile of the second gate insulating layer 230.

The second lower metal layer 222 may be formed around the periphery of the second wire pattern 210 and around the fourth wire pattern 410. The second lower metal layer 222 may cover the second gate insulating layer 230 formed along the outer surfaces of the second wire pattern 210 and the fourth wire pattern 410.

26 to 27B, the second lower metal layer 222 surrounding the second wire pattern 210 and the second lower metal layer 222 surrounding the fourth wire pattern 410 may be spaced apart from each other.

The second upper metal layer 224 may be formed on the second lower metal layer 222. The second upper metal layer 224 may fill the second trench 240t with the second lower metal layer 222 formed thereon.

The second upper metal layer 224 may be interposed between the second wire pattern 210 and the fourth wire pattern 410. The second upper metal layer 224 may be interposed between the second wire pattern 210 and the second pin protrusion 200P, that is, between the second wire pattern 210 and the substrate 100.

That is, the second gate insulating layer 230 and the second lower metal layer 222 may be sequentially disposed around the second wire pattern 210 and the fourth wire pattern 410, respectively. The second upper metal layer 224 covers each of the second wire pattern 210 and the fourth wire pattern 410 in which the second gate insulating layer 230 and the second lower metal layer 222 are sequentially disposed, .

The first epitaxial pattern 150 may be disposed on both sides of the first wire pattern 110 and the third wire pattern 310 and may be connected to the first wire pattern 110 and the third wire pattern 310, respectively .

The second epitaxial pattern 250 may be disposed on both sides of the second wire pattern 210 and the fourth wire pattern 410 and may be connected to the second wire pattern 210 and the fourth wire pattern 410, .

The width SW11 of the first gate spacer 140 interposed between the first gate electrode 120 and the first epitaxial pattern 150 between the first wire pattern 110 and the substrate 100 is smaller than the width May be smaller than the width SW21 of the second gate spacer 240 interposed between the second gate electrode 220 and the second epitaxial pattern 250 between the wire pattern 210 and the substrate 100. [

The distance G11 between the first wire pattern 110 and the substrate 100 and the distance between the first gate spacer 140 and the second wire pattern 210 is greater than the distance G11 between the second wire pattern 210 and the substrate 100. In other words, The spacers 240 may be larger than the spaced distance G21.

The distance G11 between the first inner spacers 142 and the second inner spacers 242 is greater than the distance G21 between the first inner spacers 142 and the second inner spacers 242, The width W11 of the electrode 120 may be greater than the width W21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100. [

The height SH11 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 is greater than the height SH11 of the second gate spacer 240 between the second wire pattern 210 and the substrate 100. [ (SH21).

The height h11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is greater than the height h11 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100 The height h21 of the first and second electrodes 22a and 22b may be substantially the same.

The width SW11 of the first gate spacer 140 interposed between the first gate electrode 120 and the first epitaxial pattern 150 between the first wire pattern 110 and the substrate 100 is larger than the width The width SW12 of the first gate spacer 140 interposed between the first gate electrode 120 and the first epitaxial pattern 150 between the first wire pattern 110 and the third wire pattern 310, May be substantially the same.

The distance G11 between the first wire pattern 110 and the substrate 100 at which the first gate spacer 140 is spaced apart is smaller than the distance G11 between the first wire pattern 110 and the third wire pattern 310, (140) may be substantially the same as the spaced distance (G12).

The height SH11 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 is greater than the height SH11 between the first wire pattern 110 and the third wire pattern 310, 140, respectively, as shown in FIG.

The width W11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is equal to or greater than the width W11 between the first wire pattern 110 and the third wire pattern 310 And may be substantially equal to the width W12 of the gate electrode 120. [

The width W11 of the first wire pattern 110 and the first wire pattern 110 overlapping the first gate electrode 120 and the first wire pattern 110 is greater than the width W11 of the first wire pattern 110 and the third wire pattern 110, May be substantially the same as the width W12 at which the first gate electrode 120 overlaps the first wire pattern 110 between the wire patterns 310. [

The height h11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is greater than the height h11 of the first gate electrode 120 between the first wire pattern 110 and the third wire pattern 310 The height h12 of the first and second electrodes 120 and 120 may be substantially the same.

The width SW21 of the second gate spacer 240 interposed between the second gate electrode 220 and the second epitaxial pattern 250 between the second wire pattern 210 and the substrate 100 is larger than the width The width SW22 of the second gate spacer 240 interposed between the second gate electrode 220 and the second epitaxial pattern 250 between the second wire pattern 210 and the fourth wire pattern 410 May be substantially the same.

The distance G21 between the second wire pattern 210 and the substrate 100 at which the second gate spacer 240 is spaced apart is smaller than the distance G21 between the second wire pattern 210 and the fourth wire pattern 410, (240) may be substantially equal to the spaced distance (G22).

The height SH21 of the second gate spacer 240 between the second wire pattern 210 and the substrate 100 is greater than the height SH21 of the second gate spacer 240 between the second wire pattern 210 and the fourth wire pattern 410 240). ≪ / RTI >

The width W21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100 is greater than the width W21 between the second wire pattern 210 and the fourth wire pattern 410 And may be substantially the same as the width W22 of the gate electrode 220. [

The width W21 of the second wire pattern 210 and the second wire pattern 210 overlapping the second gate electrode 220 and the second wire pattern 210 between the second wire pattern 210 and the substrate 100 is greater than the width W21 of the second wire pattern 210, May be substantially the same as the width W22 at which the second gate electrode 220 and the second wire pattern 210 are overlapped between the wire patterns 410. [

The height h21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100 is greater than the height h21 of the second gate electrode 220 between the second wire pattern 210 and the fourth wire pattern 410 The height h22 of the first and second electrodes 220 and 220 may be substantially the same.

The distance G11 between the first wire pattern 110 and the substrate 100 at which the first gate spacer 140 is spaced apart is smaller than the distance G11 between the first wire pattern 110 and the third wire pattern 310, The distance G21 between the second gate pattern 240 and the second wire pattern 210 is substantially equal to the distance G12 between the first wire pattern 210 and the substrate 100. The distance G21 between the second wire pattern 210 and the substrate 100, 210 and the fourth wire pattern 410 may be substantially the same as the spaced distance G22 between the second gate spacer 240 and the fourth wire pattern 410. [

The distance G12 between the first wire pattern 110 and the third wire pattern 310 and the distance between the first gate spacer 140 and the second wire pattern 210 is greater than the distance between the second wire pattern 210 and the fourth wire pattern 410. [ The second gate spacer 240 may be greater than the spaced distance G22.

The width SW12 of the first gate spacer 140 interposed between the first gate electrode 120 and the first epitaxial pattern 150 between the first wire pattern 110 and the third wire pattern 310 Of the second gate spacer 240 interposed between the second gate electrode 220 and the second epitaxial pattern 250 between the second wire pattern 210 and the fourth wire pattern 410 SW22).

The width W12 of the first gate electrode 120 between the first wire pattern 110 and the third wire pattern 310 is greater than the width W12 between the second wire pattern 210 and the fourth wire pattern 410 The width W22 of the second gate electrode 220 of FIG.

28 is a view for explaining a semiconductor device according to some embodiments of the present invention. 29 is a view for explaining a semiconductor device according to some embodiments of the present invention. 30 is a view for explaining a semiconductor device according to some embodiments of the present invention. For convenience of explanation, differences from those described with reference to Figs. 25 to 27B will be mainly described.

28, in the semiconductor device according to some embodiments of the present invention, the thickness t1 of the first wire pattern 110 is different from the thickness t3 of the third wire pattern 310, The thickness t2 of the fourth wire pattern 410 may be different from the thickness t4 of the fourth wire pattern 410. [

The thicknesses of the first wire pattern 110 and the third wire pattern 310 stacked on the substrate 100 of the first region I are different from each other, The thickness of the second wire pattern 210 and the thickness of the fourth wire pattern 410 may be different from each other.

For example, the thickness t1 of the first wire pattern 110 is thicker than the thickness t3 of the third wire pattern 310, and the thickness t2 of the second wire pattern 210 is thicker than the thickness t3 of the fourth wire pattern 310 410). ≪ / RTI >

In other words, as the distance from the upper surface of the substrate 100 is increased, the thickness of each of the stacked wire patterns can be reduced.

29, in the semiconductor device according to some embodiments of the present invention, the distance G11 between the first gate pattern 140 and the first wire pattern 110 and the distance between the first gate pattern 140 and the substrate 100, The first gate spacer 140 between the pattern 110 and the third wire pattern 310 may be greater than the spaced distance G12.

The width SW11 of the first gate spacer 140 interposed between the first gate electrode 120 and the first epitaxial pattern 150 between the first wire pattern 110 and the substrate 100 is larger than the width May be smaller than the width SW12 of the first gate spacer 140 interposed between the first gate electrode 120 and the first epitaxial pattern 150 between the wire pattern 110 and the third wire pattern 310 have.

The distance G21 between the second wire pattern 210 and the substrate 100 at which the second gate spacer 240 is spaced apart is larger than the distance G21 between the second wire pattern 210 and the fourth wire pattern 410, The gate spacers 240 may be greater than the spaced distance G22.

The width SW21 of the second gate spacer 240 interposed between the second gate electrode 220 and the second epitaxial pattern 250 between the second wire pattern 210 and the substrate 100 is larger than the width May be smaller than the width SW22 of the second gate spacer 240 interposed between the second gate electrode 220 and the second epitaxial pattern 250 between the wire pattern 210 and the fourth wire pattern 410 have.

The width W11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is equal to or greater than the width W11 between the first wire pattern 110 and the third wire pattern 310 May be larger than the width W12 of the gate electrode 120. [

The width W11 of the first wire pattern 110 and the first wire pattern 110 overlapping the first gate electrode 120 and the first wire pattern 110 is greater than the width W11 of the first wire pattern 110 and the third wire pattern 110, The width W12 between the first gate electrode 120 and the first wire pattern 110 between the wire patterns 310 may be larger than the width W12.

The width W21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100 is larger than the width W21 of the second gate electrode 220 between the second wire pattern 210 and the fourth wire pattern 410 220).

The width W21 of the second wire pattern 210 and the second wire pattern 210 overlapping the second gate electrode 220 and the second wire pattern 210 between the second wire pattern 210 and the substrate 100 is greater than the width W21 of the second wire pattern 210, May be greater than the width W22 between the second gate electrode 220 and the second wire pattern 210 between the wire patterns 410. [

In other words, as the distance from the top surface of the substrate 100 increases, the width of the first inner spacer 142 and the width of the second inner spacer 242 may increase, respectively.

On the other hand, as the distance from the upper surface of the substrate 100 is increased, the distance between the first inner spacer 142 and the second inner spacer 242 may decrease, respectively.

30, the height SH11 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 is greater than the height SH11 between the first wire pattern 110 and the third wire pattern 310 May be greater than the height (SH12) of the first gate spacer.

The height SH21 of the second gate spacer 240 between the second wire pattern 210 and the substrate 100 is greater than the height SH21 of the second gate spacer 240 between the second wire pattern 210 and the fourth wire pattern 410. [ May be greater than the height (SH22)

In other words, as the distance from the upper surface of the substrate 100 increases, the height of the first inner spacer 142 and the height of the second inner spacer 242 may increase, respectively.

The height h11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is greater than the height h11 between the first wire pattern 110 and the third wire pattern 310 May be larger than the height (h12) of the gate electrode (120).

The height h21 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100 is greater than the height h21 of the second gate electrode 220 between the second wire pattern 210 and the fourth wire pattern 410 220).

The height h11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is equal to the height h11 of the first gate pattern 120 between the first wire pattern 110 and the third wire pattern 310. [ The first gate electrode 120 and the first wire pattern 110 and the third wire pattern 310 between the first wire pattern 110 and the substrate 100 are larger than the height h12 of the electrode 120, The first gate electrode 120 may include a first lower metal layer 122 and a first upper metal layer 124 that are sequentially stacked on the first wire pattern 110, respectively.

The second gate electrode 220 between the second wire pattern 210 and the substrate 100 and the second gate electrode 220 between the second wire pattern 210 and the fourth wire pattern 410 are And a second lower metal layer 222 and a second upper metal layer 224 that are sequentially stacked on the second wire pattern 210.

31 is a view for explaining a semiconductor device according to some embodiments of the present invention. 32 is a view for explaining a semiconductor device according to some embodiments of the present invention. For convenience of explanation, differences from those described with reference to Fig. 30 will be mainly described.

31, in a semiconductor device according to some embodiments of the present invention, a first gate electrode 120 between a first wire pattern 110 and a substrate 100 is sequentially formed on a first wire pattern 110 A first lower metal layer 122 and a first upper metal layer 124 stacked on the first lower metal layer 122.

However, the first gate electrode 120 between the first wire pattern 110 and the third wire pattern 310 includes the first lower metal layer 122 but not the first upper metal layer 124 have.

Similarly, the second gate electrode 220 between the second wire pattern 210 and the substrate 100 includes a second lower metal layer 222 and a second upper metal layer 222 sequentially stacked on the second wire pattern 210 224).

The second gate electrode 220 between the second wire pattern 210 and the fourth wire pattern 410 includes the second lower metal layer 222 but not the second upper metal layer 224. [ have.

That is, the first upper metal layer 124 may not be formed between the first wire pattern 110 and the third wire pattern 310, and only the first lower metal layer 122 may be formed. The second upper metal layer 224 is not formed between the second wire pattern 210 and the fourth wire pattern 410 and only the second lower metal layer 222 is formed.

27A, the first upper metal layer 124 is not formed between the first wire pattern 110 and the third wire pattern 310, but may be formed on the field insulating film 105. The second upper metal layer 224 is not formed between the second wire pattern 210 and the fourth wire pattern 410 but may be formed on the field insulating film 105.

The height SH12 of the first gate spacer between the first wire pattern 110 and the third wire pattern 310 is greater than the height SH12 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100. [ The space for forming the first upper metal layer 124 between the first wire pattern 110 and the third wire pattern 310 may be insufficient.

The second upper metal layer 224 between the second wire pattern 210 and the fourth wire pattern 410 may not be formed for the reasons described above.

32, in the semiconductor device according to some embodiments of the present invention, the first gate electrode 120 between the first wire pattern 110 and the substrate 100 does not include an air gap, The first gate electrode 120 between the pattern 110 and the third wire pattern 310 may include a first gate electrode air gap 120g.

The second gate electrode 220 between the second wire pattern 210 and the substrate 100 does not include an air gap but the second gate electrode 220 between the second wire pattern 210 and the fourth wire pattern 410 The gate electrode 220 may include a second gate electrode air gap 220g.

33 is a view for explaining a semiconductor device according to some embodiments of the present invention. For convenience of explanation, differences from those described with reference to Figs. 25 to 27B will be mainly described.

33, in a semiconductor device according to some embodiments of the present invention, the height SH11 of the first gate spacer 140 between the first wire pattern 110 and the substrate 100 is larger than the height SH11 of the second wire pattern 110, May be greater than the height SH21 of the second gate spacer 240 between the substrate 210 and the substrate 100.

The height SH12 of the first gate spacer 140 between the first wire pattern 110 and the third wire pattern 310 is greater than the height SH12 between the second wire pattern 210 and the fourth wire pattern 410 May be greater than the height SH22 of the second gate spacer 240.

The height h11 of the first gate electrode 120 between the first wire pattern 110 and the substrate 100 is greater than the height h11 of the second gate electrode 220 between the second wire pattern 210 and the substrate 100 (H21). The height h12 of the first gate electrode 120 between the first wire pattern 110 and the third wire pattern 310 is equal to the height h12 between the second wire pattern 210 and the fourth wire pattern 410 2 gate electrode 220. In this case,

34 is a view for explaining a semiconductor device according to some embodiments of the present invention. 35 is a view for explaining a semiconductor device according to some embodiments of the present invention. For convenience of explanation, the differences from those described with reference to Fig. 33 will be mainly described.

Referring to FIG. 34, in a semiconductor device according to some embodiments of the present invention, the second gate electrode 220 includes a second lower metal layer 222 sequentially stacked on the second gate insulating film 230, And an upper metal layer 224.

The second gate electrode 220 between the second wire pattern 210 and the substrate 100 and the second gate electrode 220 between the second wire pattern 210 and the fourth wire pattern 410 Includes the second lower metal layer 222, but may not include the second upper metal layer 224.

The first gate electrode 120 may include a first lower metal layer 122 and a first upper metal layer 124 sequentially stacked on the first gate insulating layer 130.

The first gate electrode 120 between the first wire pattern 110 and the substrate 100 and the first gate electrode 120 between the first wire pattern 110 and the third wire pattern 310 are also connected to the first And may include a lower metal layer 122 and a first upper metal layer 124.

35, in a semiconductor device according to some embodiments of the present invention, the first gate electrode 120 does not include an air gap, the second gate electrode 220 includes a second gate electrode air gap 220g, . ≪ / RTI >

The second gate electrode air gap 220g may be formed between the second wire pattern 210 and the substrate 100 and between the second wire pattern 210 and the fourth wire pattern 410. [

The second upper metal layer 224 is not formed between the second wire pattern 210 and the substrate 100 and between the second wire pattern 210 and the fourth wire pattern 410, Gap 220g may be formed, but this is merely exemplary and not limiting.

36 to 46 are intermediate-level diagrams for explaining a semiconductor device manufacturing method according to some embodiments of the present invention.

37A and 38A are cross-sectional views taken along lines G-G and I-I in Fig. 36. Fig. 37B and 38B are cross-sectional views taken along H-H and J-J in Fig. 36;

36 to 37B, a substrate 100 including a first region I and a second region II may be provided.

Then, a sacrifice film 2001 and an active film 2002 can be sequentially formed on the substrate 100. [ The sacrificial film 2001 and the active film 2002 can be formed using, for example, an epitaxial growth method.

The active film 2002 may comprise a material having an etch selectivity to the sacrificial film 2001.

In Fig. 36, the active film 2002 and the sacrificial film 2001 are shown as two layers, respectively. However, the present invention is not limited thereto. Further, although the active film 2002 is shown at the top, it is not limited thereto.

Subsequently, a first mask pattern 2101 may be formed on the sacrificial layer 2001 of the first region I and the second region II, respectively.

In the first region I, the first mask pattern 2101 may be elongated in the first direction X1. In the second region II, the first mask pattern 2101 may be elongated in the second direction X2.

Referring to FIGS. 38A and 38B, the first fin structure F1 and the second fin structure F2 can be formed by performing the etching process using the first mask pattern 2101 as a mask.

The first fin type structure F1 may be formed in the first region I. The first fin structure F1 includes a first fin-shaped protrusion 100P sequentially stacked on a substrate 100, a first sacrificial pattern 111, a first active pattern 112, a first sacrificial pattern 111, and a first active pattern 112. [

And the second fin type structure F2 may be formed in the second region II. The second fin structure F2 includes a second fin-shaped protrusion 200P sequentially stacked on the substrate 100, a second sacrificial pattern 211, a second active pattern 212, a second sacrificial pattern 211, and a second active pattern 212. [

38B, all of the sacrificial films on the substrate 100 are shown as removed except for the sacrificial film 2001 used to form the first fin type structure F1 and the second fin type structure F2, But is not limited thereto.

Then, a field insulating film 105 covering the side wall of the first fin type structure F1 and at least a part of the side wall of the second fin type structure F2 may be formed on the substrate 100. [

During the process of forming the field insulating film 105, the first mask pattern 2101 may be removed.

Then, in the first region I, a first dummy gate electrode 120P which intersects with the first fin structure F1 and extends in the third direction Y1 may be formed.

A second dummy gate electrode 220P that intersects the second fin structure F2 and extends in the fourth direction Y2 may be formed in the second region II.

The first dummy gate electrode 120P and the second dummy gate electrode 220P may be formed using the second mask pattern 2102. [

The first dummy gate insulating film 130P and the second dummy gate insulating film 130P are formed between the first dummy gate electrode 120P and the first fin structure F1 and between the second dummy gate electrode 220P and the second fin structure F2. A gate insulating film 230P may be formed.

On the sidewalls of the first dummy gate electrode 120P, a first pre-gate spacer 140P may be formed. A second pre-gate spacer 240P may be formed on the sidewall of the second dummy gate electrode 220P.

The following description will be made with reference to Fig. 38A.

Referring to FIG. 39, a third mask pattern 2103 is formed on the second region II. The first region I not covered by the third mask pattern 2103 is exposed.

It is needless to say that the third mask pattern 2103 may be formed along the profile of the second fin type structure F2 and the second dummy gate electrode 120P.

Then, a part of the first fin type structure F1 can be removed by using the first dummy gate electrode 120P and the first pre-gate spacer 140P as a mask.

Through this, a first recess 150r can be formed on both sides of the first dummy gate electrode 120P and the first pre-gate spacer 140P.

Referring to FIG. 40, a first inner spacer 142 is formed between the first active pattern 112 and the first pin-shaped protrusion 100P. The first inner spacers 142 are also formed between the first active patterns 112 on the first fin-shaped protrusions 100P.

Specifically, a part of the first sacrificial pattern 111 can be removed by using the etching selectivity ratio between the first active pattern 112 and the first sacrificial pattern 111. [

Then, a first inner spacer 142 may be formed at a portion where a part of the first sacrificial pattern 111 is removed.

Referring to FIG. 41, a first epitaxial pattern 150 may be formed in the first recess 150r.

The first epitaxial pattern 150 may be included in the raised source / drain.

Then, the third mask pattern 2103 formed in the second region II can be removed.

Referring to FIG. 42, a fourth mask pattern 2104 is formed on the first region I. The second region II not covered by the fourth mask pattern 2104 is exposed.

It is needless to say that the fourth mask pattern 2104 may be formed along the profile of the first epitaxial pattern 150 and the second dummy gate electrode 120P.

Subsequently, a part of the second fin structure F2 can be removed by using the second dummy gate electrode 220P and the second pre-gate spacer 240P as a mask.

Through this, a second recess 250r can be formed on both sides of the second dummy gate electrode 220P and the second pre-gate spacer 240P.

Referring to FIG. 43, a second inner spacer 242 is formed between the second active pattern 212 and the second pin-shaped protrusion 200P. The second inner spacers 242 are also formed between the second active patterns 212 on the second pin-shaped protrusions 200P.

Specifically, a part of the second sacrificial pattern 211 can be removed by using the etching selectivity ratio between the second active pattern 212 and the second sacrificial pattern 211.

Then, a second inner spacer 242 may be formed at a portion where a part of the second sacrificial pattern 211 is removed.

At this time, the width of the second inner spacer 242 may be larger than the width of the first inner spacer 142.

Referring to FIG. 44, a second epitaxial pattern 150 may be formed in the second recess 250r.

Then, the fourth mask pattern 2104 formed in the first region I may be removed.

Referring to FIG. 45, an interlayer insulating film 190 covering the first epitaxial pattern 150 and the second epitaxial pattern 250 may be formed on the substrate 100.

The first dummy gate electrode 120P and the second dummy gate electrode 220P can be exposed by the interlayer insulating film 190. [

During formation of the interlayer insulating film 190, the second mask pattern 2102 can be removed. Also, while the interlayer insulating film 190 is formed, the first outer spacers 141 and the second outer spacers 241 may be formed, respectively.

46, by removing the first dummy gate electrode 120P, the first dummy gate insulating film 130P, and the first sacrificial pattern 111, the first sacrificial pattern 111 is formed on the substrate 100 of the first region I The first wire pattern 110 and the third wire pattern 310 may be formed.

The second dummy gate insulating film 230P and the second sacrificial pattern 211 are removed so that the second wire pattern 220 is formed on the substrate 100 of the second region II by removing the second dummy gate electrode 220P, The first wire pattern 210 and the fourth wire pattern 410 may be formed.

The first wire pattern 110 is formed apart from the first pin protrusion 100P and the third wire pattern 310 is formed apart from the first wire pattern 110. [

The second wire pattern 210 is spaced apart from the second pin protrusion 200P and the fourth wire pattern 410 is spaced apart from the second wire pattern 210.

The first dummy gate electrode 120P and the first dummy gate insulating film 130P and the first sacrificial pattern 111 are removed to form the first trench 140t defined by the first gate spacer 140. [ .

The second trench 240t defined by the second gate spacer 240 can be formed by removing the second dummy gate electrode 220P, the second dummy gate insulating film 230P and the second sacrificial pattern 211. [ .

Then, a first gate insulating film 130 and a first gate electrode 120 are formed in the first trench 140t. Also, a second gate insulating film 230 and a second gate electrode 220 are formed in the second trench 240t.

47 is a block diagram of a SoC system including a semiconductor device according to embodiments of the present invention.

Referring to FIG. 47, the SoC system 1000 includes an application processor 1001 and a DRAM 1060.

The application processor 1001 may include a central processing unit 1010, a multimedia system 1020, a bus 1030, a memory system 1040, and a peripheral circuit 1050.

The central processing unit 1010 can perform operations necessary for driving the SoC system 1000. [ In some embodiments of the invention, the central processing unit 1010 may be configured in a multicore environment that includes a plurality of cores.

The multimedia system 1020 may be used in the SoC system 1000 to perform various multimedia functions. The multimedia system 1020 may include a 3D engine module, a video codec, a display system, a camera system, a post-processor, and the like .

The bus 1030 can be used for data communication between the central processing unit 1010, the multimedia system 1020, the memory system 1040, and the peripheral circuit 1050. In some embodiments of the invention, such a bus 1030 may have a multi-layer structure. For example, the bus 1030 may be a multi-layer Advanced High-performance Bus (AHB) or a multi-layer Advanced Extensible Interface (AXI). However, the present invention is not limited thereto.

The memory system 1040 can be connected to an external memory (for example, DRAM 1060) by the application processor 1001 to provide an environment necessary for high-speed operation. In some embodiments of the invention, the memory system 1040 may include a separate controller (e.g., a DRAM controller) for controlling an external memory (e.g., DRAM 1060).

The peripheral circuit 1050 can provide an environment necessary for the SoC system 1000 to be smoothly connected to an external device (e.g., a main board). Accordingly, the peripheral circuit 1050 may include various interfaces for allowing an external device connected to the SoC system 1000 to be compatible.

The DRAM 1060 may function as an operation memory required for the application processor 1001 to operate. In some embodiments of the invention, the DRAM 1060 may be located external to the application processor 1001 as shown. Specifically, the DRAM 1060 can be packaged in an application processor 1001 and a package on package (PoP).

At least one of the elements of the SoC system 1000 may include at least one of the semiconductor devices according to the embodiments of the present invention described above.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

100: substrate 105: field insulating film
110, 210, 310, 410: wire pattern 120, 220: gate electrode
122, 222: lower metal layer 124, 224: upper metal layer
130, 230: gate insulating film 140, 240: gate spacer
141, 241: outer spacer 142, 242: inner spacer
150, 250: epitaxial pattern

Claims (20)

A substrate comprising a first region and a second region;
A first wire pattern spaced apart from the substrate on the substrate in the first region;
A second wire pattern spaced apart from the substrate and the first wire pattern on the substrate of the second region;
A first gate electrode crossing the first wire pattern and overlapping the first wire pattern by a first width; And
And a second gate electrode crossing the second wire pattern and overlapping the second wire pattern by a second width different from the first width. The method according to claim 1,
Wherein the first width is a width at which the first gate electrode and the first wire pattern overlap between the first wire pattern and the substrate,
Wherein the second width is such that the second gate electrode and the second wire pattern overlap each other between the second wire pattern and the substrate. The method according to claim 1,
A first gate spacer positioned at both ends of the first wire pattern, a second gate spacer positioned at both ends of the second wire pattern, a first epitaxial pattern disposed on both sides of the first wire pattern, And a second epitaxial pattern disposed on both sides of the second wire pattern,
Wherein the first gate electrode is disposed between the first gate spacer and the second gate electrode is disposed between the second gate spacer. The method of claim 3,
Wherein a width of the first gate spacer interposed between the first epitaxial pattern and the first gate electrode between the substrate and the first wire pattern is larger than a width of the second epitaxial pattern between the substrate and the second wire pattern, Pattern and the width of the second gate spacer interposed between the second gate electrode. The method of claim 3,
The first gate spacer defining a first trench, the second gate spacer defining a second trench,
A first gate insulating film extending along the sidewalls of the first trench and around the first wire pattern and a second gate insulating film extending along the sidewalls of the second trench and around the second wire pattern A semiconductor device. The method according to claim 1,
A third wire pattern crossing the first gate electrode on the first wire pattern of the first region,
And a fourth wire pattern crossing the second gate electrode on the second wire pattern of the second region. The method according to claim 6,
Wherein a width of overlapping the first gate electrode and the first wire pattern between the first wire pattern and the substrate is larger than a width between the first wire pattern and the third wire pattern, Is substantially the same as the overlapping width of the pattern,
Wherein a width of overlapping the second gate electrode and the second wire pattern between the second wire pattern and the substrate is set to be larger than a width of the second gate pattern between the second gate electrode and the second wire pattern, Wherein the width of the pattern is substantially the same as the width of the overlapping pattern. The method according to claim 6,
Wherein a width of overlapping the first gate electrode and the first wire pattern between the first wire pattern and the substrate is larger than a width between the first wire pattern and the third wire pattern, The pattern is larger than the overlapping width,
Wherein a width of overlapping the second gate electrode and the second wire pattern between the second wire pattern and the substrate is set to be larger than a width of the second gate pattern between the second gate electrode and the second wire pattern, Wherein the pattern is larger than the overlapping width. A substrate comprising a first region and a second region;
A first wire pattern spaced apart from the substrate on the substrate in the first region;
A second wire pattern spaced apart from the first wire pattern on the first wire pattern;
A third wire pattern spaced apart from the substrate on the substrate in the second region;
A fourth wire pattern spaced apart from the third wire pattern on the third wire pattern;
A first gate spacer positioned at both ends of the first wire pattern and the second wire pattern;
A second gate spacer located at both ends of the third wire pattern and the fourth wire pattern, the distance between the third wire pattern and the fourth wire pattern being spaced apart from the second gate pattern, A second gate spacer between the second wire patterns, the first gate spacer being smaller than the spaced distance;
A first gate electrode intersecting the first wire pattern and the second wire pattern between the first gate spacers; And
And a second gate electrode intersecting the third wire pattern and the fourth wire pattern between the second gate spacers. 10. The method of claim 9,
A first epitaxial pattern disposed on both sides of the first gate electrode and a second epitaxial pattern disposed on both sides of the second gate electrode,
Wherein a width of the first gate spacer interposed between the first epitaxial pattern and the first gate electrode between the first wire pattern and the second wire pattern is between the third wire pattern and the fourth wire pattern, Wherein the width of the second gate spacer is smaller than the width of the second gate spacer interposed between the second epitaxial pattern and the second gate electrode. 11. The method of claim 10,
Wherein a width of the first gate spacer interposed between the first epitaxial pattern and the first gate electrode between the first wire pattern and the substrate is larger than a width of the second epitaxial pattern between the third wire pattern and the substrate, Pattern and the second gate spacer sandwiched between the second gate electrode. 10. The method of claim 9,
Wherein the width of the first gate electrode between the first wire pattern and the second wire pattern is larger than the width of the second gate electrode between the third wire pattern and the fourth wire pattern. 10. The method of claim 9,
Wherein a width of the first gate electrode between the first wire pattern and the second wire pattern is substantially equal to a width of the first gate electrode between the first wire pattern and the substrate,
The width of the second gate electrode between the third wire pattern and the fourth wire pattern is substantially equal to the width of the second gate electrode between the third wire pattern and the substrate. 10. The method of claim 9,
The width of the first gate electrode between the first wire pattern and the second wire pattern is smaller than the width of the first gate electrode between the first wire pattern and the substrate,
And the width of the second gate electrode between the third wire pattern and the fourth wire pattern is smaller than the width of the second gate electrode between the third wire pattern and the substrate. 10. The method of claim 9,
The height of the first gate electrode between the first wire pattern and the substrate is substantially the same as the height of the first gate electrode between the first wire pattern and the second wire pattern,
And a height of the second gate electrode between the third wire pattern and the substrate is substantially equal to a height of the second gate electrode between the third wire pattern and the fourth wire pattern. 10. The method of claim 9,
The height of the first gate electrode between the first wire pattern and the substrate is larger than the height of the first gate electrode between the first wire pattern and the second wire pattern,
The height of the second gate electrode between the third wire pattern and the substrate is greater than the height of the second gate electrode between the third wire pattern and the fourth wire pattern. A substrate comprising a first region and a second region;
A first wire pattern spaced apart from the substrate on the substrate in the first region;
A second wire pattern spaced apart from the substrate on the substrate in the second region;
A first gate spacer positioned at both ends of the first wire pattern;
A second gate spacer positioned at both ends of the second wire pattern;
A first gate electrode intersecting the first wire pattern, between the first gate spacers;
A second gate electrode between the second gate spacers, the second gate electrode intersecting the second wire pattern;
A first epitaxial pattern disposed on both sides of the first gate electrode and connected to the first wire pattern; And
And a second epitaxial pattern disposed on both sides of the second gate electrode and connected to the second wire pattern,
Wherein a width of the first gate spacer interposed between the first epitaxial pattern and the first gate electrode between the first wire pattern and the substrate is greater than a width of the second epitaxial pattern between the second wire pattern and the substrate, Pattern and the width of the second gate spacer interposed between the second gate electrode. A substrate comprising a first region and a second region;
A first wire pattern spaced apart from the substrate on the substrate in the first region;
A second wire pattern spaced apart from the substrate on the substrate in the second region;
A first gate spacer positioned at both ends of the first wire pattern;
A second gate spacer positioned at both ends of the second wire pattern;
A first gate electrode intersecting the first wire pattern, between the first gate spacers; And
And a second gate electrode, intersecting the second wire pattern, between the second gate spacers,
Wherein a height of the first gate spacer between the first wire pattern and the substrate is greater than a height of the second gate spacer between the second wire pattern and the substrate. A substrate comprising a first region and a second region;
A first wire pattern spaced apart from the substrate on the substrate in the first region;
A second wire pattern spaced apart from the substrate on the substrate in the second region;
A first gate spacer positioned at both ends of the first wire pattern;
A second gate spacer positioned at both ends of the second wire pattern;
A first gate electrode intersecting the first wire pattern, between the first gate spacers; And
And a second gate electrode, intersecting the second wire pattern, between the second gate spacers,
The thickness of the first wire pattern is constant as the distance from the first gate spacer at the longitudinal section of the first wire pattern is constant,
The first wire pattern includes a first portion having a first thickness and a second portion having a second thickness less than the first thickness, and the first portion of the first wire pattern 1 < / RTI > portions are disposed on both sides of the second portion of the first wire pattern. A substrate comprising a first region and a second region;
A first wire pattern spaced apart from the substrate on the substrate in the first region;
A second wire pattern spaced apart from the substrate on the substrate in the second region;
A first gate spacer positioned at both ends of the first wire pattern;
A second gate spacer positioned at both ends of the second wire pattern;
A first gate insulating film extending along the sidewall of the first gate spacer and around the first wire pattern;
A second gate insulating film which is formed on the sidewall of the second gate spacer and extends along the periphery of the second wire pattern, the thickness of the second gate insulating film being different from the thickness of the first gate insulating film;
A first gate electrode crossing the first wire pattern on the first gate insulating film; And
And a second gate electrode crossing the second wire pattern on the second gate insulating film.

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