KR20170080260A - Array substrate and Display device including the same - Google Patents

Array substrate and Display device including the same Download PDF

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KR20170080260A
KR20170080260A KR1020150191589A KR20150191589A KR20170080260A KR 20170080260 A KR20170080260 A KR 20170080260A KR 1020150191589 A KR1020150191589 A KR 1020150191589A KR 20150191589 A KR20150191589 A KR 20150191589A KR 20170080260 A KR20170080260 A KR 20170080260A
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layer
electrode
substrate
insulating layer
thin film
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KR1020150191589A
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Korean (ko)
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김주혁
김병후
김도형
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엘지디스플레이 주식회사
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • H01L27/3225—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G02F2001/134372—

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Nanotechnology (AREA)
  • Materials Engineering (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

The present invention prevents hydrogen from diffusing into the oxide semiconductor layer because the insulating layer located below and / or above the oxide semiconductor layer includes the silica nanotube.
Accordingly, the display quality of the array substrate including the thin film transistor and the display device is improved.

Description

[0001] The present invention relates to an array substrate and a display device including the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to an array substrate and a display device including the same that can prevent degradation of characteristics of an oxide semiconductor layer.

BACKGROUND ART [0002] In the information age, a display field for processing and displaying a large amount of information has been rapidly developed. Recently, flat panel display devices having advantages of thinning, light weight, and low power consumption have been widely used as a liquid crystal display device or an organic light emitting diode A display device has been developed and replacing a conventional cathode ray tube (CRT).

Among liquid crystal display devices, an active matrix type liquid crystal display device including an array substrate having a thin film transistor, which is a switching device capable of controlling on / off of a voltage for each pixel, is widely used .

In addition, the organic light emitting diode display device has high luminance and low operating voltage characteristics, and is self-emitting type that emits light by itself. Therefore, the contrast ratio is large, the response time is short, and the viewing angle is not limited.

Such a liquid crystal display device and an organic light emitting diode display device commonly require an array substrate including a thin film transistor for driving each pixel region.

1 is a schematic cross-sectional view of an array substrate for a conventional liquid crystal display device.

1, the array substrate 1 includes a first substrate 10, a thin film transistor Tr located on the first substrate 10, a second thin film transistor Tr located on the top side of the thin film transistor Tr, And a pixel electrode 70 connected to the thin film transistor Tr and positioned above the common electrode 50. [

Although not shown, gate wirings are formed along the first direction on the first substrate 10, and data wirings formed along the second direction are formed on the gate wirings. The gate wiring and the data wiring intersect to define a pixel region.

The thin film transistor Tr is electrically connected to the gate wiring and the data wiring.

The thin film transistor Tr includes a gate electrode 12 connected to the gate wiring and positioned on the first substrate 10 and a gate electrode 12 disposed on the gate electrode 12 and overlapped with the gate electrode 12. [ And a source electrode 32 and a drain electrode 34 which are spaced apart from each other on the semiconductor layer 20. [

At this time, the source electrode 32 is connected to the data line. A gate insulating film 14 made of an inorganic insulating material such as silicon oxide or silicon nitride is formed between the gate electrode 12 and the semiconductor layer 20.

A first passivation layer 40 is formed to cover the thin film transistor Tr and a common electrode 50 having a plate shape is formed on the first passivation layer 40.

A second passivation layer 60 is formed on the common electrode 50 and a drain contact hole 42 is formed in the first and second passivation layers 40 and 60 to expose the drain electrode 34 .

The pixel electrode 70 is formed on the second passivation layer 60 and is connected to the drain electrode 34 through the drain contact hole 42. At least one pixel electrode 70 corresponding to the common electrode 50, And has an opening 72.

Although not shown, a liquid crystal layer including liquid crystal molecules is formed on the array substrate 1, and a second substrate including a color filter layer is formed on the liquid crystal layer. That is, the second substrate, which is called a color filter substrate, is bonded together via the array substrate 1 and the liquid crystal layer to constitute a liquid crystal display device.

The semiconductor layer of the thin film transistor Tr is made of an oxide semiconductor material. Since the oxide semiconductor material has a high charge mobility, the characteristics of the thin film transistor Tr are improved and the display quality of the liquid crystal display device is improved.

However, such a problem of lowering the characteristics of the thin film transistor Tr in the array substrate 1 occurs.

2, which is a graph showing driving characteristics of a thin film transistor Tr formed on a conventional array substrate, a threshold voltage (Vth) value of a thin film transistor Tr is shifted, A problem arises.

The present invention attempts to solve the threshold voltage shift problem of a thin film transistor.

In order to solve the above problems, in the array substrate of the present invention, the insulating layer located on the lower and / or upper portions of the oxide semiconductor layer includes the silica nanotubes.

The insulating layer may further comprise a siloxane copolymer and / or metal particles.

Further, the present invention provides a display device including the array substrate described above.

In the present invention, the insulating film used in the array substrate of the display device includes a silica nano-tube to prevent hydrogen from diffusing into the oxide semiconductor layer.

That is, since the insulating layer located between the oxide semiconductor layer and the silicon nitride layer containing hydrogen includes the silica nanotube having a molecular sieve function, the hydrogen in the silicon nitride layer is prevented from diffusing into the oxide semiconductor layer do.

Therefore, problems of degradation of the characteristics of the thin film transistor due to diffusion of hydrogen into the oxide semiconductor layer and display quality degradation of the display device are minimized or prevented.

1 is a schematic cross-sectional view of an array substrate for a conventional liquid crystal display device.
2 is a graph showing driving characteristics of a thin film transistor formed on a conventional array substrate.
3 is a schematic cross-sectional view of a display device according to the first embodiment of the present invention.
4A and 4B are schematic views for explaining the silica nanotubes.
5 is a graph showing driving characteristics of the thin film transistor in the display device of the present invention.
6 is a schematic cross-sectional view of a display device according to a second embodiment of the present invention.
7 is a schematic cross-sectional view of a display device according to a third embodiment of the present invention.

In a conventional array substrate for a display device, a threshold voltage (Vth) value shift problem of a thin film transistor is caused by diffusion of hydrogen into the oxide semiconductor layer.

1, the second passivation layer 60 positioned between the common electrode 50 and the pixel electrode 70 is made of silicon nitride, and the second passivation layer 60 of silicon nitride is formed. Contains excess hydrogen.

The hydrogen of the second protective layer 60 is diffused into the oxide semiconductor layer 20 through the first protective layer 40 and the characteristics of the oxide semiconductor layer 20 are deteriorated thereby. That is, the threshold voltage value of the thin film transistor Tr shifts due to the diffusion of hydrogen, and the display quality of the display device deteriorates.

On the other hand, by forming an etch-stopper corresponding to the center of the upper surface of the semiconductor layer 20, the hydrogen diffusion problem can be reduced. However, since a mask process for forming an etch-stopper is required, the manufacturing process becomes complicated and the manufacturing cost increases.

In order to solve such a problem, the present invention provides a semiconductor device comprising a first substrate, a thin film transistor located on the first substrate and including an oxide semiconductor layer, a first insulating layer located above the thin film transistor, And a first electrode disposed on the first insulating layer and connected to the thin film transistor. The first insulating layer includes a first insulating layer and a second insulating layer. The second insulating layer includes a silica nanotube.

In another aspect, the present invention provides a thin film transistor comprising a first substrate, a first insulating layer disposed on the first substrate, a thin film transistor disposed on the first insulating layer and including an oxide semiconductor layer, And a first electrode disposed on the first insulating layer and connected to the thin film transistor. The first insulating layer includes a first insulating layer and a second insulating layer. The second insulating layer includes a silica nanotube.

In the array substrate of the present invention, the second insulating layer may further include a siloxane copolymer.

In the array substrate of the present invention, the second insulating layer may further include metal particles.

The array substrate of the present invention includes first and second touch electrodes positioned on the first substrate, a third insulating layer covering the first and second touch electrodes, and a third insulating layer between the third insulating layer and the thin film transistor And the fourth insulating layer may include a silica nanotube.

The array substrate of the present invention may further include first and second touch electrodes positioned between the first insulating layer and the first substrate.

The array substrate of the present invention may further include a third insulating layer located between the thin film transistor and the first electrode and including silica nanotubes.

In another aspect, the present invention provides a display device including the above-described array substrate, an organic light emitting layer positioned on the first electrode, and a second electrode located on the organic light emitting layer.

The display device of the present invention may further include an encapsulation film covering the light emitting diode.

According to still another aspect of the present invention, there is provided a liquid crystal display comprising the above-described array substrate, a second substrate facing the first substrate, a liquid crystal layer positioned between the first and second substrates, A color filter layer positioned in either one of the first and second substrates, and a second electrode disposed on either one of the first and second substrates.

In the display device of the present invention, the second electrode is located between the first and second insulating layers, the second electrode has a plate shape, and the first electrode has at least one opening Lt; / RTI >

Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

- First Embodiment -

3 is a schematic cross-sectional view of a display device according to the first embodiment of the present invention.

3, the display device 100 according to the first embodiment of the present invention includes an array substrate 180 and a color filter substrate 190 facing each other, and the array substrate 180 and the color And a liquid crystal layer 170 positioned between the filter substrates 190. [ That is, the display device 100 according to the first embodiment of the present invention is a liquid crystal display device.

The array substrate 180 includes a first substrate 110, a thin film transistor Tr, a common electrode 140, and a pixel electrode 150.

For example, the first substrate 110 may be a glass substrate or a plastic substrate such as polyimide.

Although not shown, a gate wiring line extends along the first direction on the first substrate 110, and an extension extends along the second direction on the gate wiring line. The gate wiring and the data wiring intersect to define a pixel region.

The thin film transistor Tr is electrically connected to the gate wiring and the data wiring.

The thin film transistor Tr includes a gate electrode 112 connected to the gate wiring and positioned on the first substrate 110 and a gate electrode 112 disposed on the gate electrode 112 and overlapped with the gate electrode 112. [ And a source electrode 122 and a drain electrode 124 which are spaced apart from each other on the oxide semiconductor layer 120. The source electrode 122 and the drain electrode 124 are formed on the oxide semiconductor layer 120,

Each of the gate electrode 112, the source electrode 122, and the drain electrode 124 is made of a low-resistance metal material. For example, each of the gate electrode 112, the source electrode 122, and the drain electrode 124 may be formed of any one of copper (Cu), aluminum (Al), titanium (Ti), and alloys thereof .

The oxide semiconductor layer 120 is made of an oxide semiconductor material. For example, the oxide semiconductor material may be any one of indium gallium zinc oxide (IGZO), zinc indium oxide (ZIO), zinc gallium oxide (ZGO), and zinc tin oxide (ZTO).

At this time, the source electrode 122 is connected to the data line. A gate insulating layer 114 made of silicon oxide is formed between the gate electrode 112 and the oxide semiconductor layer 120.

A first passivation layer 130 is formed on the entire surface of the first substrate 110 to cover the thin film transistor Tr. Since the thin film transistor Tr does not include an etch stopper, the first passivation layer 130 contacts the central upper surface of the semiconductor layer 120.

The first passivation layer 130 includes a polymer matrix (not shown) and a silica nanotube 132 to prevent diffusion of hydrogen into the oxide semiconductor layer 120.

The polymer matrix may be a siloxane (-Si-O-) copolymer. For example, the polymer matrix may be represented by the following formula (1).

[Chemical Formula 1]

Figure pat00001

In Formula 1, R 1 may be a C1 to C10 alkyl group, a C1 to C10 alkenyl group, a C6 to C30 aryl group, or a C1 to C10 halogenated alkyl group, and m may be an integer of 5 to 50 .

The silica nanotubes 132 serve as molecular sieves for preventing hydrogen diffusion.

4A and 4B, which are schematic views for explaining the silica nanotubes, the silica nanotubes 132 are in the shape of a tube having an internal space 134, and by the action of reduction at the surface, 132, respectively.

The silica nanotubes 132 may have a specific surface area of 100 m 2 / g or more and a size of the internal space (pore) may be 200 nm or less. Accordingly, the silica nanotubes 132 efficiently adsorb hydrogen.

On the other hand, a carbon nano-tube can be used as a substance capable of adsorbing hydrogen. Since the protective layer containing carbon nanotubes is not transparent, . ≪ / RTI >

Further, the carbon nanotubes have poor dispersibility with the siloxane copolymer, and it is difficult to provide a flat upper surface.

However, since the first protective layer 130 including the silica nanotubes 132 is transparent, it can be used as an insulating layer covering the display area, and since it is the same silicon compound as the siloxane copolymer, the polymer matrix and excellent dispersion characteristics . Therefore, it can be used without a separate dispersant, and the flatness of the first protective layer 130 can be increased.

The first passivation layer 130 may further include metal particles (not shown) such as Au, Ag, and Pt. The metal particles serve as a thermal curing initiator in the curing process of the first passivation layer 130 and improve the adsorption efficiency of hydrogen.

The silica nanotubes 132 may have a weight ratio of about 0.1 to 5% based on the polymer matrix, and the metal particles may have a weight ratio of about 0.1 to 1 wt%. If the weight ratio of the silica nanotubes 132 is less than 0.1%, it is difficult to obtain desired hydrogen adsorption characteristics. If the weight ratio of the silica nanotubes 132 is greater than 5%, the surface flatness of the first passivation layer 130 is decreased and the etching property is deteriorated.

A common electrode 140 having a plate shape with respect to the entire display region is formed on the first passivation layer 130. The common electrode 14 may be made of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

A second passivation layer 142 is formed on the common electrode 140 and a drain contact hole 136 exposing the drain electrode 124 is formed in the first and second passivation layers 130 and 142 .

The second passivation layer 142 may be made of silicon nitride. At this time, the second passivation layer 142 is formed by a chemical vapor deposition process. Further, by forming under a high temperature condition of about 350 ° C, the residual hydrogen concentration in the second protective layer 142 can be lowered.

That is, the present invention includes the silica nanotubes 132 that lower the hydrogen concentration in the second passivation layer 142 and serve as the molecular sieve of the first passivation layer 130, so that the oxide semiconductor layer 120 Can be minimized.

On the other hand, in the case of a general protective layer, damage may occur at the process temperature (350 DEG C) of forming the second protective layer 142, and the flatness may be reduced or a crack may be generated. However, in the present invention, since the first protective layer 130 includes the polymer matrix of the siloxane copolymer, damage to the first protective layer 130 by the high temperature process is prevented.

The pixel electrode 150 is formed on the second passivation layer 142 and is made of a transparent conductive material such as ITO or IZO.

The pixel electrode 150 is connected to the drain electrode 124 through the drain contact hole 136 and has at least one opening 152 corresponding to the common electrode 140. Accordingly, the pixel electrode 150 and the common electrode 140 form a fringe field.

The color filter substrate 190 includes a second substrate 160 and a black matrix 162 and a color filter layer 164 disposed on the second substrate 160.

The second substrate 160 may be a glass substrate or a plastic substrate such as polyimide, and the black matrix 162 may correspond to a non-display region such as the thin film transistor Tr, the gate line, and the data line Located.

The color filter layer 164 may include red, green, and blue color filter patterns corresponding to each pixel region. Although not shown, an overcoat layer may be formed on the entire surface of the color filter layer 164.

The black matrix 162 and the color filter layer 164 may be formed on the array substrate 180 or may be omitted.

The liquid crystal layer 170 is disposed between the array substrate 180 and the color filter substrate 190 and includes liquid crystal molecules 172. The liquid crystal molecules 172 are driven by an electric field formed between the pixel electrode 150 and the common electrode 140.

Although not shown, first and second alignment layers are formed between the array substrate 180 and the liquid crystal layer 170, between the color filter substrate 190 and the liquid crystal layer 170, and the array substrate 180, And a seal pattern may be formed on the edge of the color filter substrate 190.

The first and second polarizers may be attached to the outer sides of the first and second substrates 110 and 160, respectively.

As described above, in the display device 100 and the array substrate 180 of the present invention, the first passivation layer 130 located between the oxide semiconductor layer 120 and the second passivation layer 142 made of silicon nitride By including the silica nanotubes 132, diffusion of hydrogen in the second passivation layer 142 into the oxide semiconductor layer 120 is minimized or prevented. Therefore, deterioration of the characteristics of the thin film transistor Tr can be prevented.

In addition, since the silica nanotubes 132 are porous materials having an internal space 134, the dielectric index of the first passivation layer 130 including the silica nanotubes 132 is reduced. Therefore, the parasitic capacitance generated in the array substrate 180 is reduced and problems such as signal delay are prevented. For example, parasitic capacitance may occur due to the overlap of the common electrode 140 and the data line, and a signal delay may occur in the data line. In the present invention, the common line 140 and data The parasitic capacitance between the common wiring 140 and the data wiring decreases because the dielectric constant of the first protective layer 130 located between the wirings decreases.

That is, in the first embodiment of the present invention, by providing the first passivation layer 130 that can prevent damage to the oxide semiconductor layer 120 due to hydrogen diffusion and signal delay due to parasitic capacitance without damage in a high-temperature process , The array substrate 180 and the display device 100 can be improved in quality.

Display production

1. Experimental Example

(A weight ratio of 5% based on a polymer matrix), metal particles (a weight ratio of 1% based on a polymer matrix), a solvent (polyethylene glycol methyl ether acetate (PGMEA), a polymer And a weight ratio of 400% based on the matrix) was coated and thermally cured to form a display device including the first protective layer.

2. Comparative Example

A composition without silica nanotubes was coated and thermally cured to form a display device including the first protective layer.

(1) Thin film transistor characteristics

As shown in Fig. 2, in the display device of the comparative example, the threshold voltage value of the thin film transistor is shifted, and the display quality of the display device is deteriorated.

5, which is a graph showing the driving characteristics of the thin film transistor in the display device of the present invention, diffusion of hydrogen is blocked by the silica nanotube in the present invention, thereby preventing the characteristic deterioration of the thin film transistor.

(2) Permittivity of the first protective layer

The first protective layer of the experimental example has a dielectric constant of about 2.8, while the first protective layer of the comparative example has a dielectric constant of about 3.5.

Therefore, in the display device and the array substrate of the present invention, parasitic capacitance is reduced and problems such as signal delay are prevented.

(3) Transmittance

The transmittance of the first protective layer prepared in Experimental Examples and Comparative Examples was measured and described in Table 1 below.

Figure pat00002

As shown in Table 1, even if silica nanotubes are included, the transmittance of the first protective layer does not decrease.

- Second Embodiment -

6 is a schematic cross-sectional view of a display device according to a second embodiment of the present invention.

6, a display device 200 according to a second embodiment of the present invention includes a first substrate 210, an oxide semiconductor layer 214 disposed on the first substrate 210, A second protective layer 250 covering the driving thin film transistor Tr and a light emitting diode D disposed on the second protective layer 250, And a first passivation layer 230 interposed between the oxide semiconductor layer 214 and the second passivation layer 250. The second passivation layer 230 may be formed on the second passivation layer 230,

That is, the display device 200 according to the second embodiment of the present invention is an organic light emitting diode display device in which a light emitting diode D is formed on an array substrate 280.

The first substrate 210 may be a glass substrate or a plastic substrate such as polyimide. When the first substrate 210 is flexible with a plastic substrate, the first substrate 210 is not attached to a carrier substrate (not shown) such as a glass substrate because the first substrate 210 is not suitable for forming the light emitting diode D. The process of forming the light emitting diode D proceeds. The display device 200 can be obtained by forming the light emitting diode D on the first substrate 210 and separating the carrier substrate from the first substrate 210. [

A buffer layer 212 made of an inorganic insulating material such as silicon oxide or silicon nitride is formed on the first substrate 210 and a driving thin film transistor Tr is formed on the buffer layer 212. The buffer layer 212 may be omitted.

An oxide semiconductor layer 214 is formed on the buffer layer 212. The oxide semiconductor layer 214 is made of an oxide semiconductor material. For example, the oxide semiconductor material may be any one of indium gallium zinc oxide (IGZO), zinc indium oxide (ZIO), zinc gallium oxide (ZGO), and zinc tin oxide (ZTO).

Although not shown, a light shielding pattern (not shown) may be formed under the semiconductor layer 214. The light shielding pattern prevents light from being incident on the semiconductor layer 214, Thereby preventing deterioration.

A gate insulating layer 216 made of silicon oxide is formed on the semiconductor layer 214.

A gate electrode 220 made of a conductive material such as metal is formed on the gate insulating layer 216 to correspond to the center of the semiconductor layer 214.

6, the gate insulating layer 216 is patterned to have the same shape as that of the gate electrode 220, but a gate insulating layer 216 may be formed on the entire surface of the first substrate 210.

A first passivation layer 230 is formed on the gate electrode 220. The first passivation layer 230 includes a polymer matrix (not shown) and a silica nanotube 232 to prevent hydrogen from diffusing into the oxide semiconductor layer 214.

The polymer matrix may be a siloxane copolymer. For example, the polymer matrix may be represented by the formula (1).

The silica nanotubes 232 serve as a molecular sieve for preventing diffusion of hydrogen.

Referring again to FIGS. 4A and 4B, the silica nanotubes 232 are in the form of a tube having an internal space 134, and hydrogen is adsorbed on the silica nanotubes 232 by a reducing action on the surface. The silica nanotubes 232 may have a specific surface area of 100 m 2 / g or more, and the inner space (pore size) may be 200 nm or less. Accordingly, the silica nanotubes 232 efficiently adsorb hydrogen.

The first passivation layer 230 may further include metal particles (not shown) such as Au, Ag, and Pt. The metal particles serve as a thermosetting initiator in the curing process of the first passivation layer 230 and improve the adsorption efficiency of hydrogen.

The silica nanotubes 232 may have a weight ratio of about 0.1 to 5% based on the polymer matrix, and the metal particles may have a weight ratio of about 0.1 to 1 wt%. If the weight ratio of the silica nanotubes 232 is less than 0.1%, it is difficult to obtain desired hydrogen adsorption characteristics. If the weight ratio of the silica nanotubes 232 is greater than 5%, the surface flatness of the first passivation layer 230 is decreased and the etching characteristics are deteriorated.

The first passivation layer 230 has first and second contact holes 234 and 236 exposing both sides of the oxide semiconductor layer 214. The first and second contact holes 234 and 236 are spaced apart from the gate electrode 220 on both sides of the gate electrode 220.

A source electrode 240 and a drain electrode 242 made of a conductive material such as metal are formed on the first passivation layer 230.

The source electrode 240 and the drain electrode 242 are spaced apart from each other around the gate electrode 220 and are electrically connected to the oxide semiconductor layer 214 through the first and second contact holes 234 and 236, Contact both sides.

The oxide semiconductor layer 214 and the gate electrode 220, the source electrode 240 and the drain electrode 242 constitute the driving thin film transistor Tr.

Although not shown, a gate line and a data line cross each other to define a pixel region, and a switching element connected to the gate line and the data line is further formed. The switching element is connected to the driving thin film transistor Tr.

Further, a storage capacitor is further formed so that a power wiring is formed in parallel to the gate wiring or the data wiring, and the voltage of the gate electrode of the driving thin film transistor Tr is kept constant during one frame .

A second passivation layer 250 having a drain contact hole 252 exposing the drain electrode 242 of the driving thin film transistor Tr is formed to cover the driving thin film transistor Tr. The second passivation layer 250 is made of silicon nitride.

At this time, the second passivation layer 250 is formed by a chemical vapor deposition process. Further, by forming under a high temperature condition of about 350 ° C, the residual hydrogen concentration in the second passivation layer 250 can be lowered.

That is, in the present invention, since the hydrogen concentration in the second passivation layer 250 is lowered and the first passivation layer 230 includes the silica nanotube 232 serving as a molecular sieve, the oxide semiconductor layer 214 Can be minimized.

On the other hand, in the case of a general protective layer, damage may occur at a forming temperature (350 ° C) of the second protective layer 250, resulting in reduced flatness or cracking. However, in the present invention, since the first protective layer 230 includes the polymer matrix of the siloxane copolymer, damage to the first protective layer 230 by the high temperature process is prevented.

A first electrode 260 connected to the drain electrode 242 of the driving thin film transistor Tr through the drain contact hole 252 is formed on the second passivation layer 250 separately for each pixel region . The first electrode 260 may be an anode and may be formed of a conductive material having a relatively large work function value. For example, the first electrode 260 may be made of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) .

A bank layer 266 covering the edge of the first electrode 260 is formed on the second passivation layer 250. The bank layer 266 exposes the center of the first electrode 260 corresponding to the pixel region.

An organic emission layer 262 is formed on the first electrode 260. The organic light emitting layer 262 may have a single layer structure of a light emitting material layer made of a light emitting material. The organic light emitting layer 262 may include a hole injection layer, a hole transporting layer, a light emitting material layer, and an electron transporting layer sequentially stacked on the first electrode 260. [ (electron transporting layer) and an electron injection layer (multilayer structure).

A second electrode 264 is formed on the first substrate 210 on which the organic light emitting layer 262 is formed. The second electrode 264 is disposed on the entire surface of the display region and is made of a conductive material having a relatively small work function value and can be used as a cathode. For example, the second electrode 264 may be formed of any one of aluminum (Al), magnesium (Mg), and aluminum-magnesium alloy (AlMg).

The first electrode 260, the organic light emitting layer 262, and the second electrode 264 form a light emitting diode (D).

A second substrate 270 is attached to the second electrode 264. The second substrate 270 may be an encapsulation film for preventing external moisture from penetrating into the LED. At this time, the second substrate 270 may have a laminated structure of a first inorganic insulating layer 272, an organic insulating layer 274, and a second inorganic insulating layer 276, but is not limited thereto.

In addition, a polarizer (not shown) may be attached on the second substrate 270 to reduce external light reflection. For example, the polarizer may be a circular polarizer.

As described above, in the display device 200 and the array substrate 280 of the present invention, the first passivation layer 230 located between the oxide semiconductor layer 214 and the second passivation layer 250 made of silicon nitride By including the silica nanotubes 232, diffusion of hydrogen into the oxide semiconductor layer 214 in the second passivation layer 250 is minimized or prevented. Therefore, deterioration of the characteristics of the driving thin film transistor Tr can be prevented.

In addition, since the silica nanotubes 232 are porous materials having an internal space 234, the dielectric index of the first protective layer 230 including the silica nanotubes 232 is reduced, The parasitic capacitance generated in the transistor 280 is reduced.

That is, in the second embodiment of the present invention, by providing the first passivation layer 230 that can prevent the damage of the oxide semiconductor layer 214 due to hydrogen diffusion and the signal delay due to the parasitic capacitance, , The array substrate 280 and the display device 200 can be improved in quality.

- Third Embodiment -

7 is a schematic cross-sectional view of a display device according to a third embodiment of the present invention.

7, a display device 300 according to a third embodiment of the present invention includes an array (not shown) in which a driving thin film transistor Tr including the touch electrodes 312 and 314 and the oxide semiconductor layer 340 is formed And a light emitting diode (D) formed on the array substrate (380). That is, the third embodiment of the present invention relates to an in-cell touch organic light emitting diode display device.

That is, the touch of the user is sensed by the touch wirings 312 and 314. The light emitting diode D serves as a display element, and the light emitting diode D is driven by the array substrate 380, Is controlled.

The substrate 310 may be a glass substrate or a plastic substrate such as polyimide. Although not shown, a gate line and a data line are formed on the substrate 310 so as to define pixel regions intersecting with each other, and a switching element connected to the gate line and the data line is further formed.

Further, a storage capacitor is further formed so that a power wiring is formed in parallel to the gate wiring or the data wiring, and the voltage of the gate electrode of the driving thin film transistor Tr is kept constant during one frame .

A first touch electrode 312 and a second touch electrode 314 are formed on the substrate 310.

The first touch electrodes 312 are arranged along a first direction and the second touch electrodes 314 are arranged along a second direction different from the first direction. For example, the first direction may be parallel to a data line (not shown), and the second direction may be parallel to a gate line (not shown), but is not limited thereto.

The first touch electrode 312 and the second touch electrode 314 are spaced apart from each other. For example, the plurality of first touch electrodes 312 may be integrally formed on the substrate 310 along a first direction, and may be formed as a plurality of islands separated from each other along a second direction The second touch electrode 314 may be formed.

A driving line connected to the first touch electrode 312 and a sensing line connected to the second touch electrode 314 may be used in addition to the first and second touch electrodes 312 and 314, And a touch pad may be formed. The touch pad (not shown) may be electrically connected to a plurality of transmission lines (not shown) or reception lines (not shown).

A first buffer layer 316 covering the first and second touch electrodes 312 and 324 is formed on the substrate 310. The first buffer layer 316 may be made of silicon nitride.

A first planarization layer 330 is formed on the first buffer layer 316 to provide a planar top surface.

The first planarization layer 330 includes a polymer matrix (not shown) and a silica nanotube 332 and prevents hydrogen in the first buffer layer 316 made of silicon nitride from diffusing into the oxide semiconductor layer 340. do.

The polymer matrix may be a siloxane copolymer. For example, the polymer matrix may be represented by the formula (1).

The silica nanotube 332 serves as a molecular sieve for preventing hydrogen diffusion.

Referring again to FIGS. 4A and 4B, the silica nanotubes 332 are in the shape of a tube having an internal space 134, and hydrogen is adsorbed on the silica nanotubes 332 by a reducing action on the surface. The silica nanotubes 332 may have a specific surface area of 100 m 2 / g or more and the inner space (pore size) may be 200 nm or less. Accordingly, the silica nanotube 332 efficiently adsorbs hydrogen.

In addition, the first planarization layer 330 may further include metal particles (not shown) such as Au, Ag, and Pt. The metal particles serve as a thermal curing initiator in the curing process of the first planarization layer 330 and improve the adsorption efficiency of hydrogen.

The silica nanotubes 332 may have a weight ratio of about 0.1 to 5% based on the polymer matrix, and the metal particles may have a weight ratio of about 0.1 to 1 wt%. If the weight ratio of the silica nanotubes 332 is less than 0.1%, it is difficult to obtain desired hydrogen adsorption characteristics. If the weight ratio of the silica nanotubes 332 is more than 5%, the surface flatness of the first planarization layer 330 is decreased and the etching property is deteriorated.

A second buffer layer 334 is formed on the first planarization layer 330. The buffer layer 334 may be formed of silicon oxide and may be omitted.

A gate line extends along the first direction on the second buffer layer 334 and extends along the second direction above the gate line. The gate wiring and the data wiring intersect to define a pixel region.

A gate electrode 322 connected to the gate wiring is formed on the second buffer layer 334 and an oxide semiconductor layer 340 is formed on the gate electrode 322 and overlaps with the gate electrode 322. A source electrode 352 and a drain electrode 354 are formed on the oxide semiconductor layer 340 to form the driving thin film transistor Tr.

Each of the gate electrode 322, the source electrode 352, and the drain electrode 354 is made of a low-resistance metal material. For example, each of the gate electrode 322, the source electrode 352, and the drain electrode 354 may be formed of any one of copper (Cu), aluminum (Al), titanium (Ti), and alloys thereof .

The oxide semiconductor layer 340 is made of an oxide semiconductor material. For example, the oxide semiconductor material may be any one of indium gallium zinc oxide (IGZO), zinc indium oxide (ZIO), zinc gallium oxide (ZGO), and zinc tin oxide (ZTO).

At this time, the source electrode 352 is connected to the data line. A gate insulating layer 324 made of silicon oxide is formed between the gate electrode 322 and the oxide semiconductor layer 340.

A protective layer 360 covering the driving thin film transistor Tr is formed on the entire surface of the substrate 310. The passivation layer 360 may be formed of silicon oxide and may be omitted.

A second planarization layer 362 is formed on the passivation layer 360 to provide a planar top surface.

The second planarization layer 362 may be formed of an organic insulating material such as photo-acryl or benzocyclobutene. Alternatively, the second planarization layer 362 may include a polymer matrix (not shown) and a silica nanotube (not shown) to prevent hydrogen from diffusing into the oxide semiconductor layer 120.

That is, in the third embodiment of the present invention, the first and second planarization layers 330 and 362 located below and above the oxide semiconductor layer 340 include the silica nanotubes to form the oxide semiconductor layer 340 Can be minimized.

If the protective layer 360 is omitted, the second planarization layer 362 contacts the oxide semiconductor layer 340.

The second planarization layer 362 is connected to the drain electrode 354 of the driving thin film transistor Tr through the second planarization layer 362 and the drain contact hole 364 formed in the passivation layer 360. [ The first electrode 372 is formed separately for each pixel region. The first electrode 372 may be an anode and may be formed of a conductive material having a relatively large work function value. For example, the first electrode 372 may be formed of a transparent conductive material such as ITO or IZO.

A bank layer 377 covering the edge of the first electrode 372 is formed on the second planarization layer 362. The bank layer 377 exposes the center of the first electrode 372 corresponding to the pixel region.

An organic emission layer 374 is formed on the first electrode 372. The organic light emitting layer 374 may be a single layer structure of a light emitting material layer made of a light emitting material. The organic light emitting layer 374 may include a hole injection layer, a hole transporting layer, a light emitting material layer, and an electron transporting layer, which are sequentially stacked on the first electrode 372, (electron transporting layer) and an electron injection layer (multilayer structure).

A second electrode 376 is formed on the substrate 310 on which the organic light emitting layer 374 is formed. The second electrode 376 is disposed on the entire surface of the display region and is made of a conductive material having a relatively small work function value and can be used as a cathode. For example, the second electrode 376 may be formed of any one of aluminum (Al), magnesium (Mg), and aluminum-magnesium alloy (AlMg).

The first electrode 372, the organic light emitting layer 374, and the second electrode 376 form a light emitting diode (D).

Although not shown, an encapsulation film may be formed on the second electrode 376 to prevent external moisture from penetrating into the light emitting diode D. Referring to FIG. For example, the encapsulation film may have a laminated structure of a first inorganic insulating layer (272 in FIG. 6), an organic insulating layer (274 in FIG. 6) and a second inorganic insulating layer But is not limited thereto.

In addition, a polarizing plate for reducing external light reflection may be attached on the encapsulation film. For example, the polarizer may be a circular polarizer.

As described above, in the display device 300 and the array substrate 380 of the present invention, the first and second planarization layers 330 and 362 located below and above the oxide semiconductor layer 340 are formed of silica nanotubes The diffusion of hydrogen into the oxide semiconductor layer 340 can be minimized. Therefore, deterioration of the characteristics of the driving thin film transistor Tr can be prevented.

Since the silica nanotubes 332 are porous materials, the dielectric constant of the first and second planarization layers 330 and 362 including the silica nanotubes 332 decreases, Is reduced.

That is, in the third embodiment of the present invention, the first and second planarization layers 330 and 362, which can prevent damage to the oxide semiconductor layer 340 due to hydrogen diffusion and signal delay due to parasitic capacitance, The quality of the array substrate 380 and the display device 300 can be improved.

In the display devices 100 and 200 of FIGS. 3 and 6, between the buffer layers 114 and 212 and the first substrates 110 and 210, a touch electrode (312 and 314 in FIG. 7) and a first planarization layer 7) may be formed to provide an in-cell touch type display device.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It can be understood that

100, 200, 300: display devices 120, 214, 340: oxide semiconductor layer
130, 230: protective layer
132, 232, 332: silica nanotubes 330: planarization layer
180, 280, 380: array substrate

Claims (11)

A first substrate;
A thin film transistor located on the first substrate and including an oxide semiconductor layer;
A first insulating layer disposed on the thin film transistor;
A second insulating layer located between the oxide semiconductor layer and the first insulating layer and including a silica nanotube;
And a second electrode disposed on the first insulating layer and connected to the thin film transistor,
≪ / RTI >
A first substrate;
A first insulating layer located on the first substrate;
A thin film transistor disposed on the first insulating layer and including an oxide semiconductor layer;
A second insulating layer located between the oxide semiconductor layer and the first insulating layer and including a silica nanotube;
The first electrode connected to the thin film transistor
≪ / RTI >
3. The method according to claim 1 or 2,
Wherein the second insulating layer further comprises a siloxane copolymer.
The method of claim 3,
Wherein the second insulating layer further comprises metal particles.
The method according to claim 1,
First and second touch electrodes positioned on the first substrate;
A third insulating layer covering the first and second touch electrodes;
And a fourth insulating layer positioned between the third insulating layer and the thin film transistor,
Wherein the fourth insulating layer comprises silica nanotubes.
3. The method of claim 2,
Further comprising first and second touch electrodes positioned between the first insulating layer and the first substrate.
3. The method of claim 2,
And a third insulating layer located between the thin film transistor and the first electrode and comprising silica nanotubes.
An array substrate according to claim 1 or 2;
An organic light emitting layer disposed on the first electrode;
And a second electrode located on the organic light-
.
9. The method of claim 8,
And an encapsulation film covering the light emitting diode.
An array substrate according to claim 1 or 2;
A second substrate facing the first substrate;
A liquid crystal layer disposed between the first and second substrates;
A color filter layer disposed on one of the first and second substrates;
A second electrode disposed on one of the first and second substrates,
.
11. The method of claim 10,
Wherein the second electrode is positioned between the first and second insulating layers, the second electrode has a plate shape, and the first electrode has at least one opening corresponding to the second electrode.
KR1020150191589A 2015-12-31 2015-12-31 Array substrate and Display device including the same KR20170080260A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113241353A (en) * 2021-05-28 2021-08-10 北京京东方传感技术有限公司 Photodetection substrate, method for manufacturing photodetection substrate, image sensor, and electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113241353A (en) * 2021-05-28 2021-08-10 北京京东方传感技术有限公司 Photodetection substrate, method for manufacturing photodetection substrate, image sensor, and electronic device

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