KR20170074626A - Tft substrate, display panel and display device having the same - Google Patents

Abstract

A thin film transistor substrate according to an embodiment includes: a support substrate; A bonding layer disposed over the support substrate; A first channel layer disposed over the bonding layer and including a nitride based semiconductor layer and having a first recessed region recessed upwardly in a bottom surface thereof, a first channel layer disposed on the bottom surface of the first channel layer, the first channel layer electrically connected to the first region, A switching thin film transistor including an electrode, a first drain electrode electrically connected to a second region of a lower surface of the first channel layer, and a first gate electrode disposed in a first recess region of the first channel layer; A second channel layer disposed on the bonding layer and including a nitride based semiconductor layer and having a second recessed region recessed upwardly in a bottom surface thereof, a second channel layer disposed on the bottom surface of the second channel layer, A second drain electrode electrically connected to the second region of the lower surface of the second channel layer, and a second gate electrode disposed in the second recess region of the second channel layer; A lower electrode disposed on the driving thin film transistor and electrically connected to the driving thin film transistor; A light emitting layer disposed on the lower electrode; An upper electrode disposed on the light emitting layer; . ≪ / RTI >

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a thin film transistor substrate,

The present invention relates to a thin film transistor substrate, a display panel including the same, and a display device.

As the information society develops, the demand for display devices for displaying images is increasing in various forms, and the demand for high resolution display devices is also increasing. As a method for implementing a high-resolution display device, the number of pixels per unit area is increasing. However, in order to supply gate signals and data signals in accordance with increased pixels, the number of gate wirings and the number of data wirings are increasing. However, as the number of gate wirings increases, the gate on time for providing a gate signal for one pixel becomes shorter. Therefore, development of a thin film transistor having a high carrier mobility is required.

As a method for smooth moving picture reproduction, a method of increasing a driving frequency has been studied. Even when the driving frequency is increased, a time (Gate on Time) during which a gate signal can be provided for one pixel is shortened, It is required to develop a thin film transistor having high mobility.

The embodiment provides a thin film transistor substrate, a display panel and a display device including the thin film transistor substrate, which can increase carrier mobility and ensure product reliability.

A thin film transistor substrate according to an embodiment includes: a support substrate; A bonding layer disposed on the support substrate; A first channel layer disposed on the bonding layer and including a nitride based semiconductor layer and having a first recessed region recessed upwardly on a lower surface thereof; a first channel layer disposed on the lower surface of the first channel layer, A switching transistor including a first source electrode, a first drain electrode electrically connected to a second region of a lower surface of the first channel layer, and a first gate electrode disposed in a first recess region of the first channel layer; A second channel layer disposed over the bonding layer and including a nitride based semiconductor layer and having a second recessed region recessed upwardly in a lower surface thereof; a second channel layer disposed on the lower surface of the second channel layer, A source electrode, a second drain electrode electrically connected to the second region of the lower surface of the second channel layer, and a second gate electrode disposed in the second recess region of the second channel layer; A lower electrode disposed on the driving thin film transistor and electrically connected to the driving thin film transistor; A light emitting layer disposed on the lower electrode; An upper electrode disposed on the light emitting layer; . ≪ / RTI >

A display panel according to an embodiment includes: a support substrate; A bonding layer disposed on the support substrate; A first channel layer disposed on the bonding layer and including a nitride based semiconductor layer and having a first recessed region recessed upwardly on a lower surface thereof; a first channel layer disposed on the lower surface of the first channel layer, A switching transistor including a first source electrode, a first drain electrode electrically connected to a second region of a lower surface of the first channel layer, and a first gate electrode disposed in a first recess region of the first channel layer; A second channel layer disposed over the bonding layer and including a nitride based semiconductor layer and having a second recessed region recessed upwardly in a lower surface thereof; a second channel layer disposed on the lower surface of the second channel layer, A source electrode, a second drain electrode electrically connected to the second region of the lower surface of the second channel layer, and a second gate electrode disposed in the second recess region of the second channel layer; A lower electrode disposed on the driving thin film transistor and electrically connected to the driving thin film transistor; A light emitting layer disposed on the lower electrode; An upper electrode disposed on the light emitting layer; And a thin film transistor substrate.

A display device according to an embodiment includes: a support substrate; A bonding layer disposed on the support substrate; A first channel layer disposed on the bonding layer and including a nitride based semiconductor layer and having a first recessed region recessed upwardly on a lower surface thereof; a first channel layer disposed on the lower surface of the first channel layer, A switching transistor including a first source electrode, a first drain electrode electrically connected to a second region of a lower surface of the first channel layer, and a first gate electrode disposed in a first recess region of the first channel layer; A second channel layer disposed over the bonding layer and including a nitride based semiconductor layer and having a second recessed region recessed upwardly in a lower surface thereof; a second channel layer disposed on the lower surface of the second channel layer, A source electrode, a second drain electrode electrically connected to the second region of the lower surface of the second channel layer, and a second gate electrode disposed in the second recess region of the second channel layer; A lower electrode disposed on the driving thin film transistor and electrically connected to the driving thin film transistor; A light emitting layer disposed on the lower electrode; An upper electrode disposed on the light emitting layer; A display panel including a thin film transistor substrate including a thin film transistor substrate; and a panel driver for driving the display panel.

The thin film transistor substrate, the display panel and the display device including the thin film transistor substrate according to the embodiments have a merit that high resolution can be realized by providing a high carrier mobility and a smooth moving image can be reproduced.

1 is a view illustrating a thin film transistor substrate according to an embodiment of the present invention.
2 to 14 are views illustrating an example of a manufacturing process of the thin film transistor substrate shown in FIG. 1 according to an embodiment of the present invention.
15 is a view showing an example in which a plurality of pixels are arranged on a thin film transistor substrate according to an embodiment of the present invention.
16 is a view showing an example of arrangement of source / drain contact portions and source / drain connection wirings in a thin film transistor substrate according to an embodiment of the present invention.
17 and 18 are views showing another example of the thin film transistor substrate according to the embodiment of the present invention.
19 is a view showing still another example of the thin film transistor substrate according to the embodiment of the present invention.
20 and 21 are views showing still another example of the thin film transistor substrate according to the embodiment of the present invention.
22 is a view showing another example of the thin film transistor substrate according to the embodiment of the present invention.
23 is a view showing another example of the thin film transistor substrate according to the embodiment of the present invention.
24 is a view showing still another example of the thin film transistor substrate according to the embodiment of the present invention.
25 is a view showing another example of the thin film transistor substrate according to the embodiment of the present invention.
26 is a view showing still another example of the thin film transistor substrate according to the embodiment of the present invention.
27 is a block diagram showing an example of a display device including a thin film transistor substrate according to an embodiment of the present invention.
28 is a view showing another example of the thin film transistor substrate according to the embodiment of the present invention.
FIG. 29 is a cross-sectional view of the thin film transistor substrate shown in FIG. 28 taken along line DD of FIG. 28 according to an embodiment of the present invention.
FIG. 30 is a cross-sectional view of the thin film transistor substrate shown in FIG. 28 taken along the line EE according to the embodiment of the present invention.
31 is a circuit diagram equivalent to one pixel in the thin film transistor substrate described with reference to FIGS. 28 to 30. FIG.
32 to 34 are views showing still another example of the thin film transistor substrate according to the embodiment of the present invention.
35 and 36 are views showing still another example of the thin film transistor substrate according to the embodiment of the present invention.
37 is a block diagram showing an example of a display device including a thin film transistor substrate according to an embodiment of the present invention.

In the description of the embodiments, it is to be understood that each layer (film), region, pattern or structure may be referred to as being "on" or "under" a substrate, each layer It is to be understood that the terms " on "and " under" include both " directly "or" indirectly " do. In addition, the criteria for the top / bottom or bottom / bottom of each layer are described with reference to the drawings.

Hereinafter, a thin film transistor substrate, a display panel, a display device, and a method of manufacturing a thin film transistor substrate according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view illustrating a thin film transistor substrate according to an embodiment of the present invention.

1, a thin film transistor substrate according to an embodiment of the present invention includes a support substrate 55 and a thin film transistor 30 disposed on the support substrate 55, a thin film transistor 30 electrically connected to the thin film transistor 30, And a pixel electrode 80 connected thereto.

The thin film transistor 30 according to the embodiment may include a depletion forming layer 15, a gate electrode 33, a channel layer 60, a source electrode 71, and a drain electrode 72 . The source electrode 71 may be electrically connected to a first region of the channel layer 60. The source electrode 71 may be electrically connected to the lower surface of the channel layer 60. The drain electrode 72 may be electrically connected to a second region of the channel layer 60. The drain electrode 72 may be electrically connected to the lower surface of the channel layer 60. The gate electrode 33 may be disposed under the channel layer 60. The depletion-inducing layer 15 may be disposed between the first region and the second region of the channel layer 60. The depletion-forming layer 15 may be disposed between the channel layer 60 and the gate electrode 33.

The channel layer 60 may be formed of, for example, a Group III-V compound semiconductor. For example, the channel layer 60 may be formed of a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + . The channel layer 60 may comprise a single layer or multiple layers selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP,

The channel layer 60 may include a first nitride semiconductor layer 61 and a second nitride semiconductor layer 62. The first nitride semiconductor layer 61 may be a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + . ≪ / RTI > The second nitride semiconductor layer 62 may be a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + . ≪ / RTI >

According to the embodiment, the first nitride semiconductor layer 61 may include a GaN semiconductor layer, and the second nitride semiconductor layer 62 may include an AlGaN semiconductor layer. The second nitride semiconductor layer 62 may be disposed between the first nitride semiconductor layer 61 and the depletion-forming layer 15.

The depletion-forming layer 15 may be formed of, for example, a Group III-V compound semiconductor. For example, the depletion-inducing layer 15 may be a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + Can be implemented. The depletion-forming layer 15 may include a single layer or multiple layers selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, The depletion-forming layer 15 may include a nitride semiconductor layer doped with a p-type dopant. For example, the depletion layer 15 may include a GaN semiconductor layer doped with a p-type dopant or an AlGaN semiconductor layer doped with a p-type dopant. The depletion-forming layer 15 may comprise a single layer or multiple layers embodied in a semiconductor material having a composition formula of, for example, p-Al _x Ga _1-x N (0? _X ? 0.3). The depletion-forming layer 15 may be provided with a thickness of, for example, 2 to 300 nm.

The depletion layer 15 may serve to form a depletion region in the 2DEG provided in the channel layer 60. The energy bandgap of the portion of the second nitride semiconductor layer 62 positioned thereon can be increased by the depletion-forming layer 15, and as a result, the energy bandgap of the portion corresponding to the depletion- A depletion region of the two-dimensional electron gas (2DEG) may be provided in the channel layer 60 portion. Therefore, the region corresponding to the position where the depletion-inducing layer 15 is disposed in the two-dimensional electron gas (2DEG) provided in the channel layer 60 can be cut off. The region where the two-dimensional electron gas (2DEG) is broken in the channel layer 60 may be referred to as a cut-off region. For example, a cut-off region may be formed in the second nitride semiconductor layer 62. The thin film transistor 30 may have a normally-off characteristic by the cut-off region. When a voltage equal to or higher than a threshold voltage is applied to the gate electrode 33, a two-dimensional electron gas (2DEG) is generated in the cut-off region, and the thin film transistor 30 is turned on. When the channel formed on the gate electrode 33 is turned on, a current can flow through the two-dimensional electron gas (2DEG) formed on the channel layer 60. Accordingly, the current flow from the first region to the second region of the channel layer 60 can be controlled according to the voltage applied to the gate electrode 33.

The support substrate 55 may include a transparent substrate. The support substrate 55 may be embodied as a transparent substrate having a thickness of 0.1 mm to 3 mm, for example. The support substrate 55 may include at least one material selected from materials including silicon, glass, polyimide, and plastic. The supporting substrate 55 may include a flexible substrate.

The supporting substrate 55 serves as a substrate to be used in a transfer process, which will be described later, to support the thin film transistor 30. In addition, the thin film transistor substrate according to the embodiment may include a bonding layer 50 provided between the support substrate 55 and the thin film transistor 30.

The bonding layer 50 may include an organic material. The bonding layer 50 may be formed of a transparent material. The bonding layer 50 may be formed of a material having a transmittance of 70% or more, for example. The bonding layer 50 may include an organic insulating material. The bonding layer 50 may include at least one material selected from the group consisting of acryl, benzocyclobutene (BCB), SU-8 polymer, and the like. The bonding layer 50 may be provided in a thickness of 0.5 to 6 mu m, for example.

The thin film transistor 30 according to the embodiment includes a source contact portion 31 disposed under the first region of the channel layer 60 and a drain contact portion 32 disposed under the second region of the channel layer 60 ). The source contact portion 31 may be disposed in contact with the first region of the channel layer 60. The drain contact portion 32 may be disposed in contact with the second region of the channel layer 60.

The thin film transistor 30 according to the embodiment may include a source connection wiring 42 disposed below the source contact portion 31 and a drain connection wiring 43 disposed below the drain contact portion 32 . In addition, the thin film transistor 30 may include a gate wiring 41 disposed under the gate electrode 33. The source connection wiring 42 may be electrically connected to the source contact portion 31. For example, the upper surface of the source connection wiring 42 may be disposed in contact with the lower surface of the source contact portion 31. The drain connection wiring 43 may be electrically connected to the drain contact portion 32. For example, the upper surface of the drain connection wiring 43 may be disposed in contact with the lower surface of the drain contact portion 32. The gate wiring 41 may be electrically connected to the gate electrode 33. The upper surface of the gate wiring 41 may be disposed in contact with the lower surface of the gate electrode 33.

The source electrode 71 may be electrically connected to the source connection wiring 42. The source electrode 71 may be disposed in contact with the upper surface of the source connection wiring 42. For example, the source electrode 71 may be electrically connected to the first region of the channel layer 60 through the source connection line 42 and the source contact portion 31. The drain electrode 72 may be electrically connected to the drain connection wiring 43. The drain electrode 72 may be disposed in contact with the upper surface of the drain connection wiring 43. For example, the drain electrode 72 may be electrically connected to the second region of the channel layer 60 through the drain connection wiring 43 and the drain contact portion 32.

The source contact portion 31 and the drain contact portion 32 may be formed of a material that makes an ohmic contact with the channel layer 60. [ The source contact portion 31 and the drain contact portion 32 may include a material that makes an ohmic contact with the second nitride semiconductor layer 62. For example, the source contact portion 31 and the drain contact portion 32 may be formed of a metal such as aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy Mo, Ag, Ag alloy, Au, Au alloy, Cr, Ti, Ti alloy, molybdenum tungsten, And may include a single layer or multiple layers comprising at least one material selected from the group consisting of moly titanium (MoTi), copper / moly titanium (Cu / MoTi). The source contact portion 31 and the drain contact portion 32 may be provided in a thickness of 0.1 to 1 mu m, for example.

The gate electrode 33 may be formed of a material that makes an ohmic contact with the depletion layer 15. For example, the gate electrode 33 may be formed of a metallic material in ohmic contact with the p-type nitride layer. The gate electrode 33 may be formed of tungsten (W), tungsten silicon (WSi ₂ ), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), palladium (Pd), nickel (Ni) Or a single layer or multiple layers comprising at least one material selected from the group consisting of < RTI ID = 0.0 > The gate electrode 33 may be provided in a thickness of 0.1 to 1 mu m, for example.

The gate wiring 41 may be formed of a metal such as aluminum (Al), an aluminum alloy (Al alloy), tungsten (W), copper (Cu), a copper alloy, molybdenum (Mo), silver (Ag) (Au), Au alloy, chromium (Cr), titanium (Ti), titanium alloy, molybdenum tungsten (MoW), molybdenum titanium (MoTi), copper / molybdenum titanium / MoTi). ≪ / RTI > < RTI ID = 0.0 > The gate wiring 41 may be provided in a thickness of 0.1 to 3 占 퐉, for example.

The source connection wiring 42 and the drain connection wiring 43 may be formed of a material such as aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum The present invention relates to a method of manufacturing a semiconductor device using a metal such as silver (Ag), silver alloy, gold (Au), gold alloy, chromium (Cr), titanium (Ti), titanium alloy, molybdenum tungsten (MoW) MoTi), copper / moly titanium (Cu / MoTi), and the like. The source connection wiring 42 and the drain connection wiring 43 may be provided with a thickness of 0.1 to 3 μm, for example.

The source electrode 71 and the drain electrode 72 may be formed of one selected from the group consisting of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Ag), Ag alloy, Au, Au alloy, Cr, Ti, Ti alloy, molybdenum tungsten (MoW), molybdenum titanium (MoTi) , Copper / moly titanium (Cu / MoTi), and the like. The source electrode 71 and the drain electrode 72 may be provided with a thickness of 0.1 to 3 m, for example.

The thin film transistor substrate according to the embodiment may include a first protective film 21 disposed under the channel layer 60. The first passivation layer 21 may be disposed under the second nitride semiconductor layer 62. The upper surface of the first passivation layer 21 may be disposed in contact with the lower surface of the second nitride semiconductor layer 62.

According to the embodiment, the source contact portion 31 may be disposed through the first protective film 21. The source contact portion 31 may be surrounded by the first protective film 21. The source contact portion 31 may be provided through the first protective film 21 and in contact with the first region of the channel layer 60. The drain contact portion 32 may be disposed to penetrate the first protective film 21. The drain contact portion 32 may be surrounded by the first protective film 21. The drain contact portion 32 may be disposed through the first protective layer 21 and may be provided in contact with the second region of the channel layer 60.

The first passivation layer 21 may be formed of an insulating material. The first passivation layer 21 may include a single layer or multiple layers including at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide containing Al ₂ O ₃ , and an organic insulating material .

The source connection wiring 42 may be disposed in contact with the source contact portion 31 and surrounded by the bonding layer 50. The drain connection wiring 43 may be disposed in contact with the drain contact portion 32 and surrounded by the bonding layer 50. The gate line 41 may be disposed under the gate electrode 33 and surrounded by the bonding layer 50.

The upper surface of the source connection wiring 42 may be disposed higher than the upper surface of the gate wiring 41. The upper surface of the source connection wiring 42 may be disposed higher than the lower surface of the gate electrode 33. The upper surface of the drain connection wiring 43 may be disposed higher than the upper surface of the gate wiring 41. The upper surface of the drain connection wiring 43 may be disposed higher than the lower surface of the gate electrode 33.

The thin film transistor substrate according to the embodiment may include the first protective film 21 and the second protective film 22 disposed on the channel layer 60. The source electrode 71 may be electrically connected to the source connection wiring 42 through the first protection film 21 and the second protection film 22. The source electrode 71 may include a first region disposed on the second protective layer 22. The source electrode 71 may include a second region penetrating the second protective film 22 and the first protective film 21. The drain electrode 72 may be electrically connected to the drain connection wiring 43 through the first protective film 21 and the second protective film 22. The drain electrode 72 may include a first region disposed on the second protective layer 22. The drain electrode 72 may include a second region penetrating the second passivation layer 22 and the first passivation layer 21.

The first passivation layer 21 is disposed in contact with the lower surface of the channel layer 60 and is disposed in contact with the lower surface of the second passivation layer 22 and having a first thickness, . ≪ / RTI > A region of the first protective film 21 having a first thickness may be disposed between the lower surface of the channel layer 60 and the upper surface of the gate wiring 41. A region having the second thickness of the first protective film 21 is disposed between the lower surface of the second protective film 22 and the upper surface of the source connection wiring 42 or the upper surface of the drain connection wiring 43 . A region of the first protective layer 21 having a second thickness may be disposed between the lower surface of the second protective layer 22 and the upper surface of the bonding layer 50. The first thickness of the first protective layer 21 may be thicker than the second thickness.

The second protective layer 22 may include an insulating material. The second passivation layer 22 may comprise a single layer or multiple layers including, for example, at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide containing Al ₂ O ₃ , or an organic insulating material .

The thin film transistor substrate according to the embodiment may include a third protective film 23 disposed on the second protective film 22. The third protective layer 23 may be disposed on the source electrode 71 and the drain electrode 72. The third passivation layer 23 may include a contact hole H3 provided on the drain electrode 72. [

The third protective film 23 may include a single layer or multiple layers including at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide including Al ₂ O ₃ , and an organic insulating material .

According to the embodiment, the pixel electrode 80 may be disposed on the third protective layer 23. The pixel electrode 80 may be electrically connected to the drain electrode 72 through the contact hole H3 provided in the third protective layer 23. [ The lower surface of the pixel electrode 80 may be disposed in contact with the upper surface of the drain electrode 72.

The pixel electrode 80 may be formed of a transparent conductive material. The pixel electrode 80 may be formed of a transparent conductive oxide film, for example. The pixel electrode 80 may be formed of one of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (IZTO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

Hereinafter, an example of a manufacturing process of a thin film transistor substrate according to an embodiment of the present invention will be described with reference to FIGS. 2 to 14. FIG. 2 to 13 show plan views of respective drawings, and (b) of each drawing show cross-sectional views along a line A-A in a plan view.

2, the first layer 11, the second layer 12, and the third layer 13 may be successively grown on the growth substrate 10.

The growth substrate 10 may be a substrate on which the first layer 11, the second layer 12, and the third layer 13 can be grown. The growth substrate 10 may include at least one of, for example, sapphire, SiC, GaAs, GaN, ZnO, Si, GaP, InP and Ge. A buffer layer may be further formed between the growth substrate 10 and the first layer 11.

The first layer 11, the second layer 12, and the third layer 13 may be formed of a Group III-V compound semiconductor, for example. The first layer 11, the second layer 12 and the third layer 13 may be In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, 0? _X + y < / = 1). The first layer 11, the second layer 12 and the third layer 13 may be formed of a material such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP , ≪ / RTI > and the like.

For example, the first layer 11 may be formed of a GaN semiconductor layer, and the second layer 12 may be formed of an AlGaN semiconductor layer. The third layer 13 may include a nitride semiconductor layer doped with a p-type dopant. For example, the third layer 13 may include a GaN semiconductor layer doped with a p-type dopant or an AlGaN semiconductor layer doped with a p-type dopant. The third layer 13 may comprise a single layer or multiple layers embodied in a semiconductor material having a composition formula of, for example, p-Al _x Ga _{1 - x} N (0? _X ? 0.3).

Next, as shown in FIG. 3, a depletion-forming layer 15 disposed on the second layer 12 through the etching of the third layer 13 may be formed. The depletion-forming layer 15 may be formed through, for example, a photolithography process and an etching process.

4, the first protective layer 21 may be formed on the second layer 12 and the depletion layer 15. The first passivation layer 21 may be formed of an insulating material. The first passivation layer 21 may include a single layer or multiple layers including at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide containing Al ₂ O ₃ , and an organic insulating material .

As shown in FIG. 5, a source contact portion 31 and a drain contact portion 32 may be formed on the second layer 12. The source contact portion 31 and the drain contact portion 32 may be formed on the second layer 12 through the first protective layer 21. For example, the source contact portion 31 and the drain contact portion 32 may be formed through a self-align process. The source contact portion 31 and the drain contact portion 32 may be in ohmic contact with the second layer 12. For example, the source contact portion 31 and the drain contact portion 32 may be formed of a metal such as aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy Mo, Ag, Ag alloy, Au, Au alloy, Cr, Ti, Ti alloy, molybdenum tungsten, And may include a single layer or multiple layers comprising at least one material selected from the group consisting of moly titanium (MoTi), copper / moly titanium (Cu / MoTi). The source contact portion 31 and the drain contact portion 32 may be formed to have a thickness of, for example, 0.1 to 1 m.

5 (a), the source contact portion 31 may have a length L1 in a first direction and the drain contact portion 32 may have a length L2 in the first direction have. The depletion-inducing layer 15 may be formed to have a length L3 in the first direction. For example, the side surface of the source contact portion 31 and the side surface of the drain contact portion 32 are disposed opposite to each other, and the depletion forming layer 15 is formed on the side surface of the source contact portion 31 and the drain And extend in one direction between the side surfaces of the contact portion 32. The length L3 of the depletion forming layer 15 extending in one direction may be longer than the side length L1 of the source contact portion 31. [ The length L3 of the depression forming layer 15 may be longer than the side length L2 of the drain contact portion 32. [ The depletion-imparting layer 15 disposed between the source contact portion 31 and the drain contact portion 32 is longer than the depletion-forming layer 15, It is possible to prevent a current from flowing from the source contact portion 31 to the drain contact portion 32 when the gate voltage is not applied . Thus, according to the embodiment, it is possible to provide a transistor of normally off driving.

As shown in FIG. 6, a gate electrode 33 may be formed on the depletion-inducing layer 15. The gate electrode 33 may be formed through the first protective film 21.

The gate electrode 33 may be formed of a material that makes an ohmic contact with the depletion layer 15. For example, the gate electrode 33 may be formed of a metallic material in ohmic contact with the p-type nitride layer. The gate electrode 33 may be formed of tungsten (W), tungsten silicon (WSi ₂ ), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), palladium (Pd), nickel (Ni) Or a single layer or multiple layers comprising at least one material selected from the group consisting of < RTI ID = 0.0 > The gate electrode 33 may be formed to a thickness of 0.1 to 1 占 퐉, for example.

Next, as shown in Fig. 7, a gate wiring 41, a source connection wiring 42, and a drain connection wiring 43 may be formed. The gate wiring 41 may contact the gate electrode 33 and extend in the first direction. The source connection wiring 42 may be formed in contact with the source contact portion 31 and extend in the first direction. The drain connection wiring 43 may be formed in contact with the drain contact portion 32 and extend in the first direction.

For example, the gate wiring 41, the source connection wiring 42, and the drain connection wiring 43 may be formed of aluminum (Al), aluminum alloy (Al), tungsten (W), copper (Cu) (Au), a gold alloy, a chromium (Cr), a titanium (Ti), a titanium alloy (Ti alloy), a copper alloy, a copper alloy, a molybdenum (Mo) , Molybdenum (Mo), molybdenum (Mo), molybdenum (Mo), molybdenum (Mo), molybdenum tungsten (MoW), molybdenum titanium (MoTi) and copper / moly titanium (Cu / MoTi). The gate wiring 41, the source connection wiring 42, and the drain connection wiring 43 may be provided with a thickness of 0.1 to 3 μm, for example.

Next, the bonding layer 50 and the supporting substrate 55 may be formed on the gate wiring 41, the source connection wiring 42, and the drain connection wiring 43. 8 is a view showing a structure in which the support substrate 55 is disposed at the bottom and the growth substrate 10 is disposed at the top.

The bonding layer 50 may include an organic material. The bonding layer 50 may be formed of a transparent material. The bonding layer 50 may be formed of a material having a transmittance of 70% or more, for example. The bonding layer 50 may include an organic insulating material. The bonding layer 50 may include at least one material selected from the group consisting of acryl, benzocyclobutene (BCB), SU-8 polymer, and the like. The bonding layer 50 may be formed to a thickness of 0.5 to 6 탆.

The support substrate 55 may include a transparent substrate. The support substrate 55 may be embodied as a transparent substrate having a thickness of 0.1 mm to 3 mm, for example. The support substrate 55 may include at least one material selected from materials including silicon, glass, polyimide, and plastic. The supporting substrate 55 may include a flexible substrate.

According to the embodiment, a semiconductor layer having a good quality can be formed using the growth substrate 10, and a transfer process using the support substrate 55 can be applied to the thin film transistor substrate . ≪ / RTI >

9 and 10, the growth substrate 10 is removed, and the first layer 11 and the second layer 12 are etched to form a channel layer 60 . The channel layer 60 may include a first nitride semiconductor layer 61 and a second nitride semiconductor layer 62, for example. A part of the first protective layer 21 may be exposed through the etching of the first layer 11 and the second layer 12. For example, the channel layer 60 may be formed to have the same length L3 as the depletion-forming layer 15. When the length of the depletion-forming layer 15 is smaller than the length of the channel layer 60, a leakage current may be generated.

Next, as shown in FIG. 11, a second passivation layer 22 may be formed on the channel layer 60 and the first passivation layer 21. The second protective film 22 may be referred to as a planarization layer or an overcoat layer.

A first contact hole H1 may be formed through the second protective film 22 and the first protective film 21 to expose a part of the source connection wiring 42. [ A second contact hole H2 may be formed through the second protective film 22 and the first protective film 21 to expose a part of the drain connection wiring 43. [

The second protective layer 22 may include an insulating material. The second passivation layer 22 may comprise a single layer or multiple layers including, for example, at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide containing Al ₂ O ₃ , or an organic insulating material .

As shown in FIG. 12, a source electrode 71 and a drain electrode 72 may be formed on the second protective film 22. A first region of the source electrode 71 is formed on the second protective film 22 and a second region of the source electrode 71 is formed in the first contact hole H1, As shown in FIG. A first region of the drain electrode 72 is formed on the second protective film 22 and a second region of the drain electrode 72 is formed in the second contact hole H2, As shown in FIG. A data line 73 connected to the source electrode 71 may be formed. The data line 73 may extend in one direction intersecting with the gate line 41.

For example, the source electrode 71 and the drain electrode 72 may be formed of a metal such as aluminum (Al), aluminum alloy (Al), tungsten (W), copper (Cu), copper alloy, molybdenum , Silver (Ag), silver alloy, gold (Au), gold alloy, chromium (Cr), titanium (Ti), titanium alloy, molybdenum tungsten (MoTi), copper / moly titanium (Cu / MoTi), and the like. The source electrode 71 and the drain electrode 72 may be provided with a thickness of 0.1 to 3 m, for example.

As shown in FIGS. 13 and 14, a third protective layer 23 may be formed on the source electrode 71 and the drain electrode 72. A third contact hole H3 may be formed in the third passivation layer 23 to expose the drain electrode 72. Referring to FIG.

A pixel electrode 80 may be formed on the third passivation layer 23. The pixel electrode 80 may be electrically connected to the drain electrode 72 through the third contact hole H3 provided in the third protective layer 23. [

The pixel electrode 80 may be formed of a transparent conductive material. The pixel electrode 80 may be formed of a transparent conductive oxide film, for example. The pixel electrode 80 may be formed of one of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (IZTO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

Through such a process, a basic thin film transistor substrate according to the embodiment can be formed. The manufacturing process described with reference to Figs. 2 to 14 is only one example, and the process method or the process order in each step may be modified and carried out.

15 is a view showing an example in which a plurality of pixels are arranged on a thin film transistor substrate according to an embodiment of the present invention.

The thin film transistor substrate according to the embodiment may include a plurality of thin film transistors 30 arranged in a region where the gate wiring 41 and the data wiring 73 intersect each other, as shown in FIG. The pixel electrode 80 may be disposed in an area defined by the gate line 41 and the data line 73. A portion of the pixel electrode 80 may overlap with the gate line 41.

The thin film transistor substrate according to the embodiment can be bonded to the color filter substrate to provide a liquid crystal display panel. A liquid crystal layer may be provided between the thin film transistor substrate and the color filter substrate. The color filter substrate may be provided with a common electrode, and the arrangement of the liquid crystal layers disposed therebetween may be adjusted by the voltage difference applied between the common electrode and the pixel electrode provided on the TFT substrate, and the light transmission amount of the pixel may be controlled . A liquid crystal display panel having such a structure may be referred to as a vertical electric field type liquid crystal display panel.

16 is a view showing an example of arrangement of source / drain contact portions and source / drain connection wirings in a thin film transistor substrate according to an embodiment of the present invention. 16 is an enlarged view showing a specific example of the P region shown in Fig.

As shown in FIG. 16, a part of the drain connection wiring 43 according to the embodiment may be disposed between the drain contact portion 32 and the first protective film 21. May be provided in the space between the side surface of the drain contact part 32 and the first protective film 21 in the process of forming the drain contact part 32, Some regions may be formed.

In the process of forming the through hole in the first protective film 21 to form the drain contact portion 32, the side surface of the first protective film 21 surrounding the drain contact portion 32 is formed to be inclined . The angle a2 formed by the side surface of the first protective film 21 and the top surface of the first protective film 21 may be provided at an acute angle. For example, the angle a2 formed by the side surface of the first protective film 21 and the top surface of the first protective film 21 may be 10 degrees to 90 degrees. More preferably, the angle a2 formed between the side surface of the first protective film 21 and the upper surface of the first protective film 21 may be from 30 degrees to 90 degrees. A predetermined gap t2 may be provided between the side surface of the first protective film 21 and the drain contact portion 32. For example, an interval of 0 to 3 mu m may be provided.

For example, when the first passivation layer 21 is formed of a silicon oxide such as SiO ₂ , the first passivation layer 21 may be etched by wet etching or dry etching. When the etching is performed by wet etching, the angle of a2 may be about 10 degrees to about 60 degrees, and a wider shape may be provided within a few micrometers than the pattern to be etched. When wet etching is performed, the angle of a2 may be formed at an angle of about 35 to 45 degrees. When the etching is performed by dry etching, the angle of a2 may be about 60 to 90 degrees, and a shape having a width similar to the pattern to be etched may be provided. When dry etching is performed, the angle of a2 may be formed at an angle of about 65 to 75 degrees.

Although not shown in the drawing, a part of the source connection wiring 42 according to the embodiment may be disposed between the source contact portion 31 and the first protective film 21. The source contact portion 31 may be provided in a space between the side surface of the source contact portion 31 and the first protective film 21 in the process of forming the source contact portion 31, Some regions may be formed.

The angle a1 formed by the side surface of the channel layer 60 and the lower surface of the channel layer 60 may be provided at an acute angle since the channel layer 60 is formed through the etching process . For example, the angle a1 formed between the side surface of the channel layer 60 and the lower surface of the channel layer 60 may be 30 degrees to 90 degrees. The upper surface of the first nitride semiconductor layer 61 may be provided shorter than the lower surface. The upper surface of the second nitride semiconductor layer 62 may be provided shorter than the lower surface. The lower surface of the first nitride semiconductor layer 61 and the upper surface of the second nitride semiconductor layer 62 may have the same length.

In the step of forming the channel layer 60 by etching, a partial overgrowth may be generated in the end region of the channel layer 60. Accordingly, a step may be provided on the upper surface of the first protective film 21. That is, the first protective layer 21 may be provided with a thickness different from that of a region disposed below the channel layer 60 and a region where the channel layer 60 is not disposed. As an example, the thickness t1 of the step may be provided on the order of 0 to 1 mu m. Accordingly, the lower surface of the second protective film 22 disposed on the first protective film 21 may be extended below the lower surface of the channel layer 60.

According to the thin film transistor substrate according to the embodiment, a high carrier mobility can be realized by providing the thin film transistor including the nitride based semiconductor layer. For example, the electron mobility (cm 2 / Vs) varies depending on the material used as the channel layer in the thin film transistor. In the amorphous silicon semiconductor, the electron mobility is 1, and in the case of the oxide semiconductor, And in the case of a polysilicon semiconductor, it is reported to be 100 or less. However, the thin film transistor including the nitride based semiconductor layer according to the embodiment has been measured to have an electron mobility of 1500. Accordingly, the thin film transistor including the nitride based semiconductor layer according to the embodiment can realize a 15 times higher electron mobility than the thin film transistor to which the polysilicon semiconductor is applied.

According to the embodiments, a semiconductor layer with good quality can be formed using a growth substrate, and a thin film transistor substrate having excellent electron mobility can be provided by applying a transfer process using a supporting substrate.

Therefore, according to the thin film transistor substrate, the display panel and the display device including the thin film transistor substrate according to the embodiment, it is possible to provide a high carrier mobility, thereby realizing a high resolution and reproducing a smooth moving image.

17 and 18 are views showing another example of the thin film transistor substrate according to the embodiment of the present invention. 17 and 18, the description of the thin film transistor substrate according to the embodiment may be omitted from the description of the thin film transistor substrate described with reference to FIGS. 1 to 16, Will be mainly described.

The thin film transistor substrate described with reference to FIGS. 1 to 16 can be applied to a vertical electric field type liquid crystal display panel. A pixel electrode 80 is disposed on the thin film transistor substrate and a common electrode for forming an electric field in the pixel along with the pixel electrode 80 is provided on a separate color filter substrate to realize a vertical electric field type liquid crystal display panel. Meanwhile, the thin film transistor substrate described with reference to FIGS. 17 and 18 can be applied to a horizontal electric field type liquid crystal display panel.

The thin film transistor substrate according to the embodiment may include a pixel electrode 81, a common electrode 85, and a fourth protective film 24, as shown in FIGS. 17 and 18. FIG.

The common electrode 85 may be disposed on the third protective film 23. The fourth protective film 24 may be disposed on the third protective film 23. The fourth protective film 24 may be disposed on the common electrode 85 and the third protective film 23. The common electrode 85 may be disposed between the third protective layer 23 and the fourth protective layer 24. Also, the fourth protective layer 24 may be provided on the drain electrode 72 exposed through the third protective layer 23. The pixel electrode 81 may be disposed on the fourth protective layer 24. A portion of the pixel electrode 81 may be electrically connected to the drain electrode 72 through a fourth contact hole H4 provided in the fourth protective layer 24. [ A portion of the pixel electrode 81 may be disposed in contact with the upper surface of the drain electrode 72 through the fourth contact hole H4. The pixel electrode 81 may be disposed in contact with the upper surface of the drain electrode 72 through the third protective film 23 and the fourth protective film 24. A part of the pixel electrode 81 and a part of the common electrode 85 may be overlapped with each other in the vertical direction.

The thin film transistor substrate according to the embodiment may include a plurality of thin film transistors 30 arranged in regions where the gate wiring 41 and the data wiring 73 intersect each other. The pixel electrode 81 may be disposed in a region defined by the gate line 41 and the data line 73. The pixel electrode 81 may include a finger extended portion. A portion of the pixel electrode 81 may overlap with the gate line 41.

The common electrode 85 may be formed of a transparent conductive material. The common electrode 85 may be formed of, for example, a transparent conductive oxide film. The common electrode 85 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

The pixel electrode 81 may be formed of a transparent conductive material. The pixel electrode 81 may be formed of a transparent conductive oxide film, for example. The pixel electrode 81 may be formed of one of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (IZTO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

The fourth passivation layer 24 may comprise a single layer or multiple layers including, for example, at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide containing Al ₂ O ₃ , .

The thin film transistor substrate according to the embodiment can be bonded to the color filter substrate to provide a liquid crystal display panel. A liquid crystal layer may be provided between the thin film transistor substrate and the color filter substrate. In the thin film transistor substrate according to the embodiment, the arrangement of the liquid crystal layer is adjusted by the voltage difference applied between the common electrode 85 and the pixel electrode 81, and the light transmission amount of the pixel can be controlled. The liquid crystal display panel having such a structure may be referred to as a horizontal electric field type liquid crystal display panel, a transverse electric field type liquid crystal display panel, or an IPS (In Plane Switching) liquid crystal display panel. Since the liquid crystal display panel itself has no light source, the display unit can be implemented by providing the light unit that supplies light to the liquid crystal display panel.

According to the thin film transistor substrate according to the embodiment, a high carrier mobility can be realized by providing the thin film transistor including the nitride based semiconductor layer. For example, the electron mobility (cm 2 / Vs) varies depending on the material used as the channel layer in the thin film transistor. In the amorphous silicon semiconductor, the electron mobility is 1, and in the case of the oxide semiconductor, And in the case of a polysilicon semiconductor, it is reported to be 100 or less. However, the thin film transistor including the nitride based semiconductor layer according to the embodiment has been measured to have an electron mobility of 1500. Accordingly, the thin film transistor including the nitride based semiconductor layer according to the embodiment can realize a 15 times higher electron mobility than the thin film transistor to which the polysilicon semiconductor is applied.

According to the embodiments, a semiconductor layer with good quality can be formed using a growth substrate, and a thin film transistor substrate having excellent electron mobility can be provided by applying a transfer process using a supporting substrate.

Therefore, according to the thin film transistor substrate, the display panel and the display device including the thin film transistor substrate according to the embodiment, it is possible to provide a high carrier mobility, thereby realizing a high resolution and reproducing a smooth moving image.

19 is a view showing still another example of the thin film transistor substrate according to the embodiment of the present invention. Referring to FIG. 19, a thin film transistor substrate according to an embodiment of the present invention will be described with reference to FIGS. 1 to 18, and description thereof will be omitted. .

The thin film transistor substrate according to the embodiment may include a pixel electrode 82, a common electrode 85, a metal layer 90, a touch panel lower electrode 91, and a touch panel upper electrode 92.

The common electrode 85 may be disposed on the third protective film 23. The pixel electrode 82 may be disposed on the fourth protective layer 24. The pixel electrode 82 may be electrically connected to the drain electrode 72. A metal layer 90 may be provided between the pixel electrode 82 and the drain electrode 72. The metal layer 90 may be disposed in contact with the drain electrode 72 exposed through the third protective layer 23. A portion of the pixel electrode 82 may be electrically connected to the drain electrode 72 through the metal layer 90 through the fifth contact hole H5 provided in the fourth protective layer 24. [

The touch panel upper electrode 92 may be provided on the fourth protective layer 24 and the touch panel lower electrode 91 may be disposed below the touch panel upper electrode 92. [ The touch panel lower electrode 91 may be disposed on the third protective layer 23 and may be electrically connected to the common electrode 85. The touch panel lower electrode 91 may be disposed between the common electrode 85 and the fourth protective film 24. The touch panel upper electrode 92 may be disposed to overlap with the touch panel lower electrode 91 in the vertical direction.

The touch panel upper electrode 92 and the touch panel lower electrode 91 may constitute an inshell touch panel provided in the display panel. Accordingly, the thin film transistor substrate according to the embodiment can detect whether or not the display panel is contacted from the outside by using the incelel touch panel.

The common electrode 85 may be formed of a transparent conductive material. The common electrode 85 may be formed of, for example, a transparent conductive oxide film. The common electrode 85 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

The pixel electrode 82 may be formed of a transparent conductive material. The pixel electrode 82 may be formed of a transparent conductive oxide film, for example. The pixel electrode 82 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

The touch panel lower electrode 91 and the touch panel upper electrode 92 may be formed of a transparent conductive material. The pixel electrode 82 may be formed of a transparent conductive oxide film, for example. The pixel electrode 82 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

The Insel touch panel monolithic thin film transistor substrate according to the embodiment may be bonded to a color filter substrate to provide a liquid crystal display panel. A liquid crystal layer may be provided between the in-cell touch panel integrated thin film transistor substrate and the color filter substrate. In the in-cell touch panel integrated thin film transistor substrate according to the embodiment, the arrangement of the liquid crystal layer is adjusted by the voltage difference applied between the common electrode 85 and the pixel electrode 82, and the light transmission amount of the corresponding pixel can be controlled . The Insel touch panel integrated type liquid crystal display panel having such a structure may be referred to as a horizontal electric field type liquid crystal display panel, a transverse electric field type liquid crystal display panel, or an IPS (In Plane Switching) liquid crystal display panel. Since the in-line touch panel integrated type liquid crystal display panel has no light source itself, the display unit can be implemented by providing the light unit that supplies light to the in-line touch panel integrated liquid crystal display panel.

According to the thin film transistor substrate according to the embodiment, a high carrier mobility can be realized by providing the thin film transistor including the nitride based semiconductor layer. For example, the electron mobility (cm 2 / Vs) varies depending on the material used as the channel layer in the thin film transistor. In the amorphous silicon semiconductor, the electron mobility is 1, and in the case of the oxide semiconductor, And in the case of a polysilicon semiconductor, it is reported to be 100 or less. However, the thin film transistor including the nitride based semiconductor layer according to the embodiment has been measured to have an electron mobility of 1500. Accordingly, the thin film transistor including the nitride based semiconductor layer according to the embodiment can realize a 15 times higher electron mobility than the thin film transistor to which the polysilicon semiconductor is applied.

According to the embodiments, a semiconductor layer with good quality can be formed using a growth substrate, and a thin film transistor substrate having excellent electron mobility can be provided by applying a transfer process using a supporting substrate.

Therefore, according to the thin film transistor substrate, the display panel and the display device including the thin film transistor substrate according to the embodiment, it is possible to provide a high carrier mobility, thereby realizing a high resolution and reproducing a smooth moving image.

20 and 21 are views showing still another example of the thin film transistor substrate according to the embodiment of the present invention. The thin film transistor substrate shown in FIGS. 20 and 21 is an embodiment to which a thin film transistor having a double gate structure is applied, and the description overlapping with those described with reference to FIGS. 1 to 19 may be omitted.

20 and 21, a thin film transistor substrate according to an embodiment of the present invention includes a support substrate 55 and a thin film transistor 130 disposed on the support substrate 55, the thin film transistor 130, And a pixel electrode 80 electrically connected to the pixel electrode 80.

The thin film transistor 130 according to the embodiment includes a depletion forming layer 15, a first gate electrode 35, a second gate electrode 36, a channel layer 60, a source electrode 71, Drain electrodes 72, as shown in FIG. The source electrode 71 may be electrically connected to a first region of the channel layer 60. The source electrode 71 may be electrically connected to the lower surface of the channel layer 60. The drain electrode 72 may be electrically connected to a second region of the channel layer 60. The drain electrode 72 may be electrically connected to the lower surface of the channel layer 60. The first gate electrode 35 may be disposed under the channel layer 60. The second gate electrode 36 may be disposed on the channel layer 60. The depletion-inducing layer 15 may be disposed between the first region and the second region of the channel layer 60. The depletion layer 15 may be disposed between the channel layer 60 and the first gate electrode 35.

The channel layer 60 may be formed of, for example, a Group III-V compound semiconductor. For example, the channel layer 60 may be formed of a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + . The channel layer 60 may comprise a single layer or multiple layers selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP,

The channel layer 60 may include a first nitride semiconductor layer 61 and a second nitride semiconductor layer 62. The first nitride semiconductor layer 61 may be a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + . ≪ / RTI > The second nitride semiconductor layer 62 may be a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + . ≪ / RTI >

According to the embodiment, the first nitride semiconductor layer 61 may include a GaN semiconductor layer, and the second nitride semiconductor layer 62 may include an AlGaN semiconductor layer. The second nitride semiconductor layer 62 may be disposed between the first nitride semiconductor layer 61 and the depletion-forming layer 15.

The depletion-forming layer 15 may be formed of, for example, a Group III-V compound semiconductor. For example, the depletion-inducing layer 15 may be a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + Can be implemented. The depletion-forming layer 15 may include a single layer or multiple layers selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, The depletion-forming layer 15 may include a nitride semiconductor layer doped with a p-type dopant. For example, the depletion layer 15 may include a GaN semiconductor layer doped with a p-type dopant or an AlGaN semiconductor layer doped with a p-type dopant. The depletion-forming layer 15 may comprise a single layer or multiple layers embodied in a semiconductor material having a composition formula of, for example, p-Al _x Ga _1-x N (0? _X ? 0.3). The depletion-forming layer 15 may be provided with a thickness of, for example, 2 to 300 nm.

The depletion layer 15 may serve to form a depletion region in the 2DEG provided in the channel layer 60. The energy bandgap of the portion of the second nitride semiconductor layer 62 positioned thereon can be increased by the depletion-forming layer 15, and as a result, the energy bandgap of the portion corresponding to the depletion- A depletion region of the two-dimensional electron gas (2DEG) may be provided in the channel layer 60 portion. Therefore, the region corresponding to the position where the depletion-inducing layer 15 is disposed in the two-dimensional electron gas (2DEG) provided in the channel layer 60 can be cut off. The region where the two-dimensional electron gas (2DEG) is broken in the channel layer 60 may be referred to as a cut-off region. For example, a cut-off region may be formed in the second nitride semiconductor layer 62. The thin film transistor 30 may have a normally-off characteristic by the cut-off region. When a voltage equal to or higher than a threshold voltage is applied to the gate electrode 33, a two-dimensional electron gas (2DEG) is generated in the cut-off region, and the thin film transistor 30 is turned on. When the channel formed on the upper portion of the first gate electrode 35 is turned on, a current can flow through the two-dimensional electron gas (2DEG) formed in the channel layer 60. Accordingly, the current flow from the first region to the second region of the channel layer 60 can be controlled according to the voltage applied to the first gate electrode 35 and the second gate electrode 36 . Meanwhile, according to the present embodiment, the second gate electrode 36 may be disposed on the channel layer 60. The first gate electrode 35 and the second gate electrode 36 may be overlapped with each other in the vertical direction. According to the embodiment, since the first gate electrode 35 and the second gate electrode 36 are disposed below and above the channel layer 60, the current flow in the channel layer 60 can be efficiently And can be reliably adjusted.

The support substrate 55 may include a transparent substrate. The support substrate 55 may be embodied as a transparent substrate having a thickness of 0.1 mm to 3 mm, for example. The support substrate 55 may include at least one material selected from materials including silicon, glass, polyimide, and plastic. The supporting substrate 55 may include a flexible substrate.

The supporting substrate 55 is a substrate to be used in a transfer process and supports the thin film transistor 130. In addition, the thin film transistor substrate according to the embodiment may include a bonding layer 50 provided between the supporting substrate 55 and the thin film transistor 130.

The bonding layer 50 may include an organic material. The bonding layer 50 may be formed of a transparent material. The bonding layer 50 may be formed of a material having a transmittance of 70% or more, for example. The bonding layer 50 may include an organic insulating material. The bonding layer 50 may include at least one material selected from the group consisting of acryl, benzocyclobutene (BCB), SU-8 polymer, and the like. The bonding layer 50 may be provided in a thickness of 0.5 to 6 mu m, for example.

The thin film transistor 130 according to the embodiment includes a source contact portion 31 disposed under the first region of the channel layer 60 and a drain contact portion 32 disposed under the second region of the channel layer 60 ). The source contact portion 31 may be disposed in contact with the first region of the channel layer 60. The drain contact portion 32 may be disposed in contact with the second region of the channel layer 60.

The thin film transistor 130 according to the embodiment may include a source connection wiring 42 disposed below the source contact portion 31 and a drain connection wiring 43 disposed below the drain contact portion 32 . In addition, the thin film transistor 130 may include a gate wiring 41 disposed under the first gate electrode 35. The source connection wiring 42 may be electrically connected to the source contact portion 31. For example, the upper surface of the source connection wiring 42 may be disposed in contact with the lower surface of the source contact portion 31. The drain connection wiring 43 may be electrically connected to the drain contact portion 32. For example, the upper surface of the drain connection wiring 43 may be disposed in contact with the lower surface of the drain contact portion 32. The gate line 41 may be electrically connected to the first gate electrode 35. The upper surface of the gate wiring 41 may be disposed in contact with the lower surface of the first gate electrode 35.

The source electrode 71 may be electrically connected to the source connection wiring 42. The source electrode 71 may be disposed in contact with the upper surface of the source connection wiring 42. For example, the source electrode 71 may be electrically connected to the first region of the channel layer 60 through the source connection line 42 and the source contact portion 31. The drain electrode 72 may be electrically connected to the drain connection wiring 43. The drain electrode 72 may be disposed in contact with the upper surface of the drain connection wiring 43. For example, the drain electrode 72 may be electrically connected to the second region of the channel layer 60 through the drain connection wiring 43 and the drain contact portion 32.

The source contact portion 31 and the drain contact portion 32 may be formed of a material that makes an ohmic contact with the channel layer 60. [ The source contact portion 31 and the drain contact portion 32 may include a material that makes an ohmic contact with the second nitride semiconductor layer 62. For example, the source contact portion 31 and the drain contact portion 32 may be formed of a metal such as aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy Mo, Ag, Ag alloy, Au, Au alloy, Cr, Ti, Ti alloy, molybdenum tungsten, And may include a single layer or multiple layers comprising at least one material selected from the group consisting of moly titanium (MoTi), copper / moly titanium (Cu / MoTi). The source contact portion 31 and the drain contact portion 32 may be provided in a thickness of 0.1 to 1 mu m, for example.

The first gate electrode 35 may be formed of a material that makes an ohmic contact with the depletion layer 15. For example, the first gate electrode 35 may be formed of a metallic material in ohmic contact with the p-type nitride layer. The first gate electrode 35 may be formed of tungsten (W), tungsten silicon (WSi ₂ ), titanium nitride (TiN), tantalum (Ta), tantalum nitrogen (TaN), palladium (Pd), nickel (Ni) 0.0 > Pt). ≪ / RTI > The first gate electrode 35 may be provided in a thickness of 0.1 to 1 mu m, for example.

The gate wiring 41 may be formed of a metal such as aluminum (Al), an aluminum alloy (Al alloy), tungsten (W), copper (Cu), a copper alloy, molybdenum (Mo), silver (Ag) (Au), Au alloy, chromium (Cr), titanium (Ti), titanium alloy, molybdenum tungsten (MoW), molybdenum titanium (MoTi), copper / molybdenum titanium / MoTi). ≪ / RTI > < RTI ID = 0.0 > The gate wiring 41 may be provided in a thickness of 0.1 to 3 占 퐉, for example.

The source connection wiring 42 and the drain connection wiring 43 may be formed of a material such as aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum The present invention relates to a method of manufacturing a semiconductor device using a metal such as silver (Ag), silver alloy, gold (Au), gold alloy, chromium (Cr), titanium (Ti), titanium alloy, molybdenum tungsten (MoW) MoTi), copper / moly titanium (Cu / MoTi), and the like. The source connection wiring 42 and the drain connection wiring 43 may be provided with a thickness of 0.1 to 3 μm, for example.

The source electrode 71 and the drain electrode 72 may be formed of one selected from the group consisting of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Ag), Ag alloy, Au, Au alloy, Cr, Ti, Ti alloy, molybdenum tungsten (MoW), molybdenum titanium (MoTi) , Copper / moly titanium (Cu / MoTi), and the like. The source electrode 71 and the drain electrode 72 may be provided with a thickness of 0.1 to 3 m, for example.

The thin film transistor substrate according to the embodiment may include a first protective film 21 disposed under the channel layer 60. The first passivation layer 21 may be disposed under the second nitride semiconductor layer 62. The upper surface of the first passivation layer 21 may be disposed in contact with the lower surface of the second nitride semiconductor layer 62.

According to the embodiment, the source contact portion 31 may be disposed through the first protective film 21. The source contact portion 31 may be surrounded by the first protective film 21. The source contact portion 31 may be provided through the first protective film 21 and in contact with the first region of the channel layer 60. The drain contact portion 32 may be disposed to penetrate the first protective film 21. The drain contact portion 32 may be surrounded by the first protective film 21. The drain contact portion 32 may be disposed through the first protective layer 21 and may be provided in contact with the second region of the channel layer 60.

The first passivation layer 21 may be formed of an insulating material. The first passivation layer 21 may include a single layer or multiple layers including at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide containing Al ₂ O ₃ , and an organic insulating material .

The source connection wiring 42 may be disposed in contact with the source contact portion 31 and surrounded by the bonding layer 50. The drain connection wiring 43 may be disposed in contact with the drain contact portion 32 and surrounded by the bonding layer 50. The gate line 41 may be disposed in contact with the first gate electrode 35 and surrounded by the bonding layer 50.

The upper surface of the source connection wiring 42 may be disposed higher than the upper surface of the gate wiring 41. The upper surface of the source connection wiring 42 may be disposed higher than the lower surface of the first gate electrode 35. The upper surface of the drain connection wiring 43 may be disposed higher than the upper surface of the gate wiring 41. The upper surface of the drain connection wiring 43 may be disposed higher than the lower surface of the first gate electrode 35.

The thin film transistor substrate according to the embodiment may include the first protective film 21 and the second protective film 22 disposed on the channel layer 60. The source electrode 71 may be electrically connected to the source connection wiring 42 through the first protection film 21 and the second protection film 22. The source electrode 71 may include a first region disposed on the second protective layer 22. The source electrode 71 may include a second region penetrating the second protective film 22 and the first protective film 21. The drain electrode 72 may be electrically connected to the drain connection wiring 43 through the first protective film 21 and the second protective film 22. The drain electrode 72 may include a first region disposed on the second protective layer 22. The drain electrode 72 may include a second region penetrating the second passivation layer 22 and the first passivation layer 21.

The second gate electrode 36 may include a first region disposed on the second protective film 22. The second gate electrode 36 may include a second region penetrating the second protective layer 22. The second gate electrode 36 may be disposed in contact with the upper surface of the channel layer 60 through the second protective layer 22. The second gate electrode 36 may be Schottky contact with the first nitride semiconductor layer 61. The second gate electrode 36 may be a single layer or multiple layers comprising at least one material selected from the group consisting of nickel (Ni), platinum (Pt), gold (Au), palladium (Pd) . By way of example, the sharkey contact may be implemented by plasma treatment of the channel layer 60.

The first gate electrode 35 and the second gate electrode 36 may be electrically connected as shown in FIG. The thin film transistor 130 according to the embodiment includes a first gate electrode 35 disposed under the first protective film 21 and electrically connected to the first gate electrode 35, And may include a wiring 37. The thin film transistor 130 according to the embodiment may include a second gate connection wiring 38 disposed on the second protective film 22 and extending from the second gate electrode 36. The first gate connection wiring 37 and the second gate connection wiring 38 may be electrically connected through the first protection film 21 and the second protection film 22. For example, the first gate electrode 35 and the gate wiring 41 may be integrally formed in the same process. The first gate electrode 35 and the gate wiring 41 may be separately formed and electrically connected to each other.

As shown in FIG. 21, the channel layer 60 and the depletion-imparting layer 15 may have the same width. When the width of the depletion-forming layer 15 is smaller than the width of the channel layer 60, a leakage current may be generated. In other words, the length of the channel layer 60 and the length of the depletion-imparting layer 15 provided along the direction in which the gate electrode 35 is extended and disposed may be provided equally.

The first passivation layer 21 is disposed in contact with the lower surface of the channel layer 60 and is disposed in contact with the lower surface of the second passivation layer 22 and having a first thickness, . ≪ / RTI > A region of the first protective film 21 having a first thickness may be disposed between the lower surface of the channel layer 60 and the upper surface of the gate wiring 41. A region having the second thickness of the first protective film 21 is disposed between the lower surface of the second protective film 22 and the upper surface of the source connection wiring 42 or the upper surface of the drain connection wiring 43 . A region of the first protective layer 21 having a second thickness may be disposed between the lower surface of the second protective layer 22 and the upper surface of the bonding layer 50. The first thickness of the first protective layer 21 may be thicker than the second thickness.

The second protective layer 22 may include an insulating material. The second passivation layer 22 may comprise a single layer or multiple layers including, for example, at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide containing Al ₂ O ₃ , or an organic insulating material .

The thin film transistor substrate according to the embodiment may include a third protective film 23 disposed on the second protective film 22. The third protective layer 23 may be disposed on the source electrode 71 and the drain electrode 72. The third passivation layer 23 may be disposed on the second gate electrode 36. The third passivation layer 23 may include a contact hole H3 provided on the drain electrode 72. [

The third protective film 23 may include a single layer or multiple layers including at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide including Al ₂ O ₃ , and an organic insulating material .

According to the embodiment, the pixel electrode 80 may be disposed on the third protective layer 23. The pixel electrode 80 may be electrically connected to the drain electrode 72 through the contact hole H3 provided in the third protective layer 23. [ The lower surface of the pixel electrode 80 may be disposed in contact with the upper surface of the drain electrode 72.

The pixel electrode 80 may be formed of a transparent conductive material. The pixel electrode 80 may be formed of a transparent conductive oxide film, for example. The pixel electrode 80 may be formed of one of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (IZTO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

Similarly, as described with reference to FIG. 16, a part of the drain connection interconnection 43 according to the embodiment may be disposed between the drain contact portion 32 and the first protective film 21. May be provided in the space between the side surface of the drain contact part 32 and the first protective film 21 in the process of forming the drain contact part 32, Some regions may be formed. In the process of forming the through hole in the first protective film 21 to form the drain contact portion 32, the side surface of the first protective film 21 surrounding the drain contact portion 32 is formed to be inclined . The angle a2 formed by the side surface of the first protective film 21 and the top surface of the first protective film 21 may be provided at an acute angle. For example, the angle a2 formed by the side surface of the first protective film 21 and the top surface of the first protective film 21 may be 10 degrees to 90 degrees. More preferably, the angle a2 formed between the side surface of the first protective film 21 and the upper surface of the first protective film 21 may be from 30 degrees to 90 degrees. A predetermined gap t2 may be provided between the side surface of the first protective film 21 and the drain contact portion 32. For example, an interval of 0 to 3 mu m may be provided.

For example, when the first passivation layer 21 is formed of a silicon oxide such as SiO ₂ , the first passivation layer 21 may be etched by wet etching or dry etching. When the etching is performed by wet etching, the angle of a2 may be about 10 degrees to about 60 degrees, and a wider shape may be provided within a few micrometers than the pattern to be etched. When wet etching is performed, the angle of a2 may be formed at an angle of about 35 to 45 degrees. When the etching is performed by dry etching, the angle of a2 may be about 60 to 90 degrees, and a shape having a width similar to the pattern to be etched may be provided. When dry etching is performed, the angle of a2 may be formed at an angle of about 65 to 75 degrees.

Although not shown in the drawing, a part of the source connection wiring 42 according to the embodiment may be disposed between the source contact portion 31 and the first protective film 21. The source contact portion 31 may be provided in a space between the side surface of the source contact portion 31 and the first protective film 21 in the process of forming the source contact portion 31, Some regions may be formed. The angle a1 formed by the side surface of the channel layer 60 and the lower surface of the channel layer 60 may be provided at an acute angle since the channel layer 60 is formed through the etching process . For example, the angle a1 formed between the side surface of the channel layer 60 and the lower surface of the channel layer 60 may be 30 degrees to 90 degrees. The upper surface of the first nitride semiconductor layer 61 may be provided shorter than the lower surface. The upper surface of the second nitride semiconductor layer 62 may be provided shorter than the lower surface. The lower surface of the first nitride semiconductor layer 61 and the upper surface of the second nitride semiconductor layer 62 may have the same length. In the step of forming the channel layer 60 by etching, a partial overgrowth may be generated in the end region of the channel layer 60. Accordingly, a step may be provided on the upper surface of the first protective film 21. That is, the first protective layer 21 may be provided with a thickness different from that of a region disposed below the channel layer 60 and a region where the channel layer 60 is not disposed. As an example, the thickness t1 of the step may be provided on the order of 0 to 1 mu m. Accordingly, the lower surface of the second protective film 22 disposed on the first protective film 21 may be extended below the lower surface of the channel layer 60.

The thin film transistor substrate according to the embodiment can be bonded to the color filter substrate to provide a liquid crystal display panel. A liquid crystal layer may be provided between the thin film transistor substrate and the color filter substrate. The color filter substrate may be provided with a common electrode, and the arrangement of the liquid crystal layers disposed therebetween may be adjusted by the voltage difference applied between the common electrode and the pixel electrode provided on the TFT substrate, and the light transmission amount of the pixel may be controlled . A liquid crystal display panel having such a structure may be referred to as a vertical electric field type liquid crystal display panel.

According to the thin film transistor substrate according to the embodiment, a high carrier mobility can be realized by providing the thin film transistor including the nitride based semiconductor layer. For example, the electron mobility (cm 2 / Vs) varies depending on the material used as the channel layer in the thin film transistor. In the amorphous silicon semiconductor, the electron mobility is 1, and in the case of the oxide semiconductor, And in the case of a polysilicon semiconductor, it is reported to be 100 or less. However, the thin film transistor including the nitride based semiconductor layer according to the embodiment has been measured to have an electron mobility of 1500. Accordingly, the thin film transistor including the nitride based semiconductor layer according to the embodiment can realize a 15 times higher electron mobility than the thin film transistor to which the polysilicon semiconductor is applied.

According to the embodiments, a semiconductor layer with good quality can be formed using a growth substrate, and a thin film transistor substrate having excellent electron mobility can be provided by applying a transfer process using a supporting substrate.

Therefore, according to the thin film transistor substrate, the display panel and the display device including the thin film transistor substrate according to the embodiment, it is possible to provide a high carrier mobility, thereby realizing a high resolution and reproducing a smooth moving image.

22 is a view showing another example of the thin film transistor substrate according to the embodiment of the present invention. The thin film transistor substrate shown in FIG. 22 is an embodiment to which a thin film transistor having a double gate structure is applied, and description overlapping with those described with reference to FIGS. 1 to 21 may be omitted.

The thin film transistor substrate described with reference to FIGS. 20 and 21 can be applied to a vertical electric field type liquid crystal display panel. A pixel electrode 80 is disposed on the thin film transistor substrate and a common electrode for forming an electric field in the pixel along with the pixel electrode 80 is provided on a separate color filter substrate to realize a vertical electric field type liquid crystal display panel. Meanwhile, the thin film transistor substrate described with reference to FIG. 22 can be applied to a horizontal electric field type liquid crystal display panel.

The thin film transistor substrate according to the embodiment may include a pixel electrode 81, a common electrode 85, and a fourth protective film 24, as shown in FIG.

The common electrode 85 may be disposed on the third protective film 23. The fourth protective film 24 may be disposed on the third protective film 23. The fourth protective film 24 may be disposed on the common electrode 85 and the third protective film 23. The common electrode 85 may be disposed between the third protective layer 23 and the fourth protective layer 24. Also, the fourth protective layer 24 may be provided on the drain electrode 72 exposed through the third protective layer 23. The pixel electrode 81 may be disposed on the fourth protective layer 24. A portion of the pixel electrode 81 may be electrically connected to the drain electrode 72 through a fourth contact hole H4 provided in the fourth protective layer 24. [ A portion of the pixel electrode 81 may be disposed in contact with the upper surface of the drain electrode 72 through the fourth contact hole H4. The pixel electrode 81 may be disposed in contact with the upper surface of the drain electrode 72 through the third protective film 23 and the fourth protective film 24. A part of the pixel electrode 81 and a part of the common electrode 85 may be overlapped with each other in the vertical direction.

The thin film transistor substrate according to the embodiment may include a plurality of thin film transistors 130 arranged in regions where the gate wiring 41 and the data wiring 73 intersect each other. The pixel electrode 81 may be disposed in a region defined by the gate line 41 and the data line 73. The pixel electrode 81 may include a finger extended portion. A portion of the pixel electrode 81 may overlap with the gate line 41.

The common electrode 85 may be formed of a transparent conductive material. The common electrode 85 may be formed of, for example, a transparent conductive oxide film. The common electrode 85 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

The pixel electrode 81 may be formed of a transparent conductive material. The pixel electrode 81 may be formed of a transparent conductive oxide film, for example. The pixel electrode 81 may be formed of one of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (IZTO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

The fourth passivation layer 24 may comprise a single layer or multiple layers including, for example, at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide containing Al ₂ O ₃ , .

The thin film transistor substrate according to the embodiment can be bonded to the color filter substrate to provide a liquid crystal display panel. A liquid crystal layer may be provided between the thin film transistor substrate and the color filter substrate. In the thin film transistor substrate according to the embodiment, the arrangement of the liquid crystal layer is adjusted by the voltage difference applied between the common electrode 85 and the pixel electrode 81, and the light transmission amount of the pixel can be controlled. The liquid crystal display panel having such a structure may be referred to as a horizontal electric field type liquid crystal display panel, a transverse electric field type liquid crystal display panel, or an IPS (In Plane Switching) liquid crystal display panel. Since the liquid crystal display panel itself has no light source, the display unit can be implemented by providing the light unit that supplies light to the liquid crystal display panel.

According to the thin film transistor substrate according to the embodiment, a high carrier mobility can be realized by providing the thin film transistor including the nitride based semiconductor layer. For example, the electron mobility (cm 2 / Vs) varies depending on the material used as the channel layer in the thin film transistor. In the amorphous silicon semiconductor, the electron mobility is 1, and in the case of the oxide semiconductor, And in the case of a polysilicon semiconductor, it is reported to be 100 or less. However, the thin film transistor including the nitride based semiconductor layer according to the embodiment has been measured to have an electron mobility of 1500. Accordingly, the thin film transistor including the nitride based semiconductor layer according to the embodiment can realize a 15 times higher electron mobility than the thin film transistor to which the polysilicon semiconductor is applied.

According to the embodiments, a semiconductor layer with good quality can be formed using a growth substrate, and a thin film transistor substrate having excellent electron mobility can be provided by applying a transfer process using a supporting substrate.

Therefore, according to the thin film transistor substrate, the display panel and the display device including the thin film transistor substrate according to the embodiment, it is possible to provide a high carrier mobility, thereby realizing a high resolution and reproducing a smooth moving image.

23 is a view showing another example of the thin film transistor substrate according to the embodiment of the present invention. The thin film transistor substrate shown in FIG. 23 is an embodiment to which a thin film transistor having a double gate structure is applied, and a description of portions overlapping with those described with reference to FIGS. 1 to 22 may be omitted.

The thin film transistor substrate according to the embodiment may include a pixel electrode 82, a common electrode 85, a metal layer 90, a touch panel lower electrode 91, and a touch panel upper electrode 92.

The common electrode 85 may be disposed on the third protective film 23. The pixel electrode 82 may be disposed on the fourth protective layer 24. The pixel electrode 82 may be electrically connected to the drain electrode 72. A metal layer 90 may be provided between the pixel electrode 82 and the drain electrode 72. The metal layer 90 may be disposed in contact with the drain electrode 72 exposed through the third protective layer 23. A portion of the pixel electrode 82 may be electrically connected to the drain electrode 72 through the metal layer 90 through the fifth contact hole H5 provided in the fourth protective layer 24. [

The touch panel upper electrode 92 may be provided on the fourth protective layer 24 and the touch panel lower electrode 91 may be disposed below the touch panel upper electrode 92. [ The touch panel lower electrode 91 may be disposed on the third protective layer 23 and may be electrically connected to the common electrode 85. The touch panel lower electrode 91 may be disposed between the common electrode 85 and the fourth protective film 24. The touch panel upper electrode 92 may be disposed to overlap with the touch panel lower electrode 91 in the vertical direction.

The touch panel upper electrode 92 and the touch panel lower electrode 91 may constitute an inshell touch panel provided in the display panel. Accordingly, the thin film transistor substrate according to the embodiment can detect whether or not the display panel is contacted from the outside by using the incelel touch panel.

The common electrode 85 may be formed of a transparent conductive material. The common electrode 85 may be formed of, for example, a transparent conductive oxide film. The common electrode 85 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

The pixel electrode 82 may be formed of a transparent conductive material. The pixel electrode 82 may be formed of a transparent conductive oxide film, for example. The pixel electrode 82 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

The touch panel lower electrode 91 and the touch panel upper electrode 92 may be formed of a transparent conductive material. The pixel electrode 82 may be formed of a transparent conductive oxide film, for example. The pixel electrode 82 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

The Insel touch panel monolithic thin film transistor substrate according to the embodiment may be bonded to a color filter substrate to provide a liquid crystal display panel. A liquid crystal layer may be provided between the in-cell touch panel integrated thin film transistor substrate and the color filter substrate. In the in-cell touch panel integrated thin film transistor substrate according to the embodiment, the arrangement of the liquid crystal layer is adjusted by the voltage difference applied between the common electrode 85 and the pixel electrode 82, and the light transmission amount of the corresponding pixel can be controlled . The Insel touch panel integrated type liquid crystal display panel having such a structure may be referred to as a horizontal electric field type liquid crystal display panel, a transverse electric field type liquid crystal display panel, or an IPS (In Plane Switching) liquid crystal display panel. Since the in-line touch panel integrated type liquid crystal display panel has no light source itself, the display unit can be implemented by providing the light unit that supplies light to the in-line touch panel integrated liquid crystal display panel.

According to the thin film transistor substrate according to the embodiment, a high carrier mobility can be realized by providing the thin film transistor including the nitride based semiconductor layer. For example, the electron mobility (cm 2 / Vs) varies depending on the material used as the channel layer in the thin film transistor. In the amorphous silicon semiconductor, the electron mobility is 1, and in the case of the oxide semiconductor, And in the case of a polysilicon semiconductor, it is reported to be 100 or less. However, the thin film transistor including the nitride based semiconductor layer according to the embodiment has been measured to have an electron mobility of 1500. Accordingly, the thin film transistor including the nitride based semiconductor layer according to the embodiment can realize a 15 times higher electron mobility than the thin film transistor to which the polysilicon semiconductor is applied.

According to the embodiments, a semiconductor layer with good quality can be formed using a growth substrate, and a thin film transistor substrate having excellent electron mobility can be provided by applying a transfer process using a supporting substrate.

Therefore, according to the thin film transistor substrate, the display panel and the display device including the thin film transistor substrate according to the embodiment, it is possible to provide a high carrier mobility, thereby realizing a high resolution and reproducing a smooth moving image.

24 is a view showing still another example of the thin film transistor substrate according to the embodiment of the present invention. The thin film transistor substrate shown in FIG. 24 is an embodiment in which a thin film transistor having a structure in which gates are disposed in a recessed region of a channel layer is applied, and description overlapping with those described in FIGS. 1 to 23 will be described Can be omitted.

24, a thin film transistor substrate according to an embodiment of the present invention includes a support substrate 55 and a thin film transistor 230 disposed on the support substrate 55, a thin film transistor 230 electrically connected to the thin film transistor 230, And a pixel electrode 80 connected thereto.

The thin film transistor 230 according to the embodiment may include a gate electrode 233, a channel layer 260, a source electrode 71, and a drain electrode 72. The source electrode 71 may be electrically connected to a first region of the channel layer 260. The source electrode 71 may be electrically connected to the lower surface of the channel layer 260. The drain electrode 72 may be electrically connected to a second region of the channel layer 260. The drain electrode 72 may be electrically connected to the lower surface of the channel layer 260. The gate electrode 233 may be disposed under the channel layer 260.

The channel layer 260 may include a recessed region recessed upwardly in the lower surface. The gate electrode 233 may be disposed in the recessed region of the channel layer 60.

The channel layer 260 may be formed of, for example, a Group III-V compound semiconductor. For example, the channel layer 260 may be formed of a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + . The channel layer 260 may include a single layer or multiple layers selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP,

The channel layer 260 may include a first nitride semiconductor layer 261 and a second nitride semiconductor layer 262. The first nitride semiconductor layer 261 may be a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + y? . ≪ / RTI > The second nitride semiconductor layer 262 may be a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + y? . ≪ / RTI > And may be provided in a recessed region recessed upwardly on the lower surface of the second nitride semiconductor layer 262. The gate electrode 233 may be disposed in a recessed region of the second nitride semiconductor layer 262. The upper surface of the gate electrode 233 may be disposed higher than the lower surface of the second nitride semiconductor layer 262. The gate electrode 233 and the second nitride semiconductor layer 262 may be Schottky contact.

According to the embodiment, the first nitride semiconductor layer 261 may include a GaN semiconductor layer, and the second nitride semiconductor layer 262 may include an AlGaN semiconductor layer.

The support substrate 55 may include a transparent substrate. The support substrate 55 may be embodied as a transparent substrate having a thickness of 0.1 mm to 3 mm, for example. The support substrate 55 may include at least one material selected from materials including silicon, glass, polyimide, and plastic. The supporting substrate 55 may include a flexible substrate.

The supporting substrate 55 is a substrate to be used in a transfer process and supports the thin film transistor 230. In addition, the thin film transistor substrate according to the embodiment may include a bonding layer 50 provided between the supporting substrate 55 and the thin film transistor 230.

The bonding layer 50 may include an organic material. The bonding layer 50 may be formed of a transparent material. The bonding layer 50 may be formed of a material having a transmittance of 70% or more, for example. The bonding layer 50 may include an organic insulating material. The bonding layer 50 may include at least one material selected from the group consisting of acryl, benzocyclobutene (BCB), SU-8 polymer, and the like. The bonding layer 50 may be provided in a thickness of 0.5 to 6 mu m, for example.

The thin film transistor 230 according to the embodiment includes a source contact portion 31 disposed under the first region of the channel layer 260 and a drain contact portion 32 disposed under the second region of the channel layer 260. [ ). The source contact portion 31 may be disposed in contact with the first region of the channel layer 260. The drain contact portion 32 may be disposed in contact with the second region of the channel layer 260.

The thin film transistor 230 according to the embodiment may include a source connection wiring 42 disposed below the source contact portion 31 and a drain connection wiring 43 disposed below the drain contact portion 32 . In addition, the thin film transistor 230 may include a gate wiring 41 disposed under the gate electrode 233. The source connection wiring 42 may be electrically connected to the source contact portion 31. For example, the upper surface of the source connection wiring 42 may be disposed in contact with the lower surface of the source contact portion 31. The drain connection wiring 43 may be electrically connected to the drain contact portion 32. For example, the upper surface of the drain connection wiring 43 may be disposed in contact with the lower surface of the drain contact portion 32. The gate wiring 41 may be electrically connected to the gate electrode 233. The upper surface of the gate wiring 41 may be disposed in contact with the lower surface of the gate electrode 233. [

The source electrode 71 may be electrically connected to the source connection wiring 42. The source electrode 71 may be disposed in contact with the upper surface of the source connection wiring 42. For example, the source electrode 71 may be electrically connected to the first region of the channel layer 260 through the source connection line 42 and the source contact portion 31. The drain electrode 72 may be electrically connected to the drain connection wiring 43. The drain electrode 72 may be disposed in contact with the upper surface of the drain connection wiring 43. For example, the drain electrode 72 may be electrically connected to the second region of the channel layer 260 through the drain connection wiring 43 and the drain contact portion 32.

The source contact portion 31 and the drain contact portion 32 may be formed of a material that makes an ohmic contact with the channel layer 260. The source contact portion 31 and the drain contact portion 32 may include a material that makes an ohmic contact with the second nitride semiconductor layer 262. For example, the source contact portion 31 and the drain contact portion 32 may be formed of a metal such as aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy Mo, Ag, Ag alloy, Au, Au alloy, Cr, Ti, Ti alloy, molybdenum tungsten, And may include a single layer or multiple layers comprising at least one material selected from the group consisting of moly titanium (MoTi), copper / moly titanium (Cu / MoTi). The source contact portion 31 and the drain contact portion 32 may be provided in a thickness of 0.1 to 1 mu m, for example.

The gate electrode 233 may be formed of a material that makes shark-contacting with the channel layer 260. The gate electrode 233 may be formed of a material which is in contact with the second nitride semiconductor layer 262 in a shark-like manner. The gate electrode 233 may comprise a single layer or multiple layers comprising at least one material selected from the group consisting of nickel (Ni), platinum (Pt), gold (Au), palladium . By way of example, the sharkey contact may be implemented by a plasma treatment for the channel layer 260. As the plasma treatment, for example, fluorine (F) ion treatment may be applied. Accordingly, the thin film transistor 230 according to the embodiment can be provided with a threshold voltage by the sharkey contact and can have a normally off characteristic. When a voltage equal to or higher than the threshold voltage is applied to the gate electrode 233, a channel formed on the gate electrode 233 is turned on to allow current to flow through the channel layer 260.

The gate wiring 41 may be formed of a metal such as aluminum (Al), an aluminum alloy (Al alloy), tungsten (W), copper (Cu), a copper alloy, molybdenum (Mo), silver (Ag) (Au), Au alloy, chromium (Cr), titanium (Ti), titanium alloy, molybdenum tungsten (MoW), molybdenum titanium (MoTi), copper / molybdenum titanium / MoTi). ≪ / RTI > < RTI ID = 0.0 > The gate wiring 41 may be provided in a thickness of 0.1 to 3 占 퐉, for example.

The source connection wiring 42 and the drain connection wiring 43 may be formed of a material such as aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum The present invention relates to a method of manufacturing a semiconductor device using a metal such as silver (Ag), silver alloy, gold (Au), gold alloy, chromium (Cr), titanium (Ti), titanium alloy, molybdenum tungsten (MoW) MoTi), copper / moly titanium (Cu / MoTi), and the like. The source connection wiring 42 and the drain connection wiring 43 may be provided with a thickness of 0.1 to 3 μm, for example.

The source electrode 71 and the drain electrode 72 may be formed of one selected from the group consisting of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum (Ag), Ag alloy, Au, Au alloy, Cr, Ti, Ti alloy, molybdenum tungsten (MoW), molybdenum titanium (MoTi) , Copper / moly titanium (Cu / MoTi), and the like. The source electrode 71 and the drain electrode 72 may be provided with a thickness of 0.1 to 3 m, for example.

The thin film transistor substrate according to an embodiment may include a first protective film 21 disposed under the channel layer 260. The first passivation layer 21 may be disposed under the second nitride semiconductor layer 262. The upper surface of the first passivation layer 21 may be disposed in contact with the lower surface of the second nitride semiconductor layer 262.

According to the embodiment, the source contact portion 31 may be disposed through the first protective film 21. The source contact portion 31 may be surrounded by the first protective film 21. The source contact portion 31 may be disposed through the first protective layer 21 and may be provided in contact with the first region of the channel layer 260. The drain contact portion 32 may be disposed to penetrate the first protective film 21. The drain contact portion 32 may be surrounded by the first protective film 21. The drain contact portion 32 may be provided through the first protective film 21 and in contact with the second region of the channel layer 260.

The first passivation layer 21 may be formed of an insulating material. The first passivation layer 21 may include a single layer or multiple layers including at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide containing Al ₂ O ₃ , and an organic insulating material .

The source connection wiring 42 may be disposed in contact with the source contact portion 31 and surrounded by the bonding layer 50. The drain connection wiring 43 may be disposed in contact with the drain contact portion 32 and surrounded by the bonding layer 50. The gate line 41 may be disposed in contact with the gate electrode 233 and surrounded by the bonding layer 50.

The thin film transistor substrate according to the embodiment may include the first protective film 21 and the second protective film 22 disposed on the channel layer 260. The source electrode 71 may be electrically connected to the source connection wiring 42 through the first protection film 21 and the second protection film 22. The source electrode 71 may include a first region disposed on the second protective layer 22. The source electrode 71 may include a second region penetrating the second protective film 22 and the first protective film 21. The drain electrode 72 may be electrically connected to the drain connection wiring 43 through the first protective film 21 and the second protective film 22. The drain electrode 72 may include a first region disposed on the second protective layer 22. The drain electrode 72 may include a second region penetrating the second passivation layer 22 and the first passivation layer 21.

The second protective layer 22 may include an insulating material. The second passivation layer 22 may comprise a single layer or multiple layers including, for example, at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide containing Al ₂ O ₃ , or an organic insulating material .

The thin film transistor substrate according to the embodiment may include a third protective film 23 disposed on the second protective film 22. The third protective layer 23 may be disposed on the source electrode 71 and the drain electrode 72. The third passivation layer 23 may include a contact hole H3 provided on the drain electrode 72. [

The third protective film 23 may include a single layer or multiple layers including at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide including Al ₂ O ₃ , and an organic insulating material .

According to the embodiment, the pixel electrode 80 may be disposed on the third protective layer 23. The pixel electrode 80 may be electrically connected to the drain electrode 72 through the contact hole H3 provided in the third protective layer 23. [ The lower surface of the pixel electrode 80 may be disposed in contact with the upper surface of the drain electrode 72.

The pixel electrode 80 may be formed of a transparent conductive material. The pixel electrode 80 may be formed of a transparent conductive oxide film, for example. The pixel electrode 80 may be formed of one of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (IZTO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

The thin film transistor substrate according to the embodiment can be bonded to the color filter substrate to provide a liquid crystal display panel. A liquid crystal layer may be provided between the thin film transistor substrate and the color filter substrate. The color filter substrate may be provided with a common electrode, and the arrangement of the liquid crystal layers disposed therebetween may be adjusted by the voltage difference applied between the common electrode and the pixel electrode provided on the TFT substrate, and the light transmission amount of the pixel may be controlled . A liquid crystal display panel having such a structure may be referred to as a vertical electric field type liquid crystal display panel.

According to the thin film transistor substrate according to the embodiment, a high carrier mobility can be realized by providing the thin film transistor including the nitride based semiconductor layer. For example, the electron mobility (cm 2 / Vs) varies depending on the material used as the channel layer in the thin film transistor. In the amorphous silicon semiconductor, the electron mobility is 1, and in the case of the oxide semiconductor, And in the case of a polysilicon semiconductor, it is reported to be 100 or less. However, the thin film transistor including the nitride based semiconductor layer according to the embodiment has been measured to have an electron mobility of 1500. Accordingly, the thin film transistor including the nitride based semiconductor layer according to the embodiment can realize a 15 times higher electron mobility than the thin film transistor to which the polysilicon semiconductor is applied.

According to the embodiments, a semiconductor layer with good quality can be formed using a growth substrate, and a thin film transistor substrate having excellent electron mobility can be provided by applying a transfer process using a supporting substrate.

Therefore, according to the thin film transistor substrate, the display panel and the display device including the thin film transistor substrate according to the embodiment, it is possible to provide a high carrier mobility, thereby realizing a high resolution and reproducing a smooth moving image.

25 is a view showing another example of the thin film transistor substrate according to the embodiment of the present invention. The thin film transistor substrate shown in FIG. 25 is an embodiment in which a thin film transistor having a structure in which gates are disposed in a recessed region of a channel layer is applied, and description overlapping with those described in FIGS. 1 to 24 will be described Can be omitted.

The thin film transistor substrate described with reference to FIG. 24 can be applied to a vertical electric field type liquid crystal display panel. Meanwhile, the thin film transistor substrate described with reference to FIG. 25 can be applied to a horizontal electric field type liquid crystal display panel.

The thin film transistor substrate according to the embodiment may include a pixel electrode 81, a common electrode 85, and a fourth protective film 24 as shown in FIG.

The common electrode 85 may be disposed on the third protective film 23. The fourth protective film 24 may be disposed on the third protective film 23. The fourth protective film 24 may be disposed on the common electrode 85 and the third protective film 23. The common electrode 85 may be disposed between the third protective layer 23 and the fourth protective layer 24. Also, the fourth protective layer 24 may be provided on the drain electrode 72 exposed through the third protective layer 23. The pixel electrode 81 may be disposed on the fourth protective layer 24. A portion of the pixel electrode 81 may be electrically connected to the drain electrode 72 through a fourth contact hole H4 provided in the fourth protective layer 24. [ A portion of the pixel electrode 81 may be disposed in contact with the upper surface of the drain electrode 72 through the fourth contact hole H4. The pixel electrode 81 may be disposed in contact with the upper surface of the drain electrode 72 through the third protective film 23 and the fourth protective film 24. A part of the pixel electrode 81 and a part of the common electrode 85 may be overlapped with each other in the vertical direction.

The thin film transistor substrate according to the embodiment may include a plurality of thin film transistors 230 arranged in a region where the gate wiring 41 and the data wiring 73 intersect each other. The pixel electrode 81 may be disposed in a region defined by the gate line 41 and the data line 73. The pixel electrode 81 may include a finger extended portion. A portion of the pixel electrode 81 may overlap with the gate line 41.

The common electrode 85 may be formed of a transparent conductive material. The common electrode 85 may be formed of, for example, a transparent conductive oxide film. The common electrode 85 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

The pixel electrode 81 may be formed of a transparent conductive material. The pixel electrode 81 may be formed of a transparent conductive oxide film, for example. The pixel electrode 81 may be formed of one of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (IZTO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

The fourth passivation layer 24 may comprise a single layer or multiple layers including, for example, at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide containing Al ₂ O ₃ , .

The thin film transistor substrate according to the embodiment can be bonded to the color filter substrate to provide a liquid crystal display panel. A liquid crystal layer may be provided between the thin film transistor substrate and the color filter substrate. In the thin film transistor substrate according to the embodiment, the arrangement of the liquid crystal layer is adjusted by the voltage difference applied between the common electrode 85 and the pixel electrode 81, and the light transmission amount of the pixel can be controlled. The liquid crystal display panel having such a structure may be referred to as a horizontal electric field type liquid crystal display panel, a transverse electric field type liquid crystal display panel, or an IPS (In Plane Switching) liquid crystal display panel. Since the liquid crystal display panel itself has no light source, the display unit can be implemented by providing the light unit that supplies light to the liquid crystal display panel.

According to the thin film transistor substrate according to the embodiment, a high carrier mobility can be realized by providing the thin film transistor including the nitride based semiconductor layer. For example, the electron mobility (cm 2 / Vs) varies depending on the material used as the channel layer in the thin film transistor. In the amorphous silicon semiconductor, the electron mobility is 1, and in the case of the oxide semiconductor, And in the case of a polysilicon semiconductor, it is reported to be 100 or less. However, the thin film transistor including the nitride based semiconductor layer according to the embodiment has been measured to have an electron mobility of 1500. Accordingly, the thin film transistor including the nitride based semiconductor layer according to the embodiment can realize a 15 times higher electron mobility than the thin film transistor to which the polysilicon semiconductor is applied.

According to the embodiments, a semiconductor layer with good quality can be formed using a growth substrate, and a thin film transistor substrate having excellent electron mobility can be provided by applying a transfer process using a supporting substrate.

Therefore, according to the thin film transistor substrate, the display panel and the display device including the thin film transistor substrate according to the embodiment, it is possible to provide a high carrier mobility, thereby realizing a high resolution and reproducing a smooth moving image.

26 is a view showing still another example of the thin film transistor substrate according to the embodiment of the present invention. The thin film transistor substrate shown in FIG. 26 is an embodiment in which a thin film transistor having a structure in which gates are arranged in a recessed region of a channel layer is applied, and description overlapping with those described in FIGS. 1 to 25 will be described Can be omitted.

The thin film transistor substrate according to the embodiment may include a pixel electrode 82, a common electrode 85, a metal layer 90, a touch panel lower electrode 91, and a touch panel upper electrode 92.

The common electrode 85 may be disposed on the third protective film 23. The pixel electrode 82 may be disposed on the fourth protective layer 24. The pixel electrode 82 may be electrically connected to the drain electrode 72. A metal layer 90 may be provided between the pixel electrode 82 and the drain electrode 72. The metal layer 90 may be disposed in contact with the drain electrode 72 exposed through the third protective layer 23. A portion of the pixel electrode 82 may be electrically connected to the drain electrode 72 through the metal layer 90 through the fifth contact hole H5 provided in the fourth protective layer 24. [

The touch panel upper electrode 92 may be provided on the fourth protective layer 24 and the touch panel lower electrode 91 may be disposed below the touch panel upper electrode 92. [ The touch panel lower electrode 91 may be disposed on the third protective layer 23 and may be electrically connected to the common electrode 85. The touch panel lower electrode 91 may be disposed between the common electrode 85 and the fourth protective film 24. The touch panel upper electrode 92 may be disposed to overlap with the touch panel lower electrode 91 in the vertical direction.

The touch panel upper electrode 92 and the touch panel lower electrode 91 may constitute an inshell touch panel provided in the display panel. Accordingly, the thin film transistor substrate according to the embodiment can detect whether or not the display panel is contacted from the outside by using the incelel touch panel.

The common electrode 85 may be formed of a transparent conductive material. The common electrode 85 may be formed of, for example, a transparent conductive oxide film. The common electrode 85 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

The pixel electrode 82 may be formed of a transparent conductive material. The pixel electrode 82 may be formed of a transparent conductive oxide film, for example. The pixel electrode 82 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

The touch panel lower electrode 91 and the touch panel upper electrode 92 may be formed of a transparent conductive material. The pixel electrode 82 may be formed of a transparent conductive oxide film, for example. The pixel electrode 82 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), aluminum gallium zinc oxide (AGZO), indium zinc tin oxide (IZTO) ), IGZO (Indium Gallium Zinc Oxide), IGTO (Indium Gallium Tin Oxide), ATO (Antimony Tin Oxide), GZO (Gallium Zinc Oxide) and IZON (IZO Nitride).

The Insel touch panel monolithic thin film transistor substrate according to the embodiment may be bonded to a color filter substrate to provide a liquid crystal display panel. A liquid crystal layer may be provided between the in-cell touch panel integrated thin film transistor substrate and the color filter substrate. In the in-cell touch panel integrated thin film transistor substrate according to the embodiment, the arrangement of the liquid crystal layer is adjusted by the voltage difference applied between the common electrode 85 and the pixel electrode 82, and the light transmission amount of the corresponding pixel can be controlled . The Insel touch panel integrated type liquid crystal display panel having such a structure may be referred to as a horizontal electric field type liquid crystal display panel, a transverse electric field type liquid crystal display panel, or an IPS (In Plane Switching) liquid crystal display panel. Since the in-line touch panel integrated type liquid crystal display panel has no light source itself, the display unit can be implemented by providing the light unit that supplies light to the in-line touch panel integrated liquid crystal display panel.

According to the thin film transistor substrate according to the embodiment, a high carrier mobility can be realized by providing the thin film transistor including the nitride based semiconductor layer. For example, the electron mobility (cm 2 / Vs) varies depending on the material used as the channel layer in the thin film transistor. In the amorphous silicon semiconductor, the electron mobility is 1, and in the case of the oxide semiconductor, And in the case of a polysilicon semiconductor, it is reported to be 100 or less. However, the thin film transistor including the nitride based semiconductor layer according to the embodiment has been measured to have an electron mobility of 1500. Accordingly, the thin film transistor including the nitride based semiconductor layer according to the embodiment can realize a 15 times higher electron mobility than the thin film transistor to which the polysilicon semiconductor is applied.

According to the embodiments, a semiconductor layer with good quality can be formed using a growth substrate, and a thin film transistor substrate having excellent electron mobility can be provided by applying a transfer process using a supporting substrate.

Therefore, according to the thin film transistor substrate, the display panel and the display device including the thin film transistor substrate according to the embodiment, it is possible to provide a high carrier mobility, thereby realizing a high resolution and reproducing a smooth moving image.

27 is a block diagram showing an example of a display device including a thin film transistor substrate according to an embodiment of the present invention.

The display device according to the embodiment may include a display panel 1100, a light unit 1200, and a panel driver 1300 as shown in Fig.

The display panel 1100 may include any one of the thin film transistor substrates described with reference to FIGS. 1 to 26 and a color filter substrate disposed on the thin film transistor substrate. The display panel 1100 may include a liquid crystal layer disposed between the thin film transistor substrate and the color filter substrate.

The light unit 1200 may be disposed below the display panel 1100 and may supply light to the display panel 1100. The panel driver 1300 may provide a driving signal to the display panel 1100. The panel driver 1300 may control the light transmittance of a plurality of pixels provided in the display panel 1100 and may display an image on the display panel 1100 using light provided from the light unit 1200 .

According to the thin film transistor substrate according to the embodiment, a high carrier mobility can be realized by providing the thin film transistor including the nitride based semiconductor layer. For example, the electron mobility (cm 2 / Vs) varies depending on the material used as the channel layer in the thin film transistor. In the amorphous silicon semiconductor, the electron mobility is 1, and in the case of the oxide semiconductor, And in the case of a polysilicon semiconductor, it is reported to be 100 or less. However, the thin film transistor including the nitride based semiconductor layer according to the embodiment has been measured to have an electron mobility of 1500. Accordingly, the thin film transistor including the nitride based semiconductor layer according to the embodiment can realize a 15 times higher electron mobility than the thin film transistor to which the polysilicon semiconductor is applied.

According to the embodiments, a semiconductor layer with good quality can be formed using a growth substrate, and a thin film transistor substrate having excellent electron mobility can be provided by applying a transfer process using a supporting substrate.

Therefore, according to the thin film transistor substrate, the display panel and the display device including the thin film transistor substrate according to the embodiment, it is possible to provide a high carrier mobility, thereby realizing a high resolution and reproducing a smooth moving image.

28 is a view showing another example of the thin film transistor substrate according to the embodiment of the present invention. FIG. 29 is a cross-sectional view taken along the line D-D of the thin film transistor substrate shown in FIG. 28, and FIG. 30 is a cross-sectional view taken along the line E-E of the thin film transistor substrate shown in FIG.

The embodiments described with reference to FIGS. 1 to 27 relate to a thin film transistor substrate that can be applied to a liquid crystal display, and the thin film transistor substrate described with reference to FIGS. 28 to 30 can be applied to an organic light emitting display .

The thin film transistor substrate according to the embodiment may include a switching thin film transistor 330 and a driving thin film transistor 430. The switching thin film transistor 330 may receive a signal from the gate line 341 and the data line 373 and may provide a gate signal and a data signal to the pixel. The switching thin film transistor 330 may include a first gate electrode 333, a first source electrode 371, and a first drain electrode 372. The driving thin film transistor 430 may include a second gate electrode 433, a second source electrode 471, and a second drain electrode 472. The second gate electrode 433 of the driving thin film transistor 430 may be electrically connected to the first drain electrode 372 of the switching thin film transistor 330. The second source electrode 471 of the driving thin film transistor 430 may be connected to a driving power supply line (Vdd, 474). The operation of the switching thin film transistor 330 and the driving thin film transistor 430 will be described later with reference to FIG.

The thin film transistor substrate according to the embodiment of the present invention includes a support substrate 355 and the switching thin film transistor 330 disposed on the support substrate 355, (430), and a light emitting layer (488) electrically connected to the driving thin film transistor (430).

The switching thin film transistor 330 according to the embodiment includes a first depletion forming layer 315, a first gate electrode 333, a first channel layer 360, a first source electrode 371, 1 drain electrode 372, as shown in FIG. The first source electrode 371 may be electrically connected to a first region of the first channel layer 360. The first source electrode 371 may be electrically connected to the lower surface of the first channel layer 360. The first drain electrode 372 may be electrically connected to a second region of the first channel layer 360. The first drain electrode 372 may be electrically connected to the lower surface of the first channel layer 360. The first gate electrode 333 may be disposed under the first channel layer 360. The first depletion layer 315 may be disposed between the first region and the second region of the first channel layer 360. The first depletion layer 315 may be disposed between the first channel layer 360 and the first gate electrode 333.

The driving thin film transistor 430 according to the embodiment includes a second depletion forming layer 415, a second gate electrode 433, a second channel layer 460, a second source electrode 471, 2 drain electrode 472, as shown in FIG. The second source electrode 471 may be electrically connected to the first region of the second channel layer 460. The second source electrode 471 may be electrically connected to the lower surface of the second channel layer 460. The second drain electrode 472 may be electrically connected to a second region of the second channel layer 460. The second drain electrode 472 may be electrically connected to the lower surface of the second channel layer 460. The second gate electrode 433 may be disposed under the second channel layer 460. The second depletion layer 415 may be disposed between the first and second regions of the second channel layer 460. The second depletion layer 415 may be disposed between the second channel layer 460 and the second gate electrode 433. [

The structure of the switching thin film transistor 330 and the driving thin film transistor 430 is similar to that of the driving thin film transistor 430. In the description of the driving thin film transistor 430, The description may be omitted.

The first channel layer 360 and the second channel layer 460 may be formed of a Group III-V compound semiconductor, for example. For example, the first channel layer 360 and the second channel layer 460 may be formed of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, 0? _X + Lt; RTI ID = 0.0 > of < / RTI > The first channel layer 360 and the second channel layer 460 may be a single layer or multiple layers selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, Layer. The first channel layer 360 and the second channel layer 460 may be formed of different materials.

Each of the first channel layer 360 and the second channel layer 460 may include first and second nitride semiconductor layers 361 and 461 and second nitride semiconductor layers 362 and 462. The first nitride semiconductor layer 361 461 has a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + y? 1) Semiconductor material. The second nitride semiconductor layers 362 and 462 have a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + y? 1) Semiconductor material.

According to the first channel layer 360 and the second channel layer 460 according to the embodiment, the first nitride semiconductor layers 361 and 461 include GaN semiconductor layers, and the second nitride semiconductor layers 362, and 462 may include an AlGaN semiconductor layer. The second nitride semiconductor layer 362 of the first channel layer 360 may be disposed between the first nitride semiconductor layer 361 and the first depletion-forming layer 315. The second nitride semiconductor layer 462 of the second channel layer 460 may be disposed between the first nitride semiconductor layer 461 and the second depletion-forming layer 415.

The first and second depletion-forming layers 315 and 415 may be formed of, for example, Group III-V compound semiconductors. For example, the first depletion-forming layer 315 and the second depletion-forming layer 415 is _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤ x + y < / = 1). The first depletion layer 315 and the second depletion layer 415 may be formed of a material selected from the group consisting of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, Single layer or multiple layers. The first and second depletion-forming layers 315 and 415 may include a nitride semiconductor layer doped with a p-type dopant. For example, the first and second depletion-forming layers 315 and 415 may include a GaN semiconductor layer doped with a p-type dopant or an AlGaN semiconductor layer doped with a p-type dopant. The first and second depletion-forming layers 315 and 415 may be formed of a single material, for example, a semiconductor material having a composition formula of p-Al _x Ga _1-x N (0? _X ? 0.3) Layer or multiple layers. The first and second depletion-forming layers 315 and 415 may be provided with a thickness of, for example, 2 to 300 nm. The first and second depletion-forming layers 315 and 415 may include different materials. The addition amount of the substance added to the first depletion generation layer 315 and the amount of the added substance to the second depletion formation layer 415 may be different from each other.

The first depletion layer 315 and the second depletion layer 415 are formed on the second channel layer 460 and the second channel layer 460. The first and second depletion- And can form a depletion region. The energy band gap of the portion of the second nitride semiconductor layer 362 located on the first depletion layer 315 may be increased by the first depletion layer 315, A depletion region of a two-dimensional electron gas (2DEG) may be provided in the portion of the first channel layer 360 corresponding to the second channel layer 360. [ Therefore, the region corresponding to the position where the first depletion-imparting layer 315 is disposed in the two-dimensional electron gas (2DEG) provided in the first channel layer 360 may be broken. The region where the two-dimensional electron gas (2DEG) is broken in the first channel layer 360 may be referred to as a cut-off region. For example, a cut-off region may be formed in the second nitride semiconductor layer 362. The switching thin film transistor 330 may have a normally-off characteristic by the cut-off region. When a voltage equal to or higher than a threshold voltage is applied to the first gate electrode 333, a two-dimensional electron gas (2DEG) is generated in the disconnected region, and the switching thin film transistor 330 is turned on. When the channel formed on the first gate electrode 333 is turned on, a current can flow through the two-dimensional electron gas (2DEG) formed on the first channel layer 360. Accordingly, the current flow from the first region to the second region of the first channel layer 360 can be controlled according to the voltage applied to the first gate electrode 333. The second depletion-forming layer 415 may have a role similar to that of the first depletion-forming layer 315.

The supporting substrate 355 may include a transparent substrate. The support substrate 355 may be embodied as a transparent substrate having a thickness of 0.1 mm to 3 mm, for example. The support substrate 355 may include at least one material selected from materials including silicon, glass, polyimide, and plastic. The supporting substrate 355 may include a flexible substrate.

The supporting substrate 355 is a substrate to be used in a transfer process and supports the switching thin film transistor 330 and the driving thin film transistor 430. In addition, the thin film transistor substrate according to the embodiment may include a bonding layer 350 provided between the supporting substrate 355 and the switching thin film transistor 330. The bonding layer 350 may be disposed between the supporting substrate 355 and the driving TFT 430.

The bonding layer 350 may include an organic material. The bonding layer 350 may be formed of a transparent material. The bonding layer 350 may be formed of a material having a transmittance of 70% or more. The bonding layer 350 may include an organic insulating material. The bonding layer 350 may include at least one material selected from the group consisting of acryl, benzocyclobutene (BCB), SU-8 polymer, and the like. The bonding layer 350 may be provided in a thickness of 0.5 to 6 mu m, for example.

The switching thin film transistor 330 according to the embodiment includes a first source contact portion 331 disposed under the first region of the first channel layer 360 and a second source contact portion 332 disposed under the second region of the first channel layer 360. [ And may include a first drain contact portion 332 disposed therein. The first source contact portion 331 may be disposed in contact with the first region of the first channel layer 360. The first drain contact portion 332 may be disposed in contact with a second region of the first channel layer 360.

The switching thin film transistor 330 according to the embodiment includes a first source connection wiring 342 disposed under the first source contact portion 331 and a first drain connection 332 disposed below the first drain contact portion 332. [ And a wiring 343. In addition, the switching thin film transistor 330 may include a first gate wiring 341 disposed under the first gate electrode 333. The first source connection wiring 342 may be electrically connected to the first source contact portion 331. For example, the upper surface of the first source connection wiring 342 may be disposed in contact with the lower surface of the first source contact portion 331. The first drain connection wiring 343 may be electrically connected to the first drain contact portion 332. For example, the upper surface of the first drain connection wiring 343 may be disposed in contact with the lower surface of the first drain contact portion 332. The first gate wiring 341 may be electrically connected to the first gate electrode 333. The upper surface of the first gate wiring 341 may be disposed in contact with the lower surface of the first gate electrode 333.

The first source electrode 371 may be electrically connected to the first source connection wiring 342. The first source electrode 371 may be disposed in contact with the upper surface of the first source connection wiring 342. For example, the first source electrode 371 may be electrically connected to the first region of the first channel layer 360 through the first source connection line 342 and the first source contact portion 331 have. The first drain electrode 372 may be electrically connected to the first drain connection wiring 343. The first drain electrode 372 may be disposed in contact with the upper surface of the first drain connection wiring 343. The first drain electrode 372 may be electrically connected to the second region of the first channel layer 360 through the first drain connection line 343 and the first drain contact 332 have.

The driving thin film transistor 430 according to the embodiment includes a second source contact portion 431 disposed under the first region of the second channel layer 460 and a second source contact portion 431 disposed under the second region of the second channel layer 460 And a second drain contact portion 432 disposed therein. The second source contact portion 431 may be disposed in contact with the first region of the second channel layer 460. The second drain contact portion 432 may be disposed in contact with a second region of the second channel layer 460.

The driving thin film transistor 430 according to the embodiment includes a second source connection wiring 442 disposed below the second source contact portion 431 and a second drain connection 432 disposed below the second drain contact portion 432. [ And may include wiring 443. In addition, the driving thin film transistor 430 may include a second gate line 441 disposed under the second gate electrode 433. The second source connection wiring 442 may be electrically connected to the second source contact portion 431. For example, the upper surface of the second source connection wiring 442 may be disposed in contact with the lower surface of the second source contact portion 431. The second drain connection line 443 may be electrically connected to the second drain contact 432. For example, the upper surface of the second drain connection wiring 443 may be disposed in contact with the lower surface of the second drain contact portion 432. The second gate line 441 may be electrically connected to the second gate electrode 433. The upper surface of the second gate wiring 441 may be disposed in contact with the lower surface of the second gate electrode 433.

The second source electrode 471 may be electrically connected to the second source connection wiring 442. The second source electrode 471 may be disposed in contact with the upper surface of the second source connection wiring 442. For example, the second source electrode 471 may be electrically connected to the first region of the second channel layer 460 through the second source connection line 442 and the second source contact portion 431 have. The second drain electrode 472 may be electrically connected to the second drain connection line 443. The second drain electrode 472 may be disposed in contact with the upper surface of the second drain connection wiring 443. For example, the second drain electrode 472 may be electrically connected to the second region of the second channel layer 460 through the second drain connection line 443 and the second drain contact 432 have.

The first source contact portion 331 and the first drain contact portion 332 may be formed of a material that makes an ohmic contact with the first channel layer 360. The first source contact portion 331 and the first drain contact portion 332 may include a material that makes an ohmic contact with the second nitride semiconductor layer 362. The second source contact portion 431 and the second drain contact portion 432 may be formed of a material that makes an ohmic contact with the second channel layer 460. [ The second source contact portion 431 and the second drain contact portion 432 may include a material that makes an ohmic contact with the second nitride semiconductor layer 462. For example, the first source contact portion 331, the first drain contact portion 332, the second source contact portion 431, and the second drain contact portion 432 may be formed of aluminum (Al), aluminum alloy The present invention relates to a method for manufacturing a semiconductor device comprising the steps of forming an Al alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy, At least any one material selected from the group consisting of chromium (Cr), titanium (Ti), titanium alloy, molybdenum tungsten (MoW), moly titanium (MoTi), copper / moly titanium (Cu / MoTi) ≪ RTI ID = 0.0 > and / or < / RTI > The first source contact portion 331, the first drain contact portion 332, the second source contact portion 431 and the second drain contact portion 432 are provided with a thickness of, for example, .

The first gate electrode 333 may be formed of a material that makes an ohmic contact with the first depletion layer 315. The second gate electrode 433 may be formed of a material that makes an ohmic contact with the second depletion layer 415. For example, the first gate electrode 333 and the second gate electrode 433 may be formed of a material in ohmic contact with the p-type nitride layer. The first gate electrode 333 and the second gate electrode 433 may be formed of tungsten (W), tungsten silicon (WSi ₂ ), titanium nitride (TiN), tantalum (Ta), tantalum nitrogen (TaN), palladium ), Nickel (Ni), platinum (Pt), or the like. The first gate electrode 333 and the second gate electrode 433 may be provided with a thickness of, for example, 0.1-1 탆.

The first gate wiring 341 and the second gate wiring 441 may be formed of a metal such as aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum ), Silver (Ag), silver alloy, gold (Au), gold alloy, chromium (Cr), titanium (Ti), titanium alloy, molybdenum tungsten And may include a single layer or multiple layers comprising at least one material selected from the group consisting of titanium (MoTi), copper / moly titanium (Cu / MoTi). The first gate wiring 341 and the second gate wiring 441 may be provided in a thickness of 0.1 to 3 占 퐉, for example.

The first source connection wiring 342, the first drain connection wiring 343, the second source connection wiring 442 and the second drain connection wiring 443 are made of aluminum (Al), an aluminum alloy ), Tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy, gold (Au) (Ti), Ti alloy, molybdenum tungsten (MoW), moly titanium (MoTi), copper / moly titanium (Cu / MoTi) Single layer or multiple layers. The first source connection wiring 342, the first drain connection wiring 343, the second source connection wiring 442 and the second drain connection wiring 443 are provided with a thickness of, for example, 0.1 to 3 μm .

The first source electrode 371, the first drain electrode 372, the second source electrode 471 and the second drain electrode 472 may be formed of aluminum (Al), aluminum alloy (Al alloy), tungsten (W ), Copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy, gold (Au), gold alloy, chromium (Cr) A single layer or multiple layers comprising at least one material selected from the group consisting of Ti, Ti alloy, molybdenum (MoW), moly titanium (MoTi), copper / moly titanium (Cu / MoTi) . ≪ / RTI > The first source electrode 371, the first drain electrode 372, the second source electrode 471 and the second drain electrode 472 may be provided with a thickness of 0.1 to 3 μm, for example.

The thin film transistor substrate according to the embodiment may include the first channel layer 360 and the first passivation layer 321 disposed under the second channel layer 460. The first passivation layer 321 may be disposed below the second nitride semiconductor layer 362 of the first channel layer 360 and the second nitride semiconductor layer 462 of the second channel layer 460 . The upper surface of the first protective layer 321 is formed on the lower surface of the second nitride semiconductor layer 362 of the first channel layer 360 and the second nitride semiconductor layer 462 of the second channel layer 460 Can be disposed in contact with each other.

According to the embodiment, the first source contact portion 331 may be disposed through the first protective film 321. The first source contact portion 331 may be surrounded by the first protective layer 321. The first source contact portion 331 may be disposed through the first protective layer 321 and may be provided in contact with the first region of the first channel layer 360. The first drain contact part 332 may be disposed through the first protective film 321. The first drain contact portion 332 may be surrounded by the first protective layer 321. The first drain contact portion 332 may be disposed through the first passivation layer 321 and may be provided in contact with the second region of the first channel layer 360.

According to the embodiment, the second source contact part 431 may be arranged to penetrate the first protective film 321. The second source contact portion 431 may be surrounded by the first protective layer 321. The second source contact portion 431 may be disposed through the first protective layer 321 and may be provided in contact with the first region of the second channel layer 460. The second drain contact portion 432 may be disposed through the first passivation layer 321. The second drain contact part 432 may be surrounded by the first protective film 321. The second drain contact portion 432 may be disposed through the first passivation layer 321 and may be provided in contact with the second region of the second channel layer 460.

The first passivation layer 321 may be formed of an insulating material. The first passivation layer 321 may include a single layer or multiple layers including at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide including Al ₂ O ₃ , and an organic insulating material .

The first source connection wiring 342 may be disposed in contact with the first source contact portion 331 and surrounded by the bonding layer 350. The first drain connection line 343 may be disposed in contact with the first drain contact portion 332 and surrounded by the bonding layer 350. The first gate line 341 may be disposed in contact with the first gate electrode 333 and surrounded by the bonding layer 350.

The upper surface of the first source connection wiring 342 may be disposed higher than the upper surface of the first gate wiring 341. The upper surface of the first source connection wiring 342 may be disposed higher than the lower surface of the first gate electrode 333. The upper surface of the first drain connection wiring 343 may be disposed higher than the upper surface of the first gate wiring 341. The upper surface of the first drain connection wiring 343 may be disposed higher than the lower surface of the first gate electrode 333.

The second source connection wiring 442 may be disposed in contact with the second source contact portion 431 and surrounded by the bonding layer 350. The second drain connection line 443 may be disposed in contact with the second drain contact portion 432 and surrounded by the bonding layer 350. The second gate line 441 may be disposed in contact with the second gate electrode 433 and surrounded by the bonding layer 350.

The upper surface of the second source connection wiring 442 may be disposed higher than the upper surface of the second gate wiring 441. The upper surface of the second source connection wiring 442 may be disposed higher than the lower surface of the second gate electrode 433. The upper surface of the second drain connection wiring 443 may be disposed higher than the upper surface of the second gate wiring 441. The upper surface of the second drain connection wiring 443 may be disposed higher than the lower surface of the second gate electrode 433.

The thin film transistor substrate according to the embodiment may include the first protective layer 321, the first channel layer 360, and the second protective layer 322 disposed on the second channel layer 460. The first source electrode 371 may be electrically connected to the first source connection wiring 342 through the first passivation layer 321 and the second passivation layer 322. The first source electrode 371 may include a first region disposed on the second passivation layer 322. The first source electrode 371 may include a second region penetrating the second protective film 322 and the first protective film 321. The first drain electrode 372 may be electrically connected to the first drain connection wiring 343 through the first passivation layer 321 and the second passivation layer 322. The first drain electrode 372 may include a first region disposed on the second passivation layer 322. The first drain electrode 372 may include a second region passing through the second passivation layer 322 and the first passivation layer 321.

The second source electrode 471 may be electrically connected to the second source connection wiring 442 through the first passivation layer 321 and the second passivation layer 322. The second source electrode 471 may include a first region disposed on the second passivation layer 322. The second source electrode 471 may include a second region penetrating the second protective layer 322 and the first protective layer 321. The second drain electrode 472 may be electrically connected to the second drain connection wiring 443 through the first passivation layer 321 and the second passivation layer 322. The second drain electrode 472 may include a first region disposed on the second passivation layer 322. The second drain electrode 472 may include a second region penetrating the second passivation layer 322 and the first passivation layer 321.

According to the embodiment, the first drain-gate connection line 375 may be disposed on the second passivation layer 322. The first drain-gate connection line 375 may include a first region disposed over the second passivation layer 322. The first drain-gate connection line 375 may include a second region penetrating the second passivation layer 322 and the first passivation layer 321. A first region of the first drain-gate connection wiring 375 may be electrically connected to the first drain electrode 372. A first region of the first drain-gate connection line 375 may extend from the first drain electrode 372. For example, the first drain-gate connection line 375 may be formed integrally with the first drain electrode 372 in the same process. Also, the first drain-gate connection line 375 and the first drain electrode 372 may be separately formed and electrically connected to each other.

According to the embodiment, a second drain-gate connection line 475 may be disposed under the first passivation layer 321. The second drain-gate connection line 475 may be electrically connected to the first drain-gate connection line 375. The second region of the first drain-gate connection line 375 may be disposed in contact with the second drain-gate connection line 475. The second drain-gate connection line 475 may be electrically connected to the second gate line 441. The second drain-gate connection line 475 may extend from the second gate line 441. For example, the second drain-gate connection line 475 may be formed integrally with the second gate line 441 in the same process. In addition, the second drain-gate connection line 475 may be formed and electrically connected to the second gate line 441 in a separate process. A part of the second gate connection wiring 475 may be disposed in contact with the upper surface of the second gate wiring 441. The first drain electrode 372 is electrically connected to the second gate electrode 433 through the first drain-gate connection line 375, the second drain-gate connection line 475, As shown in FIG.

As shown in FIG. 30, the second channel layer 460 and the second depletion-imparting layer 415 may have the same width. If the width of the second depletion-forming layer 415 is smaller than the width of the second channel layer 460, a leakage current may be generated. In other words, the length of the second channel layer 460 provided along the direction in which the second gate electrode 433 is extended and arranged and the length of the second depletion-imparting layer 415 may be provided equally have.

The first protective layer 321 is disposed in contact with a lower surface of the first channel layer 360 and is disposed in contact with a lower surface of the second protective layer 322 and has a first thickness, Lt; / RTI > A region of the first protective layer 321 having a first thickness may be disposed between the lower surface of the first channel layer 360 and the upper surface of the first gate wiring 341. A region of the first protective layer 321 having a second thickness is formed on the lower surface of the second protective layer 322 and the upper surface of the first source connection wiring 342 or the upper surface of the first drain connection wiring 343 Plane. ≪ / RTI > A region of the first protective layer 321 having a second thickness may be disposed between the lower surface of the second protective layer 322 and the upper surface of the bonding layer 350. The first thickness of the first protective layer 321 may be greater than the second thickness.

The second passivation layer 322 may include an insulating material. The second passivation layer 322 may comprise a single layer or multiple layers including, for example, at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide containing Al ₂ O ₃ , .

The thin film transistor substrate according to the embodiment may include a third protective film 323 disposed on the second protective film 322. The third passivation layer 323 may be disposed on the first source electrode 371, the first drain electrode 372, the second source electrode 471, and the second drain electrode 472.

The third passivation layer 323 may include a single layer or multiple layers including at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide containing Al ₂ O ₃ , and an organic insulating material .

The thin film transistor substrate according to the embodiment may include a lower electrode 486 disposed on the driving thin film transistor 430. The lower electrode 486 may be electrically connected to the driving thin film transistor 430. The lower electrode 486 may be electrically connected to the second drain electrode 472 of the driving thin film transistor 430. The lower electrode 486 may be disposed on the third protective layer 423. The lower electrode 486 may be electrically connected to the second drain electrode 472 through a contact hole provided in the third passivation layer 323. The lower surface of the lower electrode 486 may be disposed in contact with the upper surface of the second drain electrode 472.

In addition, the thin film transistor substrate according to the embodiment may include a fourth protective film 324 disposed on the third protective film 323. The light emitting layer 488 may be disposed on the lower electrode 486 and the upper electrode 487 may be disposed on the light emitting layer 488. The light emitting layer 488 and the upper electrode 487 may be disposed on the fourth protective layer 324. The first region of the light emitting layer 488 is disposed on the fourth protective film 324 and the second region of the light emitting layer 488 is electrically connected to the lower electrode 486 through a contact hole provided in the fourth protective film 324. [ And can be disposed in contact with the upper surface. The light emitting layer 488 may emit any one of red, green, blue, and white light. The light emitting layer 488 may be formed of an organic material, for example.

The lower electrode 486 and the upper electrode 487 may comprise one material selected from, for example, ITO, ITO / Ag, ITO / Ag / ITO, ITO / Ag / IZO, have. The lower electrode 486 and the upper electrode 487 may include different materials. One of the upper electrode 486 and the lower electrode 487 may be formed as a transparent electrode so that the light emitted from the light emitting layer 488 may be emitted to the outside in the direction of the transparent electrode.

Similarly, as described with reference to FIG. 16, a portion of the first drain connection wiring 343 according to the embodiment is disposed between the first drain contact portion 332 and the first protective film 321 . May be provided in a space between a side surface of the first drain contact part 332 and the first protective film 321 in the process of forming the first drain contact part 332, A part of the connection wiring 343 may be formed. In the process of forming the through hole in the first protective film 321 to form the first drain contact 332, the side surface of the first protective film 321 surrounding the first drain contact 332 Can be formed to be inclined. The angle a2 formed by the side surface of the first protective film 321 and the top surface of the first protective film 321 may be provided at an acute angle. For example, the angle a2 formed between the side surface of the first protective film 321 and the top surface of the first protective film 321 may be 10 degrees to 90 degrees. More preferably, the angle a2 formed by the side surface of the first protective film 321 and the top surface of the first protective film 321 may be 30 degrees to 90 degrees. A predetermined gap t2 may be provided between the side surface of the first protective layer 321 and the first drain contact portion 332. For example, an interval of 0 to 3 mu m may be provided. Although not shown in the drawings, a portion of the first source connection wiring 342 according to the embodiment may be disposed between the first source contact portion 331 and the first protective film 321. May be provided in a space between a side surface of the first source contact portion 331 and the first protective film 321 in the process of forming the first source contact portion 331, A part of the connection wiring 343 may be formed. Since the first channel layer 360 is formed through the etching process, the angle a1 between the side surface of the first channel layer 360 and the lower surface of the first channel layer 360 is May be provided at an acute angle. For example, the angle a1 formed between the side surface of the first channel layer 360 and the lower surface of the first channel layer 360 may be 30 degrees to 90 degrees.

For example, when the first passivation layer 321 is formed of a silicon oxide such as SiO ₂ , the first passivation layer 321 may be etched by wet etching or dry etching. When the etching is performed by wet etching, the angle of a2 may be about 10 degrees to about 60 degrees, and a wider shape may be provided within a few micrometers than the pattern to be etched. When wet etching is performed, the angle of a2 may be formed at an angle of about 35 to 45 degrees. When the etching is performed by dry etching, the angle of a2 may be about 60 to 90 degrees, and a shape having a width similar to the pattern to be etched may be provided. When dry etching is performed, the angle of a2 may be formed at an angle of about 65 to 75 degrees.

The upper surface of the first nitride semiconductor layer 361 may be provided shorter than the lower surface. The upper surface of the second nitride semiconductor layer 362 may be provided shorter than the lower surface. The lower surface of the first nitride semiconductor layer 361 and the upper surface of the second nitride semiconductor layer 362 may have the same length. In the step of forming the first channel layer 360 by etching, a partial overgrowth may be generated in the end region of the first channel layer 360. Accordingly, a step may be provided on the upper surface of the first protective film 321. That is, the first protective layer 321 may have a thickness different from that of the first channel layer 360 and the region of the first channel layer 360 where the first channel layer 360 is not disposed. As an example, the thickness t1 of the step may be provided on the order of 0 to 1 mu m. Accordingly, the lower surface of the second protective layer 322 disposed on the first protective layer 321 may extend below the lower surface of the first channel layer 360.

31 is a circuit diagram equivalent to one pixel in the thin film transistor substrate described with reference to FIGS. 28 to 30. FIG.

31, the pixel of the thin film transistor substrate according to the embodiment of the present invention includes an organic light emitting diode (OLED), data lines D and gate lines G intersecting with each other, A switching thin film transistor 330 for sequentially transmitting data to the pixels in the scan pulse SP, a driving thin film transistor 430 for generating a current by a voltage between the gate and the source terminals, And a storage capacitor (Cst) for storing data. The structure consisting of the two transistors 330 and 430 and one capacitor Cst can be simply referred to as a 2T-1C structure.

The switching thin film transistor 330 turns on in response to the scan pulse SP from the gate line G, thereby conducting a current path between the source electrode and the drain electrode. The data voltage from the data line D during the gate on time of the switching TFT 330 is applied to the gate electrode of the driving TFT 430 through the source and drain electrodes of the switching TFT 330 And is applied to the storage capacitor Cst. The driving thin film transistor 430 controls the current flowing in the organic light emitting diode OLED according to the difference voltage between its gate electrode and the source electrode. The storage capacitor Cst maintains the voltage supplied to the gate electrode of the driving thin film transistor 430 constant for one frame period by storing the data voltage applied to one electrode of the storage capacitor Cst. A driving power supply line VDD may be connected to a source electrode of the driving TFT 430. 31 may be connected between the drain electrode of the driving thin film transistor 430 and the low potential driving voltage source VSS. The organic light emitting diode OLED may be connected between the source electrode of the driving thin film transistor 430 and the driving power supply line VDD.

According to the thin film transistor substrate according to the embodiment, a high carrier mobility can be realized by providing the thin film transistor including the nitride based semiconductor layer. For example, the electron mobility (cm 2 / Vs) varies depending on the material used as the channel layer in the thin film transistor. In the amorphous silicon semiconductor, the electron mobility is 1, and in the case of the oxide semiconductor, And in the case of a polysilicon semiconductor, it is reported to be 100 or less. However, the thin film transistor including the nitride based semiconductor layer according to the embodiment has been measured to have an electron mobility of 1500. Accordingly, the thin film transistor including the nitride based semiconductor layer according to the embodiment can realize a 15 times higher electron mobility than the thin film transistor to which the polysilicon semiconductor is applied.

According to the embodiments, a semiconductor layer with good quality can be formed using a growth substrate, and a thin film transistor substrate having excellent electron mobility can be provided by applying a transfer process using a supporting substrate.

Therefore, according to the thin film transistor substrate, the display panel and the display device including the thin film transistor substrate according to the embodiment, it is possible to provide a high carrier mobility, thereby realizing a high resolution and reproducing a smooth moving image.

32 to 34 are views showing still another example of the thin film transistor substrate according to the embodiment of the present invention. FIG. 32 is a cross-sectional view along the DD line of the thin film transistor substrate shown in FIG. 28, FIG. 33 is a cross-sectional view along the EE line of the thin film transistor substrate shown in FIG. 28, FF of Fig.

The thin film transistor substrate shown in FIGS. 32 to 34 is an embodiment in which a switching thin film transistor having a double gate structure is applied, and the description overlapping with those described with reference to FIGS. 1 to 31 may be omitted.

The thin film transistor substrate according to an embodiment may include a switching thin film transistor 530 and a driving thin film transistor 430. The switching thin film transistor 530 can receive a signal from the gate line 341 and the data line 373 and can provide a gate signal and a data signal to the pixel. The gate electrode 433 of the driving thin film transistor 430 may be electrically connected to the drain electrode 372 of the switching thin film transistor 530.

32 to 34, the thin film transistor substrate according to the exemplary embodiment of the present invention includes a support substrate 355 and the switching thin film transistor 530, the driving thin film transistor (430), and a light emitting layer (488) electrically connected to the driving thin film transistor (430).

The switching thin film transistor 530 according to the embodiment includes a first depletion forming layer 315, a first gate electrode 535, a double gate electrode 536, a first channel layer 360, A source electrode 371, and a first drain electrode 372. The first source electrode 371 may be electrically connected to a first region of the first channel layer 360. The first source electrode 371 may be electrically connected to the lower surface of the first channel layer 360. The first drain electrode 372 may be electrically connected to a second region of the first channel layer 360. The first drain electrode 372 may be electrically connected to the lower surface of the first channel layer 360. The first gate electrode 535 may be disposed under the first channel layer 360. The double gate electrode 536 may be disposed on the first channel layer 360. The first depletion layer 315 may be disposed between the first region and the second region of the first channel layer 360. The first depletion layer 315 may be disposed between the first channel layer 360 and the first gate electrode 535.

The driving thin film transistor 430 according to the embodiment includes a second depletion forming layer 415, a second gate electrode 433, a second channel layer 460, a second source electrode 471, 2 drain electrode 472, as shown in FIG. The second source electrode 471 may be electrically connected to the first region of the second channel layer 460. The second source electrode 471 may be electrically connected to the lower surface of the second channel layer 460. The second drain electrode 472 may be electrically connected to a second region of the second channel layer 460. The second drain electrode 472 may be electrically connected to the lower surface of the second channel layer 460. The second gate electrode 433 may be disposed under the second channel layer 460. The second depletion layer 415 may be disposed between the first and second regions of the second channel layer 460. The second depletion layer 415 may be disposed between the second channel layer 460 and the second gate electrode 433. [

The first channel layer 360 and the second channel layer 460 may be formed of a Group III-V compound semiconductor, for example. For example, the first channel layer 360 and the second channel layer 460 may be formed of In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, 0? _X + Lt; RTI ID = 0.0 > of < / RTI > The first channel layer 360 and the second channel layer 460 may be a single layer or multiple layers selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, Layer. The first channel layer 360 and the second channel layer 460 may be formed of different materials.

Each of the first channel layer 360 and the second channel layer 460 may include first and second nitride semiconductor layers 361 and 461 and second nitride semiconductor layers 362 and 462. The first nitride semiconductor layer 361 461 has a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + y? 1) Semiconductor material. The second nitride semiconductor layers 362 and 462 have a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + y? 1) Semiconductor material.

According to the first channel layer 360 and the second channel layer 460 according to the embodiment, the first nitride semiconductor layers 361 and 461 include GaN semiconductor layers, and the second nitride semiconductor layers 362, and 462 may include an AlGaN semiconductor layer. The second nitride semiconductor layer 362 of the first channel layer 360 may be disposed between the first nitride semiconductor layer 361 and the first depletion-forming layer 315. The second nitride semiconductor layer 462 of the second channel layer 460 may be disposed between the first nitride semiconductor layer 461 and the second depletion-forming layer 415.

The first and second depletion-forming layers 315 and 415 may be formed of, for example, Group III-V compound semiconductors. For example, the first depletion-forming layer 315 and the second depletion-forming layer 415 is _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤ x + y < / = 1). The first depletion layer 315 and the second depletion layer 415 may be formed of a material selected from the group consisting of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, AlGaInP, Single layer or multiple layers. The first and second depletion-forming layers 315 and 415 may include a nitride semiconductor layer doped with a p-type dopant. For example, the first and second depletion-forming layers 315 and 415 may include a GaN semiconductor layer doped with a p-type dopant or an AlGaN semiconductor layer doped with a p-type dopant. The first and second depletion-forming layers 315 and 415 may be formed of a single material, for example, a semiconductor material having a composition formula of p-Al _x Ga _1-x N (0? _X ? 0.3) Layer or multiple layers. The first and second depletion-forming layers 315 and 415 may be provided with a thickness of, for example, 2 to 300 nm. The first and second depletion-forming layers 315 and 415 may include different materials. The addition amount of the substance added to the first depletion generation layer 315 and the amount of the added substance to the second depletion formation layer 415 may be different from each other.

The first depletion layer 315 and the second depletion layer 415 are formed on the second channel layer 460 and the second channel layer 460. The first and second depletion- And can form a depletion region. The energy band gap of the portion of the second nitride semiconductor layer 362 located on the first depletion layer 315 may be increased by the first depletion layer 315, A depletion region of a two-dimensional electron gas (2DEG) may be provided in the portion of the first channel layer 360 corresponding to the second channel layer 360. [ Therefore, the region corresponding to the position where the first depletion-imparting layer 315 is disposed in the two-dimensional electron gas (2DEG) provided in the first channel layer 360 may be broken. The region where the two-dimensional electron gas (2DEG) is broken in the first channel layer 360 may be referred to as a cut-off region. For example, a cut-off region may be formed in the second nitride semiconductor layer 362. The switching thin film transistor 530 may have a normally-off characteristic by the cut-off region. When a voltage equal to or higher than a threshold voltage is applied to the first gate electrode 535, a two-dimensional electron gas (2DEG) is generated in the cut-off region, and the switching thin film transistor 530 is turned on. When a channel formed on the first gate electrode 535 is turned on, a current can flow through the two-dimensional electron gas (2DEG) formed on the first channel layer 360. Accordingly, current flow from the first region to the second region of the first channel layer 360 can be controlled according to the voltage applied to the first gate electrode 535 and the double gate electrode 536 do. The second depletion-forming layer 415 may have a role similar to that of the first depletion-forming layer 315.

According to the present embodiment, the double gate electrode 536 may be disposed on the first channel layer 360. The first gate electrode 535 and the double gate electrode 536 may be overlapped with each other in the vertical direction. The first gate electrode 535 and the double gate electrode 536 are disposed on the lower portion and the upper portion of the first channel layer 360 and the second gate layer 536 is disposed on the first channel layer 360. Accordingly, 32 to FIG. 34, only the switching thin film transistor is provided in a double gate structure. However, the switching thin film transistor And the driving thin film transistor may be provided in a double gate structure, or only the driving thin film transistor may be provided in a double gate structure.

The supporting substrate 355 may include a transparent substrate. The support substrate 355 may be embodied as a transparent substrate having a thickness of 0.1 mm to 3 mm, for example. The support substrate 355 may include at least one material selected from materials including silicon, glass, polyimide, and plastic. The supporting substrate 355 may include a flexible substrate. The supporting substrate 355 is a substrate to be used in a transfer process and supports the switching thin film transistor 530 and the driving thin film transistor 430. In addition, the thin film transistor substrate according to the embodiment may include a bonding layer 350 provided between the supporting substrate 355 and the switching thin film transistor 530. The bonding layer 350 may be disposed between the supporting substrate 355 and the driving TFT 430.

The bonding layer 350 may include an organic material. The bonding layer 350 may be formed of a transparent material. The bonding layer 350 may be formed of a material having a transmittance of 70% or more. The bonding layer 350 may include an organic insulating material. The bonding layer 350 may include at least one material selected from the group consisting of acryl, benzocyclobutene (BCB), SU-8 polymer, and the like. The bonding layer 350 may be provided in a thickness of 0.5 to 6 mu m, for example.

The switching thin film transistor 530 according to the embodiment includes a first source contact portion 331 disposed under the first region of the first channel layer 360 and a second source contact portion 331 disposed under the second region of the first channel layer 360. [ And may include a first drain contact portion 332 disposed therein. The first source contact portion 331 may be disposed in contact with the first region of the first channel layer 360. The first drain contact portion 332 may be disposed in contact with a second region of the first channel layer 360.

The switching thin film transistor 530 according to the embodiment includes a first source connection wiring 342 disposed under the first source contact portion 331 and a first drain connection portion 332 disposed under the first drain contact portion 332. [ And a wiring 343. In addition, the switching thin film transistor 530 may include a first gate wiring 341 disposed under the first gate electrode 535. The first source connection wiring 342 may be electrically connected to the first source contact portion 331. For example, the upper surface of the first source connection wiring 342 may be disposed in contact with the lower surface of the first source contact portion 331. The first drain connection wiring 343 may be electrically connected to the first drain contact portion 332. For example, the upper surface of the first drain connection wiring 343 may be disposed in contact with the lower surface of the first drain contact portion 332. The first gate wiring 341 may be electrically connected to the first gate electrode 535. The upper surface of the first gate wiring 341 may be disposed in contact with the lower surface of the first gate electrode 535.

The first source electrode 371 may be electrically connected to the first source connection wiring 342. The first source electrode 371 may be disposed in contact with the upper surface of the first source connection wiring 342. For example, the first source electrode 371 may be electrically connected to the first region of the first channel layer 360 through the first source connection line 342 and the first source contact portion 331 have. The first drain electrode 372 may be electrically connected to the first drain connection wiring 343. The first drain electrode 372 may be disposed in contact with the upper surface of the first drain connection wiring 343. The first drain electrode 372 may be electrically connected to the second region of the first channel layer 360 through the first drain connection line 343 and the first drain contact 332 have.

The driving thin film transistor 430 according to the embodiment includes a second source contact portion 431 disposed under the first region of the second channel layer 460 and a second source contact portion 431 disposed under the second region of the second channel layer 460 And a second drain contact portion 432 disposed therein. The second source contact portion 431 may be disposed in contact with the first region of the second channel layer 460. The second drain contact portion 432 may be disposed in contact with a second region of the second channel layer 460.

The driving thin film transistor 430 according to the embodiment includes a second source connection wiring 442 disposed below the second source contact portion 431 and a second drain connection 432 disposed below the second drain contact portion 432. [ And may include wiring 443. In addition, the driving thin film transistor 430 may include a second gate line 441 disposed under the second gate electrode 433. The second source connection wiring 442 may be electrically connected to the second source contact portion 431. For example, the upper surface of the second source connection wiring 442 may be disposed in contact with the lower surface of the second source contact portion 431. The second drain connection line 443 may be electrically connected to the second drain contact 432. For example, the upper surface of the second drain connection wiring 443 may be disposed in contact with the lower surface of the second drain contact portion 432. The second gate line 441 may be electrically connected to the second gate electrode 433. The upper surface of the second gate wiring 441 may be disposed in contact with the lower surface of the second gate electrode 433.

The second source electrode 471 may be electrically connected to the second source connection wiring 442. The second source electrode 471 may be disposed in contact with the upper surface of the second source connection wiring 442. For example, the second source electrode 471 may be electrically connected to the first region of the second channel layer 460 through the second source connection line 442 and the second source contact portion 431 have. The second drain electrode 472 may be electrically connected to the second drain connection line 443. The second drain electrode 472 may be disposed in contact with the upper surface of the second drain connection wiring 443. For example, the second drain electrode 472 may be electrically connected to the second region of the second channel layer 460 through the second drain connection line 443 and the second drain contact 432 have.

The first source contact portion 331 and the first drain contact portion 332 may be formed of a material that makes an ohmic contact with the first channel layer 360. The first source contact portion 331 and the first drain contact portion 332 may include a material that makes an ohmic contact with the second nitride semiconductor layer 362. The second source contact portion 431 and the second drain contact portion 432 may be formed of a material that makes an ohmic contact with the second channel layer 460. [ The second source contact portion 431 and the second drain contact portion 432 may include a material that makes an ohmic contact with the second nitride semiconductor layer 462. For example, the first source contact portion 331, the first drain contact portion 332, the second source contact portion 431, and the second drain contact portion 432 may be formed of aluminum (Al), aluminum alloy The present invention relates to a method for manufacturing a semiconductor device comprising the steps of forming an Al alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy, At least any one material selected from the group consisting of chromium (Cr), titanium (Ti), titanium alloy, molybdenum tungsten (MoW), moly titanium (MoTi), copper / moly titanium (Cu / MoTi) ≪ RTI ID = 0.0 > and / or < / RTI > The first source contact portion 331, the first drain contact portion 332, the second source contact portion 431 and the second drain contact portion 432 are provided with a thickness of, for example, .

The first gate electrode 535 may be formed of a material that makes an ohmic contact with the first depletion-forming layer 315. The second gate electrode 433 may be formed of a material that makes an ohmic contact with the second depletion layer 415. For example, the first gate electrode 535 and the second gate electrode 433 may be formed of a material in ohmic contact with the p-type nitride layer. The first gate electrode 535 and the second gate electrode 433 may be formed of tungsten (W), tungsten silicon (WSi ₂ ), titanium nitride (TiN), tantalum (Ta), tantalum nitrogen (TaN), palladium ), Nickel (Ni), platinum (Pt), or the like. The first gate electrode 535 and the second gate electrode 433 may be provided with a thickness of 0.1 to 1 m, for example.

The first gate wiring 341 and the second gate wiring 441 may be formed of a metal such as aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum ), Silver (Ag), silver alloy, gold (Au), gold alloy, chromium (Cr), titanium (Ti), titanium alloy, molybdenum tungsten And may include a single layer or multiple layers comprising at least one material selected from the group consisting of titanium (MoTi), copper / moly titanium (Cu / MoTi). The first gate wiring 341 and the second gate wiring 441 may be provided in a thickness of 0.1 to 3 占 퐉, for example.

The first source connection wiring 342, the first drain connection wiring 343, the second source connection wiring 442 and the second drain connection wiring 443 are made of aluminum (Al), an aluminum alloy ), Tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy, gold (Au) (Ti), Ti alloy, molybdenum tungsten (MoW), moly titanium (MoTi), copper / moly titanium (Cu / MoTi) Single layer or multiple layers. The first source connection wiring 342, the first drain connection wiring 343, the second source connection wiring 442 and the second drain connection wiring 443 are provided with a thickness of, for example, 0.1 to 3 μm .

The first source electrode 371, the first drain electrode 372, the second source electrode 471 and the second drain electrode 472 may be formed of aluminum (Al), aluminum alloy (Al alloy), tungsten (W ), Copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy, gold (Au), gold alloy, chromium (Cr) A single layer or multiple layers comprising at least one material selected from the group consisting of Ti, Ti alloy, molybdenum (MoW), moly titanium (MoTi), copper / moly titanium (Cu / MoTi) . ≪ / RTI > The first source electrode 371, the first drain electrode 372, the second source electrode 471 and the second drain electrode 472 may be provided with a thickness of 0.1 to 3 μm, for example.

The thin film transistor substrate according to the embodiment may include the first channel layer 360 and the first passivation layer 321 disposed under the second channel layer 460. The first passivation layer 321 may be disposed below the second nitride semiconductor layer 362 of the first channel layer 360 and the second nitride semiconductor layer 462 of the second channel layer 460 . The upper surface of the first protective layer 321 is formed on the lower surface of the second nitride semiconductor layer 362 of the first channel layer 360 and the second nitride semiconductor layer 462 of the second channel layer 460 Can be disposed in contact with each other.

According to the embodiment, the first source contact portion 331 may be disposed through the first protective film 321. The first source contact portion 331 may be surrounded by the first protective layer 321. The first source contact portion 331 may be disposed through the first protective layer 321 and may be provided in contact with the first region of the first channel layer 360. The first drain contact part 332 may be disposed through the first protective film 321. The first drain contact portion 332 may be surrounded by the first protective layer 321. The first drain contact portion 332 may be disposed through the first passivation layer 321 and may be provided in contact with the second region of the first channel layer 360.

According to the embodiment, the second source contact part 431 may be arranged to penetrate the first protective film 321. The second source contact portion 431 may be surrounded by the first protective layer 321. The second source contact portion 431 may be disposed through the first protective layer 321 and may be provided in contact with the first region of the second channel layer 460. The second drain contact portion 432 may be disposed through the first passivation layer 321. The second drain contact part 432 may be surrounded by the first protective film 321. The second drain contact portion 432 may be disposed through the first passivation layer 321 and may be provided in contact with the second region of the second channel layer 460.

The first passivation layer 321 may be formed of an insulating material. The first passivation layer 321 may include a single layer or multiple layers including at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide including Al ₂ O ₃ , and an organic insulating material .

The first source connection wiring 342 may be disposed in contact with the first source contact portion 331 and surrounded by the bonding layer 350. The first drain connection line 343 may be disposed in contact with the first drain contact portion 332 and surrounded by the bonding layer 350. The first gate line 341 may be disposed in contact with the first gate electrode 535 and surrounded by the bonding layer 350.

The upper surface of the first source connection wiring 342 may be disposed higher than the upper surface of the first gate wiring 341. The upper surface of the first source connection wiring 342 may be disposed higher than the lower surface of the first gate electrode 333. The upper surface of the first drain connection wiring 343 may be disposed higher than the upper surface of the first gate wiring 341. The upper surface of the first drain connection wiring 343 may be disposed higher than the lower surface of the first gate electrode 535.

The second source connection wiring 442 may be disposed in contact with the second source contact portion 431 and surrounded by the bonding layer 350. The second drain connection line 443 may be disposed in contact with the second drain contact portion 432 and surrounded by the bonding layer 350. The second gate line 441 may be disposed in contact with the second gate electrode 433 and surrounded by the bonding layer 350.

The upper surface of the second source connection wiring 442 may be disposed higher than the upper surface of the second gate wiring 441. The upper surface of the second source connection wiring 442 may be disposed higher than the lower surface of the second gate electrode 433. The upper surface of the second drain connection wiring 443 may be disposed higher than the upper surface of the second gate wiring 441. The upper surface of the second drain connection wiring 443 may be disposed higher than the lower surface of the second gate electrode 433.

The thin film transistor substrate according to the embodiment may include the first protective layer 321, the first channel layer 360, and the second protective layer 322 disposed on the second channel layer 460. The first source electrode 371 may be electrically connected to the first source connection wiring 342 through the first passivation layer 321 and the second passivation layer 322. The first source electrode 371 may include a first region disposed on the second passivation layer 322. The first source electrode 371 may include a second region penetrating the second protective film 322 and the first protective film 321. The first drain electrode 372 may be electrically connected to the first drain connection wiring 343 through the first passivation layer 321 and the second passivation layer 322. The first drain electrode 372 may include a first region disposed on the second passivation layer 322. The first drain electrode 372 may include a second region passing through the second passivation layer 322 and the first passivation layer 321.

The second source electrode 471 may be electrically connected to the second source connection wiring 442 through the first passivation layer 321 and the second passivation layer 322. The second source electrode 471 may include a first region disposed on the second passivation layer 322. The second source electrode 471 may include a second region penetrating the second protective layer 322 and the first protective layer 321. The second drain electrode 472 may be electrically connected to the second drain connection wiring 443 through the first passivation layer 321 and the second passivation layer 322. The second drain electrode 472 may include a first region disposed on the second passivation layer 322. The second drain electrode 472 may include a second region penetrating the second passivation layer 322 and the first passivation layer 321.

According to the embodiment, the first drain-gate connection line 375 may be disposed on the second passivation layer 322. The first drain-gate connection line 375 may include a first region disposed over the second passivation layer 322. The first drain-gate connection line 375 may include a second region penetrating the second passivation layer 322 and the first passivation layer 321. A first region of the first drain-gate connection wiring 375 may be electrically connected to the first drain electrode 372. A first region of the first drain-gate connection line 375 may extend from the first drain electrode 372. For example, the first drain-gate connection line 375 may be formed integrally with the first drain electrode 372 in the same process. The first drain electrode 372 may be formed separately from the first drain-gate connection line 375 and may be electrically connected to the first drain-gate connection line 375. According to an embodiment of the present invention, The second drain-gate connection wiring 475 may be disposed. The second drain-gate connection line 475 may be electrically connected to the first drain-gate connection line 375. The second region of the first drain-gate connection line 375 may be disposed in contact with the second drain-gate connection line 475. The second drain-gate connection line 475 may be electrically connected to the second gate line 441. The second drain-gate connection line 475 may extend from the second gate line 441. For example, the second drain-gate connection line 475 may be formed integrally with the second gate line 441 in the same process. The second drain-gate connection line 475 and the second gate line 441 may be separately formed and electrically connected to each other. A part of the second drain-gate connection wiring 475 may be disposed in contact with the upper surface of the second gate wiring 441. The first drain electrode 372 is electrically connected to the second gate electrode 433 through the first drain-gate connection line 375, the second drain-gate connection line 475, As shown in FIG.

The double gate electrode 536 may include a first region disposed over the second passivation layer 322. The double gate electrode 536 may include a second region through the second passivation layer 322. The double gate electrode 536 may be disposed in contact with the upper surface of the first channel layer 360 through the second protective layer 322. The double gate electrode 536 may be Schottky contact with the first nitride semiconductor layer 361. The double gate electrode 536 may comprise a single layer or multiple layers comprising at least one material selected from the group consisting of nickel (Ni), platinum (Pt), gold (Au), palladium can do. By way of example, the sharkey contact may be implemented by plasma treatment of the first channel layer 360.

The first gate electrode 535 and the double gate electrode 536 may be electrically connected as shown in FIG. The switching thin film transistor 530 according to the embodiment includes a first thin film transistor 530 disposed under the first protective film 321 and electrically connected to the first gate electrode 535, And a gate connection wiring 537. The switching thin film transistor 530 according to the embodiment may include a second gate connection wiring 538 disposed on the second protective film 322 and extended from the double gate electrode 536. The first gate connection wiring 537 and the second gate connection wiring 538 may be electrically connected through the first protective layer 321 and the second protective layer 322. The first protective layer 321 is disposed in contact with a lower surface of the first channel layer 360 and is disposed in contact with a lower surface of the second protective layer 322 and has a first thickness, Lt; / RTI > A region of the first protective layer 321 having a first thickness may be disposed between the lower surface of the first channel layer 360 and the upper surface of the first gate wiring 341. A region of the first protective layer 321 having a second thickness is formed on the lower surface of the second protective layer 322 and the upper surface of the first source connection wiring 342 or the upper surface of the first drain connection wiring 343 Plane. ≪ / RTI > A region of the first protective layer 321 having a second thickness may be disposed between the lower surface of the second protective layer 322 and the upper surface of the bonding layer 350. The first thickness of the first protective layer 321 may be greater than the second thickness.

As shown in FIG. 33, the second channel layer 460 and the second depletion-imparting layer 415 may have the same width. If the width of the second depletion-forming layer 415 is smaller than the width of the second channel layer 460, a leakage current may be generated. In other words, the length of the second channel layer 460 provided along the direction in which the second gate electrode 433 is extended and arranged and the length of the second depletion-imparting layer 415 may be provided equally have.

Also, as shown in FIG. 34, the second channel layer 360 and the first deformation-forming layer 315 may be provided with the same width. If the width of the first depletion-forming layer 315 is smaller than the width of the first channel layer 360, a leakage current may be generated. As another expression, the length of the first channel layer 360 provided along the direction in which the first gate electrode 535 is extended and arranged and the length of the first depletion-imparting layer 315 may be provided equally have. The width of the first channel layer 360 and the width of the lower surface of the second gate electrode 536 may be the same.

The second passivation layer 322 may include an insulating material. The second passivation layer 322 may comprise a single layer or multiple layers including, for example, at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide containing Al ₂ O ₃ , .

The thin film transistor substrate according to the embodiment may include a third protective film 323 disposed on the second protective film 322. The third passivation layer 323 may be disposed on the first source electrode 371, the first drain electrode 372, the second source electrode 471, and the second drain electrode 472. The third protective film 323 may be disposed on the double gate electrode 536.

The third passivation layer 323 may include a single layer or multiple layers including at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide containing Al ₂ O ₃ , and an organic insulating material .

The thin film transistor substrate according to the embodiment may include a lower electrode 486 disposed on the driving thin film transistor 430. The lower electrode 486 may be electrically connected to the driving thin film transistor 430. The lower electrode 486 may be electrically connected to the second drain electrode 472 of the driving thin film transistor 430. The lower electrode 486 may be disposed on the third protective layer 423. The lower electrode 486 may be electrically connected to the second drain electrode 472 through a contact hole provided in the third passivation layer 323. The lower surface of the lower electrode 486 may be disposed in contact with the upper surface of the second drain electrode 472.

In addition, the thin film transistor substrate according to the embodiment may include a fourth protective film 324 disposed on the third protective film 323. The light emitting layer 488 may be disposed on the lower electrode 486 and the upper electrode 487 may be disposed on the light emitting layer 488. The light emitting layer 488 and the upper electrode 487 may be disposed on the fourth protective layer 324. The first region of the light emitting layer 488 is disposed on the fourth protective film 324 and the second region of the light emitting layer 488 is electrically connected to the lower electrode 486 through a contact hole provided in the fourth protective film 324. [ And can be disposed in contact with the upper surface. The light emitting layer 488 may emit any one of red, green, blue, and white light. The light emitting layer 488 may be formed of an organic material, for example.

The lower electrode 486 and the upper electrode 487 may comprise one material selected from, for example, ITO, ITO / Ag, ITO / Ag / ITO, ITO / Ag / IZO, have. The lower electrode 486 and the upper electrode 487 may include different materials. One of the upper electrode 486 and the lower electrode 487 may be formed as a transparent electrode so that the light emitted from the light emitting layer 488 may be emitted to the outside in the direction of the transparent electrode.

Similarly, as described with reference to FIG. 16, a portion of the first drain connection wiring 343 according to the embodiment is disposed between the first drain contact portion 332 and the first protective film 321 . May be provided in a space between a side surface of the first drain contact part 332 and the first protective film 321 in the process of forming the first drain contact part 332, A part of the connection wiring 343 may be formed. In the process of forming the through hole in the first protective film 321 to form the first drain contact 332, the side surface of the first protective film 321 surrounding the first drain contact 332 Can be formed to be inclined. The angle a2 formed by the side surface of the first protective film 321 and the top surface of the first protective film 321 may be provided at an acute angle. For example, the angle a2 formed between the side surface of the first protective film 321 and the top surface of the first protective film 321 may be 10 degrees to 90 degrees. More preferably, the angle a2 formed by the side surface of the first protective film 321 and the top surface of the first protective film 321 may be 30 degrees to 90 degrees. A predetermined gap t2 may be provided between the side surface of the first protective layer 321 and the first drain contact portion 332. For example, an interval of 0 to 3 mu m may be provided. Although not shown in the drawings, a portion of the first source connection wiring 342 according to the embodiment may be disposed between the first source contact portion 331 and the first protective film 321. May be provided in a space between a side surface of the first source contact portion 331 and the first protective film 321 in the process of forming the first source contact portion 331, A part of the connection wiring 343 may be formed. Since the first channel layer 360 is formed through the etching process, the angle a1 between the side surface of the first channel layer 360 and the lower surface of the first channel layer 360 is May be provided at an acute angle. For example, the angle a1 formed between the side surface of the first channel layer 360 and the lower surface of the first channel layer 360 may be 30 degrees to 90 degrees.

For example, when the first passivation layer 321 is formed of a silicon oxide such as SiO ₂ , the first passivation layer 321 may be etched by wet etching or dry etching. When the etching is performed by wet etching, the angle of a2 may be about 10 degrees to about 60 degrees, and a wider shape may be provided within a few micrometers than the pattern to be etched. When wet etching is performed, the angle of a2 may be formed at an angle of about 35 to 45 degrees. When the etching is performed by dry etching, the angle of a2 may be about 60 to 90 degrees, and a shape having a width similar to the pattern to be etched may be provided. When dry etching is performed, the angle of a2 may be formed at an angle of about 65 to 75 degrees.

The upper surface of the first nitride semiconductor layer 361 may be provided shorter than the lower surface. The upper surface of the second nitride semiconductor layer 362 may be provided shorter than the lower surface. The lower surface of the first nitride semiconductor layer 361 and the upper surface of the second nitride semiconductor layer 362 may have the same length. In the step of forming the first channel layer 360 by etching, a partial overgrowth may be generated in the end region of the first channel layer 360. Accordingly, a step may be provided on the upper surface of the first protective film 321. That is, the first protective layer 321 may have a thickness different from that of the first channel layer 360 and the region of the first channel layer 360 where the first channel layer 360 is not disposed. As an example, the thickness t1 of the step may be provided on the order of 0 to 1 mu m. Accordingly, the lower surface of the second protective layer 322 disposed on the first protective layer 321 may extend below the lower surface of the first channel layer 360.

According to the thin film transistor substrate according to the embodiment, a high carrier mobility can be realized by providing the thin film transistor including the nitride based semiconductor layer. For example, the electron mobility (cm 2 / Vs) varies depending on the material used as the channel layer in the thin film transistor. In the amorphous silicon semiconductor, the electron mobility is 1, and in the case of the oxide semiconductor, And in the case of a polysilicon semiconductor, it is reported to be 100 or less. However, the thin film transistor including the nitride based semiconductor layer according to the embodiment has been measured to have an electron mobility of 1500. Accordingly, the thin film transistor including the nitride based semiconductor layer according to the embodiment can realize a 15 times higher electron mobility than the thin film transistor to which the polysilicon semiconductor is applied.

According to the embodiments, a semiconductor layer with good quality can be formed using a growth substrate, and a thin film transistor substrate having excellent electron mobility can be provided by applying a transfer process using a supporting substrate.

Therefore, according to the thin film transistor substrate, the display panel and the display device including the thin film transistor substrate according to the embodiment, it is possible to provide a high carrier mobility, thereby realizing a high resolution and reproducing a smooth moving image.

35 and 36 are views showing still another example of the thin film transistor substrate according to the embodiment of the present invention. FIG. 35 is a cross-sectional view taken along line D-D of the thin film transistor substrate shown in FIG. 28, and FIG. 36 is a cross-sectional view taken along line E-E of the thin film transistor substrate shown in FIG.

The thin film transistor substrate shown in FIGS. 35 and 36 is an embodiment to which a thin film transistor having a structure in which a gate electrode is disposed in a recessed region of a channel layer is applied, and the thin film transistor substrate shown in FIGS. The description may be omitted.

The thin film transistor substrate according to an embodiment may include a switching thin film transistor 730 and a driving thin film transistor 830. The switching thin film transistor 730 can receive a signal from the gate line 341 and the data line 373 and can provide a gate signal and a data signal to the pixel. The gate electrode 833 of the driving thin film transistor 830 may be electrically connected to the drain electrode 372 of the switching thin film transistor 330.

35 and 36, a thin film transistor substrate according to an embodiment of the present invention includes a support substrate 355 and the switching thin film transistor 730, the driving thin film transistor (not shown) disposed on the support substrate 355, 830, and a light emitting layer 488 electrically connected to the driving thin film transistor 830.

The switching thin film transistor 730 according to the embodiment may include a first gate electrode 733, a first channel layer 760, a first source electrode 371, and a first drain electrode 372. The first source electrode 371 may be electrically connected to a first region of the first channel layer 760. The first source electrode 371 may be electrically connected to the lower surface of the first channel layer 760. The first drain electrode 372 may be electrically connected to a second region of the first channel layer 760. The first drain electrode 372 may be electrically connected to the lower surface of the first channel layer 760. The first gate electrode 733 may be disposed under the first channel layer 760.

The first channel layer 760 may include a recessed region recessed upwardly in the lower surface. The first gate electrode 733 may be disposed in the recessed region of the first channel layer 760.

The driving thin film transistor 830 according to the embodiment may include a second gate electrode 433, a second channel layer 860, a second source electrode 471, and a second drain electrode 472. The second source electrode 471 may be electrically connected to the first region of the second channel layer 860. The second source electrode 471 may be electrically connected to the lower surface of the second channel layer 860. The second drain electrode 472 may be electrically connected to a second region of the second channel layer 860. The second drain electrode 472 may be electrically connected to the lower surface of the second channel layer 860. The second gate electrode 833 may be disposed below the second channel layer 860.

The second channel layer 860 may include a recessed region recessed upwardly in the lower surface. The second gate electrode 833 may be disposed in the recessed region of the second channel layer 860.

The structure of the switching thin film transistor 730 and the driving thin film transistor 830 are similar to each other. In the description of the driving thin film transistor 830, the description of the switching thin film transistor 730 The description may be omitted.

The first channel layer 760 and the second channel layer 860 may be formed of a Group III-V compound semiconductor, for example. For example, the first channel layer 760 and the second channel layer 860 may be In _x Al _y Ga _1-xy N (0? X? 1, 0? _Y? 1, 0? _X + Lt; RTI ID = 0.0 > of < / RTI > The first channel layer 760 and the second channel layer 860 may be a single layer or multiple layers selected from, for example, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP, Layer. The first channel layer 760 and the second channel layer 860 may be formed of different materials.

Each of the first channel layer 760 and the second channel layer 860 may include first and second nitride semiconductor layers 761 and 861 and second nitride semiconductor layers 762 and 862. The first nitride semiconductor layer 761. 861 has a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + y? 1) Semiconductor material. The second nitride semiconductor layers 762 and 862 have a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + y? 1) Semiconductor material. May be provided in a recessed region recessed upwardly on the lower surface of the second nitride semiconductor layer (762, 862). The first gate electrode 733 may be disposed in a recessed region of the second nitride semiconductor layer 762. The upper surface of the first gate electrode 733 may be disposed higher than the lower surface of the second nitride semiconductor layer 762. The first gate electrode 733 and the second nitride semiconductor layer 762 may be Schottky contact. The second gate electrode 833 may be disposed in a recessed region of the second nitride semiconductor layer 862. The upper surface of the second gate electrode 833 may be disposed higher than the lower surface of the second nitride semiconductor layer 862. The second gate electrode 833 and the second nitride semiconductor layer 862 may be Schottky contact. According to the first channel layer 760 and the second channel layer 860 according to the embodiment, the first nitride semiconductor layers 761 and 861 include GaN semiconductor layers, and the second nitride semiconductor layer 762, and 862 may include an AlGaN semiconductor layer.

The supporting substrate 355 may include a transparent substrate. The support substrate 355 may be embodied as a transparent substrate having a thickness of 0.1 mm to 3 mm, for example. The support substrate 355 may include at least one material selected from materials including silicon, glass, polyimide, and plastic. The supporting substrate 355 may include a flexible substrate.

The supporting substrate 355 is a substrate to be used in a transfer process and supports the switching thin film transistor 730 and the driving thin film transistor 830. In addition, the thin film transistor substrate according to the embodiment may include a bonding layer 350 provided between the supporting substrate 355 and the switching thin film transistor 730. The bonding layer 350 may be disposed between the supporting substrate 355 and the driving thin film transistor 830.

The bonding layer 350 may include an organic material. The bonding layer 350 may be formed of a transparent material. The bonding layer 350 may be formed of a material having a transmittance of 70% or more. The bonding layer 350 may include an organic insulating material. The bonding layer 350 may include at least one material selected from the group consisting of acryl, benzocyclobutene (BCB), SU-8 polymer, and the like. The bonding layer 350 may be provided in a thickness of 0.5 to 6 mu m, for example.

The switching thin film transistor 730 according to the embodiment includes a first source contact portion 331 disposed under the first region of the first channel layer 760 and a second source contact portion 332 under the second region of the first channel layer 760 And may include a first drain contact portion 332 disposed therein. The first source contact portion 331 may be disposed in contact with the first region of the first channel layer 760. The first drain contact portion 332 may be disposed in contact with a second region of the first channel layer 760.

The switching thin film transistor 730 according to the embodiment includes a first source connection wiring 342 disposed below the first source contact portion 331 and a first drain connection portion 332 disposed below the first drain contact portion 332. [ And a wiring 343. In addition, the switching thin film transistor 730 may include a first gate wiring 341 disposed under the first gate electrode 733. The first source connection wiring 342 may be electrically connected to the first source contact portion 331. For example, the upper surface of the first source connection wiring 342 may be disposed in contact with the lower surface of the first source contact portion 331. The first drain connection wiring 343 may be electrically connected to the first drain contact portion 332. For example, the upper surface of the first drain connection wiring 343 may be disposed in contact with the lower surface of the first drain contact portion 332. The first gate wiring 341 may be electrically connected to the first gate electrode 733. The upper surface of the first gate wiring 341 may be disposed in contact with the lower surface of the first gate electrode 733. [

The first source electrode 371 may be electrically connected to the first source connection wiring 342. The first source electrode 371 may be disposed in contact with the upper surface of the first source connection wiring 342. For example, the first source electrode 371 may be electrically connected to the first region of the first channel layer 760 through the first source connection line 342 and the first source contact portion 331 have. The first drain electrode 372 may be electrically connected to the first drain connection wiring 343. The first drain electrode 372 may be disposed in contact with the upper surface of the first drain connection wiring 343. For example, the first drain electrode 372 may be electrically connected to the second region of the first channel layer 760 through the first drain connection line 343 and the first drain contact 332 have.

The driving thin film transistor 830 according to the embodiment includes a second source contact portion 431 disposed under the first region of the second channel layer 860 and a second source contact portion 431 disposed under the second region of the second channel layer 860 And a second drain contact portion 432 disposed therein. The second source contact portion 431 may be disposed in contact with the first region of the second channel layer 860. The second drain contact portion 432 may be disposed in contact with a second region of the second channel layer 860.

The driving thin film transistor 830 according to the embodiment includes a second source connection wiring 442 disposed below the second source contact portion 431 and a second drain connection portion 432 disposed below the second drain contact portion 432. [ And may include wiring 443. In addition, the driving thin film transistor 830 may include a second gate wiring 441 disposed under the second gate electrode 433. The second source connection wiring 442 may be electrically connected to the second source contact portion 431. For example, the upper surface of the second source connection wiring 442 may be disposed in contact with the lower surface of the second source contact portion 431. The second drain connection line 443 may be electrically connected to the second drain contact 432. For example, the upper surface of the second drain connection wiring 443 may be disposed in contact with the lower surface of the second drain contact portion 432. The second gate line 441 may be electrically connected to the second gate electrode 833. The upper surface of the second gate wiring 441 may be disposed in contact with the lower surface of the second gate electrode 833.

The second source electrode 471 may be electrically connected to the second source connection wiring 442. The second source electrode 471 may be disposed in contact with the upper surface of the second source connection wiring 442. For example, the second source electrode 471 may be electrically connected to the first region of the second channel layer 860 through the second source connection line 442 and the second source contact portion 431 have. The second drain electrode 472 may be electrically connected to the second drain connection line 443. The second drain electrode 472 may be disposed in contact with the upper surface of the second drain connection wiring 443. The second drain electrode 472 may be electrically connected to the second region of the second channel layer 860 through the second drain connection line 443 and the second drain contact 432 have.

The first source contact portion 331 and the first drain contact portion 332 may be formed of a material that makes an ohmic contact with the first channel layer 760. The first source contact portion 331 and the first drain contact portion 332 may include a material that makes an ohmic contact with the second nitride semiconductor layer 762. The second source contact portion 431 and the second drain contact portion 432 may be formed of a material that makes an ohmic contact with the second channel layer 860. The second source contact portion 431 and the second drain contact portion 432 may include a material that makes an ohmic contact with the second nitride semiconductor layer 862. [ For example, the first source contact portion 331, the first drain contact portion 332, the second source contact portion 431, and the second drain contact portion 432 may be formed of aluminum (Al), aluminum alloy The present invention relates to a method for manufacturing a semiconductor device comprising the steps of forming an Al alloy, tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy, At least any one material selected from the group consisting of chromium (Cr), titanium (Ti), titanium alloy, molybdenum tungsten (MoW), moly titanium (MoTi), copper / moly titanium (Cu / MoTi) ≪ RTI ID = 0.0 > and / or < / RTI > The first source contact portion 331, the first drain contact portion 332, the second source contact portion 431 and the second drain contact portion 432 are provided with a thickness of, for example, .

The first gate electrode 733 may be formed of a material which is in sharky contact with the first channel layer 760. The first gate electrode 733 may be formed of a material which is in contact with the second nitride semiconductor layer 762 in a shark-like manner. The first gate electrode 733 may be a single layer or multiple layers including at least one material selected from the group consisting of nickel (Ni), platinum (Pt), gold (Au), palladium (Pd) . By way of example, the sharkey contact may be implemented by a plasma treatment for the first channel layer 760. As the plasma treatment, for example, fluorine (F) ion treatment may be applied. Accordingly, the switching thin film transistor 730 according to the embodiment may be provided with a threshold voltage by the shark touch and may have a normally off characteristic. When a voltage equal to or higher than a threshold voltage is applied to the first gate electrode 733, a channel formed on the first gate electrode 733 is turned on to allow current to flow through the first channel layer 760.

The second gate electrode 833 may be formed of a material which is in sharky contact with the second channel layer 860. The second gate electrode 833 may be formed of a material which is in contact with the second nitride semiconductor layer 862 in a shark-like manner. The second gate electrode 833 may be a single layer or multiple layers including at least one material selected from the group consisting of nickel (Ni), platinum (Pt), gold (Au), palladium (Pd) . By way of example, the sharkey contact may be implemented by a plasma treatment for the second channel layer 860. As the plasma treatment, for example, fluorine (F) ion treatment may be applied. Accordingly, the driving thin film transistor 830 according to the embodiment may be provided with a threshold voltage by the shark touch, and may have a normally off characteristic. When a voltage equal to or higher than a threshold voltage is applied to the second gate electrode 833, a channel formed on the second gate electrode 833 is turned on, and a current can flow through the second channel layer 860.

The first gate wiring 341 and the second gate wiring 441 may be formed of a metal such as aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), copper alloy, molybdenum ), Silver (Ag), silver alloy, gold (Au), gold alloy, chromium (Cr), titanium (Ti), titanium alloy, molybdenum tungsten And may include a single layer or multiple layers comprising at least one material selected from the group consisting of titanium (MoTi), copper / moly titanium (Cu / MoTi). The first gate wiring 341 and the second gate wiring 441 may be provided in a thickness of 0.1 to 3 占 퐉, for example.

The first source connection wiring 342, the first drain connection wiring 343, the second source connection wiring 442 and the second drain connection wiring 443 are made of aluminum (Al), an aluminum alloy ), Tungsten (W), copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy, gold (Au) (Ti), Ti alloy, molybdenum tungsten (MoW), moly titanium (MoTi), copper / moly titanium (Cu / MoTi) Single layer or multiple layers. The first source connection wiring 342, the first drain connection wiring 343, the second source connection wiring 442 and the second drain connection wiring 443 are provided with a thickness of, for example, 0.1 to 3 μm .

The first source electrode 371, the first drain electrode 372, the second source electrode 471 and the second drain electrode 472 may be formed of aluminum (Al), aluminum alloy (Al alloy), tungsten (W ), Copper (Cu), copper alloy, molybdenum (Mo), silver (Ag), silver alloy, gold (Au), gold alloy, chromium (Cr) A single layer or multiple layers comprising at least one material selected from the group consisting of Ti, Ti alloy, molybdenum (MoW), moly titanium (MoTi), copper / moly titanium (Cu / MoTi) . ≪ / RTI > The first source electrode 371, the first drain electrode 372, the second source electrode 471 and the second drain electrode 472 may be provided with a thickness of 0.1 to 3 μm, for example.

The thin film transistor substrate according to the embodiment may include the first channel layer 760 and the first protective film 321 disposed under the second channel layer 860. The first passivation layer 321 may be disposed under the second nitride semiconductor layer 762 of the first channel layer 760 and the second nitride semiconductor layer 862 of the second channel layer 860 . The upper surface of the first protective film 321 is formed on the lower surface of the second nitride semiconductor layer 762 of the first channel layer 760 and the second nitride semiconductor layer 862 of the second channel layer 860 Can be disposed in contact with each other.

According to the embodiment, the first source contact portion 331 may be disposed through the first protective film 321. The first source contact portion 331 may be surrounded by the first protective layer 321. The first source contact portion 331 may be disposed through the first protective layer 321 and may be provided in contact with the first region of the first channel layer 760. The first drain contact part 332 may be disposed through the first protective film 321. The first drain contact portion 332 may be surrounded by the first protective layer 321. The first drain contact portion 332 may be disposed through the first protective layer 321 and may be provided in contact with the second region of the first channel layer 760.

According to the embodiment, the second source contact part 431 may be arranged to penetrate the first protective film 321. The second source contact portion 431 may be surrounded by the first protective layer 321. The second source contact portion 431 may be disposed through the first protective layer 321 and may be provided in contact with the first region of the second channel layer 860. The second drain contact portion 432 may be disposed through the first passivation layer 321. The second drain contact part 432 may be surrounded by the first protective film 321. The second drain contact portion 432 may be disposed through the first protective layer 321 and may be provided in contact with the second region of the second channel layer 860.

The first passivation layer 321 may be formed of an insulating material. The first passivation layer 321 may include a single layer or multiple layers including at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide including Al ₂ O ₃ , and an organic insulating material .

The first source connection wiring 342 may be disposed in contact with the first source contact portion 331 and surrounded by the bonding layer 350. The first drain connection line 343 may be disposed in contact with the first drain contact portion 332 and surrounded by the bonding layer 350. The first gate line 341 may be disposed in contact with the first gate electrode 333 and surrounded by the bonding layer 350.

The second source connection wiring 442 may be disposed in contact with the second source contact portion 431 and surrounded by the bonding layer 350. The second drain connection line 443 may be disposed in contact with the second drain contact portion 432 and surrounded by the bonding layer 350. The second gate line 441 may be disposed in contact with the second gate electrode 433 and surrounded by the bonding layer 350.

The thin film transistor substrate according to the embodiment may include the first protective layer 321, the first channel layer 760, and the second protective layer 322 disposed on the second channel layer 860. The first source electrode 371 may be electrically connected to the first source connection wiring 342 through the first passivation layer 321 and the second passivation layer 322. The first source electrode 371 may include a first region disposed on the second passivation layer 322. The first source electrode 371 may include a second region penetrating the second protective film 322 and the first protective film 321. The first drain electrode 372 may be electrically connected to the first drain connection wiring 343 through the first passivation layer 321 and the second passivation layer 322. The first drain electrode 372 may include a first region disposed on the second passivation layer 322. The first drain electrode 372 may include a second region passing through the second passivation layer 322 and the first passivation layer 321.

The second source electrode 471 may be electrically connected to the second source connection wiring 442 through the first passivation layer 321 and the second passivation layer 322. The second source electrode 471 may include a first region disposed on the second passivation layer 322. The second source electrode 471 may include a second region penetrating the second protective layer 322 and the first protective layer 321. The second drain electrode 472 may be electrically connected to the second drain connection wiring 443 through the first passivation layer 321 and the second passivation layer 322. The second drain electrode 472 may include a first region disposed on the second passivation layer 322. The second drain electrode 472 may include a second region penetrating the second passivation layer 322 and the first passivation layer 321.

According to the embodiment, the first drain-gate connection line 375 may be disposed on the second passivation layer 322. The first drain-gate connection line 375 may include a first region disposed over the second passivation layer 322. The first drain-gate connection line 375 may include a second region penetrating the second passivation layer 322 and the first passivation layer 321. A first region of the first drain-gate connection wiring 375 may be electrically connected to the first drain electrode 372. A first region of the first drain-gate connection line 375 may extend from the first drain electrode 372.

According to the embodiment, a second drain-gate connection line 475 may be disposed under the first passivation layer 321. The second drain-gate connection line 475 may be electrically connected to the first drain-gate connection line 375. The second region of the first drain-gate connection line 375 may be disposed in contact with the second drain-gate connection line 475. The second drain-gate connection line 475 may be electrically connected to the second gate line 441. The second drain-gate connection line 475 may extend from the second gate line 441. For example, the second drain-gate connection line 475 may be formed integrally with the second gate line 441 in the same process. The second drain-gate connection line 475 and the second gate line 441 may be separately formed and electrically connected to each other. A part of the second drain-gate connection wiring 475 may be disposed in contact with the upper surface of the second gate wiring 441. The first drain electrode 372 is connected to the second gate 433 through the first drain-gate connection line 375, the second drain-gate connection line 475, The second protective layer 322 may include an insulating material. The second passivation layer 322 may comprise a single layer or multiple layers including, for example, at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide containing Al ₂ O ₃ , .

The thin film transistor substrate according to the embodiment may include a third protective film 323 disposed on the second protective film 322. The third passivation layer 323 may be disposed on the first source electrode 371, the first drain electrode 372, the second source electrode 471, and the second drain electrode 472.

The third passivation layer 323 may include a single layer or multiple layers including at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide containing Al ₂ O ₃ , and an organic insulating material .

The thin film transistor substrate according to an embodiment may include a lower electrode 486 disposed on the driving thin film transistor 830. The lower electrode 486 may be electrically connected to the driving thin film transistor 430. The lower electrode 486 may be electrically connected to the second drain electrode 472 of the driving TFT 830. The lower electrode 486 may be disposed on the third protective layer 423. The lower electrode 486 may be electrically connected to the second drain electrode 472 through a contact hole provided in the third passivation layer 323. The lower surface of the lower electrode 486 may be disposed in contact with the upper surface of the second drain electrode 472.

In addition, the thin film transistor substrate according to the embodiment may include a fourth protective film 324 disposed on the third protective film 323. The light emitting layer 488 may be disposed on the lower electrode 486 and the upper electrode 487 may be disposed on the light emitting layer 488. The light emitting layer 488 and the upper electrode 487 may be disposed on the fourth protective layer 324. The first region of the light emitting layer 488 is disposed on the fourth protective film 324 and the second region of the light emitting layer 488 is electrically connected to the lower electrode 486 through a contact hole provided in the fourth protective film 324. [ And can be disposed in contact with the upper surface. The light emitting layer 488 may emit any one of red, green, blue, and white light. The light emitting layer 488 may be formed of an organic material, for example.

The lower electrode 486 and the upper electrode 487 may comprise one material selected from, for example, ITO, ITO / Ag, ITO / Ag / ITO, ITO / Ag / IZO, have. The lower electrode 486 and the upper electrode 487 may include different materials. One of the upper electrode 486 and the lower electrode 487 may be formed as a transparent electrode so that the light emitted from the light emitting layer 488 may be emitted to the outside in the direction of the transparent electrode.

According to the thin film transistor substrate according to the embodiment, a high carrier mobility can be realized by providing the thin film transistor including the nitride based semiconductor layer. For example, the electron mobility (cm 2 / Vs) varies depending on the material used as the channel layer in the thin film transistor. In the amorphous silicon semiconductor, the electron mobility is 1, and in the case of the oxide semiconductor, And in the case of a polysilicon semiconductor, it is reported to be 100 or less. However, the thin film transistor including the nitride based semiconductor layer according to the embodiment has been measured to have an electron mobility of 1500. Accordingly, the thin film transistor including the nitride based semiconductor layer according to the embodiment can realize a 15 times higher electron mobility than the thin film transistor to which the polysilicon semiconductor is applied.

According to the embodiments, a semiconductor layer with good quality can be formed using a growth substrate, and a thin film transistor substrate having excellent electron mobility can be provided by applying a transfer process using a supporting substrate.

Therefore, according to the thin film transistor substrate, the display panel and the display device including the thin film transistor substrate according to the embodiment, it is possible to provide a high carrier mobility, thereby realizing a high resolution and reproducing a smooth moving image.

37 is a block diagram showing an example of a display device including a thin film transistor substrate according to an embodiment of the present invention.

The display device according to the embodiment may include a display panel 2100 and a panel driver 2300 as shown in FIG.

The display panel 2100 may include any one of the thin film transistor substrates described with reference to FIGS. 28 to 36. FIG. The panel driver 2300 may provide a driving signal to the display panel 2100. The panel driving unit 2300 can control the light transmittance of a plurality of pixels provided on the display panel 2100 so that an image can be displayed on the display panel 2100.

The features, structures, effects and the like described in the embodiments are included in at least one embodiment of the present invention and are not necessarily limited to one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments can be combined and modified by other persons having ordinary skill in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of illustration, It can be seen that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

10 growth substrate 15 depletion layer
21 First protective film 22 Second protective film
23 Third protective film 24 Fourth protective film
30, 130, 230 Thin film transistor 31 Source contact portion
32 drain contact portions 33, 233, 733, 833,
35 first gate electrode 36 second gate electrode
37, 537 First gate connection wiring 38, 538 Second gate connection wiring
41 Gate wiring 42 Source wiring
43 drain connection wiring 50 bonding layer
55 Support substrate 60, 260, 760, 860 Channel layer
61, 261, 761, 861 The first nitride semiconductor layer
62, 262, 762, 862 A second nitride semiconductor layer
71 source electrode 72 drain electrode
73 data wiring 80, 81, 82 pixel electrode
85 Common electrode 91 Touch panel lower electrode
92 touch panel upper electrode 330, 530, 730 switching thin film transistor
331 first source contact portion 332 first drain contact portion
333 First gate electrode 341 First gate wiring
342 First source connection wiring 343 First drain connection wiring
360 first channel layer 361 first nitride semiconductor layer
362 Second nitride semiconductor layer 371 First source electrode
372 First drain electrode 373 Data line
375 First drain-gate connection wiring 430, 830 Driving thin film transistor
431 second source contact portion 432 second drain contact portion
433 Second gate electrode 441 Second gate wiring
442 Second Source Connection Wiring 443 Third Drain Connection Wiring
460 Second channel layer 461 First nitride semiconductor layer
462 Second nitride semiconductor layer 471 Second source electrode
472 Second drain electrode 474 Driving power supply wiring
475 Second drain-gate connection wiring 486 Lower electrode
487 upper electrode 488 light emitting layer
535 First gate electrode 536 Double gate electrode

Claims (20)

A support substrate;
A bonding layer disposed on the support substrate;
A first channel layer disposed on the bonding layer and including a nitride based semiconductor layer and having a first recessed region recessed upwardly on a lower surface thereof; a first channel layer disposed on the lower surface of the first channel layer, A switching transistor including a first source electrode, a first drain electrode electrically connected to a second region of a lower surface of the first channel layer, and a first gate electrode disposed in a first recess region of the first channel layer;
A second channel layer disposed over the bonding layer and including a nitride based semiconductor layer and having a second recessed region recessed upwardly in a lower surface thereof; a second channel layer disposed on the lower surface of the second channel layer, A source electrode, a second drain electrode electrically connected to the second region of the lower surface of the second channel layer, and a second gate electrode disposed in the second recess region of the second channel layer;
A lower electrode disposed on the driving thin film transistor and electrically connected to the driving thin film transistor;
A light emitting layer disposed on the lower electrode;
An upper electrode disposed on the light emitting layer;
And a gate electrode. The method according to claim 1,
Wherein the first channel layer and the second channel layer are formed of a thin film including In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + Transistor substrate. The method according to claim 1,
Wherein the first channel layer comprises a first GaN semiconductor layer and a first AlGaN semiconductor layer disposed below the first GaN semiconductor layer and providing the first recess region,
Wherein the second channel layer comprises a second GaN semiconductor layer and a second AlGaN semiconductor layer disposed below the second GaN semiconductor layer and providing the second recess region. The method of claim 3,
Wherein the first gate electrode and the first AlGaN semiconductor layer are shaky-contacted, and the second gate electrode and the second AlGaN semiconductor layer are shaky-contacted. The method of claim 3,
The upper surface of the first gate electrode is disposed higher than the lower surface of the first AlGaN semiconductor layer and the upper surface of the second gate electrode is disposed higher than the lower surface of the second AlGaN semiconductor layer Gt; The method according to claim 1,
Wherein the bonding layer includes an organic material and has a transmittance of 70% or more. The method according to claim 1,
Wherein the supporting substrate is a transparent substrate having a thickness of 0.1 mm to 3 mm. The method according to claim 1,
And a first protective layer disposed under the first channel layer and the second channel layer,
A first source contact portion disposed through the first protective film and in contact with a first region of the first channel layer; a second source contact portion disposed through the first protective film and in contact with the second region of the first channel layer; 1 drain contact portion,
A second source contact portion disposed through the first protective film and in contact with a first region of the second channel layer; a second source contact portion disposed through the first protective film and in contact with the second region of the second channel layer; 2 drain contact portion. 9. The method of claim 8,
A first source connection wiring disposed in contact with and under the first source contact portion and surrounded by the bonding layer, a first drain connection wiring disposed in contact with the first drain contact portion and surrounded by the bonding layer, And a first gate wiring disposed in contact with and under the first gate electrode and surrounded by the bonding layer,
A second source connection wiring disposed in contact with and under the second source contact portion and surrounded by the bonding layer, a second drain connection wiring disposed in contact with the second drain contact portion and surrounded by the bonding layer, And a second gate wiring disposed in contact with the second gate electrode under the second gate electrode and surrounded by the bonding layer. 10. The method of claim 9,
A portion of the first source connection wiring is disposed between the first source contact portion and the first protective film and a portion of the first drain connection wiring is disposed between the first drain contact portion and the first protective film And,
A portion of the second source connection wiring is disposed between the second source contact portion and the first protective film and a portion of the second drain connection wiring is disposed between the second drain contact portion and the first protective film Gt; 10. The method of claim 9,
And a second protective layer disposed on the first protective layer, the first channel layer, and the second channel layer,
Wherein the first source electrode is electrically connected to the first source connection wiring through the first protective film and the second protective film and the first drain electrode penetrates the first protective film and the second protective film, 1 drain connection wiring,
Wherein the second source electrode is electrically connected to the second source connection wiring through the first protective film and the second protective film and the second drain electrode penetrates the first protective film and the second protective film, 2 Thin film transistor substrate electrically connected to drain connection wiring. 12. The method of claim 11,
And a third protective film disposed on the first source electrode, the first drain electrode, the second source electrode, the second drain electrode, and the second protective film,
Wherein the lower electrode is disposed on the third protective film and the lower electrode is electrically connected to the second drain electrode of the driving thin film transistor through a contact hole provided in the third protective film. 9. The method of claim 8,
Wherein the first passivation layer comprises a single layer or multiple layers including at least one of a silicon-based oxide, a silicon-based nitride, a metal oxide, and an organic insulating material. 12. The method of claim 11,
Wherein a first drain electrode of the switching thin film transistor and a second gate electrode of the driving thin film transistor are electrically connected to each other. 15. The method of claim 14,
And a drain-gate connection wiring disposed on the second protective film,
The first region of the drain-gate connection wiring is electrically connected to the first drain connection wiring through the second protection film and the first protection film, and the second region of the drain- And a second gate electrode electrically connected to the first gate electrode. 16. The method of claim 15,
Wherein the lower surface of the first source electrode, the lower surface of the first drain electrode, the lower surface of the second pixel electrode, the lower surface of the second drain electrode, and the lower surface of the drain- And is disposed in contact with the upper surface of the protective film. 13. The method of claim 12,
And a fourth protective film disposed on the third protective film,
Wherein the first region of the light emitting layer is disposed on the fourth protective film and the second region of the light emitting layer is disposed in contact with the upper surface of the lower electrode through a contact hole provided in the fourth protective film. The method according to claim 1,
The angle formed by the side surface of the first channel layer and the lower surface of the first channel layer is 30 to 90 degrees,
Wherein an angle formed by a side surface of the second channel layer and a lower surface of the second channel layer is 30 degrees to 90 degrees. A display panel comprising the thin film transistor substrate according to any one of claims 1 to 18. A display panel including the thin film transistor substrate according to any one of claims 1 to 18;
A panel driver for driving the display panel;
.

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