KR20170068422A - Core for reverse reflow, semiconductor package, and method of fabricating a semiconductor package - Google Patents

Abstract

The present invention relates to a core material for reverse reflow, a semiconductor package, and a method of manufacturing a semiconductor package, and more particularly, to a semiconductor device having a bump pad. And a bump portion coupled to the bump pad. At this time, the bump portion includes: a core; A first metal layer coated over the core; A second metal layer coated on the first metal layer; And a solder layer coated on the second metal layer, the thickness of the solder layer being thinner as the pad is away from the bump pad. INDUSTRIAL APPLICABILITY By using the core material for reverse reflow of the present invention, the semiconductor package and the manufacturing method of the semiconductor package of the present invention, it is possible to manufacture a semiconductor package with excellent bonding strength with high precision.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a core material for reverse reflow, a semiconductor package, an electronic system, and a method for manufacturing a semiconductor package,

The present invention relates to a core material for reverse reflow, a semiconductor package, and a method of manufacturing a semiconductor package, and more particularly, to a core material for a reverse reflow process which can be manufactured with high precision and has high bonding strength, .

BACKGROUND ART [0002] A printed circuit board (PCB) is widely used in household appliances such as televisions, mobile phones, and computers, but recently it has been widely used in automobiles. Lead (Sn) - lead (Pb) alloy products have been widely used as solders in household electrical appliances. Lead has been used as a component to determine the wettability, strength and mechanical properties of alloys. The melting point can be lowered to 183 DEG C, thereby preventing thermal damage occurring during the soldering process of electronic parts and semiconductor processes.

Meanwhile, tin (Sn) - silver (Ag) -copper (Cu) ternary lead-free solder alloys have been proposed due to the strict regulations regarding the environmental problems caused by lead. In order to mount the high- After the core is plated with Ni, a ternary system such as tin (Sn) - silver (Ag) or tin (Sn) - silver (Ag) - copper (Cu) A plating ball is used. When such a plating ball is used, since the core material does not melt during the reflow process and only the solder layer plated on the surface is melted, the stand-off characteristic is excellent. However, when the ternary solder plating layer is formed, the manufacturing cost is high, and the quality stability of the solder layer is low, which lowers the bonding strength.

Japanese Patent No. 4,488,642

A first object of the present invention is to provide a core for a reverse reflow furnace capable of manufacturing a semiconductor package with high bonding strength with high precision.

A second object of the present invention is to provide a semiconductor package having high precision and excellent bonding strength.

A third object of the present invention is to provide a method of manufacturing a semiconductor package capable of manufacturing an excellent semiconductor package with high precision.

A fourth object of the present invention is to provide an electronic system including a semiconductor package having high precision and excellent bonding strength.

The present invention, in order to achieve the first technical object, A first metal layer coated over the core; And a second metal layer coated on the first metal layer. Here, the first metal layer may be nickel (Ni) or cobalt (Co), and the second metal layer may be gold (Au) or platinum (Pt). Also, the thickness of the second metal layer may be between about 0.01 microns and about 0.3 microns.

According to a second aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor device having a bump pad; And a bump portion coupled to the bump pad. Here, the bump portion may include a core; An intermetallic compound layer formed on the core; And a solder layer coated on the intermetallic compound layer. Also, the thickness of the solder layer may become thinner away from the bump pad.

Here, the solder layer may be coated on the intermetallic compound layer so as to surround the entirety of the core. The intermetallic compound of the intermetallic compound layer may be at least one selected from the group consisting of NiCu ₃ Sn ₄ , (Cu, Ni) ₆ Sn ₅ , and Ni ₃ Sn ₄ . In addition, the semiconductor package may further include a first metal layer between the core and the intermetallic compound layer.

Here, the semiconductor device may be a semiconductor chip. Alternatively or alternatively, the semiconductor device includes a package substrate and a semiconductor chip disposed on the substrate, and the bump pad may be provided on the package substrate. In particular, the solder layer may contain substantially no organic material.

Here, the thickness of the solder layer may be monotonously thinned to a point farthest from the bump pad.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: providing a substrate having a bump pad; Dipping a solder paste on the bump pad; Providing a core for reverse reflow onto the solder paste; And reflowing the solder paste to form a solder layer on the core material for the reverse reflow. Here, the surface of the core material for reverse reflow can be a layer of gold (Au) or platinum (Pt).

At this time, the thickness of the layer of gold (Au) or platinum (Pt) may be about 0.01 탆 to about 0.3 탆. In addition, the step of reflowing the solder paste may be performed at a temperature of about 200 ° C to about 300 ° C.

The center displacement of the core material for reverse reflow before and after the step of reflowing the solder paste may be 5 탆 or less.

Also, in the step of reflowing the solder paste, the solder paste rises along the surface of the core material for reverse reflow soldering in the direction of gravity to form the solder layer.

Further, the thickness of the solder layer may become gradually thinner as it is away from the substrate.

According to a fourth aspect of the present invention, An input / output unit capable of inputting or outputting data; A memory unit capable of storing data; An interface unit capable of transmitting data with an external device; And a bus connecting the control unit, the input / output unit, the memory unit, and the interface unit so that they can communicate with each other. At least one of the control unit and the memory unit may include the semiconductor package described above.

INDUSTRIAL APPLICABILITY By using the core material for reverse reflow of the present invention, the semiconductor package and the manufacturing method of the semiconductor package of the present invention, it is possible to manufacture a semiconductor package with excellent bonding strength with high precision.

1 is a schematic view showing a cross section of a core material for reverse reflow according to an embodiment of the present invention.
2 is a flowchart illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.
3A to 3D are side cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.
4 is an enlarged view of a portion of FIG.
5 is a conceptual view illustrating a semiconductor interconnect according to another embodiment of the present invention.
6 is a side sectional view showing a semiconductor package according to another embodiment of the present invention.
7 is a partial cross-sectional perspective view showing a core for reverse reflow according to another embodiment of the present invention.
8A and 8B are side cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package to which the core for reverse reflow of FIG. 7 is applied according to another embodiment of the present invention.
9A and 9B are side cross-sectional views illustrating semiconductor interconnect portions according to various embodiments.
10 are images of the results obtained in Experimental Examples 8 to 13. FIG.
Fig. 11 shows images of the results obtained in Experimental Examples 14 to 19. Fig.
12 is a graph showing the displacement of the center of the core according to the reflow in the horizontal direction (X direction) and the vertical direction (Y direction), respectively, in respect of Experimental Examples 8 to 19. FIG.
13 are images showing the result of checking the interfacial compounds between core material and solder in gold-coated test examples 10, 11, 16 and 17.
14 is a plan view of a memory module including a semiconductor package according to the technical idea of the present invention.
15 is a schematic view of a memory card including a semiconductor package according to the technical idea of the present invention.
16 is a block diagram showing an example of a memory device including a semiconductor package according to the technical idea of the present invention.
17 is a block diagram showing an example of an electronic system including a semiconductor package according to the technical idea of the present invention.
18 is a block diagram illustrating a network implementation of a server system including an electronic device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the inventive concept may be modified in various other forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the inventive concept are desirably construed as providing a more complete understanding of the inventive concept to those skilled in the art. The same reference numerals denote the same elements at all times. Further, various elements and regions in the drawings are schematically drawn. Accordingly, the inventive concept is not limited by the relative size or spacing depicted in the accompanying drawings.

The terms first, second, etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and conversely, the second component may be referred to as a first component.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the expressions "comprising" or "having ", etc. are intended to specify the presence of stated features, integers, steps, operations, elements, parts, or combinations thereof, It is to be understood that the invention does not preclude the presence or addition of one or more other features, integers, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs, including technical terms and scientific terms. In addition, commonly used, predefined terms are to be interpreted as having a meaning consistent with what they mean in the context of the relevant art, and unless otherwise expressly defined, have an overly formal meaning It will be understood that it will not be interpreted.

1 is a schematic view showing a cross section of a core material 110 for reverse reflow according to an embodiment of the present invention.

1, the core material for reverse reflow 110 includes a core 111, a first metal layer 113 coated on the core 111, and a first metal layer 113 formed on the first metal layer 113 2 < / RTI > metal layer 115 as shown in FIG.

The core 111 may be made of a common metal or organic material, and may be formed of an organic / organic composite material or an organic / inorganic composite material.

For example, the core of the organic material may be a core of a plastic material, and the core of the plastic material may be an epoxy, melamine-formaldehyde, benzoguanamine-formaldehyde, divinylbenzene, divinyl ether, A plastic core including a thermosetting resin such as polydiacrylate and alkylene bisacrylamide resin, a plastic core including a thermoplastic resin such as polyvinyl chloride, polyethylene, polystyrene, nylon, and polyacetal resin, a natural rubber and a synthetic rubber And the like. And a plastic core formed of a resin mixed with a thermosetting resin and a thermoplastic resin.

On the other hand, a plastic material core can be formed using a polymer synthesis method. As an example, it may be formed to have a diameter of about 20 탆 to about 300 탆 by a synthesis method such as suspension, emulsification, dispersion polymerization and the like.

The metal core 111 may be made of, for example, pure copper (Cu), nickel (Ni), aluminum (Al), or an alloy thereof.

1, the core 111 has a spherical shape. However, the core 111 may have various shapes such as a columnar shape, a square columnar shape, a polygonal columnar shape, a conical shape, and a pyramidal shape.

A first metal layer 113 may be provided on the core 111. The first metal layer 113 may be formed directly on the core 111 or may be formed on the core 111 through another material layer.

The composition of the first metal layer 113 is not particularly limited and may be selected from the group consisting of Au, Ag, Ni, Zn, Sn, Al, Cr, (Co), and antimony (Sb). These may be used singly or in combination of two or more. For example, the first metal layer 113 may be formed by plating, physical vapor deposition, chemical vapor deposition, or the like. In particular, when the first metal layer 113 is formed by plating, it may be formed by, for example, performing electrolytic plating or electroless plating using nickel.

A brightener may be used to improve the roughness of the surface of the first metal layer 113 when the first metal layer 113 is formed. That is, by using a luster material, a first metal layer 113 having a more smooth surface can be obtained. The luster material includes, for example, an oxygen-containing organic compound such as a polyether compound such as polyethylene glycol; Nitrogen-containing organic compounds such as tertiary amine compounds and quaternary ammonium compounds; And / or a sulfur-containing organic compound having a sulfonate group, and the like.

The thickness of the first metal layer 113 may be between about 1 micrometer and about 5 micrometers. The first metal layer 113 may be formed of an intermetallic compound such as NiCu ₃ Sn ₄ , (Cu, Ni) ₆ Sn ₅ , or Ni ₃ Sn ₄ by reaction with a tin (Sn) .

A second metal layer 115 may be further formed on the surface of the first metal layer 113.

The second metal layer 115 may have a thickness of from about 0.01 microns to about 0.3 microns, or from about 0.1 microns to about 0.2 microns. If the thickness of the second metal layer 115 is too thin, the solder may not be formed over the entire surface when the core for reverse reflow is used for reflow later. If the thickness of the second metal layer 115 is too thick, it is economically disadvantageous. In addition, when the second metal layer 115 is used for reflow, the intermetallic compound such as AuSn ₄ reacts with the Sn- IMC) may be formed.

The second metal layer 115 may be, for example, gold (Au), platinum (Pt), or an alloy thereof. The second metal layer 115 can be easily mixed with the solder paste by heating. In addition, since the second metal layer 115 is a metal which is not easily oxidized, oxidation of the surface of the core material 110 for reverse reflow can be suppressed.

The second metal layer 115 may be formed by a method such as electrolytic plating, electroless plating, physical vapor deposition, or chemical vapor deposition. However, the present invention is not limited thereto.

The core material 110 for reverse reflow is not used as a solder bump per se, but can be part of a semiconductor interconnect by performing a reflow process together with a solder paste. This will be described in more detail below.

2 is a flowchart illustrating a method of manufacturing the semiconductor package 100 according to an embodiment of the present invention. 3A to 3D are side cross-sectional views sequentially illustrating a method of manufacturing the semiconductor package 100 according to an embodiment of the present invention.

Referring to FIGS. 2 and 3A, a semiconductor device 130 having a bump pad 132 is provided (S100). The semiconductor device 130 may include a substrate 134, a bump pad 132 formed on the surface of the substrate 134, and a semiconductor chip 136 mounted on the substrate 134.

The substrate 134 may be a printed circuit board (PCB). For example, the substrate 134 may be a rigid printed circuit board, a flexible printed circuit board, a tape substrate, or a rigid-flexible printed circuit board. Lt; / RTI >

When the substrate 134 is a printed circuit board, the substrate 134 may include a first resin layer and a second resin layer on an upper surface and a lower surface of the core board, respectively. The first resin layer and the second resin layer may each have a multilayer structure, and a signal layer, a ground layer, or a power supply layer may be interposed between the multilayer structures, and they may form a wiring pattern. In addition, a conductive wiring pattern may be formed on the first resin layer and / or the second resin layer. The conductive wiring pattern may be electrically connected to the semiconductor chip 136 and the bump pad 132.

The first resin layer and the second resin layer may be made of, for example, an epoxy resin, a urethane resin, a polyimide resin, an acrylic resin, a polyolefin resin, or the like.

The bump pad 132 may be a conductive pad, for example a metal pad. More specifically, the bump pad 132 may be, for example, a copper (Cu) pad, a nickel (Ni) pad, or a nickel plated aluminum (Al) pad. However, it is not limited thereto.

The semiconductor chip 136 may be a semiconductor substrate, for example, the semiconductor substrate may be a silicon (Si) substrate. In another embodiment of the present invention, the semiconductor substrate may be formed of a semiconductor element such as Ge (germanium) or a compound semiconductor such as SiC (silicon carbide), gallium arsenide (GaAs), indium arsenide (InAs) . In at least one embodiment, the semiconductor substrate may have a silicon on insulator (SOI) structure. For example, the semiconductor substrate may comprise a buried oxide layer.

Various semiconductor devices may be provided on the active surface of the semiconductor substrate. The semiconductor devices may include a memory device, a core circuit device, a peripheral circuit device, a logic circuit device, or a control circuit device. Examples of the memory device include volatile semiconductor memory devices such as DRAM, SRAM, and the like, for example, a flash memory, a phase-change RAM (PRAM), a resistive RAM (RRAM), a ferroelectric RAM (FeRAM) , Solid state magnetic RAM (MRAM), EPROM, EEPROM, Flash EEPROM, and the like. Alternatively, the active surface of the semiconductor substrate 222 may be provided with an image sensor such as a system LSI (large-scale integration), a CIS (CMOS imaging sensor), a micro-electro-mechanical system (MEMS) .

Optionally, the semiconductor device 130 may further include an encapsulant 138 to seal the semiconductor chip 136. The encapsulant 138 may be formed of, for example, an epoxy molding compound.

Referring to FIGS. 2 and 3B, the solder paste 120 may be dotted on the bump pad 132 (S200).

The solder paste 120 may be a mixture in which conductive metal powder is mixed with a liquid flux.

The conductive metal powder used for the solder paste 120 may be selected from the group consisting of tin (Sn), gold (Au), silver (Ag), platinum (Pt), copper (Cu), bismuth (Pd), Cr, Ca, Ni, Ge, Mn, Co, tungsten, antimony, Lead (Pb), and any alloy thereof. For example, the solder paste 120 may be a lead-containing solder alloy such as a Sn-Pb or Sn-Pb-Ag based alloy or a lead-free solder alloy such as a Sn-Ag based alloy, , A Sn-Zn alloy, a Sn-Sb alloy, or a Sn-Ag-Cu alloy. The solder paste 120 may contain at least 50%, at least 60%, or at least 90% Sn based on the total metal weight. When the metal powder has two or more metal components, they may be formed through an alloy. When the metal powder is obtained through an alloy, the metal powder may be substantially free of organic materials.

The flux may be a flux prepared by mixing components such as a solvent, rosin, a thixotropic agent, and an activator.

Examples of the solvent which can be used for the preparation of the flux include diethylene glycol monohexyl ether, diethylene glycol monobutyl ether, diethylene glycol monobutyl ether acetate, tetraethylene glycol, 2-ethyl-1,3- Hexanediol, and? -Terpineol, which have a boiling point of 180 ° C or higher.

The rosin may be gum rosin, hydrogenated rosin, polymerized rosin, ester rosin.

The thixotropic agent may be at least one selected from the group consisting of hardened castor oil, fatty acid amide, natural fat, synthetic fat, N, N'-ethylene bis-12-hydroxystearyl amide, 4-dibenzylidene-D-sorbitol and derivatives thereof.

In addition, the activator may be a hydrohalogenic acid amine salt, and specific examples thereof include triethanolamine, diphenylguanidine, ethanolamine, butylamine, aminopropanol, polyoxyethylene oleylamine, polyoxyethylene laurylamine, polyoxyethylene stearyl And examples thereof include aliphatic amines such as amine, diethylamine, triethylamine, methoxypropylamine, dimethylaminopropylamine, dibutylaminopropylamine, ethylhexylamine, ethoxypropylamine, ethylhexyloxypropylamine, bispropylamine, A hydrochloride of an amine such as isopropylamine, piperidine, 2,6-dimethylpiperidine, aniline, methylamine, ethylamine, 3-amino-1-propene, dimethylhexylamine, cyclohexylamine, It can be a salt.

However, the solvent, rosin, thixotropic agent, and activator are not limited to those listed here.

The flux can be obtained by mixing the components of the solvent, rosin, thixotropic agent, and activator in a predetermined ratio. The proportion of the solvent in the total flux amount of 100 mass% is, for example, about 30 to 60 mass%, the ratio of the thixotropic agent is about 1 to about 10 mass%, the ratio of the activator is about 0.1 to about 10 mass% can do.

If the content of the solvent is too low, the viscosity of the flux becomes excessively high, so that the viscosity of the solder paste using the solder paste increases, and the printed property may be lowered, such as lowering of the filling property of the solder or application unevenness . On the other hand, when the content of the solvent is too high, the viscosity of the flux becomes too low, so that the viscosity of the solder paste using the solder paste is also lowered, so that the solder powder and the flux component are separated by sedimentation.

If the content of the thixotropic agent is too low, the viscosity of the solder paste becomes too low, which may cause a problem that the solder powder and the flux component are separated by sedimentation. On the other hand, if the content of the thixotropic agent is too high, the viscosity of the solder paste becomes excessively high, which may cause a problem of poor printability such as solder filling property and uneven application.

If the proportion of the activator is too low, the solder powder is not melted and sufficient bonding strength can not be obtained. On the other hand, if the proportion of the activator is too high, the active agent tends to react with the solder powder during storage , The storage stability of the solder paste may deteriorate.

In addition, a viscosity stabilizer may be added to the flux. Examples of the viscosity stabilizer include polyphenols, phosphoric acid compounds, sulfur compounds, tocophenol, derivatives of tocopherol, arconvic acid and derivatives of arconvic acid which are soluble in a solvent. If the amount of the viscosity stabilizer is too large, there may be a problem such that the melting property of the solder powder is lowered. Therefore, the viscosity stabilizer may be 10 wt% or less based on the weight of the flux.

The mixing amount of the flux when preparing the solder paste may be an amount such that the proportion of the flux in 100 wt% of the paste after preparation is about 5 to about 30 wt%. If the content of the flux is too small, it becomes difficult to form a paste due to the lack of flux. On the other hand, if the content of the flux is too large, the content of the flux in the paste is excessively large and the content ratio of the metal becomes small, May be difficult to obtain.

The amount of soldering of the solder paste 120 is appropriately determined in consideration of the viscosity of the solder paste 120, the size of the bump pad 132, the size of the core material for reverse reflow disposed on the solder paste 120, Can be selected.

Referring to FIGS. 2 and 3C, the core material 110 for reverse reflow may be disposed on the solder paste 120 (S300).

The core material 110 for reverse reflow may be a core material for reverse reflow described with reference to FIG. The diameter of the core material 110 for the reverse reflow may be, for example, about 20 탆 to about 300 탆. However, the diameter of the core material 110 for the reverse reflow process is not limited thereto. Since the core material 110 for reverse reflow is described in detail with reference to FIG. 1, a further explanation will be omitted here.

Referring to FIGS. 2 and 3, the solder paste 120 may be reflowed to form a solder layer 120a on the core material 110 for reverse reflow (S400).

When the temperature of the solder paste 120 is raised, the solder paste 120 is melted to coat the surface of the core material 110 for reverse reflow. More specifically, the solder paste 120 melts and moves along the sidewalls of the core material for reverse reflow 110, thereby covering the entire surface of the core material 110 for reverse reflow.

Even if the solder paste 120 is positioned below the core material 110 for reverse reflow, the molten solder paste can rise along the surface of the core material 110 for reverse reflow while reversing the direction of gravity . At this time, since the viscosity of the molten solder paste 120 is considerably reduced, the core material 110 for the reverse reflow can move toward the substrate 134 more than when the molten solder paste 120 is first placed on the unmelted solder paste 120. Although not limited by a particular theory, it is contemplated that the movement of the core material 110 and the surface tension at the surface thereof, as well as the second metal layer and the solder paste 120 forming the surface of the core material 110 for reverse reflow, The solder paste 120 is assumed to rise in spite of gravity.

The reflow may be performed at a temperature of about 200 ° C to about 300 ° C, or at a temperature of about 230 ° C to about 260 ° C. The reflow may also be performed for about 20 seconds to about 100 seconds, or about 30 seconds to about 80 seconds.

In this manner, semiconductor interconnects 110 and 120a having a solder layer 120a on the bump pad 132 provided on the substrate 134 can be obtained.

Since the solder paste is mainly formed by an alloy other than plating, the solder paste may contain significantly less organic impurities than solder formed by plating. In other words, since a solder layer is formed on the periphery of a copper core by plating and used for packaging, a copper core solder ball (CCSB) using a conventional copper core is used as a byproduct Could be contained.

In this case, however, the solder paste is applied on the bump pad and the core is disposed thereon to reflow. Particularly, since the solder paste is mainly made of the alloy, not the plating, little or no unnecessary organic impurities are contained.

4 is an enlarged view of a portion of FIG.

Referring to FIG. 4, the thickness of the solder layer 120a formed on the surface of the core material for reverse reflow 110 may vary depending on the position. The thickness T1 of the solder layer 120a along the line extending in the direction parallel to the substrate 134 from the center of the core material 110 for the reverse reflow may be smaller than the thickness T1 of the core material 110 for the reverse reflow. May be greater than the thicknesses (T2, T3) of the solder layer (120a) along the line extending in the upper direction from the center of the solder layer (120a).

Particularly, in the solder layer 120a formed on the surface of the core material 110 for reverse reflow, the center of the core material for the reverse reflow is formed in the solder layer 120a along the line extending in the direction perpendicular to the substrate 134 And the thickness T3 of the solder layer 120a on the side away from the substrate 134 may be the thinnest.

In particular, the thickness of the solder layer 120a from the thickness T3 along a direction extension line perpendicular to the substrate 134 to the thickness T1 along a direction extension line that is horizontal to the substrate 134, . ≪ / RTI >

Although the core material 110 for reverse reflow is shown in direct contact with the bump pad 132 in FIG. 4, a solder layer (not shown) may be formed between the core material 110 for reverse reflow and the bump pad 132 120a may be interposed.

5 is a conceptual diagram illustrating a semiconductor interconnect 110a, 120a according to another embodiment of the present invention.

Referring to FIG. 5, the core 111 and the first metal layer 113 may be the same as the core material 110 for reverse reflow shown in FIG. Meanwhile, the second metal layer 115 of FIG. 1 may form an alloy with the solder layer 120a in the process of forming the solder layer 120a.

Since the second metal layer 115 in the core material 110 for reverse reflow shown in FIG. 1 has a thin thickness of about 0.1 μm to about 0.3 μm, the entire second metal layer 115 is dissolved together with the heating, To form an alloy with the metal layer 120a. In another embodiment, the second metal layer 115 may form an alloy with the solder layer 120a only for a portion of its thickness. In FIG. 5, the second metal layer 115 as a whole forms an alloy and / or an intermetallic compound with the solder layer 120a, but the present invention is not limited thereto.

When the second metal layer 115 forms an alloy with the solder layer 120a, the concentration of the second metal layer 115 gradually decreases as the distance from the surface of the core 111 increases.

In addition, a part or the whole of the first metal layer 113 may form an interfacial layer 116 by forming an intermetallic compound with the solder layer 120a. In some embodiments, the first metal layer 113 may partially form an intermetallic compound with the solder layer 120a. In some embodiments, the entire first metal layer 113 may form an intermetallic compound with the solder layer 120a. The solder layer 120a may be a tin (Sn) -based solder. In some embodiments, the intermetallic compound may comprise a component of the core 111. Particularly, when the entire first metal layer 113 forms an intermetallic compound with the solder layer 120a, the first metal layer 113 of FIG. 5 does not exist and the interface layer 116 directly contacts the surface of the core 111 Lt; / RTI >

The intermetallic compound may be at least one selected from the group consisting of, for example, NiCu ₃ Sn ₄ , (Cu, Ni) ₆ Sn ₅ , and Ni ₃ Sn ₄ , 113 and the solder layer 120a may be formed.

In the interfacial layer 116, an intermetallic compound of a component derived from the first metal layer 113 and a component derived from the solder layer 120a may be present. Furthermore, an alloy of the component derived from the second metal layer 115 and the component derived from the solder layer 120a may be present in the interface layer.

6 is a side cross-sectional view showing a semiconductor package 100a according to another embodiment of the present invention.

6, a semiconductor substrate 135 having a bump pad 132 is provided. The semiconductor substrate 135 may include an active surface 135a and an inactive surface 135b.

In an embodiment of the present invention, the semiconductor substrate 135 may be a silicon (Si) substrate. In another embodiment of the present invention, the semiconductor substrate 135 may be formed of a semiconductor material such as Ge (germanium), or a silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) Compound semiconductors. In at least one embodiment, the semiconductor substrate 135 may have a silicon on insulator (SOI) structure. For example, the semiconductor substrate 135 may include a buried oxide layer. In some embodiments, the semiconductor substrate 135 may include a conductive region, for example, a well doped with an impurity, or a structure doped with an impurity. In addition, the semiconductor substrate 135 may have various device isolation structures such as shallow trench isolation (STI) structures.

The active surface 135a of the semiconductor substrate 135 may be provided with various semiconductor devices. The semiconductor devices may include a memory device, a core circuit device, a peripheral circuit device, a logic circuit device, or a control circuit device. Examples of the memory device include volatile semiconductor memory devices such as DRAM, SRAM, and the like, for example, a flash memory, a phase-change RAM (PRAM), a resistive RAM (RRAM), a ferroelectric RAM (FeRAM) , Solid state magnetic RAM (MRAM), EPROM, EEPROM, Flash EEPROM, and the like. Alternatively, the active surface of the semiconductor substrate 135 may be provided with an image sensor such as a system LSI (large-scale integration), a CIS (CMOS imaging sensor), a micro-electro-mechanical system (MEMS) .

The active surface 135a of the semiconductor substrate 135 may be provided with a wiring layer on the semiconductor elements. The wiring layer may include a wiring pattern and an insulating layer. The wiring pattern may be electrically connected to the bump pad 132, which is an electrode terminal.

The core material 110 for reverse reflow and the solder layer 120a constituting the semiconductor interconnections 110 and 120a have been described in detail with reference to FIGS. 1 to 5, and a further explanation will be omitted here.

7 is a partial cross-sectional perspective view showing a core material 210 for reverse reflow according to another embodiment of the present invention.

7, the reverse reflow core material 210 includes a core 211, a first metal layer 213 coated on the core 211, and a second metal layer 213 formed on the first metal layer 213 And a second metal layer 215.

The core material 210 for the reverse reflow may have a diameter of about 20 mu m to about 300 mu m in the horizontal direction. The height of the core material 210 for reverse reflow may be about 50 탆 to about 1000 탆. However, the dimensions of the core material 210 for reverse reflow are not limited to these numerical ranges.

A first metal layer 213 is formed on the core 211 having a cylindrical shape and a substantially uniform thickness and a second metal layer 215 is formed on the first metal layer 213, May be formed to have a substantially constant thickness.

Since the materials of the core 211, the first metal layer 213, and the second metal layer 215 are described in detail with reference to FIG. 1, repeated description will be omitted here. The thicknesses of the first metal layer 213 and the second metal layer 215 have been described in detail with reference to FIG. 1, and a further explanation will be omitted here.

8A and 8B are side cross-sectional views sequentially illustrating a method of manufacturing a semiconductor package to which the core material 210 for reverse reflow of FIG. 7 is applied according to another embodiment of the present invention. Figs. 8A and 8B are cross-sectional views illustrating steps performed subsequent to the steps described with reference to Figs. 3A and 3B.

Referring to FIG. 8A, the core material 210 for reverse reflow may be disposed on the solder paste 120. The solder paste 120 has a somewhat fluidity because it is in a paste state, and therefore it is possible to arrange the core material 210 for a reverse reflow process having a columnar shape thereon as shown in FIG. 8A.

Since the core material 210 for reverse reflow is described in detail above with reference to FIG. 7, a further explanation will be omitted here.

Referring to FIG. 8B, the solder paste 120 may be reflowed to form a solder layer 120a on the surface of the core material 210 for reverse reflow.

Raising the temperature of the solder paste 120 of FIG. 8A causes the solder paste 120 to melt and at least partially coat the surface of the core material 210 for reverse reflow. More specifically, after the solder paste 120 is melted, the solder paste 120 rises on the sidewalls of the core material 210 for reverse reflow using the same principle as described with reference to FIG. 3D to form the core material 210 of the reverse reflow core. Thereby at least partially coating the surface.

However, if the aspect ratio (height / width) of the core material 210 for reverse reflow is large, the solder paste 120 may not reach the top of the core material 210 for reverse reflow. As described above, in the case of the core material 210 for reverse reflow shown in FIG. 7, the behavior of the solder paste 120 can be seen in a more various manner than the core material 110 for reverse reflow shown in FIG. This will be described later in more detail with reference to Figs. 9A and 9B.

8B, as the viscosity of the solder paste 120 is lowered by reflow, the core material 210 for reverse reflow can move toward the substrate 134 more than in FIG. 8A due to gravity. Since the above-described reflow condition has been described in detail with reference to FIG. 3D, further explanation is omitted here.

Thus, semiconductor interconnects 210 and 120a having a layer of solder layer 120a on the bump pad 132 provided on the substrate 134 can be obtained.

FIGS. 9A and 9B are side cross-sectional views illustrating portions of a semiconductor interconnect 210, 120a in accordance with various embodiments.

Referring to FIG. 9A, the solder layer 120a may be formed along the sidewalls of the core material 210a for reverse reflow, and may have a varying thickness depending on the position. More specifically, the solder layer 120a may have a thinner thickness along the sidewalls of the core material 210a for reverse reflow.

The solder layer 120a may not coat the entire surface of the core material 210a for reverse reflow. This may be due to the large aspect ratio or height of the core material 210a for reverse reflow. For example, when the reflowed solder layer 120a rises along the sidewalls, the solder layer 120a may have a certain level depending on the composition and amount of the solder layer 120a, the reflow temperature, the dimensions of the core material 210a for reverse reflow, It is possible to rise only to the height of

At this time, the second metal layer 215 (see FIG. 7) of the core material 210a for reverse reflow may react with the solder layer 120a to form the intermetallic compound layer 216. As a result, the core material 210a for reverse reflow after reflow can be made of the core 211a and the first metal layer 213. [

Although the core material 210a for reverse reflow is shown in direct contact with the bump pad 132 in FIG. 9A, a solder layer (not shown) may be formed between the core material 210a for reverse reflow and the bump pad 132 120a may be at least partially interposed.

9A, when the solder layer 120a does not coat the upper surface of the core material 210a for reverse reflow, the terminal (not shown) of the other substrate (not shown) to be electrically connected to the substrate 134 For example, a bump pad may further include connecting means such as solder paste.

9B differs from FIG. 9A in that the solder layer 120b is coated to the upper surface of the reverse reflow core material 210b.

The solder layer 120b is formed on the upper surface of the reverse reflow core material 210b in accordance with the conditions such as the composition and amount of the solder paste 120b, the reflow temperature, the dimensions of the core material 210b for reverse reflow, Can be coated. For example, if the reflow temperature is high, there is a high possibility that the viscosity of the solder paste 120b is reduced and the wettability is improved to coat the upper surface. Also, if the amount of the solder paste 120b is large, and if the viscosity is low, there is a high possibility that the solder paste 120b will be coated to the upper surface. If the diameter of the core material 210b for reverse reflow, that is, the diameter and / or height of the core material 210b for reverse reflow is small, there is a high possibility of coating the upper surface.

The intermetallic compound layer 216 may be formed at the interface between the solder layer 120b and the core material 210b for reverse reflow as shown in FIG. 9B. The intermetallic compound layer 216 may be formed by reacting the second metal layer 215 (see FIG. 7) and the solder layer 120b. As a result, the core material 210b for reverse reflow after reflow can be made of the core 211b and the first metal layer 213. [

Hereinafter, the constitution and effects of the present invention will be described in more detail with reference to specific experimental examples and comparative examples. However, these experimental examples are only intended to clarify the present invention and are not intended to limit the scope of the present invention.

<Experimental Example 1>

A copper core having a diameter of 184 mu m was prepared, and a degreasing process and a pickling process were performed to remove organic substances and oxide films present on the surface.

<Experimental Examples 2 to 7>

A copper core having a diameter of 180 mu m was prepared, and a degreasing process and a pickling process were performed to remove organic substances and oxide films existing on the surface. A Ni plating solution of sulfonic acid series was used and a current was applied at a current density of about 0.5 to about 1 ASD (amperes per square decimeter) to form a Ni layer having a thickness of 2 탆.

Then, a layer of gold (Au) or palladium (Pd) was formed to have an appropriate thickness as shown in Table 1 below (Experimental Examples 3 to 6). (Sn) - (3% Ag) - (0.5% Cu) (hereinafter referred to as "SAC") was formed on the copper core as shown in Table 1 below (Experimental Example 7).

The samples of Experimental Examples 1 to 7 were allowed to stand in an oven in an air atmosphere at 120 占 폚 for 48 hours to agitate and to confirm the illuminance on the surface. Changes in illuminance values were measured using a MINOLTA CR-400 colorimeter.

As a result, in Experimental Examples 1 and 7, a considerable reduction in the illuminance was observed, and in Experimental Example 2, a slight decrease in illuminance was also observed. This means that the oxidation of the surface was inhibited by surface treatment of gold (Au) or palladium (Pd) in Experimental Examples 3 to 6, and it was interpreted that Experimental Examples 1, 2 and 7 showed significant or slight surface oxidation .

It was also observed that the color of the surface was discolored in proportion to the degree of oxidation. In other words, it was observed that the samples of Experimental Examples 3 to 7 kept the surface color before and after aging, but the samples of Experimental Examples 1, 2 and 7 showed a slight change in the surface color before and after aging.

<Experimental Examples 8 to 13>

Wetting characteristics with the solder paste were examined for the samples before aging in Experimental Examples 1 to 6. To this end, SAC305 paste was applied uniformly to metal pads of a Cu-OSP (Organic Solderability Preservative) PCB using a mask having a thickness of 100 mu m and patterned with a diameter of 200 mu m, and the samples of Experimental Examples 1 to 6 were placed thereon And then a reflow process was carried out. The reflow was carried out at 245 DEG C for 50 seconds.

<Experimental Examples 14 to 19>

The wetting characteristics with the solder paste were examined in the same manner as in Experimental Examples 8 to 13 with respect to the samples after aging in Experimental Examples 1 to 6.

10 are images of the results obtained in Experimental Examples 8 to 13. FIG. Referring to FIG. 10, in the case of Experimental Examples 8, 12, and 13, it can be seen that the core material is partially exposed. From this, it seems that the wettability between the melted solder and the core material in the reflow process is not good.

In Experimental Examples 9, 10, and 11, it can be seen that the core material is not exposed and the solder forms a solder layer well over the entire surface of the core material. From this, it is judged that the wettability between solder and nickel, or between solder and gold is good.

Fig. 11 shows images of the results obtained in Experimental Examples 14 to 19. Fig. Referring to FIG. 11, it can be seen that the core material is considerably exposed in Experimental Example 15, but in Experimental Example 9, which was not aged, a solder layer is well formed over the entire surface of the core material. From this, it can be seen that the wettability between the nickel surface and the solder is deteriorated by the oxidation in aging.

On the other hand, in Examples 16 and 17 in which gold (Au) was coated, it was confirmed that the solder layer still formed well over the entire surface of the core. From this, it is judged that the gold coating layer has strong oxidation resistance.

In Examples 18 and 19 coated with palladium (Pd), no change in roughness was observed before and after aging, but the wettability between the melted solder and the palladium (Pd) surface was not as good as before aging.

From the above, it can be seen that when gold (Au) is coated as the second metal layer, stable wettability with the solder is exhibited even in long-term storage.

12 is a graph showing the displacement of the center of the core according to reflow in the horizontal direction (X direction) and the vertical direction (Y direction), respectively, for Experimental Examples 8 to 19. FIG. The core displacement was measured by performing image analysis on the position of the core before and after the reflow.

Referring to FIG. 12, the phenomenon of the core material floating in Experimental Examples 15, 18, and 19 was largely observed. In Experiments 8 and 14, the degree is somewhat weak. However, it can be seen that the core material moves about 10 占 퐉 horizontally and vertically in the reflow process.

On the other hand, it can be seen that the samples of Experimental Examples 10, 11, 16, and 17 migrate only to an extremely small extent, and move to approximately 5 탆 or less.

Therefore, when gold (Au) is coated as the second metal layer, the centering property can be assured because the position of the core is hardly changed during the reflow process.

13 are images showing the result of checking the interfacial compounds between core material and solder in gold-coated test examples 10, 11, 16 and 17.

Referring to FIG. 13, it was observed that in Experiment 11 in which aging was not performed, an intermetallic compound of AuSn ₄ was produced. Since the intermetallic compound of AuSn ₄ may have high brittleness, it may not be desirable to have the second metal layer have a thickness greater than 0.3 탆.

&Lt; Measurement of bonding strength &

Bond strength measurements were performed on the samples of Experimental Examples 7 to 13 to measure the bond strength.

For Experimental Examples 8 to 13, a force at a distance of 10 占 퐉 and a distance of 80 占 퐉 from the PCB was applied in the horizontal direction, and the force at the time when fracture started to take place was adopted as the bonding strength.

The sample of Experimental Example 7 was bonded to a PCB substrate having corresponding bump pads, and the bonding strength was measured in the same manner as Experimental Examples 8 to 13.

In each case, when the force is applied on the PCB side (10 탆 height), the bonding characteristics of the interface between the bump pad and the solder are mainly involved, and when the force is applied on the core side (80 탆 height) Characteristics are mainly involved.

The measured results are summarized in Table 2 below.

As shown in Table 2, the solder balls with a conventional copper core material in the experimental example 7-9, with (copper core solder ball, CCSB) showed poor bond strength of approximately 150 g _f or less. For the Experimental Example 12 and 13 coated with the palladium it has showed a slightly elevated bonding strength of around 170 g _f.

For the Experimental Example 10 and 11 coated with the gold (Au) There was obtained a remarkably improved bond strength in excess of 200 g _f.

14 is a plan view of a memory module 1000 including a semiconductor package according to the technical idea of the present invention.

In particular, the memory module 1000 may include a printed circuit board 1100 and a plurality of semiconductor packages 1200.

The plurality of semiconductor packages 1200 may be or include a semiconductor package according to embodiments of the present invention. In particular, the plurality of semiconductor packages 1200 may include at least one semiconductor package selected from semiconductor packages according to the above-described technical idea of the present invention.

The memory module 1000 according to the technical idea of the present invention may be a single in-line memory module (SIMM) in which a plurality of semiconductor packages 1200 are mounted on only one side of a printed circuit board or a plurality of semiconductor packages 1200, Or a dual in-line memory module (DIMM). In addition, the memory module 1000 according to the technical idea of the present invention may be a fully buffered DIMM (FBDIMM) having an advanced memory buffer (AMB) that provides signals from the outside to the plurality of semiconductor packages 1200, respectively.

15 is a schematic view of a memory card 2000 including a semiconductor package according to the technical idea of the present invention.

Specifically, the memory card 2000 can be arranged such that the controller 2100 and the memory 2200 exchange electrical signals. For example, if the controller 2100 issues a command, the memory 2200 can transmit data.

The memory 2200 may include a semiconductor package according to embodiments of the present invention. In particular, the memory 2200 may include a structure of at least one semiconductor package selected from the semiconductor packages according to the above-described embodiments of the technical concept of the present invention.

The memory card 2000 may include various types of cards such as a memory stick card, a smart media card (SM), a secure digital card (SD), a mini-secure digital card a mini-secure digital card (mini SD), and a multimedia card (MMC).

16 is a block diagram showing an example of a memory device 3200 including a semiconductor package according to the technical idea of the present invention.

Referring to FIG. 16, a memory device 3200 in accordance with an embodiment of the present invention includes a memory module 3210. The memory module 3210 may include at least one of the semiconductor packages disclosed in the above-described embodiments. In addition, the memory module 3210 may further include other types of semiconductor memory elements (e.g., nonvolatile memory and / or an Slam device). The memory device 3200 may include a memory controller 3220 that controls the exchange of data between the host and the memory module 3210.

The memory controller 3220 may include a processing unit 3222 for controlling the overall operation of the memory card. In addition, the memory controller 3220 may include an SRAM 3221 used as an operation memory of the processing unit 3222. In addition, the memory controller 3220 may further include a host interface 3223 and a memory interface 3225. The host interface 3223 may include a data exchange protocol between the memory device 3200 and a host. The memory interface 3225 can connect the memory controller 3220 and the storage device 3210. Further, the memory controller 3220 may further include an error correction block 3224 (ECC). The error correction block 3224 can detect and correct errors in data read from the memory module 3210. Although not shown, the memory device 3200 may further include a ROM device for storing code data for interfacing with a host. The memory device 3200 may be implemented as a solid state drive (SSD) capable of replacing a hard disk of a computer system.

17 is a block diagram showing an example of an electronic system 4100 including a semiconductor package according to the technical idea of the present invention.

17, an electronic system 4100 according to one embodiment of the present invention includes a controller 4110, an input / output device 4120, a memory device 4130, an interface 4140, (4150, bus). The controller 4110, the input / output device 4120, the memory device 4130 and / or the interface 4140 may be coupled to each other via the bus 4150. The bus 4150 corresponds to a path through which data is moved.

The controller 4110 may include at least one of a microprocessor, a digital signal process, a microcontroller, and logic elements capable of performing similar functions. The input / output device 4120 may include a keypad, a keyboard, a display device, and the like. The memory device 4130 may store data and / or commands and the like. The memory device 4130 may include at least one of the semiconductor packages disclosed in the embodiments described above. In addition, the memory device 4130 may further include other types of semiconductor memory devices (e.g., non-volatile memory devices and / or Slam devices). The interface 4140 may perform functions to transmit data to or receive data from a communication network. The interface 4140 may be in wired or wireless form. For example, the interface 4140 may include an antenna or a wired or wireless transceiver. Although not shown, the electronic system 4100 is an operation memory device for improving the operation of the controller 4110, and may further include a high-speed DRAM device and / or an SLAM device.

The electronic system 4100 may be a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player a digital music player, a memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

18 is a block diagram illustrating a network implementation of a server system including an electronic device according to an embodiment of the present invention.

Referring to FIG. 18, a network system 5000 according to an embodiment of the present invention may include a server system 5100 and a plurality of terminals 5300, 5400, and 5500 connected through a network 5200. A server system 5100 according to an embodiment of the present invention includes a server 5110 that processes requests received from a plurality of terminals 5300, 5400 and 5500 connected to a network 5200 and terminals 5300, 5400, 5500 And an electronic device 5120 for storing data corresponding to a request received from the plurality of devices. At this time, the electronic device 5120 can be applied to the semiconductor package according to the embodiment of the present invention shown in Figs. 4 to 6, for example. The electronic device 5120 may be, for example, a solid state disk (SSD).

Meanwhile, the above-described electronic device according to the present invention can be mounted using various types of packages. For example, the electronic device according to the present invention can be used as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC) Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic MetricQuad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package WSP), and the like.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The present invention may be modified in various ways. Therefore, modifications of the embodiments of the present invention will not depart from the scope of the present invention.

The present invention can be usefully used in the semiconductor industry.

110: reverse reflow core material 111: core
113: first metal layer 115: second metal layer
120: solder paste 120a: solder layer
132: bump pad 134: substrate
136: Semiconductor chip

Claims (8)

A core;
A first metal layer coated over the core; And
A second metal layer coated on the first metal layer;
/ RTI &gt;
Wherein the first metal layer is nickel (Ni) or cobalt (Co)
Wherein the second metal layer is gold (Au) or platinum (Pt)
Wherein the thickness of the second metal layer is from 0.01 mu m to 0.3 mu m,
And a solder layer is not provided on the surface of the second metal layer. Providing a substrate having a bump pad;
Dipping a solder paste on the bump pad;
Providing a core for reverse reflow onto the solder paste; And
Reflowing the solder paste to form a solder layer on at least the entire side of the core for reverse reflow soldering;
Lt; / RTI &gt;
Wherein the surface of the core material for reverse reflow is a layer of gold (Au) or platinum (Pt). 3. The method of claim 2,
Wherein the thickness of the gold (Au) layer or the platinum (Pt) layer is 0.1 占 퐉 to 0.3 占 퐉. 3. The method of claim 2,
Wherein the step of reflowing the solder paste is performed at a temperature of 200 ° C to 300 ° C. 3. The method of claim 2,
Wherein the displacement of the center of the core material for reverse reflow before and after reflowing the solder paste is 0 占 퐉 or more and 5 占 퐉 or less. 3. The method of claim 2,
Wherein the step of reflowing the solder paste forms the solder layer by raising the direction of gravity along the surface of the core material for reverse reflow soldering. The method according to claim 6,
And the thickness of the solder layer gradually becomes thinner as the distance from the substrate increases. 3. The method of claim 2,
Wherein the core material for reverse reflow is a cylindrical shape,
Wherein the solder layer has a concave surface profile at the side of the core for reverse reflow.

Images