KR20170064626A - Nonvolatile memory moduel - Google Patents

Abstract

A nonvolatile memory module according to the present invention is a nonvolatile memory, a cache memory of a nonvolatile memory, and includes a volatile memory including tag information for stored data, a controller configured to control the nonvolatile memory, And a module controller responsive to the received command address to transmit the first command and address to the volatile memory via the first bus and to provide the second command and address to the controller via the second bus.

Description

[0001] NONVOLATILE MEMORY MODULE [0002]

The present invention relates to a semiconductor memory, and more particularly, to a nonvolatile memory module.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP) to be. Semiconductor memory devices are classified into a volatile memory device and a nonvolatile memory device.

The volatile memory device is a memory device in which data stored in the volatile memory device is lost when power supply is interrupted. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A nonvolatile memory device is a memory device that retains data that has been stored even when power is turned off. A nonvolatile memory device includes a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Electrically Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), a flash memory device, a PRAM ), RRAM (Resistive RAM), and FRAM (Ferroelectric RAM).

In particular, since DRAM has a fast response speed and a high operation speed, it is widely used as a main memory of the system. However, since the DRAM is a volatile memory in which data is lost when the power supply is interrupted, a separate device is required to store the data stored in the DRAM. Also, because the DRAM stores data using a capacitor, the size of the unit cell is large, which makes it difficult to increase the DRAM capacity in a limited area.

An object of the present invention is to provide a nonvolatile memory module having a large capacity and a high performance by using a nonvolatile memory and a volatile memory.

A nonvolatile memory module according to an embodiment of the present invention includes a nonvolatile memory, a cache memory of the nonvolatile memory, and includes a volatile memory including tag information on stored data, a controller configured to control the nonvolatile memory, Receiving a command and an address from an external device and sending a first command and address to the volatile memory via a first bus in response to the received command address and sending a second command and address to the controller via a second bus, And a module controller.

In an embodiment, the tag information includes at least a part of addresses received from the external apparatus.

In an embodiment, the volatile memory includes a plurality of volatile memory chips, at least one of the plurality of volatile memory chips is a tag-dedicated volatile memory chip storing the tag information, and the remainder stores data .

As an embodiment, it further includes a tag control circuit sharing the tag data line with the volatile memory.

In an embodiment, the tag control circuit receives the tag via the tag data line, receives the address from the module controller, and compares at least a portion of the received address with the tag to determine a cache hit or cache miss And outputs the cache information.

In an embodiment, the tag control circuit drives the voltage of the tag data line based on at least a part of the addresses received from the external device, and transmits the tag information to the volatile memory.

In an embodiment, the non-volatile memory includes a NAND flash memory, and the volatile memory includes a dynamic random access memory (DRAM).

A nonvolatile memory module according to an embodiment of the present invention includes a first memory, a second memory that is a cache memory of the first memory, a third memory that stores tag information of data stored in the second memory, And a controller configured to receive a command and an address from an external device and to transmit a first command and an address to the controller via a first bus in response to the received command address, And a module controller for providing a second command and address to the second memory.

A memory system according to an embodiment of the present invention includes a first memory, a second memory that is a cache memory of the first memory, a second memory that shares a data bus with the first memory and the second memory, And a memory controller configured to control the second memories, wherein the second memory includes a tag only memory configured to store a tag for data stored in the second memory.

In an embodiment, the tag dedicated memory of the second memory outputs the tag through the data bus under the control of the memory controller.

In an embodiment, the memory controller receives the tag via the data bus, and determines a cache hit or a cache miss based on the received tag.

In an embodiment, the second memory is configured to output cache information based on a tag stored in the tag dedicated memory.

According to the present invention, there is provided a nonvolatile memory module having a large capacity and a high performance by using a nonvolatile memory and a volatile memory. A non-volatile memory module is used as the main memory of the system, thereby providing a non-volatile memory module with improved performance and reduced cost.

1 is a block diagram illustrating an exemplary user system in accordance with an embodiment of the present invention.
2 is a detailed block diagram of the nonvolatile memory module of FIG.
3 is a flowchart showing a write operation of the nonvolatile memory module of FIG.
4 is a timing diagram for explaining the operation method of FIG. 3 in detail.
5 is a flowchart showing a read operation of the nonvolatile memory module 100 of FIG.
6 is a timing chart for explaining the read operation of FIG. 5 in detail.
FIG. 7 is a flowchart showing another read operation of the nonvolatile memory module 100 of FIG.
8 is a timing chart for explaining the read operation of FIG. 7 in detail.
FIG. 9 is a diagram for explaining the cache structure of the volatile memory of FIG. 2. FIG.
FIG. 10 is a diagram for explaining the tag of FIG. 9 in detail.
FIG. 11 is a diagram for explaining a tag management method of the nonvolatile memory module of FIG. 2. FIG.
12 is a diagram for explaining a tag management method of the nonvolatile memory module of FIG.
13 is a timing chart for explaining a tag transmission method of the nonvolatile memory modules shown in FIG. 11 and FIG.
14 is a block diagram showing another example of the nonvolatile memory module of FIG.
15 is a block diagram showing another example of the nonvolatile memory module of FIG.
16 is a block diagram showing another example of the nonvolatile memory module of FIG.
17 is a diagram for explaining a tag according to another embodiment of the present invention in detail.
18 is a flowchart for explaining an operation method of the nonvolatile memory module of FIG.
19 is a flowchart for explaining another operation method of the nonvolatile memory module of FIG.
20 is a block diagram showing another example of the nonvolatile memory module of FIG.
FIG. 21 is a block diagram showing another example of the nonvolatile memory module of FIG. 2. FIG.
22 is a block diagram showing another example of the nonvolatile memory module of FIG.
23 is a block diagram exemplarily showing a nonvolatile memory included in the nonvolatile memory module according to the present invention.
24 is a circuit diagram illustrating a first memory block among the memory blocks included in the nonvolatile memory of the nonvolatile memory module according to the present invention.
25 is a block diagram illustrating an exemplary volatile memory of a non-volatile memory module according to the present invention.
26 is a diagram illustrating a server system to which a non-volatile memory module according to the present invention is applied.
27 is a block diagram illustrating an example of a user system to which a nonvolatile memory module according to the present invention is applied.

In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, details such as detailed configurations and structures are provided merely to assist in an overall understanding of embodiments of the present invention. Modifications of the embodiments described herein may be made by those skilled in the art without departing from the spirit and scope of the invention. Moreover, descriptions of well-known functions and structures are omitted for clarity and brevity. The terms used in the present specification are defined in consideration of the functions of the present invention and are not limited to specific functions. Definitions of terms may be determined based on the description in the detailed description.

Modules in the following figures or detailed description may be shown in the drawings or may be connected to others in addition to the components described in the detailed description. The connections between the modules or components may be direct or non-direct, respectively. The connections between the modules or components may be a communication connection or a physical connection, respectively.

The components described with reference to terms such as a unit or a unit, a module, a layer or the like used in the detailed description may be implemented in the form of software, hardware, or a combination thereof. Illustratively, the software may be machine code, firmware, embedded code, and application software. For example, the hardware may include electrical circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive components, .

Unless defined otherwise, all terms including technical and scientific meanings used herein have the meaning as understood by one of ordinary skill in the art to which this invention belongs. Generally, terms defined in the dictionary are interpreted to have equivalent meaning to the contextual meanings in the related art and are not to be construed as having ideal or overly formal meaning unless expressly defined in the text.

In the following, the present invention will be described on the basis of specific embodiments for convenience of description, but the scope of the present invention is not limited thereto, and various embodiments may be implemented or a combination of various embodiments may be implemented have.

1 is a block diagram illustrating an exemplary user system in accordance with an embodiment of the present invention. 1, a user system 10 includes non-volatile memory modules 100, a processor 101, a chipset 102, a graphics processing unit 103, an input / output device 104, a storage device 105 . Illustratively, the user system 10 may be a computing system such as a computer, a laptop, a server, a workstation, a handheld communication terminal, a PDA (Personal Digital Assistant), a Portable Media Player (PMP), a smart phone, or a wearable device Lt; / RTI >

The user system 10 includes a nonvolatile memory module 100, a processor 101, a chipset 102, a graphics processing unit 103, an input / output device 104, and a storage device 105.

The processor 101 may control all operations of the user system 100. The processor 101 may perform various operations performed on the user system 100 and process the data.

The non-volatile memory module 100 may be directly coupled to the processor 101. For example, the non-volatile memory module 100 may be in the form of a dual in-line memory module (DIMM), and the non-volatile memory module 100 may be directly coupled to the processor 101 DIMM socket and can communicate with the processor 101. < RTI ID = 0.0 > Illustratively, the non-volatile memory module 100 may communicate with the processor 101 based on the NVDIMM protocol.

The non-volatile memory module 100 may be used as the main memory or the working memory of the processor 101. [ The non-volatile memory module 100 may include a non-volatile memory and a volatile memory. The non-volatile memory may be a ROM, a PROM, an EPROM, an EEPROM, a flash memory, a phase-change RAM (PRAM), a magnetic RAM (MRAM) RRAM (Resistive RAM), FRAM (Ferroelectric RAM), and the like. The volatile memory may include a memory such as a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), or the like.

The nonvolatile memory of the nonvolatile memory module 100 is used as the main memory of the user system 10 or the processor 101 and the volatile memory is used as the main memory of the user system 10, Or as a cache memory of the non-volatile memory module 100. [

The chipset 102 is electrically connected to the processor 101 and can control the hardware of the user system 10 under the control of the processor 101. [ For example, the chipset 102 may be connected to the GPU 103, the input / output device 104, and the storage device 105 via the main buses, respectively, and may serve as a bridge to the main buses.

The GPU 103 may perform a series of arithmetic operations to output image data of the user system 10. [ Illustratively, the GPU 103 may be implemented in the processor 101 in a system-on-chip form.

The input / output device 104 includes various devices that input data or instructions to the user system 10 or output data to the outside. For example, the input / output device 104 may be a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, User input devices and user output devices such as a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display, an AMOLED (Active Matrix OLED) display, an LED, a speaker,

The storage device 105 may be used as a mass storage medium of the user system 10. Storage device 105 may include mass storage media such as hard disk drives, SSDs, memory cards, memory sticks, and the like.

2 is a detailed block diagram of the nonvolatile memory module of FIG. 1 and 2, a nonvolatile memory module 100 includes a module controller 110, a heterogeneous memory device 120, a data buffer 130, and a serial presence detection chip 140 (SPD chip; Serial Presence Detect chip.

The module controller 110 may receive the command / address CA from the processor 101 and control the disparate memory device 120 in response to the received command / address CA. For example, the module controller 110 may provide a command / address CA_n and a command / address CA_v to the disparate memory device 120 in response to a command / address CA from the processor 101 .

Illustratively, the command / address CA_n is a command / address for controlling the nonvolatile memory 123 included in the heterogeneous memory device 120, and the command / address CA_v is included in the heterogeneous memory device 120 / RTI > command / address for controlling the volatile memory < RTI ID = 0.0 > 121 < / RTI &

Hereinafter, for the sake of brevity, the command / address CA provided from the processor 101 is referred to as a 'module command / address', and a command / address CA_v provided from the module controller 110 to the volatile memory 121 And a command / address CA_n provided from the module controller 110 to the NVM controller 122 is referred to as a NVM (command for nonvolatile memory) command / address.

Illustratively, it may be provided via a different command / address bus with the NVM command / address CA_n and the VM command / address CA_v.

By way of example, the module controller may be an RCD (Register Clock Driver)

The heterogeneous memory device 120 includes a volatile memory 121, a non-volatile memory controller 122 (NVM controller), and a non-volatile memory 123. The volatile memory 121 may operate in response to the VM command / address CA_v from the module controller 110. The volatile memory 121 can output the data and the tag TAG through the memory data line MDQ and the tag data line TDQ in response to the VM command / address CA_v, respectively. The volatile memory 121 can write the data and the tag respectively received via the memory data line MDQ and the tag data line TDQ according to the VM command / address CA_v.

The NVM controller 122 may operate in response to an NVM command / address (CA_n) from the module controller 110. For example, the NVM controller 122 may program the data received via the memory data line (MDQ) to the nonvolatile memory 123, or may be programmed into the nonvolatile memory 123 according to the NVM command / address (CA_n) from the module controller 110 The data programmed in the volatile memory 123 can be output through the memory data line MDQ.

The NVM controller 122 may perform various operations for controlling the non-volatile memory 123. [ For example, the NVM controller 122 may perform operations such as garbage collection, wear leveling, address translation, etc. to efficiently use the non-volatile memory 123. Illustratively, the NVM controller 122 may further include components such as error correction circuitry, a renderer, and the like.

Illustratively, volatile memory 121 and NVM controller 122 may share the same memory data line (MDQ).

Illustratively, volatile memory 121 and module controller 110 may share tag data lines (TDQ) with one another. Or the volatile memory 121, the NVM controller 122 and the module controller 110 may share the tag data line TDQ with each other. The NVM controller 122 may output the tag (TAG) through the tag data line (TDQ).

The data buffer 130 may receive data via the memory data line MDQ and provide the received data to the processor 101 via the data line DQ. Or the data buffer 130 may receive data through the data line DQ and output the received data through the memory data line MDQ. Illustratively, the data buffer 130 may operate in response to control of the module controller 110 (e.g., a buffer command (not shown)). Illustratively, the data buffer 130 may serve to distinguish between a signal on the memory data line MDQ and a signal on the data line DQ. Or the data buffer 130 may serve to block signals between the memory data line MDQ and the data line DQ. That is, if the signal of the memory data line MDQ does not affect the data line DQ by the data buffer 130 or if the signal of the data line DQ is supplied to the memory data line MDQ by the data buffer 130, It may not affect the signal of FIG.

Illustratively, the memory data line MDQ may be a data transmission path between the components (e.g., volatile memory, nonvolatile memory, data buffer, etc.) included in the non-volatile memory module 100, The line DQ may be a data transmission path between the nonvolatile memory module 100 and the processor 101. [ The tag data line (TDQ) may be a transmission path for transmitting and receiving a tag (TAG).

Illustratively, each of the memory data line MDQ, the data line DQ, and the tag data line TDQ may include a plurality of wirings. Each of the memory data line MDQ, the data line DQ and the tag data line TDQ is connected to the memory data strobe line MDQS, the data strobe line DQS, and the tag data line TDQ, And a strobe line (TDQS). Hereinafter, in order to simplify the drawing, reference numerals and configurations of the data strobe line MDQS, the data strobe line DQS, and the tag data strobe line TDQS are omitted. However, the scope of the present invention is not limited thereto, and the components connected to the memory data line MDQ, the data line DQ, and the tag data line TDQ may be a data strobe line MDQS, a data strobe line DQS ), And a tag data strobe line (TDQS) in synchronism with each other.

SPD 140 may be an electrically erasable programmable read-only memory (EEPROM). SPD 140 may include initial information or device information DI of non-volatile memory module 100. Illustratively, SPD 140 may include device information DI such as module type, module configuration, storage capacity, module type, execution environment, etc. of non-volatile memory module 100. When the user system 10 including the nonvolatile memory module 100 is booted, the processor 101 reads the device information DI from the SPD 140 and recognizes the nonvolatile memory module 100 based on the information can do. The processor 101 may control the nonvolatile memory module 100 based on the device information DI read from the SPD 140. [

Hereinafter, for the sake of brevity, it is assumed that the volatile memory 121 is a DRAM, and the nonvolatile memory 123 is a NAND flash memory. However, the scope of the present invention is not so limited, and the volatile memory 121 may include other types of random access memory, and the non-volatile memory 123 may include other types of non-volatile memory devices .

Illustratively, the volatile memory 121 may include a plurality of volatile memory chips, and each volatile memory chip may be implemented as a separate chip, a separate package, or the like. Each volatile memory chip may be connected to the module controller 110 or the NVM controller 122 via different memory data lines or tag data lines.

Illustratively, the processor 101 can use the nonvolatile memory 123 of the nonvolatile memory module 100 as a main memory. That is, the processor 101 can recognize the storage space of the nonvolatile memory 123 as a main memory area. The volatile memory 121 may operate as a cache memory of the processor 101 and the nonvolatile memory 123. [ Illustratively, volatile memory 121 may be used as a write-back cache. That is, in response to the module command / address CA from the processor 101, the module controller 110 determines a cache hit or a cache miss, and judges whether the cache hit or the cache miss has occurred in the volatile memory 121 or the nonvolatile memory 123 Can be controlled.

 Illustratively, the cache hit indicates a case where data corresponding to the module command / address (CA) received from the processor 101 is stored in the volatile memory 121. [ The cache miss indicates a case where data corresponding to the module command / address (CA) received from the processor 101 is not stored in the volatile memory 121.

Illustratively, the module controller 110 may determine whether to cache hits or cache miss based on the tag (TAG). The module controller 110 can determine whether a cache hit or a cache miss by comparing the module command / address CA and the tag TAG received from the processor 101. [

Illustratively, the tag (TAG) may include a portion of an address corresponding to the data stored in the volatile memory (121). Illustratively, the module controller 110 can exchange tag (TAG) with the volatile memory 121 via the tag data line (TDQ). Illustratively, when data is written to the volatile memory 121, a tag (TAG) corresponding to the data can be written together with the volatile memory 121 under the control of the module controller 110. [

Illustratively, the volatile memory 121 and the nonvolatile memory 123 may have a direct mapping relationship of n: 1 (where n is a natural number). That is, the volatile memory 121 may be a direct mapped cache of the non-volatile memory 123. [ For example, the first volatile storage area of the volatile memory 121 may correspond to the first to n-th non-volatile storage areas of the non-volatile memory 123. [ At this time, the first volatile storage area and the first through n-th nonvolatile storage areas may be the same size. Illustratively, the first volatile storage area may further include an area for storing additional information (e.g., tags, ECC, dirty information, etc.).

Although not shown in the figure, the non-volatile memory module 100 may further include a separate memory (not shown). A separate memory (not shown) may store information such as data, programs, and software used in the NVM controller 122. For example, the separate memory may store information such as a mapping table, FTL, etc., managed by the NVM controller 122. Or a separate memory may be a buffer memory for temporarily storing data read from the nonvolatile memory 123 or data to be stored in the nonvolatile memory 123. [

Hereinafter, the write operation and the read operation of the nonvolatile memory module 100 will be described in detail with reference to FIG. 3 to FIG. In the following, for the sake of brevity, the components (e.g., data, tags, commands / addresses, etc.) associated with volatile memory 121 are represented using the reference symbols of '_v'. For example, the VM command / address output from the module controller 110 to control the volatile memory 121 is expressed as 'CA_v', and is output from the volatile memory 121 under the control of the module controller 110 The data is represented by 'DT_v'. More specifically, the VM write command for writing data to the volatile memory 121 is represented by 'WR_v', and the VM read command for reading data from the volatile memory 121 is represented by 'RD_v'.

Likewise, components (e.g., data, tags, commands / addresses, etc.) associated with non-volatile memory 123 are represented using the reference character of '_n'. For example, the NVM command / address output from the module controller 110 to control the nonvolatile memory 123 is expressed as 'CA_n', and is output from the nonvolatile memory 121 under the control of the module controller 110 The output data is represented by 'DT_n'. More specifically, the NVM write command for writing data to the nonvolatile memory 123 is represented by 'WR_n', and the NVM read command for reading data from the nonvolatile memory 123 is represented by 'RD_n' .

3 is a flowchart showing a write operation of the nonvolatile memory module of FIG. Referring to Figs. 1 to 3, in step S11, the processor 101 transmits a module write command and addresses WR, ADD to the nonvolatile memory module 100. [ For example, the processor 101 transmits the module write command and the addresses WR and ADD to the nonvolatile memory module 100 in order to write the write data DT_w to the nonvolatile memory module 100. Illustratively, the module write command and addresses WR and ADD may include an address ADD corresponding to write data DT_w. The address ADD corresponding to the write data may be a logical address, a memory address corresponding to a storage space of the nonvolatile memory module 100, that is, a part of the storage space of the nonvolatile memory 123. [

In step S12, the nonvolatile memory module 100 can perform a read operation to the volatile memory 121 in response to the received module write command and the addresses WR and ADD. For example, the non-volatile memory module 100 may read data and a tag (TAG) in an area corresponding to a received address ADD or a portion of the received address ADD in the area of the volatile memory 121 . Illustratively, the non-volatile memory module 100 can determine whether a cache hit or a cache miss by comparing the read tag (TAG) and the address (ADD).

In step S13, the nonvolatile memory module 100 may selectively perform the flush operation based on the result of the read operation in step S12. For example, when the result of the read operation in step S12 indicates a cache miss, the nonvolatile memory module 100 can perform a flush operation such that data read from the volatile memory 121 is stored in the nonvolatile memory 123 have. Illustratively, as described with reference to FIG. 2, the NVM controller 122 and volatile memory 121, which control the non-volatile memory 123, share a memory data line (MDQ). That is, when the voltage of the memory data line MDQ is driven by the data read from the volatile memory 121, the NVM controller 122, which controls the nonvolatile memory 123, (Or sense) the data read from the memory 121. The NVM controller 122 may program the received data into the nonvolatile memory 123.

Illustratively, when the result of the read operation in step S12 indicates a cache hit, the non-volatile memory module 100 may not perform the flush operation. Or the result of the read operation in step S12 indicates a cache hit, and the read data is dirty data, the nonvolatile memory module 100 may perform a flush operation.

Illustratively, operations such as flushing of the non-volatile memory module 100, cache hit or cache miss discrimination, dirty data discrimination can be performed by the NVM controller 122.

In step S14, the processor 101 can transmit the write data DT_w to the nonvolatile memory module 100. [ Illustratively, after the predetermined time has elapsed from step S11, the operation of step S14 may be performed. That is, the processor 101 can transmit the write data DT_w to the nonvolatile memory module 100 after a predetermined time has elapsed, by transmitting the module write command and the addresses WR and ADD. In this case, the predetermined time may be a write latency (WL). Illustratively, the write latency WL may be a predetermined time or clock period, depending on the operating characteristics of the non-volatile memory module 100. The information on the write latency WL may be stored in the SPD 140 and provided to the processor 101 as the device information DI. The processor 101 can transmit the write data DT_w based on the device information DI.

The nonvolatile memory module 100 can write or program the received write data DT_w in the volatile memory 121 or the nonvolatile memory 133 in step S15.

4 is a timing diagram for explaining the operation method of FIG. 3 in detail. Illustratively, the technical idea of the present invention is not limited to the timing and the timing of the command, the address, the data, the tag, and the like.

1 to 4, the nonvolatile memory module 100 receives the module write command and the first address WR, ADD1 from the processor 101. [ The module controller 110 of the nonvolatile memory module 100 outputs the NVM command / address CA_n and the VM memory command / address CA_n in response to the received module write command and the first address WR and ADD1 can do. At this time, the NVM command / address CA_n includes the NVM write command and the first address WR_v, ADD1, and the VM command / address CA_v includes the VM read command and the first address RD_v, ADD1, Command, and a first address WR_v, ADD1.

The volatile memory 121 of the nonvolatile memory module 100 responds to the VM read command RD_v by reading the data DT_v and the tag DT_v stored in the area corresponding to the first address ADD1 in the area of the volatile memory 121 TAG_v). For example, as described above, the volatile memory 121 can output the data DT_v via the memory data line (MD) by driving the voltage of the memory data line MDQ based on the data DT_v . The volatile memory 121 can output the tag TAG through the tag data line TDQ by driving the voltage of the tag data line TDQ based on the tag TAG.

The processor 101 can output the write data DT_w via the data line DQ. The nonvolatile memory module 100 provides the write data DT_w received via the data line DQ to the volatile memory 121 or the NVM controller 122 via the memory data line MDQ and supplies the write data DT_w (Or the first address ADD1) to the volatile memory 121 through the tag data line TDQ. The volatile memory 121 or the NVM controller 122 may perform a write operation or a program operation based on the received signals.

Although not shown in the drawing, the flush operation can be selectively performed according to the tag TAG_v read from the volatile memory 121. [

5 is a flowchart showing a read operation of the nonvolatile memory module 100 of FIG. Referring to FIGS. 1, 2 and 5, in step S21, the processor 101 transmits a module read command and addresses (RD, ADD) to the nonvolatile memory module 100.

In step S21, the nonvolatile memory module 100 performs a read operation to the volatile memory 121 in response to the module read command and the addresses (RD, ADD). For example, the module read command and the addresses (RD, ADD) may include a read command for reading data stored in the nonvolatile memory module 100 and a read address corresponding to the read data. The nonvolatile memory module 100 can read the data and the tag stored in the area corresponding to the read address in the area of the volatile memory 121.

In step S22, the nonvolatile memory module 100 can determine a cache hit or a cache miss based on the read result. As described above, the tag TAG includes some information of the address. The non-volatile memory module 100 can determine a cache hit or a cache miss by comparing the received read address and the tag (TAG). When a part of the received address matches the tag (TAG), the nonvolatile memory module 100 determines that it is a cache hit, and if the tag (TAG) does not match a part of the received address, the nonvolatile memory module 100) is judged as a cache miss.

Illustratively, a read operation in the case of being determined as a cache miss will be described with reference to Figs. 7 and 8. Fig.

The nonvolatile memory module 100 transfers the data read from the volatile memory 121 and the cache information INFO to the processor 101 in step S24. The cache information INFO includes information on whether the outputted data is a cache hit or a cache miss. The processor 101 can determine whether the data DT_v received via the cache information INFO is valid data. That is, since the nonvolatile memory module 100 provides the cache hit information H as cache information INFO, the processor 101 can recognize that the received data is valid data.

Illustratively, after the predetermined time has elapsed from step S21, the operation of step S24 may be performed. That is, the processor 101 transmits the module read command and the addresses (RD, ADD), and read data will be received from the nonvolatile memory module 100 after a predetermined time has elapsed. At this time, the predetermined time may be a read latency (RL). The read latency RL may be a predetermined time or a clock cycle depending on the operating characteristics of the nonvolatile memory module 100. [ Information about the read latency RL may be stored in the SPD 140 and provided to the processor 101 as device information DI. The processor 101 can control the non-volatile memory module based on the read latency (RL).

6 is a timing chart for explaining the read operation of FIG. 5 in detail. Referring to Figures 1, 2, 5 and 6, the non-volatile memory module 100 receives a module read command and a first address (RD, ADD1) from the processor 101, And outputs the NVM command / address CA_n and the VM command / address CA_v. At this time, the NVM command / address CA_n may include an NVM read command for reading data stored in the nonvolatile memory 123 and a first address RD_n and ADD1. The VM command / address CA_v may include a VM read command for reading data stored in the volatile memory 121 and a first address RD_v, ADD1.

The volatile memory 121 responds to the VM read command and the first address RD_v and ADD1 to write the data DT_v and the tag TAG_v stored in the area corresponding to the first address ADD1 in the area of the volatile memory 121 Can be output. For example, as described above, the volatile memory 121 outputs the data DT_v through the memory data line MDQ by driving the voltage of the memory data line MDQ based on the data DT_v . The volatile memory 121 can output the tag TAG_v through the tag data line TDQ by driving the voltage of the tag data line TDQ based on the tag TAG_v.

The module controller 110 can receive the tag TAG_v via the tag data line TDQ and compare the received tag TAG_v and the first address ADD1 to determine whether it is a cache hit or a cache miss.

The nonvolatile memory module 100 outputs the data DT_v read from the volatile memory 131 through the data line DQ and stores the cache information INFO containing the cache hit information H Can be output. The processor 101 can recognize that the data DT_v received via the data line DQ is valid data by receiving the cache information INFO including the cache hit H information.

FIG. 7 is a flowchart showing another read operation of the nonvolatile memory module 100 of FIG. Illustratively, with reference to FIG. 7, a read operation in the case of a cache miss will be described.

Referring to FIGS. 1, 2, 5, and 7, if the determination result in step S23 indicates that the cache miss is detected, the operation in step S25 is performed. The nonvolatile memory module 100 transfers the data DT_v and the cache information INFO read from the volatile memory 121 to the processor 101 in step S25. At this time, the cache information INFO will contain information about the cache miss M.

Illustratively, as described above, the operation of step S25 may also be performed after the read latency RL from the time the module read command and the addresses RD, ADD are received.

In step S26, the non-volatile memory module 100 may perform a pre-reading operation with respect to the non-volatile memory 123. [ Illustratively, a pre-read operation refers to an operation in which the NVM controller 122 reads data from the non-volatile memory 123 and stores the read data in a data buffer (not shown) included in the NVM controller 122. Or read-ahead operation refers to an operation of preparing read data so that the NVM controller 122 can output the data from the non-volatile memory 123 within a read latency (RL) according to a command of the processor 101. [ That is, when the pre-reading operation for the non-volatile memory 123 is completed, the data from the non-volatile memory 123 will be output within the read latency RL in response to the instruction from the processor 101. [

Illustratively, a pre-read operation may be performed while operations S22 to S25 are performed. Or a pre-read operation may be performed by the NVM controller 122 if it is determined to be a cache miss. For example, the NVM controller 122 may receive the first address ADD1 from the module controller 110 and the tag TAG via the tag data line TDQ. The NVM controller 122 can determine whether a cache hit or a cache miss by comparing the received first address ADD1 and the tag TAG. According to the determination result, the NVM controller 122 can perform a pre-read operation. Illustratively, a determination operation for a cache hit or a cache miss by the NVM controller 122 may be performed after the tag TAG_v is output from the volatile memory 121. [

After the pre-read operation is completed, the nonvolatile memory module 100 provides the ready signal R to the processor 101 in step S27. Illustratively, the ready signal R may be a signal indicating that the non-volatile memory module 100 has completed the pre-read operation. The ready signal R may be provided through a signal line through which the cache information INFO is transmitted or may be provided via a separate signal line.

In step S28, the processor 101 may provide the module read command and the addresses NRD and ADD to the non-volatile memory module 100 in response to the ready signal R. [ Illustratively, the module read command (NRD) may be different from the module read command RD in step S21. The module read command NRD may be a command / address for reading data from the nonvolatile memory 123.

In step S29, the nonvolatile memory module 100 performs a read operation to the nonvolatile memory 123 and a write operation to the volatile memory 121 in response to the module read command and the addresses NRD and ADD. For example, the NVM controller 122 of the non-volatile memory module 100 may drive a memory data line (MDQ) based on data prepared in a pre-read operation. The volatile memory 121 can receive the data output from the NVM controller 122 (i.e., the data output from the nonvolatile memory 123) via the memory data line MDQ and write the received data. At this time, the write operation of the volatile memory 121 may be a read caching operation.

In step S2a, the nonvolatile memory module 100 can transfer the data DT_n from the nonvolatile memory 123 to the processor 101. [ For example, the non-volatile memory module 100 can output the data DT_n from the nonvolatile memory 123 via the data line DQ. Illustratively, the operation of step S2a may be performed after a predetermined time from the operation of step S28. The predetermined time may be the read latency RL '. 7 may be different from the read latency RL of FIG. 5, and information about them may be stored in the SPD 140 and stored in the processor 101 as device information DI. For example, the read latency RL of FIG. Lt; / RTI >

8 is a timing chart for explaining the read operation of FIG. 7 in detail. For the sake of brevity, a detailed description of the configurations overlapping with those described above is omitted.

Referring to FIGS. 1, 2, 5, 7 and 8, the nonvolatile memory module 100 receives a module read command and a first address RD, ADD1 from the processor 101. The module controller 110 of the nonvolatile memory module 100 provides the NVM read command and the first address RD_n and ADD1 to the NVM controller 122 in response to the module read command and the first address RD and ADD1 , The VM read command and the first address (RD_v, ADD1) to the volatile memory 121.

The volatile memory 121 responds to the VM read command and the first address RD_v and ADD1 to write the data DT_v and the tag TAG_v in the area corresponding to the first address ADD1 in the area of the volatile memory 121, Can be output through the memory data line MDQ. That is, the volatile memory 121 can drive voltages of the memory data line MDQ and the tag data line TDQ, respectively, based on the data DT_v and the tag TAG_v. Data DT_v on the memory data line MDQ is output through the data line DQ under the control of the module controller 110 and the data buffer 130. [

The module controller 110 can determine whether a cache hit or a cache miss by comparing the tag TAG_v and the first address ADD1 output from the volatile memory 121. [ In the case of a cache miss, the module controller 110 may transmit cache information (INFO) for the cache miss (M) to the processor 101. At this time, the processor 101 may recognize that the data DT_v received via the data line DQ is a cache miss M.

The non-volatile memory module 100 may perform a pre-read operation. Illustratively, the NVM controller 122 responds to the nonvolatile memory read command and the first address ADD1 from the module controller 110 to compare the first address ADD1 in the area of the nonvolatile memory 123 The data of the area can be prepared (or stored in a separate data buffer). When the pre-read operation is completed, the module controller 110 can transmit the ready signal R to the processor 101. [ Illustratively, the ready signal R may be provided to the processor 101 via the same line as the cache information INFO, a separate signal line, or the data line DQ.

In response to the ready signal R, the processor 101 transmits the module read command and the first addresses NRD and ADD1 to the nonvolatile memory module 100. [ In response to the module read command and the first address NRD, ADD1, the nonvolatile memory module 100 provides the NVM read command and the first address RD_n ', ADD1 to the NVM controller 122. Illustratively, the NVM read command RD_n in accordance with the module read command NRD may be different from the NVM read command RD_n in accordance with the module read command RD.

Illustratively, each of the module read commands NRD and RD may be a predefined command by a communication protocol between the processor 101 and the non-volatile memory module 100. [

The NVM controller 122 may output the data DT_n prepared in the pre-read operation through the memory data line MDQ in response to the NVM read command and the first address RD_n ', ADD1. Illustratively, the NVM controller 122 may output the tag TAG_n corresponding to the data DT_n via the tag data line TDQ. Illustratively, the tag TAG_n corresponding to the data DT_n may include a portion of the first address ADD1 corresponding to the data DT_n. The data DT_n on the memory data line MDQ may be output to the data line DQ under the control of the module controller 110 and the data buffer 130. [

Illustratively, the non-volatile memory module 100 can perform read caching while the data DT_n is output. For example, the module controller 110 may provide the VM write command and the first address WR_v, ADD1 to the volatile memory 121 in response to a nonvolatile memory read command / address (CA_NRD).

Illustratively, the VM write command and the first address WR_v, ADD1 may have a predetermined time with the NVM read command and the first address RD_n ', ADD1. That is, the NVM controller 122 synchronizes with the timing at which the NVM controller 122 outputs the data DT_n via the memory data line MDQ in response to the NVM read command and the first address RD_n ', ADD1, (WR_v, ADD1) may be provided to the volatile memory 121. [

The volatile memory 121 stores data on the memory data line MDQ in an area corresponding to the first address ADD1 in the area of the volatile memory 121 in response to the volatile memory write command and the first address WR_v and ADD1. (DT_n) and a tag (TAG_n) on the tag data line (TDQ). Through the above-described read caching, the cache hit rate of the nonvolatile memory module 100 can be increased.

The structure, write operation, or read operation of the non-volatile memory module 100 as described above is exemplary and can be variously modified without departing from the technical idea of the present invention.

FIG. 9 is a diagram for explaining the cache structure of the volatile memory of FIG. 2. FIG. For the sake of brevity, the components unnecessary for explaining the cache structure of the volatile memory 121 are omitted. It is also assumed that the storage area of the nonvolatile memory 123 is divided into the first to fourth areas AR1 to AR4. The first to fourth areas AR1 to AR4 are logically divided areas and the storage area of the nonvolatile memory 123 further includes storage areas other than the first to fourth areas AR1 to AR4 .

2 and 9, the volatile memory 121 may have a faster access rate than the non-volatile memory 123. [ That is, by storing a part of the data stored in the nonvolatile memory 123 in the volatile memory 121, the access speed according to the request of the module controller 110 or the processor 101 can be improved. For example, the volatile memory 121 can be used as the cache memory of the nonvolatile memory 123. [ Volatile memory 121 may store some of the data stored in nonvolatile memory 123 and may output the stored data upon request of module controller 110 or processor 101. For example,

Illustratively, the volatile memory 121 may have a direct mapping relationship with the non-volatile memory 123. For example, the volatile memory 121 may include a plurality of entries ET01 to ET0n. One entry (ET) may indicate a storage space for storing data and tags (TAG) in units of cache lines. The cache line unit may indicate the minimum access unit according to the request of the module controller 110 or the processor 101. The volatile memory 121 may have a storage capacity as many as the plurality of entries ET01 to ET0n.

The nonvolatile memory 123 may include first to fourth areas AR1 to AR4. Each of the first to fourth areas AR1 to AR4 may include a plurality of cache lines CL11 to CL1n, CL21 to CL2n, CL31 to CL3n, and CL41 to CL4n, respectively. Illustratively, each of the plurality of cache lines CL11 to CL1n, CL21 to CL2n, CL31 to CL3n, CL41 to CL4n indicates a storage space of a data access unit according to a request of the processor 101 or the module controller 110 .

For example, the first area AR1 may include cache lines CL11 to CL1n. Each of the cache lines CL11 to CL1n may correspond to each of the plurality of entries ET1 to ETn in a one-to-one correspondence. That is, the first cache line CL11 may correspond to the first entry ET1, and the second cache line CL12 may correspond to the second entry ET2. The second area AR1 may include cache lines CL21 to CL2n and each of the cache lines CL21 to CL2n may correspond to each of the plurality of entries ET1 to ETn in a one-to-one correspondence. Similarly, each of the third and fourth areas AR3 and AR4 includes cache lines CL31 to CL3n and CL41 to CL4n, respectively, and each of the cache lines CL31 to CL3n and CL41 to CL4n includes a plurality of entries Lt; RTI ID = 0.0 > ET1-ETn. ≪ / RTI >

As described above, the volatile memory 121 may have a direct mapping relationship with the nonvolatile memory 123. [ The first entry ET1 of the volatile memory 121 corresponds to the cache lines CL11, CL21, CL31 and CL41 of the first to fourth areas AR1 to AR4, CL1, CL31, and CL41 in the cache lines AR1 to AR4. In other words, the data DT_v stored in the first entry ET1 will correspond to any one of the cache lines CL11, CL21, CL31, and CL41 of the first to fourth areas AR1 to AR4.

The first entry ETl may comprise a tag (TAG) for the stored data DT_v. Illustratively, the tag TAG is configured such that the data DT_v stored in the first entry ET1 is stored in any one of the cache lines CL11, CL21, CL31, CL41 of the first to fourth areas AR1 to AR4 Lt; / RTI > correspond to a line.

Illustratively, each of the plurality of cache lines CL11 to CL1n, CL21 to CL2n, CL31 to CL3n, and CL41 to CL4n may be distinguished or selected by an address ADD provided from the processor 101. [ That is, at least one of the plurality of cache lines CL11 to CL1n, CL21 to CL2n, CL31 to CL3n, and CL41 to CL4n is selected by the address ADD provided from the processor 101, Can be performed.

Each of the plurality of entries ET1 to ETn may be distinguished or selected by at least a part of the addresses ADD provided from the processor 101. [ That is, at least one entry among the plurality of entries ET1 to ETn is selected by at least a part of the addresses ADD provided from the processor 101, and an access operation to the selected entry can be performed.

The tag TAG may include at least a portion or the rest of the addresses ADD provided from the processor 101. For example, if at least one of the plurality of entries ET1 to ETn is selected by at least a portion of the address ADD and the tag TAG_v from the selected entry is included in the address ADD, It can be determined that it is hit (H). At least one of the plurality of entries ET1 to ETn is selected by at least a part of the address ADD or the tag TAG_v from the selected entry is not included in the address ADD, M). ≪ / RTI >

As described above, the nonvolatile memory module 100 improves the performance of the nonvolatile memory module 100 by using the volatile memory 121 as the cache memory. At this time, the nonvolatile memory module 100 can determine whether or not the cache hit and miss based on the tag (TAG) stored in the volatile memory 121.

FIG. 10 is a diagram for explaining the tag of FIG. 9 in detail. 1, 2, and 10, an address ADD provided from the processor 101 may include a row address and a column address. The row address may include a plurality of row bits R1 to Ri and the column address may include a plurality of column bits C1 to Ck. Illustratively, at least one of the plurality of cache lines of the non-volatile memory 123 may be selected in accordance with the plurality of row bits R1 to Ri and the plurality of column bits C1 to Ck.

Illustratively, the tag TAG may comprise at least a portion of a plurality of row bits R1-Ri. For example, the tag TAG may include first through fourth row bits R1 through R4. At this time, the remaining row bits R5 to Ri and the column bits C1 to Ck may be the address ADD_vm of the volatile memory 121. [ That is, at least one of the plurality of entries of the volatile memory 121 can be selected by the remaining row bits R5 to Ri and column bits C1 to Ck. Illustratively, the tag TAG may include some of the most significant bits of a plurality of row bits of a row address.

Illustratively, the configuration of the address according to the technical idea of the present invention is not limited to the address ADD shown in Fig. For example, the address ADD from the processor 101 may further include a chip address, a bank address, a row address, or a column address. Or the address ADD from the processor 101 may be modified into various types of addresses ADD.

Further, the structure of the tag (TAG) according to the technical idea of the present invention is not limited to the tag (TAG) shown in Fig. The tag TAG may include at least a portion of the address ADD. At this time, at least a portion of the address ADD may include some or a combination of some or a plurality of column bits (C1 to Ck) of the plurality of row bits (R1 to Ri).

Also, the address bits included in the tag (TAG) according to the technical idea of the present invention may have predetermined bit digits. For example, the tag TAG may include n most significant bits of the address ADD (where n is a natural number). At this time, the n most significant bits may be a predetermined number of bits. The address bits included in the tag TAG may also be varied by the module controller 110, the tag control circuit TC, or the NVM controller 122. [

FIG. 11 is a diagram for explaining a tag management method of the nonvolatile memory module of FIG. 2. FIG. For the sake of brevity, detailed descriptions of the components that are not necessary for explaining the tag management method and the components described above are omitted. Also, for the sake of brevity, it is assumed that the non-volatile memory module 100 receives the module read command and the first address (RD, ADD1) from the processor 101 and operates in response to the received signal. It is also assumed that at least a part of the first address ADD1 corresponds to the first entry ET1 of the volatile memory 121. [ That is, the volatile memory 121 can select or activate the first entry ET1 in response to the first address ADD1.

1 and 11, the nonvolatile memory module 100 includes a module controller 110, a volatile memory 121, an NVM controller 122, a nonvolatile memory 123, and a data buffer 130 do. Since the module controller 110, the volatile memory 121, the NVM controller 122, the nonvolatile memory 123, and the data buffer 130 have been described above, detailed description thereof will be omitted.

The module controller 110 receives the module read command and the first address RD and ADD1 from the processor 101 and outputs the VM read command and the first address RD_v and ADD1 to the volatile memory 121 And transmits the NVM read command and the first address RD_n and ADD1 to the NVM controller 122. [

The volatile memory 121 selects the first entry ET1 in response to the received VM read command and the first address RD_v and ADD1 and stores the tag TAG_v and data included in the selected first entry ET1 (DT_v). At this time, the tag TAG_v is output via the tag data line TDQ shared by the volatile memory 121, the NVM controller 122, and the module controller 110, and the data DT_v is output from the volatile memory 121 And the NVM controller 122 are output via the memory data line MDQ shared by the NVM controller 122. [

Illustratively, the module controller 110 may include a tag control circuit (TC). The tag control circuit TC can be connected to the tag data line TDQ. The tag control circuit TC can receive the tag TAG from the volatile memory 121 via the tag data line TDQ and compare the received tag TAG and address ADD. The tag control circuit TC can output cache information H for the cache hit H or cache information INFO for the cache miss M to the processor 101 according to the comparison result.

For example, as described above, the tag TAG may include at least a part of the address corresponding to the data DT_v. The tag control circuit TC can compare the address received from the processor 101 (for example, the first address ADD1) and the tag (TAG) received from the volatile memory 121. [ The tag control circuit TC may output the cache information INFO for the cache hit H if at least a part of the first address ADD1 and the received tag TAG coincide with each other. On the other hand, if at least a part of the first address ADD1 and the received tag TAG do not coincide with each other, the tag control circuit TC can output the cache information INFO for the cache miss M .

Illustratively, the NVM controller 122 may receive the tag (TAG) via the tag data line (TDQ) and perform operations such as read caching, data flushing, etc. based on the received tag (TAG).

12 is a diagram for explaining a tag management method of the nonvolatile memory module of FIG. 1 and 12, the nonvolatile memory module 100 includes a module controller 110, a volatile memory 121, an NVM controller 122, a nonvolatile memory 123, and a data buffer 130 can do. For the sake of brevity, a detailed description of the components described above is omitted.

The module controller 110 receives the module write command and the first address WR and ADD1 from the processor 101 and outputs the VM write command and the first address WR_v and ADD1 to the volatile memory 121, and may transmit the NVM write command and the first address ADD1 to the NVM controller 122. [

Illustratively, the module controller 110 may transmit the VM read command and the first address RD_v, ADD1 to the volatile memory 121 in response to the received module write command and the first address WR, ADD1 . In order to simplify the drawing, such a configuration is omitted.

The volatile memory 121 can select the first entry ET1 in response to the received VM write command and the first address WR_v, ADD1. Illustratively, the first entry ET1 may point to a storage area of the volatile memory 121 that corresponds to at least a portion of the first address ADD1.

The data buffer 130 may provide the write data DT_v provided from the processor 101 to the volatile memory 121 and the NVM controller 122 via the memory data line MDQ. The volatile memory 121 can write the write data DT_w received via the memory data line MDQ to the first entry ET1 selected by at least a part of the first address ADD1. At this time, the volatile memory 121 can write the write tag TAG_w received via the tag data line TDQ to the first entry ET1 together with the write data DT_w.

Illustratively, the write tag (TAG_w) may be a tag generated by the tag control circuit (TC) of the module controller (110). For example, the tag control circuit TC may select at least a portion of the first address ADD1 received from the processor 101 as a write tag (TAG). That is, the write tag (TAG_w) may correspond to write data (DT_w) to be written to the volatile memory (121).

The tag control circuit TC can supply the write tag TAG_w to the volatile memory 121 by driving the voltage of the tag data line TDQ based on the selected write tag TAG_w.

As described above, in the write operation, the nonvolatile memory module 100 writes the write tag (TAG_w) and write data (DT_w) together in the same entry among the plurality of entries in the volatile memory 121, Or the cache miss determination operation can be normally performed.

13 is a timing chart for explaining a tag transmission method of the nonvolatile memory modules shown in FIG. 11 and FIG. Referring to Figs. 11 to 13, the X-axis in Fig. 13 indicates time.

The tag TAG_v stored in the volatile memory 121 may be output from the volatile memory 121 via the tag data line TDQ, as shown in the first section of Fig. At this time, the tag TAG can be output in synchronization with the tag data strobe line TDQS. The signal of the tag data strobe line (TDQS) can be driven by the tag control circuit (TC) or the volatile memory (121).

Similarly, as shown in the second section of Fig. 13, the write tag (TAG_w) may be output via the tag data line (TDQ). At this time, the write tag (TAG) can be output in synchronization with the tag data strobe line (TDQS). The signal of the tag data strobe line (TDQS) can be driven by the tag control circuit (TC) or the volatile memory (121).

As described above, the tag TAG can be transmitted / received via the tag data line TDQ in synchronization with the signal of the tag data strobe line TDQS. Illustratively, the tag data strobe line TDQS is connected to the data strobe line DQS between the processor 101 and the nonvolatile memory module 100, or the memory data strobe line MDQ in the nonvolatile memory module 100, It may be another signal line. The tag data strobe line TDQS is a clock signal having the same frequency as the data strobe line DQS between the processor 101 and the nonvolatile memory module 100 or the memory data strobe line MDQ in the nonvolatile memory module 100, Signal.

14 is a block diagram showing another example of the nonvolatile memory module of FIG. 1 and 14, a nonvolatile memory module 200 includes a module controller 210, first and second volatile memories 221_1 and 221_2, an NVM controller 222, a nonvolatile memory 223, And a data buffer 230. For the sake of brevity, a detailed description of the components described above is omitted.

The nonvolatile memory module 200 of FIG. 14 further includes a second volatile memory 221_2 which is a tag-dedicated volatile memory. The second volatile memory 221_2, which is a tag-dedicated volatile memory, is configured to store the tag TAG_v for the data DT_v stored in the same entry. For example, the first and second volatile memories 221_1 and 221_2 may select the first entry ET1 in response to the VM command / address CA_v from the module controller 210. [ The first entry ET1 may include a part of each of the first and second volatile memories 221_1 and 221_2.

The first entry ET1 of the first volatile memory 221_1 may include data DT_v. The first volatile memory 221_1 can transmit and receive data DT_v via the memory data line MDQ. The first entry ET1 of the second volatile memory 221_2 may include a tag TAG_v. The second volatile memory 221_2 can transmit and receive the tag TAG_v via the tag data line TDQ.

Illustratively, each of the first and second volatile memories 221_1 and 221_2 may be implemented as a separate die, a separate chip, or a separate package.

That is, the nonvolatile memory module 200 includes a tag dedicated volatile memory for storing a tag (TAG), and the tag dedicated volatile memory can be implemented as a chip separate from a volatile memory for storing data. At this time, the tag-dedicated volatile memory can operate in accordance with the VM command / address CA_v from the module controller 210 in the same manner as other volatile memories.

15 is a block diagram showing another example of the nonvolatile memory module of FIG. 1 and 15, the non-volatile memory module 300 includes a module controller 310, first to third volatile memories 321_1 to 321_3, an NVM controller 322, a non-volatile memory 323, And a data buffer 330. For the sake of brevity, a detailed description of the components described above is omitted.

Unlike the nonvolatile memory module 200 of FIG. 14, the nonvolatile memory module 300 of FIG. 15 may further include a third volatile memory 221_3, which is a volatile memory dedicated to a tag. That is, the non-volatile memory module 300 may include at least two volatile memories dedicated to the tag.

The second and third volatile memories 321_2 and 321_3 which are the tag exclusive volatile memories are configured to store the tag TAG_v corresponding to the data DT_v stored in the first volatile memory 321_1. For example, each of the first to third volatile memories 321_1 to 321_3 may operate in response to a VM command / address CA_v from the module controller 210. [ Each of the first to third volatile memories 321_1 to 321_3 includes a first entry ET1 corresponding to at least a part of the first address ADD1 in response to the VM command / address CA_v from the module controller 310, And perform access to the selected first entry ET1.

Illustratively, the first entry ET1 stores the data DT_v of the first volatile memory 221_1, the tag TAG_v of the second volatile memory 321_2, and the tag TAG_v of the third volatile memory 321_3 . The tag TAG_v of the second volatile memory 321_2 is provided to the NVM controller 322 and the module controller 210 via the first tag data line TDQ1 and the tag TAG_v of the third volatile memory 321_ May be provided to the NVM controller 322 and the RDC 310 via the second tag data line (TDQ2).

Alternatively, although not shown in the figure, the second volatile memory 321_1 receives the write tag TAG_w (see FIG. 12) through the first tag data line TDQ1 and writes the received write tag TAG_w The third volatile memory 321_3 receives the write tag TAG_w (see FIG. 12) via the second tag data line TDQ2 and writes the received write tag TAG_w into the first entry ET1 And can write to the first entry ET1. That is, the non-volatile memory module 300 may include at least two tag-specific volatile memories. Each of the at least two tag dedicated volatile memories may be implemented as a separate die, a separate chip, or a separate package.

Illustratively, the tag only volatile memory is not limited to the first and second volatile memories 221_1 and 221_2. The non-volatile memory module 200 may include at least two or more tag-dedicated volatile memories, and at least two or more tag-dedicated volatile memories may be implemented as separate chips or separate packages, respectively.

Illustratively, the tag TAG_v written in the first entry ET1 of the second volatile memory 321_2 is the same value as the tag TAG_v written in the first entry ET1 of the second volatile memory 321_3 Lt; / RTI > That is, even if any one of the second and third volatile memories 321_2 and 321_3, which are the tag-only volatile memories, does not operate normally due to a specific factor (i.e., in a chip-kill situation) By transmitting and receiving the tag TAG through the memory, the nonvolatile memory module 200 can operate normally.

16 is a block diagram showing another example of the nonvolatile memory module of FIG. 16, the non-volatile memory module 400 includes a module controller 410, a volatile memory 421, an NVM controller 422, a non-volatile memory 423, a data buffer 430, and a tag control circuit TC). For the sake of brevity, a detailed description of the components described above is omitted.

The nonvolatile memory module 400 of FIG. 16 includes a separate tag control circuit TC. As described above, the tag control circuit TC receives the tag TAG via the tag data line TDQ or supplies the write tag TAG_w via the tag data line TDQ to the volatile memory 421 can do. For example, the tag control circuit TC is disposed outside the module controller 410 and receives the first address ADD1 (i.e., the address provided from the processor 101) from the module controller 410, It is possible to generate the write tag TAG_w based on the first address ADD1. Or the tag control circuit TC may compare the tag TAG_v and the address ADD1 received via the tag data line TDQ to output cache information INFO for cache hit or cache miss.

Illustratively, the configuration of the non-volatile memory module according to the present invention is not limited to the embodiments described above. For example, a non-volatile memory module according to the present invention may include at least one volatile memory dedicated to a tag, and at least one volatile memory dedicated to tag may be configured to share a tag data line (TDQ) with a separate tag control circuit. have.

17 is a diagram for explaining a tag according to another embodiment of the present invention in detail. For the sake of brevity, a detailed description of the components described with reference to FIG. 9 is omitted.

2 and 17, the volatile memory 121 includes a plurality of entries ET1 'to ETn'. The nonvolatile memory 123 includes first to fourth areas AR1 to AR4 each of which includes a plurality of cache lines CL11 to CL1n, CL21 to CL2n, CL31 to CL3n, and CL41 to CL4n, .

Illustratively, unlike the plurality of entries ET1 to ETn described with reference to Fig. 9, each of the plurality of entries ET1 'to ETn' in Fig. 17 includes data DT_v, tag TAG, An error correction code ECC_DT, a tag error correction code ECC_TAG, and dirty information DRT.

The tag TAG may be at least a part of the address corresponding to the data DT_v stored in the same entry. The data error correction code ECC_DT may be an error correction code for the data DT_v stored in the same entry. The tag error correction code ECC_TAG may be an error correction code for the tag (TAG) stored in the same entry. The dirty information DRT may indicate dirty information for the data DT_v stored in the same entry.

Illustratively, the tag TAG, the data error correction code ECC_DT, the tag error correction code ECC_TAG, and the dirty information DRT are stored in the tag-only volatile memories described with reference to Figs. 14 and 15 . The tag TAG, the data error correction code ECC_DT, the tag error correction code ECC_TAG, and the dirty information DRT may be provided to the module controller, the NVM controller, or the tag control circuit via the tag data line TDQ. have.

18 is a flowchart for explaining an operation method of the nonvolatile memory module of FIG. Illustratively, the operation of FIG. 18 may be performed by the tag control circuit TC of the non-volatile memory module. As described above, the tag control circuit TC may be included inside the module controller, or may be disposed outside the module controller, provided as a separate chip, or included in the NVM controller. For the sake of brevity, it is assumed that the tag control circuit (TC) is included in the module controller. However, it is to be understood that the scope of the present invention is not limited thereto.

2, 11 and 18, in step S110, the module controller 110 receives the address ADD from the processor 101 (see FIG. 1). Illustratively, the module controller 110 may receive a module command / address (CA) from an external device. The module command / address CA may include an address ADD corresponding to the data or area to be accessed.

In step S120, the module controller 110 can select a part of the received address ADD as a tag (TAG). For example, as described with reference to FIG. 10, the address ADD includes a plurality of bits R1 to Ri, C1 to Ck, and some of the plurality of bits are selected as a tag TAG . That is, the tag TAG will include a part of the address ADD.

Illustratively, as described above, a portion of the address ADD selected with the tag TAG may have a predetermined number of bits. Or a part of the address ADD selected by the tag TAG may be varied by the tag control circuit TC.

In step S130, the module controller 110 may drive the voltage of the tag data line (TDQ) based on the selected tag (TAG).

Illustratively, the volatile memory 121 receives the tag TAG by sensing the voltage of the tag data line TDQ and writes the received tag TAG to the entry corresponding to at least a portion of the address ADD .

19 is a flowchart for explaining another operation method of the nonvolatile memory module of FIG. Illustratively, the operation of Fig. 19 can be performed by the tag control circuit TC of the non-volatile memory module. As described above, the tag control circuit TC may be included inside the module controller, or may be disposed outside the module controller, provided as a separate chip, or included in the NVM controller. For the sake of brevity, it is assumed that the tag control circuit (TC) is included in the module controller. However, it is to be understood that the scope of the present invention is not limited thereto.

2, 11, and 19, in step S210, the module controller 110 receives an address ADD from the processor 101 (see FIG. 1).

In step S220, the module controller 110 receives the tag (TAG) through the tag data line (TDQ). For example, the module controller 110 receives a tag (TAG) via a tag data line (TDQ) from a volatile memory or a tag dedicated volatile memory.

In step S230, the module controller 110 can determine whether the cache hit or the cache miss by comparing a part of the received address ADD and the received tag TAG. For example, as described above, the module controller 110 determines that it is a cache hit when a part of the received tag (TAG) and the received address (ADD) coincide with each other, If a part of the received address ADD does not coincide, it is determined that the cache miss is present.

In step S240, the module controller 110 outputs cache information INFO based on the determination result. For example, the module controller 110 can output information on cache hit or cache miss as cache information INFO according to the determination result.

20 is a block diagram showing another example of the nonvolatile memory module of FIG. 1 and 20, a non-volatile memory module 500 includes a module controller MC, a plurality of heterogeneous memory devices (HMD), a plurality of data buffers (DB), and an SPD. For the sake of brevity, a detailed description of the components described above is omitted. Illustratively, the non-volatile memory module 500 of FIG. 20 may have a structure of a Load Reduced Dual In-line Memory Module (LRDIMM).

The module controller MC receives the module command / address CA from the processor 101 and sends the VM command / address CA_v and the NVM command address CA_n to the plurality of disparate memory devices HDM), respectively.

Each of the plurality of heterogeneous memory devices HMD may be a heterogeneous memory device that includes volatile memories, NVM controllers, and nonvolatile memories, each of which is described with reference to Figs. 9-16. For example, each of the plurality of heterogeneous memory devices HMD may be connected to a plurality of data buffers DB via a memory data line MDQ and may share a tag data line TDQ with each other. That is, each of the plurality of heterogeneous memory devices HMD may store a tag or data, and may transmit the tag or the data via the tag data line TDQ and the memory data line MDQ, respectively, under the control of the module controller MC It can transmit and receive.

Illustratively, each of the plurality of heterogeneous memory devices (HMDs) may operate based on the method of operation described with reference to FIGS.

FIG. 21 is a block diagram showing another example of the nonvolatile memory module of FIG. 2. FIG. 1 and 21, the nonvolatile memory module 600 includes a module controller MC, a plurality of heterogeneous memory devices HMD, a tag dedicated memory device TAG HMD, a plurality of data buffers DB, , And SPD. For the sake of brevity, a detailed description of the components described above is omitted. Illustratively, the non-volatile memory module 600 of FIG. 21 may have the structure of an LRDIMM.

The nonvolatile memory module 600 of FIG. 21 includes a tag dedicated memory device (TAG HMD) unlike the nonvolatile memory module 500 of FIG. Each of the plurality of heterogeneous memory devices HMD is configured to store data DT_v and may not be connected to the tag data line TDQ. The tag-specific heterogeneous memory device (TAG HMD) may include volatile memories, NVM controllers, and non-volatile memories described with reference to FIGS. 11-19. That is, the tag dedicated heterogeneous memory device (TAG HMD) can be configured to store and output the corresponding tag (TAG) according to the VM command / address (CA_v) of the module controller (MC). At this time, the tag dedicated heterogeneous memory device (TAG HMD) may be configured to share the tag data line (TDQ) with the module controller (MC).

22 is a block diagram showing another example of the nonvolatile memory module of FIG. 1 and 22, the non-volatile memory module 700 includes a module controller MC, a plurality of volatile memories VM11 to VM1n, VM21 to VM2m, first and second NVM controllers 722a and 722b ), A plurality of nonvolatile memories (NVM11 to NVM1k, NVM21 to NVM2i), a tag dedicated volatile memory (TVM), an SPD, a plurality of data buffers (DB), and a tag control circuit do. For the sake of brevity, a description of the components described above is omitted. Illustratively, the non-volatile memory module 700 of FIG. 14 may have the structure of an LRDIMM.

Some of the volatile memories (for example, VM11 to VM1n) of the plurality of volatile memories VM11 to VM1n and VM21 to VM2m are configured to share the memory data line MDQ with the first NVM controller 722a, respectively. The remaining volatile memories (e.g., VM21 to VM2m) are configured to share the memory data line MDQ with the second NVM controller 722b, respectively. Each of the plurality of volatile memories (VM11 to VM1n, VM21 to VM2m) is configured to share a memory data line (MDQ) with each of a plurality of data buffers (DB).

Some nonvolatile memories (for example, NVM11 to NVM1k) of the plurality of nonvolatile memories (NVM11 to NVM1k, NVM21 to NVM2i) are configured to operate under the control of the first NVM controller 722a. The remaining nonvolatile memories (for example, NVM21 to NVM2i) are configured to operate under the control of the second NVM controller 722b.

The tag dedicated volatile memory (TVM) is configured to share the tag data line (TDQ) with the module controller (MC), the first NVM controller 722a, and the second NVM controller 722b.

Illustratively, each of the components shown in FIG. 12 may be implemented as a plurality of semiconductor chips, and at least some of the plurality of semiconductor chips may be implemented as a single package. For example, a plurality of volatile memories VM11 to VM1n, VM21 to VM2m, a plurality of nonvolatile memories NVM11 to NVM1k, NVM21 to NVM2i, a first NVM controller 722a, and a second NVM controller 722b May be implemented as separate semiconductor chips. Some of the plurality of volatile memories VM11 to VM1n and VM21 to VM2m, the plurality of nonvolatile memories NVM11 to NVM1k and NVM21 to NVM2i, the first NVM controller 722a and the second NVM controller 722b Elements can be implemented in a single package.

For example, some of the plurality of volatile memories (VM11 to VM1n, VM21 to VM2m) (for example, VM11 to VM1n) are constituted by one package and the NVM controller 722a and the nonvolatile memory modules NVM11 NVM1k, NVM21 to NVM2i may be implemented in another package.

Illustratively, the tag dedicated volatile memory (TVM) may comprise a plurality of semiconductor chips. For example, the tag-only volatile memory (TVM) includes a plurality of tag-dedicated volatile memory chips, and each of the plurality of volatile memory chips can store the same tag information, ECC information, dirty information, and the like. In this case, the tag information, the ECC information, the dirty information, and the like can be normally written or output through the other tag-dedicated volatile memory chip even when the normal operation of any one of the volatile tag chips dedicated to the tag is not performed. Illustratively, the tag-specific volatile memory (TVM) may be implemented in a separate package from the other components. Or tag only volatile memory (TVM) may be implemented in a package with at least some of the other components.

The tag control circuit TC is configured to share the tag data volatile memory TVM with the tag data line TDQ. That is, the tag control circuit TC receives the tag TAG from the tag-dedicated volatile memory TVM via the tag data line TDQ or transmits the tag TAG via the tag data line TDQ to the tag- (TVM).

The tag control circuit TC can determine whether the cache hit or the cache miss according to the control of the module controller MC and output the determination result as the cache information INFO. For example, the tag control circuit TC can receive the tag TAG from the tag dedicated volatile memory TVM under the control of the module controller MC. The tag control circuit TC compares the tag TAG (or the address ADD) from the module controller MC and the tag TAG from the tag dedicated volatile memory TVM to determine a cache hit or a cache miss .

Illustratively, the tag control circuit TC may be implemented in software or hardware and the tag control circuit TC may be included in the module controller MC or may be incorporated into the first and second NVM controllers 722a and 722b Respectively.

23 is a block diagram exemplarily showing a nonvolatile memory included in the nonvolatile memory module according to the present invention. Referring to FIG. 23, the nonvolatile memory 1100 includes a memory cell array 1110, an address decoder 1120, a control logic circuit 1130, a page buffer 1140, and an input / output circuit 1150.

The memory cell array 1110 includes a plurality of memory blocks, and each of the plurality of memory blocks includes a plurality of memory cells. Each of the plurality of memory cells may be connected to a plurality of word lines WL, respectively. Each of the plurality of memory cells may be a single level cell (SLC) storing one bit or a multilevel cell (MLC) storing at least two bits.

The address decoder 1120 can receive the address ADDR from the NVM controller 112 (see FIG. 2) and decode the received address ADDR. Illustratively, the address ADDR received from the NVM controller 112 may be a physical address indicating the physical location of the storage area of the non-volatile memory 1100. The address decoder 1120 may select at least one word line of the plurality of word lines WL based on the decoded address, and may drive the voltage of the selected word line.

The control logic circuit 1130 receives the command CMD and the control signal CTRL from the NVM controller 112 (see FIG. 2) and generates the address decoder 1120, page buffer 1140, And the input / output circuit 1150 can be controlled.

The page buffer 1140 is connected to the memory cell array 1110 through a plurality of bit lines BL and is connected to the input / output circuit 1150 through a plurality of data lines DL. The page buffer 1140 can sense the voltages of the plurality of bit lines BL and read data stored in the memory cell array 1110. [ Or the page buffer 1140 may control the voltages of the plurality of bit lines BL based on data received through the plurality of data lines DL.

Output circuit 1150 may receive data from the NVM controller 112 (see FIG. 2) under control of the control logic circuit 1130 and may pass the received data to the page buffer 1140. Or the I / O circuit 1150 may receive data from the page buffer 1140 and pass the received data to the NVM controller 112. [

Illustratively, the NVM controller 122 generates an address ADDR, a command CMD, and a control signal CTRL based on the NVM command / address CA_v from the module controller 110 (see FIG. 2) can do.

24 is a circuit diagram illustrating a first memory block among the memory blocks included in the nonvolatile memory of the nonvolatile memory module according to the present invention. Illustratively, the first memory block BLK1 of a three-dimensional structure will be described with reference to Fig. However, the scope of the present invention is not limited thereto, and other memory blocks may have a structure similar to that of the first memory block BLK1.

Referring to FIG. 24, the first memory block BLK1 includes a plurality of cell strings CS11, CS12, CS21, and CS22. A plurality of cell strings CS11, CS12, CS21, and CS22 may be arranged along a row direction and a column direction to form rows and columns.

Each of the plurality of cell strings CS11, CS12, CS21, and CS22 includes a plurality of cell transistors. For example, each of the plurality of cell strings CS11, CS12, CS21, and CS22 includes string selection transistors SSTa and SSTb, a plurality of memory cells MC1 to MC8, ground selection transistors GSTa and GSTb, And dummy memory cells DMC1, DMC2. Illustratively, each of the plurality of cell transistors included in the plurality of cell strings CS11, CS12, CS21, CS22 may be a charge trap flash (CTF) memory cell.

The plurality of memory cells MC1 to MC8 are connected in series and are stacked in a height direction perpendicular to the plane formed by the row direction and the column direction. The string selection transistors SSTa and SSTb are connected in series and the string selection transistors SSTa and SSTb connected in series are provided between the plurality of memory cells MC1 to MC8 and the bit line BL. The ground selection transistors GSTa and GSTb are connected in series and the ground selection transistors GSTa and GSTb connected in series are provided between the plurality of memory cells MC1 to MC8 and the common source line CSL.

Illustratively, a first dummy memory cell DMC1 may be provided between the plurality of memory cells MC1 to MC8 and the ground selection transistors GSTa and GSTb. Illustratively, a second dummy memory cell DMC2 may be provided between the plurality of memory cells MC1 to MC8 and the string selection transistors SSTa and SSTb.

The ground selection transistors GSTa and GSTb of the cell strings CS11, CS12, CS21 and CS22 can be commonly connected to the ground selection line GSL. By way of example, the ground select transistors of the same row may be connected to the same ground select line, and the other row of ground select transistors may be connected to another ground select line. For example, the first ground selection transistors GSTa of the cell strings CS11, CS12 of the first row may be connected to the first ground selection line and the first ground selection transistors GSTa of the cell strings CS21, CS12 of the second row The first ground selection transistors (GSTa) may be connected to the second ground selection line.

Illustratively, although not shown in the drawings, the ground select transistors provided at the same height from the substrate (not shown) may be connected to the same ground select line, and the ground select transistors provided at different heights may be connected to other ground select lines . For example, the first ground selection transistors GSTa of the cell strings CS11, CS12, CS21, and CS22 are connected to the first ground selection line and the second ground selection transistors GSTb are connected to the second ground selection Line. ≪ / RTI >

Memory cells of the same height from the substrate or ground select transistors (GSTa, GSTb) are commonly connected to the same word line, and memory cells of different heights are connected to different word lines. For example, the first to eighth memory cells MC8 of the cell strings CS11, CS12, CS21 and CS22 are commonly connected to the first to eighth word lines WL1 to WL8, respectively.

Of the first string selection transistors (SSTa) of the same height, the string selection transistors in the same row are connected to the same string selection line, and the other row string selection transistors are connected to another string selection line. For example, the first string selection transistors SSTa of the cell strings CS11 and CS12 of the first row are connected in common with the string selection line SSL1a and the cell strings CS21 and CS22 of the second row ) Are connected in common with the string selection line SSL1a.

Likewise, the string selection transistors of the same row among the second string selection transistors SSTb of the same height are connected to the same string selection line, and the string selection transistors of the other row are connected to another string selection line. For example, the second string selection transistors SSTb of the cell strings CS11 and CS12 of the first row are connected in common with the string selection line SSL1b and the cell strings CS21 and CS22 of the second row ) Are connected in common with the string selection line SSL2b.

Illustratively, dummy memory cells of the same height are connected to the same dummy word line, and dummy memory cells of different heights are connected to another dummy word line. For example, the first dummy memory cells DMC1 are connected to the first dummy word line DWL1, and the second dummy memory cells DMC2 are connected to the second dummy word line DWL2.

Illustratively, the first memory block BLK1 shown in FIG. 24 is exemplary and the number of cell strings may be increased or decreased, and the number of rows and columns comprised by the cell strings, depending on the number of cell strings, Increase or decrease. The number of the cell transistors GST, MC, DMC, SST, etc. of the first memory block BLK1 may be increased or decreased, and the height of the first memory block BLK1 Can be increased or decreased. Also, the number of lines (GSL, WL, DWL, SSL, etc.) connected to the cell transistors may be increased or decreased according to the number of cell transistors.

Illustratively, the nonvolatile memory according to the present invention is not limited to the above-described configuration. As an exemplary embodiment according to the technical concept of the present invention, the non-volatile memory may include a three-dimensional memory array. The three-dimensional memory array may be monolithically formed on one or more physical levels of arrays of memory cells having an active region disposed over a silicon substrate and circuits associated with operation of the memory cells. The circuitry associated with the operation of the memory cells may be located within or on the substrate. The term monolithic means that layers of each level in a three-dimensional array are deposited directly on the lower level layers of the three-dimensional array.

As an exemplary embodiment according to the technical concept of the present invention, a three-dimensional memory array has vertical directionality and includes vertical NAND strings in which at least one memory cell is located on the other memory cell. The at least one memory cell includes a charge trap layer. Each vertical NAND string may include at least one select transistor located over the memory cells. The at least one select transistor has the same structure as the memory cells and can be formed monolithically with the memory cells.

A three-dimensional memory array comprising a plurality of levels and having word lines or bit lines shared between the levels, a configuration suitable for a three-dimensional memory array is disclosed in U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466 U.S. Patent No. 8,654,587, U.S. Patent No. 8,559,235, and U.S. Patent Application Publication No. 2011/0233648, which are incorporated herein by reference.

25 is a block diagram illustrating an exemplary volatile memory of a non-volatile memory module according to the present invention. 25, a volatile memory 1200 includes a memory cell array 1210, an address buffer 1220, an X-decoder 1230, a Y-decoder 1240, a sense amplifier and a write driver 1250, Circuitry 1260.

The memory cell array 1210 includes a plurality of memory cells, and each of the plurality of memory cells is connected to a plurality of word lines WL and a plurality of bit lines BL. Each of the plurality of memory cells may be located at a point where the word line and the bit line intersect. Illustratively, each of the plurality of memory cells may include a storage capacitor and an access transistor.

The address buffer 1220 can receive the address ADD from the module controller 110 (see FIG. 2) and temporarily store the received address. Illustratively, the address buffer 1220 may provide the row address ADD_row of the received address ADD to the X-decoder 1230 and provide the column address ADD_col to the Y-decoder 1240 .

The X-decoder 1230 is connected to the memory cell array 1210 through a plurality of word lines WL. The X-decoder 1230 is responsive to a row address strobe (RAS) signal from the module controller 110 (see FIG. 2) to generate at least one word of the plurality of word lines WL Line can be activated.

The Y-decoder 1240 may receive the column address ADD_col from the address buffer 1220. Y-decoder 1240 may control sense amplifier and write driver 1250 based on column address ADD_col in response to a column address strobe (CAS) signal.

The sense amplifier and write driver 1250 is coupled to the memory cell array 1210 via a plurality of bit lines BL. The sense amplifier and write driver 1250 may sense a voltage change of the plurality of bit lines BL. Or the sense amplifier and write driver 1250 may control the voltages of the plurality of bit lines BL based on the data received from the input / output circuit 1260.

The input / output circuit 1260 can receive data from the sense amplifier and write driver 1250 and output the received data through the memory data line MDQ (or the data line DQ). Or input / output circuit 1260 can receive data via the memory data line MDQ (or data line DQ) and deliver the received data to the sense amplifier and write driver 1250.

Illustratively, the address ADD may be an address contained in the VM command / address CA_v provided from the module controller 110 (see FIG. 2). The row address strobe RAS and the column address strobe CAS may be signals included in the VM command / address CA_v provided from the module controller 110 (see FIG. 2).

26 is a diagram illustrating a server system to which a non-volatile memory module according to the present invention is applied. Referring to FIG. 26, the server system 2000 may include a plurality of server racks 2100. Each of the plurality of server racks 2100 may include a plurality of non-volatile memory modules 2200. The plurality of nonvolatile memory modules 2200 may be directly connected to the processors included in each of the plurality of server racks 2100. For example, a plurality of non-volatile memory modules 2200 may take the form of dual in-line memory modules and may be mounted in a DIMM socket electrically connected to the processor to communicate with the processor. Illustratively, a plurality of non-volatile memory modules 2200 may be used as storage in the server system 2000. Illustratively, the plurality of non-volatile memory modules 2200 may be the non-volatile memory module described with reference to Figs. 1-25 or may operate based on the method of operation.

27 is a block diagram illustrating an example of a user system to which a nonvolatile memory module according to the present invention is applied. Referring to FIG. 27, the user system 3000 may include a processor 3001 and a plurality of memories 3110 to 3140.

The processor 3001 may include a memory controller 3002. The memory controller 3002 can communicate with the plurality of memories 3110 to 3140 via the bus 3003. Illustratively, the bus 3003 may include a dedicated bus shared with each of the plurality of memories 3110 - 3140 or a shared bus shared with the plurality of memories 3110 - 3140. Illustratively, the bus 3003 may include at least one of a data line DQ, a memory data line MDQ, and a tag data line TDQ, described with reference to FIGS.

Illustratively, at least some of the plurality of memories 3110 through 3140 may be non-volatile memory modules as described with reference to Figs. 1-26, or may operate based on the method of operation described with reference to Figs. 1-26 .

Alternatively, at least some of the plurality of memory modules 3110-310 may include non-volatile memory, and the remaining portions may include volatile memory. A memory module including a volatile memory may be used as a cache memory of a memory module including a non-volatile memory. That is, as described with reference to FIGS. 1 to 26, some of the plurality of memory modules 3110 to 3140 may be used as the main memory of the user system 3000, and others may be used as the cache memory. The memories used as cache memory may be the volatile memory described with reference to Figs. 1-26 or may operate as the volatile memory described with reference to Figs. 1-26.

Illustratively, the memory controller 3002 may be the module controller or controller described with reference to Figs. 1-26, or it may operate with the module controller or controller described with reference to Figs. 1-26.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the claims.

10: User system
100: Nonvolatile memory module
101: Processor
110: Module controller
120: heterogeneous memory device
121: volatile memory
122: Nonvolatile memory controller
123: nonvolatile memory
130: DB
140: Serial Presence Detection Chip (SPD)
CA: Module command / address
CA_v: VM command / address
CA_n: NVM command / address
TAG: Tag
DQ: Data line
TDQ: Tag data line
MDQ: memory data line

Claims (10)

A nonvolatile memory;
A volatile memory of said non-volatile memory, said volatile memory including tag information for stored data;
A controller configured to control the non-volatile memory; And
Receiving a command and an address from an external device and sending a first command and address to the volatile memory via a first bus in response to the received command address and sending a second command and address to the controller via a second bus, And a module controller for providing the module controller with the module controller. The method according to claim 1,
Wherein the tag information includes at least a part of addresses received from the external device. 3. The method of claim 2,
Wherein at least some of the received addresses are part of a row address of the received addresses. The method according to claim 1,
Wherein the volatile memory comprises a plurality of volatile memory chips,
Wherein at least one of the plurality of volatile memory chips is a tag-dedicated volatile memory chip that stores the tag information, and the remaining volatile memory chips store data. 5. The method of claim 4,
Wherein the at least one tag dedicated volatile memory chip shares a tag data line with the module controller and the controller and the remaining volatile memory chip is configured to share a memory data line with the controller. 5. The method of claim 4,
Wherein the plurality of volatile memory chips operate in response to a first command and an address received via the first bus. 5. The method of claim 4,
Wherein the at least one tag volatile memory chip further comprises an error correction code of data corresponding to the tag information, an error correction code of the tag information, and dirty information of data corresponding to the tag information. Memory modules. The method according to claim 1,
And a tag control circuit sharing the tag data line with the volatile memory. 9. The method of claim 8,
The tag control circuit receives a tag via the tag data line, receives the address from the module controller, and outputs cache information for a cache hit or cache miss by comparing at least a portion of the received address with the tag Wherein the nonvolatile memory module is a nonvolatile memory module. A first memory;
A second memory that is a cache memory of the first memory; And
And a memory controller configured to share a data bus with the first memory and the second memory and to control the first and second memories via the bus,
Wherein the second memory comprises a tag only memory configured to store a tag for data stored in the second memory.

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