KR102513913B1 - Nonvolatile memory module and memory system - Google Patents

Abstract

A nonvolatile memory module according to an embodiment of the present invention includes a nonvolatile memory, a volatile memory that is a cache memory of the nonvolatile memory, a controller configured to share a memory data line with the volatile memory and control the nonvolatile memory, and an external device. In response to the module write command and the first address from, transfer a first read command and a first address to the volatile memory through a first bus, and transfer a first write command and a first address to the controller through a second bus. It includes a module controller that

Description

Non-volatile memory module and memory system {NONVOLATILE MEMORY MODULE AND MEMORY SYSTEM}

The present invention relates to semiconductor memories, and more particularly to nonvolatile memory modules and memory systems.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si, silicon), germanium (Ge, Germanium), gallium arsenide (GaAs), and indium phosphide (InP). am. Semiconductor memory devices are largely classified into volatile memory devices and nonvolatile memory devices.

A volatile memory device is a memory device in which stored data is lost when power supply is cut off. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A nonvolatile memory device is a memory device that maintains stored data even when power supply is cut off. Non-volatile memory devices include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable and Programmable ROM (EEPROM), Flash memory devices, Phase-change RAM (PRAM), Magnetic RAM (MRAM) ), Resistive RAM (RRAM), and Ferroelectric RAM (FRAM).

In particular, since DRAM has a fast response speed and a fast operating speed, it is widely used as a main memory of a system. However, since DRAM is a volatile memory in which data is lost when power is cut off, a separate device is required to preserve data stored in the DRAM. In addition, since DRAM uses a capacitor to store data, the size of a unit cell is large, and as a result, it is difficult to increase DRAM capacity in a limited area.

An object of the present invention is to provide a nonvolatile memory module and a memory system having a large capacity and high performance by using a nonvolatile memory and a volatile memory.

A nonvolatile memory module according to an embodiment of the present invention includes a nonvolatile memory, a volatile memory that is a cache memory of the nonvolatile memory, a controller configured to share a memory data line with the volatile memory and control the nonvolatile memory; and transmits a first read command and the first address to the volatile memory through a first bus in response to a module write command and a first address from an external device, and transmits a first write command and the first address through a second bus. 1 address to the controller, the volatile memory outputs a first tag and first data in response to the first read command and the first address, and the controller controls the first write command. In response to a command and the first address, the first data may be selectively programmed into the nonvolatile memory based on the first tag and the first address.

As an embodiment, the controller shares a tag data line with the volatile memory, receives the first tag through the tag data line, and receives the first data through the memory data line.

As an embodiment, a timing at which the first read command and the first address are transmitted to the volatile memory by the module controller and a timing at which the first write command and the first address are transmitted to the controller are different from each other. to be

In an embodiment, the nonvolatile memory module is disposed between the memory data line and the data line, is connected to the external device through the data line, and controls the memory data line and the data line according to the control of the module controller. It further includes a data buffer to drive.

A nonvolatile memory module according to an embodiment of the present invention includes a nonvolatile memory, a volatile memory that is a cache memory of the nonvolatile memory, a controller configured to share a memory data line with the volatile memory and control the nonvolatile memory; and transmits a first write command and the first address to the volatile memory through a first bus in response to a module read command and a first address from an external device, and transmits a first read command and the first address through a second bus. 1 address to the controller, wherein the controller outputs first data from the nonvolatile memory through the memory data line in response to the first read command and the first address; The volatile memory may receive the first data through the memory data line and write the first data in response to the first write command and the first address.

As an embodiment, the first data may be provided to the external device through the memory data line.

As an embodiment, the module controller transmits the first read command and the first address to the controller, and transmits the first write command and the first address to the volatile memory after a predetermined time has elapsed. It is characterized by doing.

A nonvolatile memory module according to an embodiment of the present invention includes a nonvolatile memory, a volatile memory that is a cache memory of the nonvolatile memory, a controller configured to share a memory data line with the volatile memory and control the nonvolatile memory; and a module controller for transmitting a first read command and the first address to the volatile memory through a first bus in response to a module read command and a first address from an external device, and controlling the module with the controller through a second bus. wherein the volatile memory outputs first data and a first tag in response to the first read command and the first address, and the controller converts the first data to the fire based on the first tag. Selectively program in volatile memory.

A memory system according to an embodiment of the present invention shares a data bus with a first memory, a second memory that is a cache memory of the first memory, and the first memory and the second memory, and the data bus through the data bus. A memory controller configured to exchange data with first and second memories, the second memory outputs cache information under the control of the memory controller, and the first memory performs the cache information based on the cache information. It is characterized in that data from the second memory is selectively programmed.

As an embodiment, the first memory is a non-volatile memory module, and the second memory is a volatile memory module.

As an embodiment, the first memory may output data according to data of the memory controller, and the second memory may selectively write data from the first memory according to control of the memory controller.

A memory system according to an embodiment of the present invention shares a data bus with a first memory, a second memory that is a cache memory of the first memory, and the first memory and the second memory, and the data bus through the data bus. and a memory controller configured to exchange data with first and second memories, wherein the memory controller selectively transfers data from the second memory to the first memory based on cache information from the second memory. It is characterized by writing.

According to the present invention, a nonvolatile memory module having a large capacity and high performance using a nonvolatile memory and a volatile memory is provided. A non-volatile memory module is used as the main memory of the system, thereby providing a non-volatile memory module and memory system with improved performance and reduced cost.

1 is a block diagram exemplarily showing a user system according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the nonvolatile memory module of FIG. 1 in detail.
FIG. 3 is a flowchart illustrating a write operation of the nonvolatile memory module of FIG. 2 .
4 is a timing diagram for explaining the operation method of FIG. 3 in detail.
FIG. 5 is a flowchart illustrating a read operation of the nonvolatile memory module 100 of FIG. 2 .
6 is a timing diagram for explaining the read operation of FIG. 5 in detail.
7 is a flowchart illustrating another read operation of the nonvolatile memory module of FIG. 2 .
8 is a timing diagram for explaining the read operation of FIG. 7 in detail.
FIG. 9 is a diagram for explaining a cache structure of the volatile memory of FIG. 2 .
FIG. 10 is a flowchart illustrating the operation of a controller of the nonvolatile memory module of FIG. 2 .
FIG. 11 is a block diagram for explaining in detail the operating method shown in FIG. 10 .
12 is a timing diagram for explaining in detail the operation method shown in FIGS. 10 and 11 .
13 is a flowchart illustrating operations of the controller of FIG. 11 according to another embodiment.
14 is a flowchart showing other operations of the nonvolatile memory module of FIG. 2 .
15 is a block diagram for explaining the operation of FIG. 14 in detail.
16 is a block diagram showing another example of the nonvolatile memory module of FIG. 2 .
FIG. 17 is a diagram for explaining the operation of the cache manager of FIG. 16 .
FIG. 18 is a timing diagram for explaining the operation of the nonvolatile memory module of FIG. 16 .
19 is a flowchart showing other operations of the nonvolatile memory module of FIG. 2 .
20 is a timing diagram for explaining the operation of FIG. 19 in detail.
21 is a block diagram exemplarily showing a nonvolatile memory included in a nonvolatile memory module according to the present invention.
22 is a circuit diagram exemplarily showing a first memory block among memory blocks included in a nonvolatile memory of a nonvolatile memory module according to the present invention.
23 is a block diagram exemplarily showing a volatile memory of a nonvolatile memory module according to the present invention.
24 is a diagram exemplarily showing a server system to which a nonvolatile memory module according to the present invention is applied.
25 is a block diagram exemplarily showing a user system to which a nonvolatile memory module according to the present invention is applied.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, details such as detailed configurations and structures are provided merely to facilitate a general understanding of embodiments of the present invention. Therefore, modifications of the embodiments described herein may be made by those skilled in the art without departing from the spirit and scope of the present invention. Moreover, descriptions of well-known functions and structures are omitted for clarity and conciseness. The terms used in the text are terms defined in consideration of the functions of the present invention, and are not limited to specific functions. Definitions of terms may be determined based on the details described in the detailed description.

Modules in the following drawings or detailed description may be connected with other components other than those shown in the drawings or described in the detailed description. Connections between modules or components may be direct or non-direct, respectively. The connection between the modules or components may be a communication connection or a physical connection, respectively.

1 is a block diagram exemplarily showing a user system according to an embodiment of the present invention. Referring to FIG. 1 , a user system 10 includes nonvolatile memory modules 100, a processor 101, a chipset 102, a graphics processing unit 103, an input/output device 104, and a storage device 105. include Illustratively, the user system 10 is a computing system such as a computer, a laptop computer, a server, a workstation, a portable communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a smart phone, or a wearable device. can be

The user system 10 includes a nonvolatile memory module 100 , a processor 101 , a chipset 102 , a graphics processing unit 103 , an input/output device 104 , and a storage device 105 .

The processor 101 may control overall operations of the user system 100 . The processor 101 may perform various operations performed in the user system 100 and process data.

The nonvolatile memory module 100 may be directly connected to the processor 101 . For example, the nonvolatile memory module 100 may have a dual in-line memory module (DIMM) form, and the nonvolatile memory module 100 is directly connected to the processor 101. It is installed in the DIMM socket and can communicate with the processor 101 . For example, the nonvolatile memory module 100 may communicate with the processor 101 based on the NVDIMM protocol.

The nonvolatile memory module 100 may be used as a main memory or operating memory of the processor 101 . The nonvolatile memory module 100 may include nonvolatile memory and volatile memory. Non-volatile memory includes ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), flash memory, PRAM (Phase-change RAM), MRAM (Magnetic RAM), A memory such as a resistive RAM (RRAM) or a ferroelectric RAM (FRAM), in which data is not lost even when power supply is cut off, may be included. Volatile memory may include memory in which data is lost when power is cut off, such as static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM).

Exemplarily, the nonvolatile memory of the nonvolatile memory module 100 is used as a main memory of the user system 10 or the processor 101, and the volatile memory is used by the user system 10, the processor 101, Alternatively, it may be used as a cache memory of the nonvolatile memory module 100.

The chipset 102 is electrically connected to the processor 101 and can control hardware of the user system 10 according to the control of the processor 101 . For example, the chipset 102 may be connected to the GPU 103 , the input/output device 104 , and the storage device 105 through main buses and serve as a bridge for the main buses.

The GPU 103 may perform a series of arithmetic operations to output image data of the user system 10 . Illustratively, the GPU 103 may be mounted in the processor 101 in the form of a system-on-chip.

The input/output device 104 includes various devices that input data or commands to the user system 10 or output data to the outside. For example, the input/output device 104 may include a keyboard, keypad, button, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, piezoelectric element, temperature sensor, biometric sensor, and the like. It may include user input devices and user output devices such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, a motor, and the like.

The storage device 105 can be used as a mass storage medium for the user system 10 . The storage device 105 may include mass storage media such as hard disk drives, SSDs, memory cards, and memory sticks.

FIG. 2 is a block diagram showing the nonvolatile memory module of FIG. 1 in detail. 1 and 2, the nonvolatile memory module 100 includes a module controller 110 (module controller; Ram Control Device), a heterogeneous memory device 120, a data buffer 130, and a serial presence detection chip ( 140) (SPD chip; Serial Presence Detect chip).

The module controller 110 may receive a command/address CA from the processor 101 and control the heterogeneous memory device 120 in response to the received command/address CA. For example, the module controller 110 may provide the command/address CA_n and the command/address CA_v to the heterogeneous memory device 120 in response to the command/address CA from the processor 101. .

For example, the command/address CA_n is a command/address for controlling the nonvolatile memory 123 included in the heterogeneous memory device 120, and the command/address CA_v is included in the heterogeneous memory device 120. may be a command/address for controlling the volatile memory 121.

Hereinafter, for concise description, the command/address CA provided from the processor 101 is referred to as a 'module command/address', and the command/address CA_v provided from the module controller 110 to the volatile memory 121 ) is referred to as a 'Volatile Memory (VM) command/address', and the command/address (CA_n) provided from the module controller 110 to the NVM controller 122 is referred to as a 'Nonvolatile Memory (NVM) command/address'.

Illustratively, the NVM command/address CA_n and the VM command/address CA_v may be provided through a different command/address bus.

The heterogeneous memory device 120 includes a volatile memory 121 , an NVM controller 122 , and a nonvolatile memory 123 . The volatile memory 121 may operate in response to a VM command/address CA_v from the module controller 110 . The volatile memory 121 may output data and the tag TAG through the memory data line MDQ and the tag data line TDQ in response to the VM command/address CA_v. The volatile memory 121 may write data and tags respectively received through the memory data line MDQ and the tag data line TDQ according to the VM command/address CA_v.

The NVM controller 122 may operate in response to the NVM command/address CA_n from the module controller 110 . For example, the NVM controller 122 programs data received through the memory data line MDQ into the nonvolatile memory 123 or nonvolatile memory 123 according to the NVM command/address CA_n from the module controller 110. Data programmed in the volatile memory 123 may be output through the memory data line MDQ.

The NVM controller 122 may perform various operations for controlling the nonvolatile memory 123 . For example, the NVM controller 122 may perform operations such as garbage collection, wear leveling, and address conversion in order to efficiently use the nonvolatile memory 123 . Illustratively, the NVM controller 122 may further include elements such as an error correction circuit and a randomizer.

For example, the volatile memory 121 and the NVM controller 122 may share the same memory data line MDQ.

For example, the volatile memory 121 and the module controller 110 may share the tag data line TDQ with each other. Alternatively, the volatile memory 121 , the NVM controller 122 , and the module controller 110 may share the tag data line TDQ with each other. The NVM controller 122 may output the tag TAG through the tag data line TDQ.

The data buffer 130 may receive data through the memory data line MDQ and provide the received data to the processor 101 through the data line DQ. Alternatively, the data buffer 130 may receive data through the data line DQ and output the received data through the memory data line MDQ. Illustratively, the data buffer 130 may operate in response to control (eg, a buffer command (not shown)) of the module controller 110 . Illustratively, the data buffer 130 may serve to distinguish between a signal on the memory data line MDQ and a signal on the data line DQ. Alternatively, the data buffer 130 may serve to block a signal between the memory data line MDQ and the data line DQ. That is, the signal of the memory data line MDQ does not affect the data line DQ due to the data buffer 130 or the signal of the data line DQ due to the data buffer 130 affects the memory data line MDQ. signal may not be affected.

Illustratively, the memory data line MDQ may be a data transmission path between components included in the nonvolatile memory module 100 (eg, a volatile memory, a nonvolatile memory, a data buffer, etc.), and data The line DQ may be a data transmission path between the nonvolatile memory module 100 and the processor 101 . The tag data line TDQ may be a transmission path for transmitting and receiving the tag TAG.

For example, each of the memory data line MDQ, data line DQ, and tag data line TDQ may include a plurality of wires. In addition, although not shown in the drawing, the memory data line MDQ, data line DQ, and tag data line TDQ include a memory data strobe line MDQS, a data strobe line DQS, and a tag data line, respectively. A strobe line (TDQS) may be included. Hereinafter, for brevity of the drawing, reference numbers and configurations of the data strobe line MDQS, the data strobe line DQS, and the tag data strobe line TDQS are omitted. However, the scope of the present invention is not limited thereto, and components connected to the memory data line (MDQ), data line (DQ), and tag data line (TDQ) include a data strobe line (MDQS) and a data strobe line (DQS). ), and data or tags can be transmitted/received in synchronization with signals of the tag data strobe line (TDQS).

The SPD 140 may be an Electrically Erasable Programmable Read-Only Memory (EEPROM). The SPD 140 may include initial information or device information DI of the nonvolatile memory module 100 . For example, the SPD 140 may include device information DI such as the module type, module configuration, storage capacity, module type, and execution environment of the nonvolatile memory module 100 . When the user system 10 including the nonvolatile memory module 100 is booted, the processor 101 reads the device information DI from the SPD 140 and recognizes the nonvolatile memory module 100 based on this. can do. The processor 101 may control the nonvolatile memory module 100 based on device information DI read from the SPD 140 .

Hereinafter, for concise description, it is assumed that the volatile memory 121 is a DRAM and the nonvolatile memory 123 is a NAND flash memory. However, the scope of the present invention is not limited thereto, and the volatile memory 121 may include other types of random access memories, and the nonvolatile memory 123 may include other types of nonvolatile memory devices. .

For example, the volatile memory 121 may include a plurality of volatile memory chips, and each volatile memory chip may be implemented as a separate chip or a separate package. Each of the volatile memory chips may be connected to the module controller 110 or the NVM controller 122 through different memory data lines or tag data lines.

For example, the processor 101 may use the nonvolatile memory 123 of the nonvolatile memory module 100 as a main memory. That is, the processor 101 may recognize the storage space of the nonvolatile memory 123 as a main memory area. The volatile memory 121 may operate as a cache memory of the processor 101 and the nonvolatile memory 123 . For example, the volatile memory 121 may be used as a write-back cache. That is, in response to the module command/address (CA) from the processor 101, the module controller 110 determines a cache hit or a cache miss, and the volatile memory 121 or the nonvolatile memory 123 is transferred according to the determination result. You can control it.

Exemplarily, a cache hit refers to a case in which data corresponding to a module command/address (CA) received from the processor 101 is stored in the volatile memory 121 . A cache miss refers to a case where data corresponding to the module command/address CA received from the processor 101 is not stored in the volatile memory 121 .

Illustratively, the module controller 110 may determine whether a cache hit or a cache miss is based on the tag TAG. The module controller 110 may determine whether there is a cache hit or a cache miss by comparing the module command/address (CA) and the tag (TAG) received from the processor 101 .

For example, the tag TAG may include a part of an address corresponding to data stored in the volatile memory 121 . Illustratively, the module controller 110 may exchange a tag TAG with the volatile memory 121 through the tag data line TDQ. For example, when data is written in the volatile memory 121 , a tag corresponding to the data may be written in the volatile memory 121 together under the control of the module controller 110 .

For example, the volatile memory 121 and the nonvolatile memory 123 may have a direct mapping relationship of n:1 (where n is a natural number). That is, the volatile memory 121 may be a direct mapped cache of the nonvolatile memory 123 . For example, the first volatile storage area of the volatile memory 121 may correspond to the first to nth nonvolatile storage areas of the nonvolatile memory 123 . In this case, each of the first volatile storage area and the first to nth nonvolatile storage areas may have the same size as each other. Exemplarily, the first volatile storage area may further include an area for storing additional information (eg, tag, ECC, dirty information, etc.).

Although not shown in the drawing, the nonvolatile memory module 100 may further include a separate memory (not shown). A separate memory (not shown) may store information such as data, programs, and software used in the NVM controller 122 . For example, a separate memory may store information such as a mapping table managed by the NVM controller 122 and FTL. Alternatively, the separate memory may be a buffer memory for temporarily storing data read from the nonvolatile memory 123 or data to be stored in the nonvolatile memory 123 .

Hereinafter, a write operation and a read operation of the nonvolatile memory module 100 will be described in detail with reference to FIGS. 3 to 8 . Hereinafter, for concise description, components related to the volatile memory 121 (eg, data, tags, commands/addresses, etc.) are expressed using a reference symbol of '_v'. For example, a VM command/address output from the module controller 110 to control the volatile memory 121 is expressed as 'CA_v', and output from the volatile memory 121 under the control of the module controller 110 Data is expressed as 'DT_v'. More specifically, a VM write command for writing data into the volatile memory 121 is expressed as 'WR_v', and a VM read command for reading data from the volatile memory 121 is expressed as 'RD_v'.

Similarly, components related to the nonvolatile memory 123 (eg, data, tags, commands/addresses, etc.) are expressed using a reference symbol of '_n'. For example, an NVM command/address output from the module controller 110 to control the nonvolatile memory 123 is expressed as 'CA_n', and is transmitted from the nonvolatile memory 121 under the control of the module controller 110. The output data is expressed as 'DT_n'. More specifically, an NVM write command for writing data into the nonvolatile memory 123 is expressed as 'WR_n', and an NVM read command for reading data from the nonvolatile memory 123 is expressed as 'RD_n'. .

FIG. 3 is a flowchart illustrating a write operation of the nonvolatile memory module of FIG. 2 . Referring to FIGS. 1 to 3 , in step S11 , the processor 101 transmits a module write command and addresses WR and ADD to the nonvolatile memory module 100 . For example, the processor 101 transmits a module write command and addresses WR and ADD to the nonvolatile memory module 100 to write write data DT_w in the nonvolatile memory module 100 . For example, the module write command and addresses WR and ADD may include an address ADD corresponding to the write data DT_w. The address ADD corresponding to the write data may be a logical address or a memory address corresponding to a part of the storage space of the nonvolatile memory module 100 , that is, the storage space of the nonvolatile memory 123 .

In step S12 , the nonvolatile memory module 100 may perform a read operation on the volatile memory 121 in response to the received module write command and addresses WR and ADD. For example, the nonvolatile memory module 100 may read data and a tag TAG from an area corresponding to the received address ADD or a part of the received address ADD among the areas of the volatile memory 121 . . Exemplarily, the nonvolatile memory module 100 may determine whether a cache hit or a cache miss occurs by comparing the read tag TAG and the address ADD.

In step S13, the nonvolatile memory module 100 may selectively perform a flush operation based on the result of the read operation in step S12. For example, when the result of the read operation in step S12 indicates a cache miss, the nonvolatile memory module 100 may perform a flush operation so that data read from the volatile memory 121 is stored in the nonvolatile memory 123. there is. Illustratively, as described with reference to FIG. 2 , the NVM controller 122 that controls the nonvolatile memory 123 and the volatile memory 121 share a memory data line MDQ. That is, when the voltage of the memory data line MDQ is driven by data read from the volatile memory 121, the NVM controller 122 that controls the nonvolatile memory 123 outputs the volatile memory through the memory data line MDQ. Data read from (121) can be received (or sensed). The NVM controller 122 may program the received data into the nonvolatile memory 123 .

For example, when the result of the read operation of step S12 indicates a cache hit, the nonvolatile memory module 100 may not perform a flush operation. Alternatively, when the result of the read operation of step S12 indicates a cache hit and the read data is dirty data, the nonvolatile memory module 100 may perform a flush operation.

Illustratively, operations such as a flush operation of the nonvolatile memory module 100 , cache hit or cache miss determination, and dirty data determination may be performed by the NVM controller 122 .

In step S14 , the processor 101 may transmit write data DT_w to the nonvolatile memory module 100 . Illustratively, after a predetermined time has elapsed from step S11, the operation of step S14 may be performed. That is, the processor 101 may transmit the module write command and addresses WR and ADD, and may transmit the write data DT_w to the nonvolatile memory module 100 after a predetermined time elapses. In this case, the predetermined time may be write latency (WL). For example, the write latency (WL) may be a predetermined time or clock period according to the operating characteristics of the nonvolatile memory module 100 . Information on the write latency (WL) may be stored in the SPD 140 and provided to the processor 101 as device information (DI). The processor 101 may transmit write data DT_w based on the device information DI.

In step S15 , the nonvolatile memory module 100 may write or program the received write data DT_w into the volatile memory 121 or the nonvolatile memory 133 .

4 is a timing diagram for explaining the operation method of FIG. 3 in detail. By way of example, the size and timing of commands, addresses, data, tags, etc. of the technical concept of the present invention are not limited to the timing diagram shown in FIG. 4 .

1 to 4 , the nonvolatile memory module 100 receives a module write command and first addresses WR and ADD1 from the processor 101 . The module controller 110 of the nonvolatile memory module 100 outputs an NVM command/address CA_n and a VM memory command/address CA_n in response to the received module write command and the first addresses WR and ADD1. can do. At this time, the NVM command/address CA_n includes an NVM write command and first addresses WR_v and ADD1, and the VM command/address CA_v includes a VM read command, first addresses RD_v and ADD1, and VM write It may include a command and a first address (WR_v, ADD1).

In response to the VM read command RD_v, the volatile memory 121 of the nonvolatile memory module 100 stores data DT_v and tags stored in an area of the volatile memory 121 corresponding to the first address ADD1. TAG_v) can be output. For example, as described above, the volatile memory 121 may output the data DT_v through the memory data line MD by driving the voltage of the memory data line MDQ based on the data DT_v. The volatile memory 121 may output the tag TAG through the tag data line TDQ by driving the voltage of the tag data line TDQ based on the tag TAG.

The processor 101 may output write data DT_w through the data line DQ. The nonvolatile memory module 100 provides the write data DT_w received through the data line DQ to the volatile memory 121 or the NVM controller 122 through the memory data line MDQ, and write data DT_w ) (or the first address ADD1) and the corresponding tag TAG_w may be provided to the volatile memory 121 through the tag data line TDQ. The volatile memory 121 or the NVM controller 122 may perform a write operation or a program operation based on the received signals.

Although not shown, a flush operation may be selectively performed according to the tag TAG_v read from the volatile memory 121 .

FIG. 5 is a flowchart illustrating a read operation of the nonvolatile memory module 100 of FIG. 2 . Referring to FIGS. 1, 2, and 5 , in step S21, the processor 101 transmits a module read command and addresses RD and ADD to the nonvolatile memory module 100.

In step S21 , the nonvolatile memory module 100 performs a read operation on the volatile memory 121 in response to the module read command and addresses RD and ADD. For example, the module read commands and addresses RD and ADD may include a read command for reading data stored in the nonvolatile memory module 100 and a read address corresponding to the read data. The nonvolatile memory module 100 may read data and tags stored in an area corresponding to a read address among areas of the volatile memory 121 .

In step S22, the nonvolatile memory module 100 may determine a cache hit or cache miss based on the read result. As described above, a tag (TAG) contains some information of an address. The nonvolatile memory module 100 may determine a cache hit or cache miss by comparing the received read address and the tag (TAG). When part of the received address and the tag TAG match, the nonvolatile memory module 100 determines it as a cache hit, and when the part of the received address and the tag TAG do not match, the nonvolatile memory module 100 ( 100) is determined as a cache miss.

By way of example, a read operation when it is determined as a cache miss will be described with reference to FIGS. 7 and 8 .

When it is determined as a cache hit, the nonvolatile memory module 100 transmits data read from the volatile memory 121 and cache information (INFO) to the processor 101 in step S24. The cache information INFO includes information on whether output data is a cache hit or a cache miss. The processor 101 may determine whether the data DT_v received through the cache information INFO is valid data. That is, since the nonvolatile memory module 100 provides information on the cache hit H as the cache information INFO, the processor 101 can recognize that the received data is valid data.

Illustratively, the operation of step S24 may be performed after a predetermined time has elapsed from step S21. That is, read data may be received from the nonvolatile memory module 100 after the processor 101 transmits the module read command and the addresses RD and ADD and a predetermined time elapses. At this time, the predetermined time may be read latency (RL). The read latency RL may be a predetermined time or a clock cycle according to operating characteristics of the nonvolatile memory module 100 . Information on the read latency (RL) may be stored in the SPD 140 and provided to the processor 101 as device information (DI). The processor 101 may control the nonvolatile memory module based on read latency (RL).

6 is a timing diagram for explaining the read operation of FIG. 5 in detail. Referring to FIGS. 1, 2, 5, and 6 , the nonvolatile memory module 100 receives a module read command and first addresses RD and ADD1 from the processor 101, and responds to the received signals. to output the NVM command/address (CA_n) and the VM command/address (CA_v). At this time, the NVM command/address CA_n may include an NVM read command for reading data stored in the nonvolatile memory 123 and first addresses RD_n and ADD1. The VM command/address CA_v may include a VM read command for reading data stored in the volatile memory 121 and first addresses RD_v and ADD1.

In response to the VM read command and the first addresses RD_v and ADD1, the volatile memory 121 stores data DT_v and tags TAG_v stored in an area corresponding to the first address ADD1 among areas of the volatile memory 121. ) can be output. For example, as described above, the volatile memory 121 outputs the data DT_v through the memory data line MDQ by driving the voltage of the memory data line MDQ based on the data DT_v. can The volatile memory 121 may output the tag TAG_v through the tag data line TDQ by driving the voltage of the tag data line TDQ based on the tag TAG_v.

The module controller 110 may receive the tag TAG_v through the tag data line TDQ and compare the received tag TAG_v with the first address ADD1 to determine whether it is a cache hit or a cache miss.

In case of a cache hit, the nonvolatile memory module 100 outputs the data DT_v read from the volatile memory 131 through the data line DQ, and outputs the cache information INFO including the cache hit H information. can be printed out. The processor 101 may recognize that the data DT_v received through the data line DQ is valid data by receiving the cache information INFO including the cache hit H information.

7 is a flowchart illustrating another read operation of the nonvolatile memory module of FIG. 2 . By way of example, referring to FIG. 7 , a read operation in the case of a cache miss will be described.

Referring to FIGS. 1, 2, 5, and 7 , when the determination result of step S23 indicates that there is a cache miss, the operation of step S25 is performed. In step S25 , the nonvolatile memory module 100 transmits data DT_v read from the volatile memory 121 and cache information INFO to the processor 101 . At this time, the cache information (INFO) will include information about the cache miss (M).

Illustratively, as described above, the operation of step S25 may also be performed after the read latency RL from the time when the module read command and the addresses RD and ADD are received.

In step S26 , the nonvolatile memory module 100 may perform a pre-read operation on the nonvolatile memory 123 . Illustratively, the pre-read operation refers to an operation in which the NVM controller 122 reads data from the nonvolatile memory 123 and stores the read data in a data buffer (not shown) included in the NVM controller 122. Alternatively, the pre-read operation refers to an operation of preparing read data so that the NVM controller 122 can output data from the nonvolatile memory 123 within a read latency (RL) according to a command of the processor 101 . That is, when the pre-read operation of the nonvolatile memory 123 is completed, data from the nonvolatile memory 123 is output within the read latency RL in response to a command from the processor 101 .

Illustratively, the pre-read operation may be performed while the operations of steps S22 to S25 are performed. Alternatively, the pre-read operation may be performed by the NVM controller 122 when it is determined as a cache miss. For example, the NVM controller 122 may receive the first address ADD1 from the module controller 110 and receive the tag TAG through the tag data line TDQ. The NVM controller 122 may determine whether it is a cache hit or a cache miss by comparing the received first address ADD1 and the tag TAG. According to the determination result, the NVM controller 122 may perform a pre-read operation. For example, an operation of determining a cache hit or a cache miss by the NVM controller 122 may be performed after the tag TAG_v is output from the volatile memory 121 .

After the pre-read operation is completed, in step S27, the nonvolatile memory module 100 provides a ready signal R to the processor 101. Illustratively, the ready signal R may be a signal indicating that the nonvolatile memory module 100 has completed a pre-read operation. The ready signal R may be provided through a signal line through which the cache information INFO is transmitted or may be provided through a separate signal line.

In step S28 , the processor 101 may provide a module read command and addresses NRD and ADD to the nonvolatile memory module 100 in response to the ready signal R. For example, the module read command NRD may be different from the module read command RD of step S21. The module read command NRD may be a command/address for reading data from the nonvolatile memory 123 .

In step S29 , the nonvolatile memory module 100 performs a read operation on the nonvolatile memory 123 and a write operation on the volatile memory 121 in response to the module read command and the addresses NRD and ADD. For example, the NVM controller 122 of the nonvolatile memory module 100 may drive the memory data line MDQ based on data prepared in a pre-read operation. The volatile memory 121 may receive data output from the NVM controller 122 (ie, data output from the nonvolatile memory 123) through the memory data line MDQ and write the received data. At this time, the write operation of the volatile memory 121 may be a read caching operation.

In step S2a, the nonvolatile memory module 100 may transmit data DT_n from the nonvolatile memory 123 to the processor 101. For example, the nonvolatile memory module 100 may output data DT_n from the nonvolatile memory 123 through the data line DQ. Illustratively, the operation of step S2a may be performed after a predetermined time from the operation of step S28. The predetermined time may be a read latency (RL'). Illustratively, the read latency (RL') of FIG. 7 may be different from the read latency (RL) of FIG. can be provided as

8 is a timing diagram for explaining the read operation of FIG. 7 in detail. For concise description, detailed descriptions of components overlapping with those described above are omitted.

Referring to FIGS. 1 , 2 , 5 , 7 , and 8 , the nonvolatile memory module 100 receives a module read command and first addresses RD and ADD1 from the processor 101 . The module controller 110 of the nonvolatile memory module 100 provides an NVM read command and first addresses RD_n and ADD1 to the NVM controller 122 in response to the module read command and the first addresses RD and ADD1, , the VM read command and the first addresses RD_v and ADD1 are provided to the volatile memory 121 .

In response to the VM read command and the first addresses RD_v and ADD1, the volatile memory 121 stores data DT_v and tags TAG_v of an area corresponding to the first address ADD1 among areas of the volatile memory 121. can be output through the memory data line MDQ. That is, the volatile memory 121 may drive voltages of the memory data line MDQ and the tag data line TDQ, respectively, based on the data DT_v and the tag TAG_v. Data DT_v on the memory data line MDQ is output through the data line DQ under the control of the module controller 110 and the data buffer 130 .

The module controller 110 may determine whether there is a cache hit or a cache miss by comparing the tag TAG_v output from the volatile memory 121 with the first address ADD1. In case of a cache miss, the module controller 110 may transmit cache information INFO about the cache miss M to the processor 101 . At this time, the processor 101 may recognize that the data DT_v received through the data line DQ is a cache miss M.

The nonvolatile memory module 100 may perform a pre-read operation. Illustratively, the NVM controller 122 responds to the nonvolatile memory read command from the module controller 110 and the first address ADD1 to correspond to the first address ADD1 in the area of the nonvolatile memory 123. You can prepare the data of the area (or store it in a separate data buffer). When the pre-read operation is completed, the module controller 110 may transmit a preparation signal R to the processor 101 . For example, the preparation signal R may be provided to the processor 101 through the same line as the cache information INFO, a separate signal line, or a data line DQ.

In response to the preparation signal R, the processor 101 transmits a module read command and first addresses NRD and ADD1 to the nonvolatile memory module 100. In response to the module read command and the first addresses NRD and ADD1 , the nonvolatile memory module 100 provides the NVM read command and the first addresses RD_n′ and ADD1 to the NVM controller 122 . For example, the NVM read command RD_n according to the module read command NRD may be different from the NVM read command RD_n according to the module read command RD.

For example, each of the module read commands NRD and RD may be a command predefined by a communication protocol between the processor 101 and the nonvolatile memory module 100 .

The NVM controller 122 may output the data DT_n prepared in the pre-read operation through the memory data line MDQ in response to the NVM read command and the first addresses RD_n' and ADD1. For example, the NVM controller 122 may output the tag TAG_n corresponding to the data DT_n through the tag data line TDQ. For example, the tag TAG_n corresponding to the data DT_n may include a part of the first address ADD1 corresponding to the data DT_n. Data DT_n on the memory data line MDQ may be output to the data line DQ under the control of the module controller 110 and the data buffer 130 .

For example, while the data DT_n is being output, the nonvolatile memory module 100 may perform read caching. For example, the module controller 110 may provide a VM write command and first addresses WR_v and ADD1 to the volatile memory 121 in response to the nonvolatile memory read command/address CA_NRD.

For example, the VM write command and the first addresses WR_v and ADD1 may have a predetermined time with the NVM read command and the first addresses RD_n' and ADD1. That is, the VM write command and the first address are synchronized when the NVM controller 122 outputs the data DT_n through the memory data line MDQ in response to the NVM read command and the first addresses RD_n' and ADD1. (WR_v, ADD1) may be provided to the volatile memory 121.

The volatile memory 121 stores data on the memory data line MDQ in an area corresponding to the first address ADD1 among areas of the volatile memory 121 in response to a volatile memory write command and the first addresses WR_v and ADD1. (DT_n) and a tag (TAG_n) on the tag data line (TDQ) can be written. Through the above-described read caching, the cache hit ratio of the nonvolatile memory module 100 may increase.

The structure, write operation, or read operation of the nonvolatile memory module 100 as described above is exemplary and may be modified in various ways without departing from the technical spirit of the present invention.

FIG. 9 is a diagram for explaining a cache structure of the volatile memory of FIG. 2 . For concise description, elements unnecessary to describe the cache structure of the volatile memory 121 are omitted. Also, it is assumed that the storage area of the nonvolatile memory 123 is divided into first to fourth areas AR1 to AR4. The first to fourth areas AR1 to AR4 are logically divided areas, and the storage area of the nonvolatile memory 123 may further include storage spaces other than the first to fourth areas AR1 to AR4. can

Referring to FIGS. 2 and 9 , the volatile memory 121 may have a faster access speed than the nonvolatile memory 123 . That is, by storing some of the data stored in the nonvolatile memory 123 in the volatile memory 121, the access speed according to the request of the module controller 110 or the processor 101 can be improved. For example, the volatile memory 121 may be used as a cache memory of the nonvolatile memory 123 . For example, the volatile memory 121 may store some of the data stored in the nonvolatile memory 123 and may output the stored data according to a request of the module controller 110 or the processor 101 .

For example, the volatile memory 121 may have a direct mapping relationship with the nonvolatile memory 123 . For example, the volatile memory 121 may include a plurality of entries ET01 to ET0n. One entry (ET; Entry) may indicate a storage space that stores data and tags (TAG) in units of cache lines, a data error correction code (ECC_DT), a tag error correction code (ECC_TAG), and dirty information (DRT). there is.

A cache line unit may indicate a minimum access unit according to a request of the module controller 110 or the processor 101 . The volatile memory 121 may have a storage capacity equal to the plurality of entries ET01 to ET0n. The tag TAG may be at least a part of an address corresponding to the data DT_v stored in the same entry. The data error correction code ECC_DT may be an error correction code for the data DT_v stored in the same entry. The tag error correction code ECC_TAG may be an error correction code for a tag TAG stored in the same entry. The dirty information DRT may indicate dirty information about the data DT_v stored in the same entry.

The nonvolatile memory 123 may include first to fourth areas AR1 to AR4. Each of the first to fourth regions AR1 to AR4 may include a plurality of cache lines CL11 to CL1n, CL21 to CL2n, CL31 to CL3n, and CL41 to CL4n, respectively. Illustratively, each of the plurality of cache lines CL11 to CL1n, CL21 to CL2n, CL31 to CL3n, and CL41 to CL4n may indicate a storage space of a data access unit according to a request of the processor 101 or the module controller 110. can

For example, the first area AR1 may include cache lines CL11 to CL1n. Each of the cache lines CL11 to CL1n may correspond 1:1 to each of the plurality of entries ET1 to ETn. That is, the first cache line CL11 may correspond to the first entry ET1, and the second cache line CL12 may correspond to the second entry ET2. The second area AR1 may include cache lines CL21 to CL2n, and each of the cache lines CL21 to CL2n may correspond 1:1 to each of the plurality of entries ET1 to ETn. Similarly, each of the third and fourth regions AR3 and AR4 includes cache lines CL31 to CL3n and CL41 to CL4n, respectively, and each of the cache lines CL31 to CL3n and CL41 to CL4n includes a plurality of entries. may correspond to (ET1 to ETn).

As described above, the volatile memory 121 may have a direct mapping relationship with the nonvolatile memory 123 . The first entry ET1 of the volatile memory 121 corresponds to the cache lines CL11 , CL21 , CL31 , and CL41 of the first to fourth areas AR1 to AR4 , and the first to fourth areas ( The data DT_v stored in any one of the cache lines CL11 , CL21 , CL31 , and CL41 of the AR1 to AR4 may be stored. In other words, the data DT_v stored in the first entry ET1 may correspond to one of the cache lines CL11 , CL21 , CL31 , and CL41 of the first to fourth regions AR1 to AR4 .

The first entry ET1 may include a tag TAG for stored data DT_v. Exemplarily, the tag TAG stores the data DT_v stored in the first entry ET1 in any one of the cache lines CL11, CL21, CL31, and CL41 of the first to fourth areas AR1 to AR4. It may be information about whether it corresponds to the line.

For example, each of the plurality of cache lines CL11 to CL1n, CL21 to CL2n, CL31 to CL3n, and CL41 to CL4n may be identified or selected by an address ADD provided from the processor 101 . That is, at least one of the plurality of cache lines CL11 to CL1n, CL21 to CL2n, CL31 to CL3n, and CL41 to CL4n is selected by the address ADD provided from the processor 101, and the selected cache line An access operation for may be performed.

Each of the plurality of entries ET1 to ETn may be distinguished or selected by at least a part of the address ADD provided from the processor 101 . That is, at least one entry among the plurality of entries ET1 to ETn is selected by at least a part of the address ADD provided from the processor 101, and an access operation on the selected entry may be performed.

The tag TAG may include at least a part or the remaining part of the address ADD provided from the processor 101 . For example, when at least one of the plurality of entries ET1 to ETn is selected by at least a part of the address ADD and the tag TAG_v from the selected entry is included in the address ADD, the cache It can be determined to be a hit (H). Alternatively, when at least one of the plurality of entries ET1 to ETn is selected by at least a part of the address ADD and the tag TAG_v from the selected entry is not included in the address ADD, a cache miss ( M) can be determined.

As described above, since the nonvolatile memory module 100 uses the volatile memory 121 as a cache memory, performance of the nonvolatile memory module 100 is improved. At this time, the nonvolatile memory module 100 may determine whether a cache hit or miss is based on a tag (TAG) stored in the volatile memory 121 .

By way of example, with reference to the following figures, a data transaction method between a volatile memory and a non-volatile memory is described. However, the embodiments described below are merely illustrative for easily explaining the technical idea of the present invention, and the scope of the present invention is not limited thereto.

10 is a flowchart illustrating an operation of an NVM controller of the nonvolatile memory module of FIG. 2 . For concise description, detailed descriptions of the components and operating methods described above are omitted. As an example, the operation method according to the flowchart of FIG. 10 shows a flush operation in a write operation for the nonvolatile memory module 100 .

Referring to FIGS. 2 and 10 , in step S110, the NVM controller 122 may receive the tag TAG through the tag data line TDQ. For example, as described with reference to FIGS. 3 and 4 , the module controller 110 receives a module write command and first addresses WR and ADD1 from the processor 101 and responds to the received signals. Thus, the VM read command and the first addresses RD_v and ADD1 are transmitted to the volatile memory 121 . The volatile memory 121 stores data DT_v stored in an entry corresponding to the first address ADD1 (or a part of the first address ADD1) in response to the VM read command and the first addresses RD_v and ADD1. A tag (TAG_v) can be output. Since the volatile memory 121 and the NVM controller 122 share the tag data line TDQ, the NVM controller 122 receives the tag TAG from the volatile memory 121 through the tag data line TDQ. can do.

In step S120, the NVM controller 122 may determine whether a cache hit or a cache miss is made based on the received tag (TAG). For example, as described above, the tag TAG includes at least a part of the address ADD corresponding to data stored in the volatile memory 121 . That is, the NVM controller 122 may determine whether a cache hit or a cache miss occurs by comparing the address ADD received from the module controller 110 and the tag TAG received through the tag data line TDQ.

When the determination result indicates a cache hit, the NVM controller 122 may not perform a separate operation.

When the determination result indicates a cache miss, in step S130, the NVM controller 122 may fetch the data DT_v on the memory data line MDQ. For example, as described above, the volatile memory 121 controls the voltage of the memory data line MDQ based on the data DT_v in response to the VM read command and the first addresses RD_v and ADD1. can Since the NVM controller 122 and the volatile memory 121 share the memory data line MDQ, the NVM controller 122 may fetch data DT_v on the memory data line MDQ.

In step S140 , the NVM controller 122 may program the fetched data DT_v into the nonvolatile memory 123 . For example, the NVM controller 122 may store the fetched data DT_v in a separate buffer circuit, and program the fetched data into the nonvolatile memory 123 when the size of the fetched data is greater than or equal to a predetermined size. there is.

Illustratively, in the operation method shown in FIG. 10 , operations of steps S110 to S130 may be performed in parallel. For example, the NVM controller 122 simultaneously receives the tag TAG and the data DT_v through the tag data line TDQ and the memory data line MDQ, respectively, and caches the tag based on the received tag TAG. It can determine hit or cache miss. In case of a cache miss, the received data DT_v is programmed into the nonvolatile memory 123, and in case of a cache hit, the received data DT_v is invalidated or a separate operation is performed on the received data DT_v may not

FIG. 11 is a block diagram for explaining in detail the operating method shown in FIG. 10 . 1, 10, and 11, the nonvolatile memory module 100 includes a module controller 110, a volatile memory 121, an NVM controller 122, a nonvolatile memory 123, and a data buffer ( 130) may be included. For concise description, it is assumed that a part of the first address ADD1 provided from the processor 101 corresponds to the first entry ET1 of the volatile memory 121 . For concise description, detailed descriptions of the components described above are omitted. Exemplarily, a broken line shown in FIG. 11 indicates a flow of a tag (TAG_v), dirty information (DRT), or data (DT_v).

The module controller 110 receives a module write command and first addresses WR and ADD1 from the processor 101 and, in response to the received signal, stores the VM read command and the first addresses RD_v and ADD1 in volatile memory ( 121), and the NVM write command and the first addresses WR_n and ADD1 may be provided to the NVM controller 122.

In response to the VM read command and the first addresses RD_v and ADD1, the volatile memory 121 stores data DT_v and a tag TAG_v in the first entry ET1 corresponding to a part of the first address ADD1. , and dirty information (DRT) may be output. For example, the volatile memory 121 may output the data DT_v through the memory data line MDQ, and output the tag TAG_v and dirty information DRT through the tag data line TDQ.

Since the NVM controller 122 shares the memory data line MDQ and the tag data line TDQ with the volatile memory 121, it receives the data DT_v through the memory data line MDQ and transmits the tag data line ( A tag (TAG_v) and dirty information (DRT) may be received through TDQ).

The NVM controller 122 may include a flush manager (FM). The flush manager FM may manage or control a flush operation of data from the volatile memory 121 . For example, the flush manager FM determines whether a cache hit or a cache miss is based on the tag TAG_v received through the tag data line MDQ and the first address ADD1 received from the module controller 110. can be identified. When the determination result indicates a cache miss, the flush manager FM may program the received data DT_v into the nonvolatile memory 123 . Alternatively, the flush manager FM manages the received data DT_v in a separate buffer circuit (not shown), and when the size of data to be flushed is greater than a certain size, the data of the buffer circuit (not shown) is stored in a nonvolatile memory (not shown). 123) can be programmed.

For example, the memory data line MDQ shared between the volatile memory 121 and the NVM controller 122 may be a flush path.

For example, the data buffer 130 may serve to block the data DT_v on the memory data line MDQ so that the data DT_v is not transmitted to the processor 101 . That is, the processor 101 will not be aware of the data transaction between the volatile memory 121 and the NVM controller 122.

12 is a timing diagram for explaining in detail the operation method shown in FIGS. 10 and 11 . For concise description, detailed descriptions of the components described above are omitted. Referring to FIGS. 1 and 11 , the module controller 110 may receive a module write command and first addresses WR and ADD1 from the processor 101 .

The module controller 110 transmits a VM read command and first addresses RD_v and ADD1 to the volatile memory 121 in response to the module write command and the first addresses WR and ADD1, and to the NVM controller 122 The NVM write command and the first addresses WR_v and ADD1 may be transmitted. In this case, a transmission time of the NVM write command and the first addresses WR_v and ADD1 may be different from a transmission time of the VM read command and the first addresses RD_v and ADD1.

For example, since the operation characteristics of the volatile memory 121 and the nonvolatile memory 123 or the NVM controller 122 controlling the nonvolatile memory 123 are different, the time required for a read or write operation may be different. can That is, the time required to read the data DT_v from the volatile memory 121 (eg, VM read latency) and the time required for the NVM controller 122 to fetch the data DT_v (eg, NVM write latency) latency) may be different from each other.

When the NVM write latency is shorter than the VM read latency, the module controller 110 first transmits the VM read command and the first addresses RD_v and ADD1 to the volatile memory 121, and then transmits the NVM write command and the first address (WR_n) may be transmitted to the NVM controller 122. Alternatively, when the NVM write latency is longer than the VM read latency, the module controller 110 first transmits the NVM write command and the first address WR_n to the NVM controller 122, and then transmits the VM read command and the first address ( RD_v, ADD1) can be transferred to the volatile memory 121.

That is, the module controller 110 transmits the VM command/address CA_v and the NVM command/address CA_n to the volatile memory 121 and the NVM controller 122 at different times according to the operating characteristics of each component. By doing so, data output from the volatile memory 121 through the memory data line MDQ can be normally received by the NVM controller 122 .

13 is a flowchart illustrating operations of the NVM controller of FIG. 11 according to another embodiment. Referring to FIGS. 11 and 13 , the NVM controller 122 may perform operations of steps S210 and S220. Operations of steps S210 and S220 are similar to those of steps S110 and S120 of FIG. 10 , so detailed description thereof is omitted.

When the determination result in step S220 indicates a cache miss, in step S230, the NVM controller 122 may determine whether the data DT_v from the volatile memory 121 is dirty data. For example, the data DT_n stored in the volatile memory 121 may not be flushed to the nonvolatile memory 123 after being updated with new data according to a request of the processor 101 . Alternatively, data stored in the non-volatile memory 123 and data corresponding to the data stored in the volatile memory 121 may be different from each other. In this case, the data of the volatile memory 121 will be dirty data. The dirty information DRT may include information on a dirty state of data stored in the same entry ET. That is, the NVM controller 122 may determine a dirty state of the data DT_n of the volatile memory 121 based on the dirty information DRT received through the tag data line TDQ.

If the determination result indicates that the data is not dirty data (ie, clean data), the NVM controller 122 may not perform a separate operation.

If the determination result of step S230 indicates that the data is dirty, the NVM controller 122 may perform a flush operation to ensure data validity. For example, the NVM controller 122 may perform operations of steps S240 and S250. Operations of steps S240 and S250 are similar to those of steps S130 and S140 of FIG. 10 , so detailed description thereof is omitted.

Illustratively, the operations of steps S210 to S240 may be performed in parallel with each other. For example, the NVM controller 122 may receive the tag TAG and the dirty information DRT through the tag data line TDQ and simultaneously receive the data DT_v through the memory data line MDQ. . At the same time, the NVM controller 122 may determine whether there is a cache hit or cache miss based on the received tag (TAG), and determine whether dirty data is present based on the received dirty information (DRT).

Exemplarily, although not shown in the drawing, during a read operation of the nonvolatile memory module 100, a flush operation between the volatile memory 121 and the NVM controller 122 similar to the flush operation in the above-described write operation this can be done For example, as described with reference to FIG. 8 , the module controller 110 receives a module read command and first addresses RD and ADD1 from the processor 101, and in response to the received signals, volatile memory The VM read command and the first addresses RD_v and ADD1 are transmitted to 121 . The volatile memory 121 may output the data DT_v and the tag TAG_v in response to the VM read command and the first addresses RD_v and ADD1. At this time, the NVM controller 122 determines whether there is a cache hit or a cache miss based on the tag TAG_v, and according to the determination result, the data DT_v received through the memory data line MDQ is transferred to the nonvolatile memory ( 123) can be flushed.

14 is a flowchart showing other operations of the nonvolatile memory module of FIG. 2 . As an example, the flush operation of moving or copying data from the volatile memory 121 to the nonvolatile memory 123 has been described with reference to FIGS. 10 to 13 . Hereinafter, a read caching operation in which data is moved from the nonvolatile memory 123 to the volatile memory 121 will be described. For concise description, detailed descriptions of the components described above are omitted.

2 and 14 , in step S310, the nonvolatile memory module 100 may output data DT_n from the nonvolatile memory 123 through the memory data line MDQ. For example, the NVM controller 122 may read data DT_n from the nonvolatile memory 123 and drive the voltage of the memory data line MDQ based on the read data DT_n.

In step S320, the nonvolatile memory module 100 may output the tag TAG_n through the tag data line TDQ. For example, the module controller 110 may generate a tag TAG_n corresponding to the data DT_n based on the address ADD provided from the processor 101 . The module controller 110 may drive the voltage of the tag data line TDQ based on the generated tag TAG_n.

In operation S320 , the nonvolatile memory module 100 may write the tag TAG_n on the tag data line TDQ and the data DT_n on the memory data line MDQ into an entry corresponding to the address ADD. For example, the volatile memory 121 may receive the tag TAG_n through the tag data line TDQ and receive the data DT_n through the memory data line MDQ. The volatile memory 121 may store the received tag TAG_n and data DT_n in an entry corresponding to a part of the address ADD among a plurality of entries.

For example, when a cache miss occurs during a read operation of the nonvolatile memory module 100 and a read operation for the cache miss address is re-performed, the read caching operation described with reference to FIG. 14 may be performed. . Alternatively, the read caching operation described with reference to FIG. 14 may be performed according to a request of the processor 101 .

15 is a block diagram for explaining the operation of FIG. 14 in detail. As an example, referring to FIG. 14 , a read caching operation in the case where a read operation for an address that has a cache miss is re-performed will be described. 1 and 14, the nonvolatile memory module 100 includes a module controller 110, a volatile memory 121, an NVM controller 122, a nonvolatile memory 123, and a data buffer 130. do. For concise description, detailed descriptions of the components described above are omitted.

As described above, when a cache miss occurs in a read operation of the nonvolatile memory module 100, the nonvolatile memory module 100 responds to the cache miss address (eg, the first address ADD1). A preparation signal R indicating that the data DT_n from the nonvolatile memory 123 to be prepared is provided to the processor 101. The processor 101 transmits a module read command and first addresses NRD and ADD1 to the nonvolatile memory module 100 in response to the preparation signal. At this time, the module read command NRD is a command for reading data DT_n from the nonvolatile memory 123 .

The module controller 110 transmits the NVM read command and the first addresses RD_v' and ADD1 to the NVM controller 122 in response to the module read command and the first addresses NRD and ADD1, and transmits the VM write command and 1 address (WR_v, ADD1) can be transferred to the volatile memory 121.

The NVM controller 122 may output data DT_n from the nonvolatile memory 123 through the memory data line MDQ in response to the NVM read command and the first addresses RD_v' and ADD1. For example, the module controller 110 may output the tag TAG_n through the tag data line TDQ in synchronization with the timing at which the data DT_n is output through the memory data line MDQ. For example, the tag TAG_n may include at least a part of the first address ADD1.

The volatile memory 121 includes data DT_n received through the memory data line MDQ and a tag TAG_n received through the tag data line TDQ in response to the VM write command and the first addresses WR_v and ADD1. may be written in the first entry ET1 corresponding to a part of the first address ADD1.

For example, the data buffer 130 may transmit the data DT_n on the memory data line MDQ to the processor 101 through the data line DQ under the control of the module controller 110 .

As described above, since the volatile memory 121 and the NVM controller 122 share the memory data line MDQ, when the data DT_n is output from the NVM controller 122, the data DT_n is volatile. may be written to the memory 121 . That is, the nonvolatile memory module 100 may perform a read caching operation.

16 is a block diagram showing another example of the nonvolatile memory module of FIG. 2 . FIG. 17 is a diagram for explaining the operation of the cache manager of FIG. 16 . FIG. 18 is a timing diagram for explaining the operation of the nonvolatile memory module of FIG. 16 . 1 and 16 to 17, the nonvolatile memory module 200 includes a module controller 210, a volatile memory 221, an NVM controller 222, a nonvolatile memory 223, and a data buffer 230. ) may be included. For concise description, detailed descriptions of the components described above are omitted.

Unlike the nonvolatile memory module 100 of FIG. 2 , the module controller 210 of the nonvolatile memory module 200 of FIG. 16 further includes a cache manager (CM).

The cache manager CM may perform an operation for efficiently managing the volatile memory 221 , which is the cache memory of the nonvolatile memory 223 . For example, when a cache miss occurs during a read operation of the nonvolatile memory module 100, the cache manager CM may manage cache miss address information. Then, when a read operation is performed on the cache miss address, the cache manager CM uses the NVM command/address CA_n and the VM command to output data corresponding to the cache miss address from the nonvolatile memory 223. / Address (CA_v) can be controlled.

Illustratively, the cache manager (CM) may assign and manage transaction IDs (TIDs) for cache miss addresses. For example, as shown in FIG. 16 , the nonvolatile memory module 200 sequentially performs a read operation on the first to sixth addresses ADD1 to ADD6 according to a request of the processor 101. can First, a cache miss may occur in a read operation for the first address ADD1. In this case, the cache manager (CM) assigns a first transaction ID (TID1) to the cache miss first address (ADD1). Thereafter, a cache hit may occur in a read operation for the second address ADD2. In this case, the cache manager (CM) may not perform a separate operation. Thereafter, a cache miss may occur in a read operation for the third address ADD3. In this case, the cache manager (CM) may assign a second transaction ID (TID2) to the third address ADD3 having a cache miss. Similarly, when a cache hit occurs in the read operations to the fourth and fifth addresses ADD4 and ADD5 and a cache miss occurs in the read operation to the sixth address ADD6, the sixth address ADD6 ), a third transaction ID (TID3) may be assigned. The first to third transaction IDs TID1, TID2, and TID3 may be implemented in a monotonically increasing form.

That is, the cache manager (CM) manages cache miss addresses, but assigns a transaction ID to cache miss addresses whenever a cache miss occurs. At this time, the transaction ID may increase monotonically.

For example, the nonvolatile memory module 200 may receive transaction IDs (TIDs) instead of address information from the processor 101 for cache miss addresses. For example, as shown in FIG. 18,

The nonvolatile memory module 200 receives a module read command and first addresses RD and ADD1 from the processor 101, and transmits the NVM read command and the first address ADD1 to the NVM controller in response to the received signals. 222, and provides the VM read command and the first address ADD1 to the volatile memory 221. The volatile memory 221 may output the first data DT_v1 and the first tag TAG_v1 in response to the VM read command and the first address ADD1.

Similarly, the nonvolatile memory module 200 receives the module read command and the second addresses RD and ADD2, and transmits the NVM read command and the second address ADD2 to the NVM controller 222 in response to the received signals. , and provides the VM read command and the second address ADD2 to the volatile memory 221 . The volatile memory 221 may output the second data DT_v2 and the second tag TAG_v2 in response to the VM read command and the second address ADD2.

The first and second data DT_v1 and DT_v2 from the volatile memory 221 may not be data corresponding to the first and second addresses ADD1 and ADD2. That is, a cache miss may occur in a read operation for the first and second addresses ADD1 and ADD2 . In this case, the cache manager CM may assign a first transaction ID TID1 to the first address ADD1 and assign a second transaction ID TID2 to the second address ADD2.

As described above, the NVM controller 222 receives the first and second tags TAG_v1 and TAG_v2, and a cache miss occurs based on the received first and second tags TAG_v1 and TAG_v2. can recognize that it has been done. In this case, the NVM controller 222 may prepare data corresponding to the first and second addresses ADD1 and ADD2 from the nonvolatile memory 223 .

For example, when the NVM controller 222 first prepares the data DT_n1 corresponding to the first address ADD1, the nonvolatile memory module 200 may provide the preparation signal R to the processor 101. there is. The processor 101 may transmit the state read command RD_STS to the nonvolatile memory module 200 in response to the preparation signal R.

The nonvolatile memory module 200 may transmit state information about the transaction ID (TID) to the processor 101 through the memory data line MDQ and data line DQ in response to the read state command RD_STS. . For example, the status read command RD_STS may be a predefined command for reading a specific area, a status register, or a multi-purpose register of the nonvolatile memory module 200 . For example, state information on the transaction ID (TID) may be set in a specific area, a state register, or a multi-purpose register of the nonvolatile memory module 200 . Illustratively, state information on a transaction ID (TID) may be implemented in a bitmap format.

Illustratively, the nonvolatile memory module 200 may transmit information on completion of preparation of the first transaction ID TID1 as state information on the transaction ID TID. The processor 101 may transmit a module read command and a first transaction ID TID1 to the nonvolatile memory module 200 in response to the received status information.

The nonvolatile memory module 200 outputs the data DT_n corresponding to the first transaction ID TID1 from the nonvolatile memory 223 in response to the received module read command and the first transaction ID TID1. Command/address CA_n and VM command/address CA_v can be controlled.

For example, the cache manager (CM) provides the NVM read command and the first addresses (RD_n', ADD1) to the NVM controller 222 in response to the received module read command and the first transaction ID (TID1), The VM write command and the first addresses WR_v and ADD1 may be provided to the volatile memory 121 . That is, the cache manager (CM) receives the transaction ID (TID) from the processor 101, converts the transaction ID (TID) into a corresponding address (ADD) and provides it to the volatile memory 221 and the NVM controller 222 can do.

Each of the volatile memory 221 and the NVM controller 222 may perform the above-described read caching operation in response to received signals.

19 is a flowchart showing other operations of the nonvolatile memory module of FIG. 2 . For concise description, detailed descriptions of the components described above are omitted. Referring to FIGS. 1 , 2 , and 19 , in step S410 , the nonvolatile memory module 100 receives a module read command and an address ADD from the processor 101 .

In step S420, the nonvolatile memory module 100 may determine whether there is a cache miss or a cache hit. For example, as described above, the nonvolatile memory module 100 detects a cache hit or cache miss based on a tag stored in an entry corresponding to a part of the address ADD among a plurality of entries of the volatile memory 121. It can be determined whether

When the determination result indicates a cache hit, in step S430 , the nonvolatile memory module 100 may output data DT_v from the volatile memory 121 and cache information INFO indicating the cache hit.

When the determination result indicates a cache miss, in step S440 , the nonvolatile memory module 100 may output data DT_v from the volatile memory 121 and cache information INFO indicating the cache miss.

Thereafter, in step S450 , the nonvolatile memory module 100 may receive a module read command and address (NCRD, ADD) from the processor 101 . For example, the module read command NCRD may be a command for reading data DT_n from the nonvolatile memory 123 without performing a read caching operation. For example, the access frequency of the data corresponding to the cache miss address ADD may be low or only one access may be performed. In this case, the processor 101 may prevent an unnecessary read caching operation by providing the module read command NCRD to the nonvolatile memory module 100 .

For example, each of the above-described module read commands RD, NRD, and NCRD may be predefined signals or commands according to communication protocols between the processor 101 and the nonvolatile memory module 100 .

In step S460, the nonvolatile memory module 100 may output data DT_n from the nonvolatile memory 123 to the processor 101 without a read caching operation.

20 is a timing diagram for explaining the operation of FIG. 19 in detail. Referring to FIGS. 1 , 2 , and 20 , the module controller 110 may receive a module read command and a first address ADD1 from the processor 101 . Since the operations of the module controller 110 and the volatile memory 121 according to the module read command and the first address ADD1 have been described with reference to FIG. 8 , a detailed description thereof will be omitted.

In a read operation according to the module read command and the first address ADD1, a cache miss M may occur. In this case, the NVM controller 122 prepares the data DT_n corresponding to the first address ADD1, and after the data DT_n is prepared, the module controller 110 transmits the preparation signal R to the processor 101 ) can be provided.

The processor 101 may provide a module read command and first addresses NCRD and ADD1 to the module controller 110 in response to the preparation signal R. For example, the module read command NCRD may be a command for reading data DT_n from the nonvolatile memory 123 without a read caching operation as described above.

The module controller 110 provides the NVM read command and the first addresses RD_n' and ADD1 to the NVM controller 122 in response to the module read command and the first addresses NCRD and ADD1, and the NVM controller 122 may output data DT_n in response to the received signal.

For example, since the module read command NCRD is a command for reading the data DT_n from the nonvolatile memory 123 without a read caching operation, the module controller 110 transfers the data to the volatile memory 121 for the read caching operation. It will not provide the VM write command and first address provided. Also, the module controller 110 will not provide a tag DT_n corresponding to the data DT_n from the nonvolatile memory 123 .

As described above, the nonvolatile memory module 100 may omit the read caching operation according to the request of the processor 101 .

21 is a block diagram exemplarily showing a nonvolatile memory included in a nonvolatile memory module according to the present invention. Referring to FIG. 21 , a nonvolatile memory 1100 includes a memory cell array 1110, an address decoder 1120, a control logic circuit 1130, a page buffer 1140, and an input/output circuit 1150.

The memory cell array 1110 includes a plurality of memory blocks, and each of the plurality of memory blocks includes a plurality of memory cells. Each of the plurality of memory cells may be respectively connected to a plurality of word lines WL. Each of the plurality of memory cells may be a single-level cell (SLC) that stores 1-bit or a multi-level cell (MLC) that stores at least 2-bits.

The address decoder 1120 may receive the address ADDR from the NVM controller 112 (see FIG. 2 ) and decode the received address ADDR. For example, the address ADDR received from the NVM controller 112 may be a physical address indicating a physical location of a storage area of the nonvolatile memory 1100 . The address decoder 1120 may select at least one word line among a plurality of word lines WL based on the decoded address and drive a voltage of the selected word line.

The control logic circuit 1130 receives a command CMD and a control signal CTRL from the NVM controller 112 (see FIG. 2), and in response to the received signals, the address decoder 1120 and the page buffer 1140 , and the input/output circuit 1150 can be controlled.

The page buffer 1140 is connected to the memory cell array 1110 through a plurality of bit lines BL and connected to the input/output circuit 1150 through a plurality of data lines DL. The page buffer 1140 may read data stored in the memory cell array 1110 by sensing voltages of the plurality of bit lines BL. Alternatively, the page buffer 1140 may control voltages of the plurality of bit lines BL based on data received through the plurality of data lines DL.

The input/output circuit 1150 may receive data from the NVM controller 112 (see FIG. 2 ) under the control of the control logic circuit 1130 and transfer the received data to the page buffer 1140 . Alternatively, the input/output circuit 1150 may receive data from the page buffer 1140 and transfer the received data to the NVM controller 112 .

Illustratively, the NVM controller 122 generates an address ADDR, a command CMD, and a control signal CTRL based on the NVM command/address CA_v from the module controller 110 (see FIG. 2). can do.

22 is a circuit diagram exemplarily showing a first memory block among memory blocks included in a nonvolatile memory of a nonvolatile memory module according to the present invention. As an example, a first memory block BLK1 having a 3D structure will be described with reference to FIG. 22 . However, the scope of the present invention is not limited thereto, and other memory blocks may also have a structure similar to that of the first memory block BLK1.

Referring to FIG. 22 , the first memory block BLK1 includes a plurality of cell strings CS11, CS12, CS21, and CS22. The plurality of cell strings CS11 , CS12 , CS21 , and CS22 may be disposed along a row direction and a column direction to form rows and columns.

Each of the plurality of cell strings CS11 , CS12 , CS21 , and CS22 includes a plurality of cell transistors. For example, each of the plurality of cell strings CS11, CS12, CS21, and CS22 includes string select transistors SSTa and SSTb, a plurality of memory cells MC1 to MC8, ground select transistors GSTa and GSTb, and dummy memory cells DMC1 and DMC2. For example, each of the plurality of cell transistors included in the plurality of cell strings CS11 , CS12 , CS21 , and CS22 may be a charge trap flash (CTF) memory cell.

The plurality of memory cells MC1 to MC8 are connected in series and stacked in a height direction that is perpendicular to a plane formed by row and column directions. The string select transistors SSTa and SSTb are connected in series, and the string select transistors SSTa and SSTb connected in series are provided between the plurality of memory cells MC1 to MC8 and the bit line BL. The ground select transistors GSTa and GSTb are serially connected, and the serially connected ground select transistors GSTa and GSTb are provided between the plurality of memory cells MC1 to MC8 and the common source line CSL.

For example, a first dummy memory cell DMC1 may be provided between the plurality of memory cells MC1 to MC8 and the ground select transistors GSTa and GSTb. For example, a second dummy memory cell DMC2 may be provided between the plurality of memory cells MC1 to MC8 and the string select transistors SSTa and SSTb.

The ground select transistors GSTa and GSTb of the cell strings CS11 , CS12 , CS21 , and CS22 may be connected to the ground select line GSL in common. For example, ground select transistors in the same row may be connected to the same ground select line, and ground select transistors in different rows may be connected to different ground select lines. For example, the first ground select transistors GSTa of the cell strings CS11 and CS12 in the first row may be connected to the first ground select line, and the cell strings CS21 and CS22 in the second row may be connected to each other. The first ground select transistors GSTa may be connected to the second ground select line.

For example, although not shown in the drawings, ground select transistors provided at the same height from a substrate (not shown) may be connected to the same ground select line, and ground select transistors provided at different heights may be connected to different ground select lines. can For example, the first ground select transistors GSTa of the cell strings CS11, CS12, CS21, and CS22 are connected to the first ground select line, and the second ground select transistors GSTb are connected to the second ground select line. can be connected to the line.

Memory cells of the same height from the substrate or ground selection transistors GSTa and GSTb are commonly connected to the same word line, and memory cells of different heights are connected to different word lines. For example, the first to eighth memory cells MC8 of the cell strings CS11, CS12, CS21, and CS22 are commonly connected to the first to eighth word lines WL1 to WL8, respectively.

Among the first string select transistors SSTa having the same height, string select transistors in the same row are connected to the same string select line, and string select transistors in different rows are connected to different string select lines. For example, the first string select transistors SSTa of the cell strings CS11 and CS12 in the first row are connected in common with the string select line SSL1a, and the cell strings CS21 and CS22 in the second row are connected in common. The first string select transistors SSTa of ) are connected in common with the string select line SSL1a.

Similarly, among the second string select transistors SSTb having the same height, string select transistors of the same row are connected to the same string select line, and string select transistors of different rows are connected to other string select lines. For example, the second string select transistors SSTb of the cell strings CS11 and CS12 in the first row are connected in common with the string select line SSL1b, and the cell strings CS21 and CS22 in the second row are connected in common. The second string select transistors SSTb of ) are connected in common with the string select line SSL2b.

For example, dummy memory cells of the same height are connected to the same dummy word line, and dummy memory cells of different heights are connected to different dummy word lines. For example, the first dummy memory cells DMC1 are connected to the first dummy word line DWL1, and the second dummy memory cells DMC2 are connected to the second dummy word line DWL2.

As an example, the first memory block BLK1 shown in FIG. 22 is exemplary, the number of cell strings may increase or decrease, and the number of rows and columns constituted by the cell strings depends on the number of cell strings. may increase or decrease. Also, the number of cell transistors (GST, MC, DMC, SST, etc.) of the first memory block BLK1 may be increased or decreased, respectively, and the height of the first memory block BLK1 depends on the number of cell transistors. may increase or decrease. Also, the number of lines (GSL, WL, DWL, SSL, etc.) connected to the cell transistors may increase or decrease according to the number of cell transistors.

By way of example, the nonvolatile memory according to the present invention is not limited to the above-described configuration. As an exemplary embodiment according to the technical spirit of the inventive concept, the nonvolatile memory may include a 3D memory array. A three-dimensional memory array may be monolithically formed on one or more physical levels of arrays of memory cells having an active region disposed over a silicon substrate and circuitry associated with operation of the memory cells. Circuitry involved in the operation of the memory cells may be located in or on the substrate. The term monolithically means that the layers of each level of the three-dimensional array are deposited directly over the layers of lower levels of the three-dimensional array.

As an exemplary embodiment according to the technical concept of the inventive concept, a 3D memory array includes vertical NAND strings having a vertical direction and at least one memory cell positioned above another memory cell. At least one memory cell includes a charge trap layer. Each vertical NAND string may include at least one select transistor located over the memory cells. At least one select transistor has the same structure as the memory cells and may be monolithically formed with the memory cells.

Configurations in which the three-dimensional memory array is composed of a plurality of levels, with word lines or bit lines shared between the levels, suitable for the three-dimensional memory array are disclosed in U.S. Patent No. 7,679,133 and U.S. Patent No. 8,553,466. , US Patent Publication No. 8,654,587, US Patent Publication No. 8,559,235, and US Patent Publication No. 2011/0233648, which are incorporated herein by reference.

23 is a block diagram exemplarily showing a volatile memory of a nonvolatile memory module according to the present invention. Referring to FIG. 23, a volatile memory 1200 includes a memory cell array 1210, an address buffer 1220, an X-decoder 1230, a Y-decoder 1240, a sense amplifier and write driver 1250, and an input/output circuit 1260.

The memory cell array 1210 includes a plurality of memory cells, and each of the plurality of memory cells is connected to a plurality of word lines WL and a plurality of bit lines BL. Each of the plurality of memory cells may be located at a point where a word line and a bit line cross each other. For example, each of the plurality of memory cells may include a storage capacitor and an access transistor.

The address buffer 1220 may receive an address ADD from the module controller 110 (see FIG. 2 ) and temporarily store the received address. For example, the address buffer 1220 may provide a row address ADD_row among the received addresses ADD to the X-decoder 1230 and a column address ADD_col to the Y-decoder 1240. .

The X-decoder 1230 is connected to the memory cell array 1210 through a plurality of word lines WL. The X-decoder 1230 generates at least one word among a plurality of word lines WL based on the row address ADD_row in response to a row address strobe (RAS) signal from the module controller 110 (see FIG. 2). line can be activated.

The Y-decoder 1240 may receive the column address ADD_col from the address buffer 1220 . The Y-decoder 1240 may control the sense amplifier and write driver 1250 based on the column address ADD_col in response to a column address strobe (CAS) signal.

The sense amplifier and write driver 1250 are connected to the memory cell array 1210 through a plurality of bit lines BL. The sense amplifier and write driver 1250 may sense voltage changes of the plurality of bit lines BL. Alternatively, the sense amplifier and write driver 1250 may control voltages of the plurality of bit lines BL based on data received from the input/output circuit 1260 .

The input/output circuit 1260 may receive data from the sense amplifier and write driver 1250 and output the received data through the memory data line MDQ (or data line DQ). Alternatively, the input/output circuit 1260 may receive data through the memory data line MDQ (or data line DQ) and transfer the received data to the sense amplifier and write driver 1250 .

For example, the address ADD may be an address included in the VM command/address CA_v provided from the module controller 110 (see FIG. 2 ). The row address strobe (RAS) and the column address strobe (CAS) may be signals included in the VM command/address CA_v provided from the module controller 110 (see FIG. 2 ).

24 is a diagram exemplarily showing a server system to which a nonvolatile memory module according to the present invention is applied. Referring to FIG. 24 , a server system 2000 may include a plurality of server racks 2100 . Each of the plurality of server racks 2100 may include a plurality of nonvolatile memory modules 2200 . The plurality of nonvolatile memory modules 2200 may be directly connected to processors included in each of the plurality of server racks 2100 . For example, the plurality of nonvolatile memory modules 2200 may have the form of a dual in-line memory module and may be mounted in a DIMM socket electrically connected to a processor to communicate with the processor. Illustratively, the plurality of nonvolatile memory modules 2200 may be used as storage of the server system 2000 . For example, the plurality of nonvolatile memory modules 2200 may be nonvolatile memory modules described with reference to FIGS. 1 to 23 or may operate based on the operation method.

25 is a block diagram exemplarily showing a user system to which a nonvolatile memory module according to the present invention is applied. Referring to FIG. 25 , a user system 3000 may include a processor 3001 and a plurality of memories 3110 to 3140 .

The processor 3001 may include a memory controller 3002 . The memory controller 3002 may communicate with the plurality of memories 3110 to 3140 through the bus 3003 . For example, the bus 3003 may include dedicated buses connected to each of the plurality of memories 3110 to 3140 or a common bus shared with the plurality of memories 3110 to 3140 . For example, the bus 3003 may include at least one of a data line DQ, a memory data line MDQ, and a tag data line TDQ described with reference to FIGS. 1 to 24 .

Illustratively, at least some of the plurality of memories 3110 to 3140 may be nonvolatile memory modules described with reference to FIGS. 1 to 24 or operate based on the operating method described with reference to FIGS. 1 to 24 . can

Alternatively, at least some of the plurality of memory modules 3110 to 3140 may include non-volatile memories, and the remaining portions may include volatile memories. A memory module including volatile memory may be used as a cache memory of a memory module including nonvolatile memory. That is, as described with reference to FIGS. 1 to 24 , some of the plurality of memory modules 3110 to 3140 may be used as a main memory of the user system 3000 and the rest may be used as a cache memory. Memories used as cache memories may be volatile memories described with reference to FIGS. 1 to 24 or may operate like the volatile memories described with reference to FIGS. 1 to 24 .

Illustratively, the memory controller 3002 may be the module controller or controller described with reference to FIGS. 1 to 24 or may operate like the module controller or controller described with reference to FIGS. 1 to 24 .

In the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments and should be defined by the claims of the present invention and equivalents as well as the claims to be described later.

10: User system
100: non-volatile memory module
101: processor
110: module controller (module controller)
120: heterogeneous memory device
121: volatile memory
122: NVM controller
123: non-volatile memory
130 DB
140: serial presence detection chip (SPD)
CA: module command/address
CA_v: VM command/address
CA_n: NVM command/address
TAG : tag
DQ: data line
TDQ: tag data line
MDQ: memory data line

Claims (10)

non-volatile memory;
a volatile memory that is a cache memory of the non-volatile memory;
a controller configured to share a memory data line with the volatile memory and to control the non-volatile memory; and
In response to a module write command and a first address from an external device, a first read command and the first address are transmitted to the volatile memory through a first bus, and a first write command and the first address are transmitted through a second bus. a module controller for transmitting an address to the controller;
The volatile memory outputs a first tag and first data in response to the first read command and the first address;
wherein the controller selectively programs the first data into the nonvolatile memory based on the first tag and the first address in response to the first write command and the first address. module. According to claim 1,
wherein the controller shares a tag data line with the volatile memory, receives the first tag through the tag data line, and receives the first data through the memory data line. According to claim 1,
The controller determines whether the first data is a cache hit or cache miss based on the first tag and the first address, and selectively programs the first data into the nonvolatile memory according to the determination result. A non-volatile memory module, characterized in that. According to claim 3,
The controller determines that the first data is a cache hit when at least a part of the first address matches the first tag, and when at least a part of the first address does not match the first tag , determining that the first data is a cache miss,
The nonvolatile memory module of claim 1 , wherein the controller programs the first data into the nonvolatile memory when the determination result indicates a cache miss. According to claim 4,
The controller stores the first data, which is the cache miss, in a separate buffer circuit as data to be flushed, and when the cumulative size of the data to be flushed stored in the buffer circuit exceeds a predetermined size, the data to be flushed is stored in the nonvolatile memory. Non-volatile memory module, characterized in that programmed in. According to claim 3,
the volatile memory further outputs dirty information on the first data in response to the first read command and the first address;
and determining whether the first data is dirty based on the dirty information when the determination result indicates a cache miss. According to claim 6,
When the determination result indicates a dirty state, the controller programs the first data into the nonvolatile memory. According to claim 1,
The nonvolatile memory module of claim 1, wherein the volatile memory is an n:1 (n is a natural number) direct mapping cache memory of the nonvolatile memory. According to claim 1,
The first tag includes at least a part of an address corresponding to the first data.

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