CN114077387A

CN114077387A - Storage device and operation method thereof

Info

Publication number: CN114077387A
Application number: CN202110369934.2A
Authority: CN
Inventors: 吴泰镇; 卢正基; 梁顺烈
Original assignee: SK Hynix Inc
Current assignee: SK Hynix Inc
Priority date: 2020-08-14
Filing date: 2021-04-07
Publication date: 2022-02-22
Also published as: KR20220021796A; US11726706B2; US20220050626A1

Abstract

The present disclosure provides a memory device and an operating method thereof. The storage device may include: a memory device including a plurality of sequential areas storing a plurality of pieces of data corresponding to consecutive logical addresses input from a host and a random area other than the plurality of sequential areas; a buffer memory device configured to temporarily store write data corresponding to a write request provided from a host; and an operation controller configured to generate combined data by adding dummy data to the write data having a size smaller than a programming unit size of the memory device, the size of the dummy data corresponding to a difference between the size of the write data and the programming unit size, store the combined data in the memory device, and store combined data information about the combined data stored in the memory device in the buffer memory device.

Description

Storage device and operation method thereof

Cross Reference to Related Applications

This application claims priority to korean patent application No. 10-2020-0102788, filed on 14.8.2020 and incorporated herein by reference in its entirety.

Technical Field

Various embodiments of the present disclosure relate generally to an electronic device, and more particularly, to a memory device and a method of operating the memory device.

Background

A storage device is a device that stores data under the control of a host device such as a computer or a smartphone. The memory device may include a memory device to store data and a memory controller to control the memory device. Memory devices may be classified into volatile memory devices and non-volatile memory devices.

A volatile memory device may be a memory device that stores data only when power is supplied thereto and loses the stored data when power is interrupted. Examples of volatile memory devices may include Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and the like.

The nonvolatile memory device may be a memory device that can retain stored data even when power supply is interrupted. Examples of non-volatile memory devices may include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), flash memory, and the like.

Disclosure of Invention

Various embodiments of the present disclosure relate to a memory device having improved memory performance and a method of operating the same.

Embodiments of the present disclosure may provide a storage device. The storage device may include: a memory device including a plurality of sequential areas storing a plurality of pieces of data corresponding to consecutive logical addresses input from a host and a random area other than the plurality of sequential areas; a buffer memory device configured to temporarily store write data corresponding to a write request provided from a host; and an operation controller configured to: generating combination data by adding dummy data to write data having a size smaller than a programming unit size of the memory device, the dummy data having a size corresponding to a difference between the size of the write data and the programming unit size; storing the combined data in a memory device; and, the combined data information related to the combined data stored in the memory device is stored in the buffer memory device.

Embodiments of the present disclosure may provide a storage device. The storage device may include: a memory device including a plurality of sequential areas storing a plurality of pieces of data corresponding to consecutive logical addresses input from a host and a random area other than the plurality of sequential areas; and a memory controller configured to receive a write request from the host and control the memory device so that a portion of write data corresponding to the write request is stored in the random area according to whether or not dummy data has been stored in a sequential area corresponding to a logical address included in the write request among the plurality of sequential areas.

Embodiments of the present disclosure may provide a storage device. The storage device may include: a memory device including a plurality of sequential areas storing a plurality of pieces of data corresponding to consecutive logical addresses input from a host and a random area other than the plurality of sequential areas; a buffer memory device configured to store a sequence mapping table including information on logical addresses of a plurality of pieces of data respectively stored in a plurality of sequence areas, a random mapping table including information on logical addresses of data stored in a random area, and combined data information including information on virtual data stored in the plurality of sequence areas; and a memory controller configured to acquire read data corresponding to a read request from at least one of the random area and a sequential area corresponding to a logical address included in the read request among the plurality of sequential areas, according to whether the logical address included in the read request input from the host is included in the combined data information, and to supply the read data to the host.

Drawings

Fig. 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

Fig. 2 is a diagram illustrating the memory device of fig. 1.

Fig. 3 is a diagram illustrating the structure of any one of the memory blocks of fig. 2.

Fig. 4 is a diagram for explaining a storage area of the memory device of fig. 1 according to an embodiment of the present disclosure.

Fig. 5 is a diagram for explaining the sequential regions described with reference to fig. 4.

Fig. 6 is a diagram illustrating an operation of the memory device of fig. 1 according to an embodiment of the present disclosure.

Fig. 7 is a diagram showing the structure of the buffer memory device of fig. 6.

Fig. 8A illustrates a state in which write data having a size smaller than the program unit size is temporarily stored in the write buffer.

Fig. 8B shows a state in which combined data in which dummy data corresponding to a difference between the size of the program unit and the size of the write data is added to the write data is generated.

Fig. 8C shows a state in which the combined data is stored in the first order area.

Fig. 8D shows the position of the write pointer after the combined data has been stored in the first sequential area.

Fig. 9A and 9B are diagrams illustrating an operation of the memory device of fig. 1 according to an embodiment of the present disclosure.

Fig. 10 is a diagram for explaining mapping information of virtual data stored in a sequential area.

Fig. 11 is a diagram showing a process for processing a read request for data.

Fig. 12A to 12C are diagrams for explaining data stored in the mapping information storage device of fig. 7.

Fig. 13 is a diagram illustrating the memory controller of fig. 1, according to an embodiment of the present disclosure.

Fig. 14 is a block diagram showing a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

Fig. 15 is a block diagram illustrating a Solid State Drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

Fig. 16 is a block diagram showing a user system to which a storage device according to an embodiment of the present disclosure is applied.

Detailed Description

Specific structural or functional descriptions in the embodiments of the present disclosure introduced in the specification or application are taken as examples to describe embodiments of the concepts according to the present disclosure. Embodiments in accordance with the disclosed concept may be practiced in various forms and should not be construed as limited to the embodiments set forth in the specification or application.

Fig. 1 is a diagram illustrating a storage device 50 according to an embodiment of the present disclosure.

Referring to fig. 1, a memory device 50 may include a memory device 100 and a memory controller 200 controlling the operation of the memory device 100. The storage device 50 may store data under the control of a host 400, such as a mobile phone, smart phone, MP3 player, laptop computer, desktop computer, game console, TV, tablet, in-vehicle infotainment system, and the like.

The storage device 50 may be manufactured as any one of various types of storage devices according to a host interface as a scheme for communicating with the host 400. For example, the storage device 50 may be implemented as any of various types of storage devices such as: a Solid State Disk (SSD), a multimedia card such as MMC, an embedded MMC (emmc), a reduced-size MMC (RS-MMC), or a micro MMC, a secure digital card such as SD, mini SD, or micro SD, a Universal Serial Bus (USB) storage device, a universal flash memory (UFS) device, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a Peripheral Component Interconnect (PCI) card type storage device, a PCI express (PCI-E) card type storage device, a Compact Flash (CF) card, a smart media card, a memory stick, or the like.

The memory device 50 may be manufactured in any of various types of packaging. For example, the storage device 50 may be manufactured in any of various types of packaging such as: package On Package (POP), System In Package (SIP), System On Chip (SOC), multi-chip package (MCP), Chip On Board (COB), wafer level manufacturing package (WFP), wafer level package on stack (WSP), etc.

The memory device 100 may store data. The memory device 100 operates in response to control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) including a plurality of memory cells storing data.

Each of the memory cells may be implemented as a single-layer cell (SLC) capable of storing one bit of data, a multi-layer cell (MLC) capable of storing two bits of data, a triple-layer cell (TLC) capable of storing three bits of data, or a quadruple-layer cell (QLC) capable of storing four bits of data.

The memory cell array (not shown) may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. A single memory block may include multiple pages. In an embodiment, a page may be a unit of storing data in the memory device 100 or reading data stored in the memory device 100. The memory block may be a unit of erase data.

In embodiments, the memory device 100 may take many alternative forms such as: double data rate synchronous dynamic random access memory (DDR SDRAM), fourth generation low power double data rate (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, low power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory devices, resistive RAM (rram), phase change memory (PRAM), magnetoresistive RAM (mram), ferroelectric RAM (fram), spin transfer torque RAM (STT-RAM), and the like. In this specification, for convenience of description, description will be made on the assumption that the memory device 100 is a NAND flash memory.

The memory device 100 may receive a command and an address from the memory controller 200 and may access a region in the memory cell array selected by the address. The memory device 100 may perform the operation indicated by the command on the area selected by the address. For example, the memory device 100 may perform a write operation (i.e., a program operation), a read operation, and an erase operation. During a programming operation, the memory device 100 may program data to a region selected by an address. During a read operation, the memory device 100 may sense data from a region selected by an address. During an erase operation, the memory device 100 may erase data stored in an area selected by an address.

The memory controller 200 may control the overall operation of the memory device 50.

When power is supplied to the storage device 50, the memory controller 200 may run Firmware (FW). When the memory device 100 is a flash memory device, the Firmware (FW) may include a Host Interface Layer (HIL) controlling communication with the host 400, a Flash Translation Layer (FTL) controlling communication between the host 400 and the memory device 100, and a Flash Interface Layer (FIL) controlling communication with the memory device 100.

In an embodiment, the memory controller 200 may receive write data and a Logical Block Address (LBA) from the host 400, and may convert the Logical Block Address (LBA) into a Physical Block Address (PBA) indicating an address of a memory unit included in the memory device 100 in which the write data is to be stored. In this specification, the terms "Logical Block Address (LBA)" and "logical address" may be used interchangeably. In this specification, the terms "Physical Block Address (PBA)" and "physical address" may be used interchangeably.

The memory controller 200 may control the memory device 100 so that a program operation, a read operation, or an erase operation is performed in the memory device 100 in response to a request received from the host 400. During a programming operation, the memory controller 200 may provide a write command, a Physical Block Address (PBA), and write data to the memory device 100. During a read operation, the memory controller 200 may provide a read command and a Physical Block Address (PBA) to the memory device 100. During an erase operation, the memory controller 200 may provide an erase command and a Physical Block Address (PBA) to the memory device 100.

In an embodiment, the memory controller 200 may autonomously generate commands, addresses, and data regardless of whether a request from the host 400 is received, and may transmit them to the memory device 100. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 needed to perform read and program operations involving performing wear leveling, read reclamation, garbage collection, and the like.

In an embodiment, memory controller 200 may control at least two memory devices 100. In this case, the memory controller 200 may control at least two memory devices 100 according to an interleaving scheme to improve operation performance. The interleaving scheme may be a scheme for controlling at least two memory devices 100 such that operations of the at least two memory devices 100 overlap each other.

In an embodiment of the present disclosure, the memory controller 200 may include an operation controller 210 and a buffer memory device 220.

The operation controller 210 may process write requests and read requests provided from the host 400.

The buffer memory device 220 may temporarily store write data corresponding to a write request provided from the host 400. Alternatively, the buffer memory device 220 may temporarily store data read from the memory device 100 in response to a read request provided from the host 400.

According to embodiments of the present disclosure, the memory device 100 may include a plurality of sequential regions, as well as a random region. The plurality of sequential areas are storage areas that store a plurality of pieces of data corresponding to consecutive logical addresses input from the host 400, and the random area is a storage area other than the plurality of sequential areas. In an embodiment, the random area may be an area storing a plurality of pieces of data corresponding to non-consecutive logical addresses.

The plurality of sequential areas may store a plurality of pieces of data of logical address groups respectively corresponding to the plurality of sequential areas. Here, each of the logical address groups may include consecutive logical addresses.

Each sequential region may be referred to as a "partition. Each sequential region may have an open state or a closed state according to a request received from the host 400.

For example, in response to an open partition request provided from the host 400, the operation controller 210 may open the corresponding sequential area. An open sequential region may mean a mapping table that generates a logical address group corresponding to the sequential region.

In response to a closed partition request provided from the host 400, the operation controller 210 may change the open state of the corresponding sequential area to the closed state. The closed partition request may be a request indicating that a write request to store data in a corresponding sequential region is not to be entered before an open partition request for the corresponding sequential region is entered again.

In an embodiment, the buffer memory device 220 may store a sequence mapping table including mapping information of a plurality of sequence areas. The order mapping table may include write pointer position information indicating a position of a logical address of data to be currently stored among logical addresses of pieces of data to be stored in respective order areas. That is, the logical address in the write request provided from the host 400 may be the logical address indicated by the write pointer position of the sequential area to which the corresponding logical address belongs. The write request may include a logical address of the write data and information on a length of the logical address of the write data. After processing the write request, the operation controller 210 may change the write pointer position information to information corresponding to a write pointer position determined by adding the length of the logical address to the previous write pointer position. Accordingly, the write pointer location information may be synchronized with a starting logical address among logical addresses of write data provided from the host 400.

In an embodiment, in response to a reset partition request provided from the host 400, the operation controller 210 may change the write pointer location information of the sequential area to a starting logical address among logical addresses corresponding to the sequential area.

The operation controller 210 may control the buffer memory device 220 and the memory device 100 so that write data corresponding to a write request provided from the host 400 is stored in the memory device 100. The operation controller 210 may provide write data to the memory device 100 in the size of a unit of programming of the memory device 100. The program unit size may be a size of write data that can be stored in the memory device 100 by performing a one-time program operation.

When the size of the write data stored in the buffer memory device 220 is smaller than the program unit size, the operation controller 210 may not provide the write data to the memory device 100. When the size of the write data stored in the buffer memory device 220 reaches the programming unit size, the operation controller 210 may provide the write data to the memory device 100.

In a state where write data having a size smaller than the size of the program unit is stored in the buffer memory device 220, the operation controller 210 may receive a clear request from the host 400 to provide the write data stored in the buffer memory device 220 to the memory device 100. In this case, the following may occur: write data having a size smaller than the size of the program unit should be stored in sequential areas of the memory device 100.

Alternatively, in a state where write data having a size smaller than the size of the program unit is stored in the buffer memory device 220, a closed partition request for a corresponding sequential area may be input from the host 400. In this case, the following may occur: write data having a size smaller than the size of the program unit should be stored in the corresponding sequential area.

Alternatively, in a state where write data having a size smaller than the program unit size is stored in the buffer memory device 220, the storage device 50 may enter a low power consumption mode. In this case, the following may occur: write data having a size smaller than the size of the program unit should be stored in sequential areas of the memory device 100.

When the size of the write data stored in the buffer memory device 220 is smaller than the programming unit size of the memory device 100, the operation controller 210 may generate the combined data by adding dummy data to the write data, the size of the dummy data corresponding to a difference between the size of the write data and the programming unit size. Then, the operation controller 210 may control the buffer memory device 220 and the memory device 100 so that the combined data is stored in the memory device 100. In this case, the location of the write pointer recognized by the host 400 may be different from the location of the actual write pointer.

Further, as the case where the combined data is stored in the sequential regions occurs more frequently, the actual data storage space of the sequential regions in the memory device 100 may decrease, thereby deteriorating the overall performance of the storage device 50.

Embodiments of the present disclosure provide the following methods: when the combined data is stored in the sequential area, a portion of the write data subsequently supplied from the host 400 is stored in the random area in the memory device 100, thereby preventing the performance degradation of the storage device 50.

The host 400 may communicate with the storage device 50 using at least one of various communication methods such as: universal Serial Bus (USB), serial AT attachment (SATA), serial SCSI (sas), high speed inter-chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI express (pcie), non-volatile memory express (NVMe), universal flash memory (UFS), Secure Digital (SD), multimedia card (MMC), embedded MMC (emmc), dual in-line memory module (DIMM), registered DIMM (rdimm), reduced-load DIMM (lrdimm), and the like.

Fig. 2 is a diagram illustrating the memory device 100 of fig. 1.

Referring to fig. 2, the memory device 100 may include a memory cell array 110, a voltage generator 120, an address decoder 130, an input/output (I/O) circuit 140, and a control logic 150.

The memory cell array 110 includes a plurality of memory blocks BLK1 through BLKi. A plurality of memory blocks BLK1 through BLKi may be coupled to address decoder 130 by row lines RL. The plurality of memory blocks BLK1 through BLKi may be coupled to the input/output circuit 140 through column lines CL. In an embodiment, the row lines RL may include word lines, source select lines, and drain select lines. In an embodiment, the column line CL may include a bit line.

Each of the memory blocks BLK1 through BLKi includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be non-volatile memory cells. Among a plurality of memory cells, memory cells coupled to the same word line may be defined as one physical page. That is, the memory cell array 110 may include a plurality of physical pages. Each of the memory cells of memory device 100 may be implemented as a single-layer cell (SLC), a multi-layer cell (MLC), a triple-layer cell (TLC), or a quad-layer cell (QLC).

In an embodiment, the voltage generator 120, the address decoder 130, and the input/output circuit 140 may be collectively referred to as a peripheral circuit. The peripheral circuits may drive the memory cell array 110 under the control of control logic 150. The peripheral circuits may drive the memory cell array 110 to perform a program operation, a read operation, and an erase operation.

The voltage generator 120 may generate a plurality of operating voltages using an external power supply voltage supplied to the memory device 100. The voltage generator 120 may operate under the control of the control logic 150.

In an embodiment, the voltage generator 120 may generate the internal supply voltage by adjusting the external supply voltage. The internal power supply voltage generated by the voltage generator 120 is used as an operation voltage of the memory device 100.

In an embodiment, the voltage generator 120 may generate the plurality of operating voltages using an external power supply voltage or an internal power supply voltage. The voltage generator 120 may generate various voltages required by the memory device 100. For example, the voltage generator 120 may generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of unselected read voltages.

The voltage generator 120 may include a plurality of pumping capacitors for receiving an internal power supply voltage to generate a plurality of operating voltages having various voltage levels, and may generate the plurality of operating voltages by selectively enabling the plurality of pumping capacitors under the control of the control logic 150.

The generated operation voltage may be supplied to the memory cell array 110 through the address decoder 130.

Address decoder 130 is coupled to memory cell array 110 by row lines RL. Address decoder 130 may operate under the control of control logic 150. Address decoder 130 receives address ADDR from control logic 150. The address decoder 130 may decode a block address among the received addresses ADDR. The address decoder 130 may select at least one of the memory blocks BLK1 through BLKi according to the decoded block address. The address decoder 130 may decode a row address among the received addresses ADDR. The address decoder 130 may select at least one of the word lines of the selected memory block according to the decoded row address. In an embodiment, the address decoder 130 may decode a column address among the received addresses ADDR. Address decoder 130 may couple input/output circuit 140 to memory cell array 110 according to the decoded column address.

According to an embodiment of the present disclosure, during a read operation, the address decoder 130 may apply a read voltage to a selected word line and apply a read pass voltage, a level of which is higher than that of the read voltage, to unselected word lines.

In an embodiment, address decoder 130 may include components such as a row decoder, a column decoder, and an address buffer.

Input/output (I/O) circuitry 140 may include multiple page buffers. The plurality of page buffers may be coupled to the memory cell array 110 through bit lines. During a programming operation, data may be stored in selected memory cells based on write data stored in the plurality of page buffers.

During a read operation, data stored in a selected memory cell may be sensed through the bit line, and the sensed data may be stored in the page buffer.

Control logic 150 may control address decoder 130, voltage generator 120, and input/output circuitry 140. The control logic 150 may operate in response to a command CMD transmitted from an external device. The control logic 150 may control the peripheral circuits by generating various types of signals in response to the command CMD and the address ADDR.

Fig. 3 illustrates a structure of a memory block BLKi indicating any one of the memory blocks BLK1 through BLKi of fig. 2.

Referring to fig. 3, a plurality of word lines arranged in parallel with each other may be coupled between a first select line and a second select line. Here, the first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. In detail, the memory block BLKi may include a plurality of strings ST coupled between the bit lines BL1 to BLn and the source lines SL. The bit lines BL1 to BLn may be respectively coupled to the strings ST, and the source lines SL may be commonly coupled to the strings ST. The strings ST may have the same structure, and thus, the first string ST coupled to the first bit line BL1 will be described in detail as an example.

The first string ST may include a source select transistor SST, a plurality of memory cells MC1 to MC16, and a drain select transistor DST coupled in series to each other between a source line SL and a first bit line BL 1. The single string ST may include at least one source select transistor SST and at least one drain select transistor DST, and may include more memory cells than the memory cells MC1 through MC16 shown in the drawings.

In the first string ST, a source of the source selection transistor SST may be coupled to a source line SL, and a drain of the drain selection transistor DST may be coupled to a first bit line BL 1. The memory cells MC1 through MC16 may be coupled in series between the source select transistor SST and the drain select transistor DST.

Gates of the source select transistors SST included in different strings ST may be coupled to a source select line SSL, gates of the drain select transistors DST included in different strings ST may be coupled to a drain select line DSL, and gates of the memory cells MC1 through MC16 may be coupled to a plurality of word lines WL1 through WL16, respectively. Among the memory cells included in different strings ST, a group of memory cells coupled to the same word line may be referred to as a "physical Page (PG)". Accordingly, the memory block BLKi may include a plurality of physical Pages (PGs) corresponding to the word lines WL1 to WL16, respectively.

One memory cell can store one bit of data. This cell is commonly referred to as a "single-level cell (SLC)". In this case, one physical Page (PG) may store data corresponding to one Logical Page (LPG). The data corresponding to one Logical Page (LPG) may include multi-bit data corresponding to the number of cells included in one physical Page (PG).

One memory cell can store two or more bits of data. In this case, one physical Page (PG) may store data corresponding to two or more Logical Pages (LPGs). The two or more Logical Pages (LPGs) may correspond to two or more data bits, respectively.

Fig. 4 is a diagram for explaining a storage area of the storage device 50 of fig. 1 according to an embodiment of the present disclosure.

Referring to fig. 4, the storage area of the storage device 50 may be divided into a random area and a plurality of sequential areas.

In fig. 4, it is assumed that the logical addresses to be provided by the host 400 described above with reference to fig. 1 range from the first logical address LBA1 to the mth logical address LBA m.

Pieces of data corresponding to the first to k-th logical addresses LBA1 to LBA k may be stored in the random area. The data to be stored in the random area may be provided regardless of the order of the logical addresses.

Pieces of data corresponding to the (k +1) th to m-th logical addresses LBA k +1 to LBA m may be stored in the sequential areas (i.e., sequential area 1 to sequential area X). The plurality of sequential areas may store a plurality of pieces of data of logical address groups respectively corresponding to the plurality of sequential areas. In this case, each of the logical address groups may include consecutive logical addresses. The data to be stored in each sequential area may be provided according to consecutive logical addresses included in the corresponding logical address group. The storage area may correspond to the memory device 100 of fig. 1.

Referring to fig. 5, the order areas may include a first order area Zone1 through an xth order area ZoneX. Each sequential region may include a plurality of memory blocks. The numbers of memory blocks allocated to the order areas Zone1 through ZoneX may be different from each other. Alternatively, the numbers of memory blocks allocated to the order areas Zone1 through ZoneX may be the same as each other. The sequential areas Zone1 through ZoneX may store pieces of data of logical address groups LBA Group1 through LBA Group x corresponding to the sequential areas Zone1 through ZoneX, respectively. In this case, each of the logical address groups LBA Group1 through LBA Group x may include consecutive logical addresses. The data to be stored in each of the sequential areas Zone1 through ZoneX may be provided according to consecutive logical addresses included in the corresponding logical address group. Each of the logical address groups LBA Group1 through LBA Group x includes a plurality of consecutive logical addresses selected from among (k +1) th logical addresses LBA k +1 through mth logical addresses LBA m.

Fig. 6 is a diagram illustrating an operation of the memory device 50 of fig. 1 according to an embodiment of the present disclosure. The operation of fig. 6 will be described using the memory device 50 shown in fig. 1.

Referring to fig. 6, the memory controller 200 may include a buffer memory device 220 and an operation controller 210 as shown in fig. 1.

The operation controller 210 may control the buffer memory device 220 and the memory device 100 (e.g., partitioned memory) so that write data corresponding to a write request provided from the host 400 is stored in the memory device 100. The operation controller 210 may provide write data to the memory device 100 in a program unit size of the memory device 100. The program unit size may be a size of write data that can be stored in the memory device 100 by performing a one-time program operation.

When the size of the write data stored in the buffer memory device 220 is smaller than the program unit size of the memory device 100, the operation controller 210 may generate the combined data by adding dummy data to the write data, the size of the dummy data corresponding to a difference between the size of the write data and the program unit size. Then, the operation controller 210 may control the buffer memory device 220 and the memory device 100 so that the combined data is stored in the memory device 100.

The operation controller 210 may store information related to the combined data in the buffer memory device 220, the combined data information indicating that the combined data has been stored in the memory device 100.

The combined data information may include information on a logical address corresponding to dummy data included in the combined data stored in the memory device 100. Alternatively, the combined data information may include information on sequential areas where the virtual data is stored. In an embodiment, the combined data information may further include information on the size of the virtual data. In this case, the information on the size of the dummy data may be information on the length of a logical address corresponding to the dummy data.

Thereafter, the operation controller 210 may receive a subsequent write request. The operation controller 210 may determine whether the combined data has been stored in the sequential area corresponding to the subsequent write request based on the combined data information. When the combined data is stored in the sequential area corresponding to the logical address included in the subsequent write request, the operation controller 210 may control the memory device 100 so that a portion of the subsequent write data corresponding to the subsequent write request is stored in the random area of the memory device 100.

In detail, the operation controller 210 may control the memory device 100 so that sub data, which is a part of subsequently written data, is stored in the random area, and the remaining data other than the sub data is successively stored in the sequential area together with the combined data. The size of the sub data corresponds to the size of the virtual data contained in the combined data. The logical address corresponding to the sub data and the logical address corresponding to the virtual data may be identical to each other. In an embodiment, the logical addresses of the remaining data may be consecutive to a last logical address among the logical addresses corresponding to the combined data.

The buffer memory device 220 may store a sequence mapping table including information on logical addresses of a plurality of pieces of data stored in the respective sequence areas, and write pointer position information including information on logical addresses of a plurality of pieces of data to be stored in the respective sequence areas. Here, the write pointer location information may be information on a start logical address of data to be subsequently stored. The buffer memory device 220 may further store a random mapping table including information on logical addresses of data stored in the random area.

Thereafter, the operation controller 210 may receive a read request from the host 400. The operation controller 210 may mainly determine whether the logical address included in the read request is the same as any logical address included in the combined data information. When any logical address corresponding to the data to be read exists in the combined data information, the data corresponding to the logical address may be stored in the random area, and when any logical address corresponding to the data to be read does not exist in the combined data information, the data corresponding to the logical address may be stored in the sequential area.

Fig. 7 is a diagram illustrating a structure of the buffer memory device 220 of fig. 6 according to an embodiment.

Referring to fig. 6 and 7, the buffer memory device 220 may include a write buffer 221, a read buffer 222, and a mapping information storage 223.

The write buffer 221 may temporarily store data to be stored in the memory device 100.

In an embodiment, the write buffer 221 may include a sequential buffer that temporarily stores pieces of data to be respectively stored in a plurality of sequential areas included in the memory device 100. Alternatively, the write buffer 221 may include a random buffer that temporarily stores data to be stored in a random area included in the memory device 100.

The read buffer 222 may temporarily store data read from the memory device 100 before the data is provided to the host 400.

The mapping information storage 223 may store a sequence mapping table 223a, a random mapping table 223b, and combined data information 223 c.

The sequence mapping table 223a may include mapping information between logical addresses and physical addresses of a plurality of pieces of data stored in respective sequence areas in the memory device 100, and write pointer location information including information on the logical addresses of the plurality of pieces of data to be stored in the respective sequence areas.

The random mapping table 223b may include mapping information between logical addresses and physical addresses of data stored in a random area in the memory device 100.

The combined data information 223c may include information on a sequential area in which combined data including dummy data is stored among the sequential areas, and information on a logical address of the dummy data stored in the sequential area. Here, the information on the logical address of the virtual data may include information on a starting logical address among the logical addresses of the virtual data and a length of the logical address corresponding to the virtual data. In an embodiment, the combined data information 223c may further include information on the size of the virtual data.

Fig. 8A, 8B, 8C, and 8D are diagrams illustrating an operation of storing write data having a size smaller than a program unit size. The operations shown in fig. 8A, 8B, 8C, and 8D will be described with reference to the buffer memory device 220 shown in fig. 7.

Fig. 8A illustrates a state in which write data having a size smaller than the program unit size is temporarily stored in the write buffer 221 of the buffer memory device 220. Thereafter, a purge request may be input from the host 400.

Fig. 8B illustrates a state in which the combined data is generated by adding dummy data corresponding to a difference between the program unit size and the size of the write data to the write data. Fig. 8C illustrates a state in which the combined data is stored in the first order Zone1 of the memory device 100 during a program operation.

Fig. 8D shows the position of the write pointer after the combined data has been stored in the first order area Zone1 of the memory device 100. After the write data has been stored in the first order area Zone1, the host 400 may identify the write pointer as the p-th logical address LBA p. However, since dummy data is added to cause the storage device 50 to store data corresponding to the program unit size, the actual position of the write pointer may indicate the q-th logical address LBA q after the combined data has been stored.

Fig. 9A and 9B are diagrams illustrating an operation of the memory device 50 of fig. 1 according to an embodiment of the present disclosure.

Fig. 9A shows the following state: dummy data is added to the write data to generate combined data, and the combined data is stored in a sequential area of the memory device 100, so that the write data having a size smaller than a size of a program unit is stored in the sequential area.

Fig. 9B illustrates a method of storing subsequent write data.

Referring to fig. 9A and 9B, the memory controller 200 may store a portion of the subsequent write data in a random area of the memory device 100 and store the remaining data of the subsequent write data in a sequential area. In detail, the memory controller 200 may control the memory device 100 so that sub data, which is a part of the subsequent write data, of the subsequent write data is stored in the random area, and the remaining data, which is the remaining data, of the subsequent write data is stored in the sequential area successively with the dummy data. The size of the sub data is the same as the size of the virtual data included in the combined data. In this embodiment, the size of the remaining data may be equal to the program unit size.

Referring to fig. 10, the random area may be an area storing data corresponding to the k-th to n-th logical addresses LBA k to LBA n, and the sequential area may be an area storing data corresponding to the (n +1) -th to m-th logical addresses LBA n +1 to LBA m.

In fig. 10, it is assumed that the combined data is stored in the sequential area, and the logical address of the dummy data included in the stored combined data is the P-th logical address LBA P. Accordingly, among the subsequent write data that is subsequently input to follow the write data contained in the combined data, the sub data that is data corresponding to the size of the dummy data among the subsequent write data can be stored in the random area.

Since the host 400 may recognize the logical address of the sub data stored in the random area as the pth logical address LBA P, the logical address of the sub data in the random mapping table may be the pth logical address LBA P. Also, the physical address corresponding to the pth logical address LBA P may be a pth physical address PBA P, which is a physical address of the sub data stored in the random area, not a physical address of the virtual data stored in the sequential area.

Fig. 11 is a diagram illustrating a process for processing a read request for stored data described with reference to fig. 9A and 9B.

In fig. 11, it is assumed that sequential read requests for the first to twelfth logical addresses LBA1 to LBA12 are received from the host 400.

The range of logical addresses of the existing data and the previously written data stored in the sequential area is the first to sixth logical addresses LBA1 to LBA 6, and the range of logical addresses of the dummy data including the combined data of the previously written data and the sub data of the subsequently written data stored in the random area is the seventh to eighth logical addresses LBA 7 to LBA 8. Further, the range of logical addresses of the remaining data of the subsequent write data stored in the sequential area is the ninth to twelfth logical addresses LBA 9 to LBA 12.

The memory device 100 may recognize that the range of logical addresses of the dummy data is the seventh to eighth logical addresses LBA 7 to LBA 8 based on the combined data information of the combined data, and the pieces of data corresponding to the logical addresses LBA 7 to LBA 8 are stored in the random area. Accordingly, when the pieces of data of the first to twelfth logical addresses LBA1 to LBA12 are temporarily stored in the read buffer 222 of the buffer memory device 220 in response to the read request to provide the pieces of data to the host 400, the memory device 100 may read the pieces of data corresponding to the first to sixth logical addresses LBA1 to LBA 6 from the sequential area, read the data corresponding to the seventh to eighth logical addresses LBA 7 to LBA 8 from the random area, and read the data corresponding to the ninth to twelfth logical addresses LBA 9 to LBA12 from the sequential area again.

Fig. 12A to 12C are diagrams for explaining data stored in the mapping information storage 223 of fig. 7.

FIG. 12A illustrates an embodiment of the order mapping table 223a described above with reference to FIG. 7.

The sequence mapping table 223a may include mapping information of sequential regions of the memory device 100, for example, information on consecutive logical addresses and information on physical addresses corresponding to the consecutive logical addresses. Fig. 12A shows a state in which mapping is performed between consecutive logical addresses and physical addresses. However, the embodiments are not limited thereto. In another embodiment, the sequence mapping table 223a may store information on the consecutive logical addresses and physical addresses corresponding to the consecutive logical addresses using a starting logical address among the consecutive logical addresses and a length of the logical address per program unit.

In an embodiment, the order mapping table 223a may further include write pointer location information indicating a logical address of data to be stored in each order area.

Fig. 12B illustrates an embodiment of the random mapping table 223B described above with reference to fig. 7.

Referring to fig. 12B, the random mapping table 223B may store mapping information between logical addresses and physical addresses of data stored in a random area of the memory device 100.

Fig. 12C illustrates an embodiment of the combined data information 223C described above with reference to fig. 7.

Referring to fig. 12C, the combined data information 223C may include information on a sequential area Zone # in which the combined data is stored among sequential areas of the memory device 100, and information on a logical address of the virtual data stored in the sequential area Zone #. Here, the information on the logical address of the dummy data may include information on a start logical address of the dummy data and a length of a logical address corresponding to the dummy data. In an embodiment, the combined data information 223c may further include information on the size of the virtual data. Referring to fig. 12C, the length of a logical address corresponding to dummy data may correspond to the size of the dummy data.

Fig. 13 is a diagram illustrating a memory controller 1300 according to an embodiment. The memory controller 1300 shown in fig. 13 may correspond to the memory controller 200 shown in fig. 1.

Referring to fig. 13, the memory controller 1300 may include a processor 1310, a RAM 1320, an Error Correction Code (ECC) circuit 1330, a ROM 1360, a host interface 1370, and a flash interface 1380.

The processor 1310 may control the overall operation of the memory controller 1300. The RAM 1320 can be used as a buffer memory, a cache memory, or a working memory of the memory controller 1300.

The ROM 1360 may store various types of information required for the operation of the memory controller 1300 in the form of firmware.

The memory controller 1300 may communicate with external devices (e.g., the host 400, the application processor, etc. of fig. 1) through a host interface 1370.

Memory controller 1300 may communicate with memory device 100 of fig. 1 through flash interface 1380. The memory controller 1300 may transmit a command CMD, an address ADDR, a control signal CTRL, etc. to the memory device 100 through the flash memory interface 1380 and receive DATA from the memory device 100. In an example, flash interface 1380 may include a NAND interface.

Fig. 14 is a block diagram showing a memory card system 2000 to which a storage device according to an embodiment of the present disclosure is applied.

Referring to fig. 14, the memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300.

The memory controller 2100 is coupled to the memory device 2200. The memory device 2200 is accessible by the memory controller 2100. For example, the memory controller 2100 may control read operations, write operations, erase operations, and background operations of the memory device 2200. The memory controller 2100 may provide an interface between the memory device 2200 and a host. The memory controller 2100 may execute firmware for controlling the memory device 2200. The memory controller 2100 may be implemented in the same manner as the memory controller 200 described above with reference to fig. 1.

In an embodiment, memory controller 2100 may include components such as a RAM, a processor, a host interface, a memory interface, and ECC circuitry.

The memory controller 2100 may communicate with external devices through the connector 2300. The memory controller 2100 may communicate with an external device (e.g., a host) based on a particular communication protocol. In an embodiment, the memory controller 2100 may communicate with external devices through at least one of various communication protocols such as: universal Serial Bus (USB), multimedia card (MMC), embedded MMC (emmc), Peripheral Component Interconnect (PCI), PCI express (PCI-E), Advanced Technology Attachment (ATA), serial ATA (sata), parallel ATA (pata), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), firewire, universal flash memory (UFS), Wi-Fi, bluetooth, and non-volatile memory at high speed (NVMe) protocols. In an embodiment, the connector 2300 may be defined by at least one of the various communication protocols described above.

In an embodiment, memory device 2200 may be implemented as any of a variety of non-volatile memory devices such as: electrically erasable programmable rom (eeprom), NAND flash memory, NOR flash memory, phase change RAM (pram), resistive RAM (reram), ferroelectric RAM (fram), spin transfer torque magnetic RAM (STT-MRAM), and the like.

The memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to configure a memory card such as the following: PC card (personal computer memory card International Association: PCMCIA), compact flash Card (CF), smart media card (SM or SMC), memory stick, multimedia card (MMC, RS-MMC, micro MMC or eMMC), SD card (SD, mini SD, micro SD or SDHC), or Universal Flash (UFS).

Fig. 15 is a block diagram showing a Solid State Drive (SSD) system 3000 to which a storage device according to an embodiment of the present disclosure is applied.

Referring to fig. 15, the SSD system 3000 may include a host 3100 and an SSD 3200. The SSD3200 may exchange signals SIG with the host 3100 through the signal connector 3001, and may receive power PWR through the power connector 3002. The SSD3200 may include an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

According to an embodiment of the present disclosure, the SSD controller 3210 may perform the functions of the memory controller 200 described above with reference to fig. 1.

The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. In an embodiment, signal SIG may be a signal based on the interface of host 3100 and SSD 3200. For example, the signal SIG may be a signal defined by at least one of various interfaces such as: universal Serial Bus (USB), multi-media card (MMC), embedded MMC (emmc), Peripheral Component Interconnect (PCI), PCI express (PCI-E), Advanced Technology Attachment (ATA), serial ATA (sata), parallel ATA (pata), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), firewire, universal flash memory (UFS), Wi-Fi, bluetooth, and non-volatile memory at high speed (NVMe) interfaces.

The auxiliary power supply 3230 may be coupled to the host 3100 via a power connector 3002. The auxiliary power supply 3230 may be supplied with power PWR from the host 3100 and may be charged. When the power supply from the host 3100 is not smooth in performance, the auxiliary power source 3230 may supply the power of the SSD 3200. In embodiments, the auxiliary power supply 3230 may be located inside the SSD3200 or outside the SSD 3200. For example, the auxiliary power supply 3230 may be provided in a main board and may supply auxiliary power to the SSD 3200.

The buffer memory 3240 serves as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or may temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322 n. The buffer memory 3240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

Fig. 16 is a block diagram illustrating a user system 4000 to which a storage device according to an embodiment of the present disclosure is applied.

Referring to fig. 16, the user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

The application processor 4100 may run a component included in the user system 4000, an Operating System (OS), or a user program. In an embodiment, the application processor 4100 may include a controller, an interface, a graphic engine, etc. for controlling components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

The memory module 4200 may be used as a main memory, a working memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include volatile RAM such as DRAM, SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile RAM such as PRAM, ReRAM, MRAM, and FRAM. In an embodiment, the application processor 4100 and the memory module 4200 may be packaged on a Package On Package (POP) basis and then may be provided as a single semiconductor package.

The network module 4300 may communicate with an external device. For example, the network module 4300 may support wireless communications, such as Code Division Multiple Access (CDMA), global system for mobile communications (GSM), wideband CDMA (wcdma), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, bluetooth, or Wi-Fi communications. In an embodiment, the network module 4300 may be included in the application processor 4100.

The memory module 4400 may store data. For example, the memory module 4400 may store data received from the application processor 4100. Alternatively, the memory module 4400 may transmit data stored in the memory module 4400 to the application processor 4100. In an embodiment, the memory module 4400 may be implemented as a non-volatile semiconductor memory device, such as a phase change ram (pram), a magnetic ram (mram), a resistive ram (rram), a NAND flash memory, a NOR flash memory, or a NAND flash memory having a three-dimensional (3D) structure. In an embodiment, the memory module 4400 may be provided as a removable storage medium (i.e., a removable drive), such as a memory card or an external drive of the user system 4000.

In an embodiment, the memory module 4400 may include a plurality of non-volatile memory devices, each of which may operate in the same manner as the memory device 100 described above with reference to fig. 1. The memory module 4400 may operate in the same manner as the memory device 50 described above with reference to fig. 1.

The user interface 4500 may include an interface that inputs data or instructions to the application processor 4100 or outputs data to an external device. In an embodiment, the user interface 4500 may include a user input interface such as a keyboard, keypad, button, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric device. The user interface 4500 may further include a user output interface such as a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display device, an active matrix OLED (amoled) display device, an LED, a speaker, and a monitor.

According to the present disclosure, a storage device having improved storage performance and a method of operating the storage device are provided.

Claims

1. A memory device, comprising:

a memory device including a plurality of sequential areas storing a plurality of pieces of data corresponding to consecutive logical addresses input from a host and a random area other than the plurality of sequential areas;

a buffer memory device temporarily storing write data corresponding to a write request provided from the host; and

an operation controller generating combined data by adding dummy data to the write data having a size smaller than a programming unit size of the memory device, the dummy data having a size corresponding to a difference between the size of the write data and the programming unit size; storing the combined data in the memory device; and storing combined data information related to the combined data stored in the memory device in the buffer memory device.

2. The storage device of claim 1, wherein:

the plurality of sequential areas are storage areas that store a plurality of pieces of data respectively corresponding to the logical address groups, and

each of the groups of logical addresses includes consecutive logical addresses.

3. The storage device of claim 1, wherein the buffer memory device further stores:

a sequence mapping table including information on logical addresses of a plurality of pieces of data respectively stored in the plurality of sequence areas and write pointer position information indicating information on a start logical address among logical addresses of each of the plurality of pieces of data to be respectively stored in the plurality of sequence areas; and

a random mapping table including information on logical addresses of data stored in the random area.

4. The storage apparatus according to claim 3, wherein the operation controller stores the combined data based on write pointer position information of a sequential area corresponding to a logical address in the write request among the plurality of sequential areas.

5. The storage apparatus according to claim 4, wherein a logical address of the write pointer position information corresponding to a sequential area corresponding to a logical address in the write request and a logical address of the combined data are consecutive addresses.

6. The storage apparatus according to claim 2, wherein the combined data information includes information on a logical address corresponding to the dummy data among logical addresses included in a logical address group of a sequential area among the plurality of sequential areas, the sequential area corresponding to the logical address in the write request; and information on a sequential area where the virtual data is stored.

7. The storage device of claim 6, wherein the combined data information further comprises information about a size of the virtual data.

8. The storage device of claim 2, wherein:

after the combined data has been stored in the memory device, the buffer memory device temporarily stores subsequent write data corresponding to a subsequent write request input from the host, and

the operation controller controls the buffer memory device and the memory device so as to store sub-data of the subsequently written data in the random area, the sub-data having a size corresponding to that of the dummy data.

9. The storage device according to claim 8, wherein the operation controller controls the buffer memory device and the memory device so that remaining data of the subsequent write data, which is remaining data other than the sub data, is stored in a sequential area corresponding to a logical address in the subsequent write request among the plurality of sequential areas.

10. The memory device according to claim 9, wherein the logical address of the remaining data is consecutive to a last logical address among the logical addresses of the combined data.

11. The storage device of claim 8, wherein the operation controller stores information on logical and physical addresses of the sub data in a random mapping table, the random mapping table including information on logical addresses of data stored in the random area.

12. A memory device, comprising:

a memory device including a plurality of sequential areas storing a plurality of pieces of data corresponding to consecutive logical addresses input from a host and a random area other than the plurality of sequential areas; and

a memory controller receiving a write request from the host and controlling the memory device to store a portion of write data corresponding to the write request in the random area according to whether dummy data has been stored in a sequential area corresponding to a logical address included in the write request among the plurality of sequential areas.

13. The storage device of claim 12, wherein:

the plurality of sequential areas are storage areas in which a plurality of pieces of data respectively corresponding to the logical address groups are stored, and

each of the groups of logical addresses includes consecutive logical addresses.

14. The storage device of claim 12, wherein the memory controller comprises a buffer memory device that stores:

a sequence mapping table including information on logical addresses of a plurality of pieces of data respectively stored in the plurality of sequence areas and write pointer position information indicating information on a start logical address among logical addresses of each of the plurality of pieces of data to be respectively stored in the plurality of sequence areas,

a random mapping table including information on logical addresses of data stored in the random area, an

Combining data information including information on the virtual data stored in the plurality of sequential areas.

15. The storage device according to claim 14, wherein the memory controller controls the buffer memory device and the memory device so that sub-data of the write data, a size of which corresponds to a size of the virtual data, is stored in the random area when the virtual data is stored in a sequential area corresponding to a logical address included in the write request.

16. The storage device according to claim 15, wherein the memory controller controls the buffer memory device and the memory device so that remaining data of the write data, which is remaining data other than the sub data, is stored in a sequential area corresponding to a logical address included in the write request.

17. The storage apparatus according to claim 16, wherein the logical address of the remaining data is consecutive to a last logical address among the logical addresses of the dummy data.

18. The storage device of claim 16, wherein the memory controller stores information on logical addresses and physical addresses of the sub data in the random mapping table, and

wherein the logical address of the sub data is the same address as the logical address of the virtual data.

19. The storage device of claim 14, wherein:

the plurality of sequential areas are storage areas that store a plurality of pieces of data respectively corresponding to the logical address groups,

each of the groups of logical addresses comprises consecutive logical addresses, an

The combined data information includes information on a logical address corresponding to the dummy data among logical addresses included in a logical address group of a sequential region among the plurality of sequential regions, the sequential region corresponding to the logical address in the write request; and information on a sequential area where the virtual data is stored.

20. A memory device, comprising:

a buffer memory device storing a sequence mapping table including information on logical addresses of a plurality of pieces of data respectively stored in the plurality of sequence areas, a random mapping table including information on logical addresses of data stored in the random area, and combined data information including information on virtual data stored in the plurality of sequence areas; and

a memory controller that acquires read data corresponding to a read request from at least one of the random area and a sequential area corresponding to a logical address included in the read request among the plurality of sequential areas according to whether the logical address included in the read request input from the host is included in the combined data information, and provides the read data to the host.