KR20170061781A - Display device - Google Patents

Abstract

The present invention includes a plurality of pixels in which a plurality of pixels defined by intersecting scan lines and data lines are arranged and includes a deformed active region including a curved portion having a center C of a circle and a bezel region disposed outside the deformed active region And a multiplexer arranged to be distributed along the curved line of the active area on the bezel area and to distribute the supplied data voltage to the data lines by time division.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device capable of implementing a narrow bezel.

Display devices are becoming smaller and slimmer for users to carry easily for use in wearable and flexible devices.

1, the display panel includes a pixel array (A / A), which is a pixel array in which an image is displayed, and a bezel area BZ, which is disposed outside an active area (A / A) . In the bezel region BZ, a multiplexer (hereinafter referred to as MUX) that receives a data signal output from the data driving circuit and supplies a data signal to the data lines of the active area (A / A) (Or a scan driver circuit) and a pixel array (A / A) that sequentially supply gate pulses (or scan pulses) synchronized with gate lines (or scan lines) (VDD, Vref, VSS) lines are arranged.

The multiplexer MUX, the high voltage line VDD and the reference voltage line Vref Line are arranged at the top of the active pixel array A / , And the gate drive circuit and the low potential voltage line (VSS Line) are disposed on both sides of the active area (Pixel Array, A / A). The high potential voltage line (VDD Line) is a line for supplying a high potential voltage for driving the driving TFT of the compensating pixel or driving the OLED. The reference voltage line Vref is a line for supplying a reference voltage for resetting the potential of the TFT and OLED when driving the compensating pixel. The low potential voltage line (VSS Line) is a line that is electrically connected to the cathode when the OLED is driven and supplies a low potential voltage which generates a potential difference with the high potential voltage. An AP switch is a switch circuit necessary for checking the lighting of a display panel.

On the other hand, the multiplexer (MUX) is concentrated on the upper portion of the active area (A / A), so that the width Y and the width X of the upper bezel area Upper BZ where the multiplexer MUX is disposed . As shown by the dotted line in FIG. 1, as the width Y and the width X of the upper bezel area Upper BZ increase, the width of the bezel area also increases, so narrow bezel can not be realized.

An object of the present invention is to provide a display device capable of implementing a narrow bezel by reducing the width and width of the upper bezel area (Upper BZ) by dispersing the multiplexer disposed in the bezel area along the edge of the release active area .

According to an aspect of the present invention, there is provided a display device including a plurality of pixels, each of which is defined by intersecting scan lines and data lines, And a multiplexer arranged to be distributed along curved lines of the active region on the display panel and the bezel region and to distribute the supplied data voltage to the data lines by time division.

The multiplexer is responsive to the mux control signal to time-divide the data voltage, to multiplexer switches for distributing the time-divided data voltage to the data lines, and to multiplexer clock wirings electrically coupled to the multiplexer switches, And a bending angle at which the multiplexer clock wiring is bent includes a range of 90 degrees or more and less than 180 degrees.

A data routing wiring which is disposed along the multiplexer clock wiring banded on the bezel area and supplies the data voltage outputted from the data driving circuit to the pixels, a data routing wiring which is disposed along the edge of the data routing wiring, And a reference voltage line portion disposed along the edge of the high potential line portion for supplying the upper power source voltage to the pixel and supplying a reference voltage lower than the high potential power source voltage from the power generating portion to the pixel.

And a gate driving circuit which is disposed along the edge of the reference voltage line portion and supplies a scan pulse to the scan lines. The first and second gate driving circuits, which are spaced apart from the center C of the circle and the outermost contacts of the gate driving circuit, And the length between the outer contact points is the same within a predetermined error range.

And a low potential line portion disposed along the edge of the gate drive circuit and supplying a low potential power supply voltage lower than the reference voltage from the power generation portion to the pixel.

The data routing wiring and the multiplexer include those disposed in the upper half of the mold release display panel.

And an AP switch circuit disposed between the mold active region and the gate driving circuit and electrically connected to the scan lines and the data lines to check the lighting of the pixels, .

The width of the high potential line portion disposed in the upper half of the bezel includes a width larger than a width of the reference voltage line portion disposed in the upper half of the bezel region.

The width of the reference voltage line portion disposed in the upper half of the bezel region includes a width smaller than a width of the reference voltage line portion disposed in the lower half of the bezel region.

The high potential line portion includes being disposed along the data routing wiring while keeping a certain distance from the data routing wiring.

The present invention can reduce the width and width of the upper bezel area (Upper BZ) by dispersing the multiplexer disposed in the bezel area along the edge of the release active area. As a result, the narrow bezel can be easily implemented.

Further, the present invention can reduce the bezel area and easily implement the narrow bezel, thereby improving the degree of freedom of design or the degree of freedom of design.

1 is a view schematically showing a conventional display device,
2 is a block diagram showing a display device according to an embodiment of the present invention,
3 is a view showing a mold release display panel according to an embodiment of the present invention,
Figure 4 is a simplified view of a portion of a pixel array,
5 is an equivalent circuit diagram showing an example of a pixel,
Figure 6 is a waveform diagram showing the operation of the pixel of Figure 5,
7A is a view showing a connection mode between a multiplex switch and a multiplex clock wiring according to an embodiment of the present invention,
7B is an equivalent circuit diagram showing an example of a multiplexer,
8 is a view showing a shift register of the GIP circuit,
9 and 10 are views showing various connection forms of the gate driving circuit and the scan lines when the GIP circuit is disposed on both sides of the mold release display panel PNL in the bezel area,
11 is a view showing AP switch circuits disposed in a bezel region,
12 is a view showing that a multiplex clock wiring is connected between a multiplexer and a neighboring multiplexer,
13 is a view showing various banding shapes of a multiplex clock wiring,
14 is a view showing the outermost contacts of the GIP circuit according to the embodiment of the present invention,
15 is a view showing a relationship between the width of the high-potential line portion and the width of the reference voltage line portion and the width of the reference voltage line portion disposed in the upper and lower hemispheres according to the embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

2 is a block diagram showing a display device according to an embodiment of the present invention. FIG. 3 is a diagram showing a display panel (PNL) 110 according to an embodiment of the present invention. FIG. 5 is an equivalent circuit diagram showing an example of a pixel, and FIG. 6 is a waveform diagram showing the operation of the pixel of FIG. 5. Referring to FIG.

2 to 6, a display device 100 according to an embodiment of the present invention includes a display panel (PNL) 110 and a display panel (PNL) And a display driving circuit for writing data of the data signal.

The mold release display panel (PNL) 110 includes data lines DL, scan lines GL orthogonal to the data lines DL, and data lines GL defined by the data lines DL and the scan lines GL. And a pixel array in which pixels 10 are arranged in a matrix form. And the mold releasing display panel (PNL) 110 includes a curved section having the center C of the circle. The mold release display panel (PNL) 110 includes a mold release active area (A / A) and a bezel area BZ. The pixel active area (A / A) includes a pixel array of the display panel (PNL) 110, and data of the input image is displayed. The differential display panel (PNL) 110 includes a reference line (REF line) commonly connected to neighboring pixels 10, a high potential Line (VDD Line). The scan lines GL include a plurality of first scan lines GL1 supplied with a first scan pulse and a plurality of second scan lines GL2 supplied with a second scan pulse. The data lines DL supply the data voltages to the pixels 10.

Each of the pixels 10 is divided into a red subpixel, a green subpixel, and a blue subpixel for color implementation. Each of the pixels 10 may further include a white subpixel. A line such as one data line DL, one scan line GL pair, one reference voltage REF line and one high potential VDD line is connected to each of the pixels 10. The pair of scan lines GL includes one first scan line GL and one second scan line GL.

The bezel area BZ is disposed outside the pixel active area (A / A). (Not shown), a multiplexer 160, a data routing wiring (Data Routing) 111, a high potential line portion (VDD Line) 112, a reference voltage line portion (Vref Line) 113 , A gate drive circuit (GIP) 120, and a low potential line portion (Vss Line) 114.

As shown in FIG. 3, dummy pixels (not shown) are arranged along the edge of the pixel active array (A / A). The dummy pixels (not shown) are formed in the same manner as the pixel array, but are pixels in which the data of the input image is not displayed.

The gate drive circuit (GIP) 120 includes a shift register. A shift register includes stages that are connected in a dependent manner. The stages output the scan pulses SCAN1 and SCAN2 in response to the start pulse Vst and shift the outputs of the scan pulses SCAN1 and SCAN2 according to the shift clocks GCLK1 to GCLK4. The gate driver circuit (GIP) 120 may be disposed directly on the bezel area BZ of the mold release display panel (PNL) 110 according to the scheme of a gate-driver In Panel (GIP) circuit. A gate-driver In Panel (GIP) circuit 120 is spaced apart from the pixel active area (A / A) by a predetermined distance on the bezel area BZ and is connected to the curved line of the pixel active area (A / A) And supplies a scan pulse to the scan lines GL. The GIP circuit 120 is disposed on each of both sides of a release active area (A / A) around a release active area (A / A). The GIP circuit 120 divides the scan lines GL into groups and supplies scan pulses to the divided groups. A description thereof will be given later. The GIP circuit 120 is arranged on both sides of the pixel active area (A / A), but the present invention is not limited thereto. The GIP circuit 120 may be disposed on one side or the other side of a pixel active array (A / A).

The data routing wiring (Data Routing) 111 is disposed between the pixel active region (A / A) and the gate drive circuit (GIP) 120 and is electrically connected to the data driving circuit (SIC) And supplies the data voltages output from the driving circuit (SIC) 140 to the pixels 10. [ The data routing wiring (Data Routing) 111 is corresponded one-to-one with the output channels of the data driving circuit (SIC) 140 via the pad portion 118. The data routing wiring (Data Routing) 111 is disposed on each of both sides of the release active area (A / A) around the release active area (A / A).

A multiplexer 160 is disposed between a pixel active area (A / A) and a data routing wiring (Data Routing) 111. The data routing wiring (Data Routing) 111 receives a data voltage and time- To the data lines DL. The multiplexer 160 is electrically connected at one end to the data routing line 111 and the other ends are electrically connected to the data lines DL. The inside of the multiplexer 160 disposed close to the pixel active area (A / A) is spaced apart from the dummy pixels (not shown) by a predetermined distance and disposed along the edge of the dummy pixel (not shown). The outside of the multiplexer 160, which is the opposite side of the inside of the multiplexer 160, is also spaced apart from the data routing wiring 111. In this manner, the multiplexer 160 is disposed apart from the dummy pixel (not shown) and the data routing wiring 111, thereby connecting the multiplexer 160 with the dummy pixel (not shown) or the data routing wiring Data Routing 111) can be prevented from occurring in advance.

The data routing wiring 111 and the multiplexer 160 are arranged in the upper half of the pixel active area (A / A). The upper half of the pixel active area (A / A) is an upper area disposed on the upper side with respect to a horizontal line passing through the center of the pixel active area (A / A), and the pixel active area / A is defined as a lower region disposed below the horizontal line passing through the center of the deformed active region (A / A).

The high potential line portion 112 is disposed between the data routing wiring 111 and the gate driving circuit GIP 120 and supplies a high potential power voltage output from the power generating portion to the pixel. The inner side of the high potential line portion 112 is disposed close to the pixel active region A / A and spaced apart from the data routing wiring 111 by a predetermined distance, , 111). Here, the high-potential power supply voltage is a power source for driving the driving TFT (Dr-Tr) of the compensating pixel or for driving the OLED.

The high potential equalization lead-in portion 117 is arranged in the upper half of the mold release display panel (PNL) 110 to uniformly supply the high potential power supply voltage VDD to the pixel 10 of the pixel active region (A / A) Can supply.

The reference voltage line portion Vref Line 113 is disposed between the high potential line portion 112 and the gate drive circuit GIP 120 and is connected to the high potential power supply voltage VDD from the power generating portion (not shown) And supplies the lower reference voltage Vref to the pixel 10. [ The inside of the reference voltage line portion (Vref Line) 113 is disposed close to the pixel active region (A / A) and is spaced apart from the high potential line portion (VDD Line) 112 by a predetermined distance, VDD Line, 112. [0035] The reference voltage Vref is a power required to reset the potential of the TFT and the OLED when the compensating pixel is driven. The reference voltage Vref may be an initial (VINI) power source.

Also, the reference voltage line portion (Vref Line) 113 is arranged in the lower hemisphere. The reference voltage line portion (Vref Line) 113 is electrically connected to the dummy capacitor 116 and the reference voltage equalization lead-in portion 118.

The dummy capacitor 116 is disposed in the lower hemisphere of the bezel region BZ and is electrically connected to the reference voltage line portion (Vref Line) 113. The dummy capacitor 116 receives a reference voltage and can compensate for the capacitance of the capacitor depending on the position of the pixel active area (A / A).

The reference voltage equalization lead-in portion 118 is disposed at a lower half of the pixel array A / A to uniformly apply the reference voltage Vref to the pixels 10 of the pixel array A / .

The low potential line portion (Vss line) 114 is disposed along the edge of the gate drive circuit (GIP) 120 and supplies a low potential power supply voltage Vss lower than the reference voltage Vref from a power generating portion And a low potential line portion (Vss Line) 114 for supplying a voltage to the pixel 10.

The data routing wiring (Data Routing) 111 and the multiplexer 160 are not arranged in the lower half of the mold active area (A / A), and the AP switch circuit 115 can be arranged. By arranging in this manner, the width of the bezel region can be prevented from increasing.

 The AP switch circuit 115 is disposed between the lower half of the pixel active area (A / A) and the gate drive circuit (GIP) 120. The AP switch circuit 115 is electrically connected to the scan lines GL and the data lines DL and operates to check the lighting of the pixel 10. [

FIG. 5 is an equivalent circuit diagram showing an example of a pixel, and FIG. 6 is a waveform showing an operation of the pixel of FIG.

5 and 6, each pixel PXL 10 includes an OLED, a driving TFT DT, first through fifth TFTs T1 through T5, and a storage capacitor Cst. This pixel (PXL) 10 is a 6T1C circuit structure including six PMOS type transistors and one capacitor.

One frame period of the pixel PXL 10 is divided into an initialization period Ti, a sampling period Ts, and an emission period Te.

The first scan signal Scan1 is generated at the ON level during the initialization period Ti and the sampling period Ts to turn the first TFT T1 on and turns off during the emission period Te. Level so as to turn off the first TFT < RTI ID = 0.0 > T1. ≪ / RTI >

The second scan signal Scan2 is generated at the ON level during the initialization period Ti and the emission period Te to turn the second TFT T2 on and turns off during the sampling period Ts Level and controls the second TFT T2 to be in the off state.

The OLED is connected between the fourth node N4 and the low potential power supply voltage VSS and emits light in accordance with the driving current applied from the driving TFT DT.

The driving TFT DT controls the driving current flowing in the OLED according to its gate-source voltage. The gate of the driving TFT DT is connected to the first node N1, the source is connected to the input terminal of the high potential power supply voltage VDD, and the drain is connected to the third node N3.

The first TFT T1 turns on / off the current path between the data line DL and the second node N2 in response to the first scan signal Scan1. The gate of the first TFT T1 is connected to the first scan line GL, the source is connected to the data line DL, and the drain is connected to the second node N2.

The second TFT T2 turns on / off the current path between the first node N1 and the third node N3 in response to the first scan signal Scan1. The gate of the second TFT T2 is connected to the first scan line GL, the source is connected to the first node N1, and the drain is connected to the third node N3.

The third TFT T3 turns on / off the current path between the input terminal of the reference voltage Vref and the fourth node N4 in response to the first scan signal Scan1. The gate of the third TFT T3 is connected to the first scan line GL, the source thereof is connected to the input terminal of the reference voltage Vref, and the drain thereof is connected to the fourth node N4.

The fourth TFT T4 turns on / off the current path between the input terminal of the reference voltage Vref and the second node N2 in response to the second scan signal Scan2. The gate of the fourth TFT T4 is connected to the second scan line GL, the source thereof is connected to the input terminal of the reference voltage Vref, and the drain thereof is connected to the second node N2.

The fifth TFT T5 turns on / off the current path between the third node N3 and the fourth node N4 in response to the second scan signal Scan2. The gate of the fifth TFT T5 is connected to the second scan line GL, the source is connected to the third node N3, and the drain is connected to the fourth node N4.

The storage capacitor Cst is connected between the first node N1 and the second node N2.

The operation of the pixel (PXL) 10 will now be described.

During the initialization period Ti, the first to fifth TFTs T1 to T5 are turned on in response to the first and second scan signals Scan1 and Scan2 at the ON level. During the initialization period Ti, the voltages of the first to fourth nodes N1 to N4 are initialized to the reference voltage Vref.

During the sampling period Ts, the first to third TFTs T1 to T3 maintain a turn-on state in response to the first scan signal Scan1 at the ON level, whereas the fourth and fifth TFTs The TFTs T4 and T5 are turned off in response to the second scan signal Scan2 of the OFF level. During the sampling period Ts, the data voltage Vdata is applied to the second node N2 through the data line DL. During the sampling period Ts, the potentials of the first and third nodes N1 and N3 become "VDD-Vth ". Vth indicates the threshold voltage of the driving TFT DT.

The emission period Te continues from the sampling period Ts to the initialization period Ti of the next frame. During the emission period Te, the first to third TFTs T1 to T3 are turned off in response to the first scan signal Scan1 of the OFF level, and the fourth and fifth TFTs T4, T5 are turned on in response to the second scan signal Scan2 of the ON level.

The reference voltage Vref is applied to the second node N2 during the emission period Te and the potential change Vref-Vdata of the second node N2 is reflected to the first node N1. During the emission period Te, the potential of the first node N1 is programmed to "(VDD-Vth) + (Vref-Vdata) ". Therefore, during the emission period Te, the gate-source voltage Vgs of the driving TFT DT is programmed to "Vdata-Vref + Vth".

The OLED emits light by the driving current Ioled flowing through the OLED during the emission period Te to express the brightness of the input image.

The display driving circuit includes a data driving circuit (SIC) 140 for outputting data voltages to the data lines DL through a multiplexer 160, a scan driving circuit And a gate driving circuit (GIP) 120 for sequentially supplying the driving signals to the scanning lines GL. A multiplexer 160 is disposed between the data driving circuit SIC 140 and the data lines DL. The display driving circuit is disposed in an area excluding the pixel active area (A / A).

The data driver circuit (SIC) 140 converts the data (DATA1 to DATA4) of the input image received from the timing controller (not shown) into a gamma compensation voltage under the control of a timing controller And outputs the data voltage. The data voltage is supplied to the data lines DL through a multiplexer 160. [ The data driving circuit SIC 140 may output a predetermined reference voltage Vref to the data lines DL during the initialization period in order to initialize the driving elements of the pixels 10. [ The data driver circuit (SIC) 140 is connected to the pad portion 118 using an anisotropic conductive film (ACF). The data driver circuit (SIC) 140 is bonded on the flexible circuit board (COF) 140a and is electrically connected to the pad portion 180 through an anisotropic conductive film (ACF). On the flexible circuit board (COF) 140a, a timing controller (not shown), a touch driving circuit (not shown), and the like can be bonded. The data driving circuit (SIC) 140, which is bonded onto the flexible circuit board (COF) 140a, can be disposed at the rear end of the mold release display panel (PNL) 110.

A multiplexer 160 is disposed between the data driving circuit SIC 140 and the data lines DL. A multiplexer 160 distributes the data voltage input from the data driving circuit (SIC) 140 to the data lines DL under the control of a timing controller (not shown). In the case of a 1: 6 multiplexer 160, a multiplexer 160 divides the data voltages input through one output channel of the data driving circuit (SIC) 140 into six data lines DL, . Therefore, by using a 1: 6 multiplexer 160, the number of ICs of the data driver circuit (SIC) 140 required for driving the display panel (PNL) 110 can be reduced to 1/6.

In addition, the multiplexer 160 has a limitation in reducing the width of the bezel area BZ when aligned in a row on the top of the display panel (PNL) 110. Accordingly, the multiplexer 160 may be disposed along the edge of the pixel active area (A / A). The multiplexer 160 is distributed and arranged in correspondence with the shape of the upper half of the mold release display panel (PNL) 110, thereby reducing the width of the bezel area BZ.

7A and 7B, a multiplexer 160 includes a multiplexer switch 162 (hereinafter, referred to as a mux switch) and a multiplexer clock wiring 161 (hereinafter, referred to as MUX clock wiring). .)).

Mux switches M1 to M6 and 162 include a plurality of MTFTs M1 to M6. The mux switches M1 to M6 and 162 operate to supply or cut off the time-divided data voltage to the data lines DL in response to the mux control signal.

The mux clock wirings (ME1 to ME6, 161) are formed of at least two or more. The mux clock wirings ME1 to ME6 and 161 are arranged to correspond to each of the plurality of MTFTs M1 to M6. Mux clock wirings (ME1 to ME6, 161) provide the mux control signals to the mux switches (M1 to M6, 162). A timing controller (not shown) outputs a mux control signal and supplies it to the mux clock wirings ME1 to ME6 and 161.

The connection relations of the mux switches M1 to M6 and 162 and the mux clock wirings ME1 to ME6 and 161 are as follows.

Mux switches M1 to M6 and 162 include first MTFT (M1) to sixth MTFT (M6). The first MTFT M1 has a gate connected to the first MUX clock line ME1 and a drain connected to the first output channel DOC1 of the data driving circuit SIC 140 and a source connected to the first data line DL1. . The second MTFT M2 has a gate connected to the second MUX clock line ME2, a drain connected to the first output channel DOC1 of the data driving circuit SIC 140, and a source coupled to the second data line DL2. . The third MTFT M3 has a gate connected to the third MUX clock line ME3, a drain connected to the first output channel DOC1 of the data driving circuit SIC 140, and a source connected to the third data line DL3. . The fourth MTFT M4 has a gate connected to the fourth mux clock wiring ME4, a drain connected to the first output channel DOC1 of the data driving circuit SIC 140, and a source connected to the fourth data line DL4. . The fifth MTFT M5 has a gate connected to the fifth MUX clock wiring ME5, a drain connected to the first output channel DOC1 of the data driving circuit SIC 140, and a source connected to the fifth data line DL5. . The sixth MTFT M6 has a gate connected to the sixth MUX clock wiring ME6, a drain connected to the first output channel DOC1 of the data driving circuit SIC 140, and a source connected to the sixth data line DL6. . Here, the first to sixth mux control signals to the sixth mux control signal may be generated in a timing controller (not shown). In addition, the first to sixth mux control signals to the sixth mux control signal may be signals amplified by a level shift after being generated by a timing controller (not shown).

The gate drive circuit GIP 120 supplies the first scan pulse SCAN1 to the first scan lines GL and the second scan pulse SCAN2 to the second scan line GL under the control of a timing controller (GL). The scan pulses SCAN1 and SCAN2 are synchronized with the data voltage. The GIP circuit 120 includes a shift register. The shift register includes the stages S (N-2) to S (N + 2) that are connected in a dependent manner, as shown in FIG. The stages S (N-2) to S (N + 2) start outputting the scan pulses SCAN1 and SCAN2 in response to the start pulse Vst and output the outputs in accordance with the shift clocks GCLK1 to GCLK4 Shift. Output signals sequentially output from the stages S (N-2) to S (N + 2) are supplied to the scan lines GL as scan pulses SCAN1 and SCAN2. The output of each of the stages S (N-2) to S (N + 2) is input as the start pulse Vst of the next stage and its output is also input to the previous stage as a reset signal . The stages may output a carry signal different from the scan pulse and supply the start pulse Vst to the next stage. The carry signal is input as the next stage start pulse, and the reset signal discharges the output of the previous stage. Scan timing control signals such as a start pulse Vst and shift clocks GCLK1 to GCLK4 are input to the stages S (N-2) to S (N + 2) through the scan lines GL.

Figs. 9 and 10 are views showing various connection forms of the gate drive circuit and the scan lines when the GIP circuit is disposed on both sides of the mold release display panel in the bezel area.

9, the GIP circuit 120 includes a first GIP circuit (GIP (L), 120) disposed at one edge of a mold release display panel (PNL) 110 and a second GIP circuit And a second GIP circuit (GIP (R), 120) disposed at the edge.

Each of the first and second GIP circuits 120, GIP (L), and GIP (R) may be connected to all the scan lines GL1 to GLn. Each of the first and second GIP circuits 120, GIP (L) and GIP (R) receives the start pulse Vst at the same time and outputs a scan pulse at the same time. Therefore, the scan pulses output from the first and second GIP circuits 120, GIP (L), and GIP (R) are simultaneously applied to both ends of the same scan line GL.

Referring to FIG. 10, the first GIP circuit 120 (GIP (L)) is connected to the first group of scan lines GL to sequentially supply scan pulses to the first group of scan lines GL . The second GIP circuit 120 (GIP (R)) is connected to the second group of scan lines GL to sequentially supply scan pulses to the second group of scan lines GL.

The first group of scan lines GL may be the odd-numbered scan lines GL1, GL3, ..., GL2n-1 as shown in FIG. The second group of scan lines GL may be the even scan lines GL2, GL4, ..., GL2n as shown in FIG. The start pulse Vst may be supplied to the first and second GIP circuits 120, GIP (L) and GIP (R) with a predetermined time difference. Therefore, there may be a predetermined time difference between the scan pulse output timing and the carry signal output timing of the first and second GIP circuits 120 (GIP (L), GIP (R)). For example, The first scan pulse is supplied from the second GIP circuit 120 (GIP (R)) to the first scan line (GL1) 2 scan line GL2.

Among the display driving circuits described so far, the GIP circuit 120 is arranged in the bezel region BZ and the data driving circuit SIC 140 is arranged in the rear stage of the display panel PNL. A timing controller (not shown) transmits the digital data of the input image to the data driving circuit (SIC) 140 and controls the operation timings of the data driving circuit (SIC) 140 and the GIP circuit 120. A timing controller (not shown) controls the multiplexer 160 to distribute the data voltages input from the data driving circuit (SIC) 140 to the data lines DL.

A timing controller (not shown) may be bonded onto the flexible circuit board (COF) 140a. A timing controller (not shown) bonded on the flexible circuit board (COF) 140a may be disposed on the rear surface of the display panel (PNL) 110 together with the data driving circuit (SIC) 140.

11 is a diagram showing AP switch circuits disposed in a bezel region.

Referring to FIG. 11, the AP switch circuit 115 includes AP lines, AP switches, and AP pads (AP PAD) 115a. AP lines include R, G, and B enable lines, R lines, G lines, and B lines. The AP lines are disposed in a bezel area BZ outside the pixel array.

The AP pads 115a may be disposed in the bezel area BZ of the lower half of the display panel (PNL) 110 and connected to the AP lines. The AP switches AP TR may be disposed in the bezel area BZ of the lower half of the release display panel (PNL) 110 and connected to the AP lines. The AP switches AP TR include a first ATFT (Q1), a second ATFT (Q2), and a third ATFT (Q3). The first ATFT (Q1) supplies the R test signal to the first data line DL1 connected to the R subpixel in response to the R enable signal R_EN. The gate of the first ATFT (Q1) is connected to the R enable line. The drain of the first ATFT (Q1) is connected to the R line, and the source of the first ATFT (Q1) is connected to the first data line (DL1). The second ATFT (Q2) supplies a G test signal to the second data line (DL2) connected to the G subpixel in response to the G enable signal (G_EN). The gate of the second ATFT (Q2) is connected to the G enable line. The drain of the second ATFT (Q2) is connected to the G line, and the source of the second ATFT (Q2) is connected to the second data line DL2. The third ATFT (Q3) supplies the B test signal to the third data line DL3 connected to the B sub-pixel in response to the B enable signal B_EN. The gate of the third ATFT (Q3) is connected to the B enable line. The drain of the third ATFT (Q3) is connected to the B line, and the source of the third TFT (T3) is connected to the third data line DL3.

The AP pads 115a are electrically connected to the AP lines and supply an enable signal and an RGB test signal to these AP lines.

In the inspection process, the auto-probe inspection apparatus supplies an enable signal, an RGB test signal through AP pads 115a, and supplies scan test signals to GIP lines via GIP pads (not shown). The GIP pads are connected to the GIP lines and are in contact with the needles of the auto-probe inspection apparatus in the inspection process. The scan test signals include signals such as a start pulse, a shift clock, and the like for driving the shift register of the GIP driving circuit GIP. When the scan lines GL and the data lines DL are driven in this manner, the data driving circuit SIC 140 is not mounted on the display panel PNL 110, .

Figure 12 shows that the multiplexer clock wiring is connected to the multiplexer and the neighboring multiplexer.

Referring to FIG. 12, a multiplexer 160 of the present invention includes mux clock wirings ME1 to ME6 and mux switches M1 to M6. The mux clock wirings ME1 to ME6 are electrically connected to each of the plurality of mux switches M1 to M6.

The MUX clock wirings ME1 to ME6 include first to Mux clock wirings ME1 to K (K is a natural number of 2 or more) MUX clock wirings (MEK). The mux clock wirings ME1 to ME6 are arranged in the same number as the number of the mux switches M1 to M6 arranged in the multiplexer 160. [ In FIG. 12, the description will be focused on that the MUX clock wirings ME1 to ME6 are the first to MUX clock wirings ME1 to ME6.

The first multiplexer MUX1 includes the first to Mux clock lines ME1 to ME6 and the eleventh MTFTs M11 to M16. The second multiplexer MUX2 includes the first to Mux clock lines ME1 to ME6 and the twenty-first MTFTs M21 to M26. At this time, the first to Mux clock lines ME1 to ME6 are commonly used in the first multiplexer MUX1 and the second multiplexer MUX2.

The first MUX clock line ME1 is commonly connected to the gate of the eleventh MTFT M11 and the gate of the twenty-first MTFT M21, the second MUX clock line ME2 is connected to the gate of the twelfth MTFT M12, 22 MTFT M22 and the third MUX clock line ME3 is commonly connected to the gate of the thirteenth MTFT M13 and the gate of the 23rd MTFT M23 and is connected to the gate of the fourth MUX clock line ME4 Is connected in common with the gate of the 14th MTFT (M14) and the gate of the 24th MTFT (M24), the fifth mux clock wiring ME5 is connected to the gate of the 15th MTFT (M15) And the sixth MUX clock wiring ME6 is commonly connected to the gates of the sixteenth MTFT M16 and the gates of the twenty sixth MTFT M26.

The first output channel DOC1 of the data driving circuit SIC 140 is connected to the drain of the eleventh MTFT M11 to the drain of the sixteenth MTFT M16, The second output channel DOC2 is connected corresponding to each drain of the twenty-first MTFT (M21) to the drains of the twenty-sixth MTFT (M26).

The first to sixth data lines DL1 to DL6 are connected to the sources of the eleventh MTFT M11 to the sixteenth MTFT M16 and the seventh data lines DL7 to DL12, The data line DL12 is connected corresponding to each of the sources of the twenty-first MTFT (M21) to the twenty-sixth MTFT (M26).

As described above, the first multiplexer MUX1 and the second multiplexer MUX2 are spaced apart from each other by a predetermined distance from the dummy pixels (not shown) disposed at the edges of the pixel active area (A / A) Not shown). Since the first multiplexer MUX1 and the second multiplexer MUX2 are distributed and arranged, a height difference occurs between the first multiplexer MUX1 and the second multiplexer MUX2. The Mux clock wirings ME1 to ME6 are bent at a predetermined angle in order to commonly connect the first multiplexer MUX1 and the second multiplexer MUX2 having a difference in height. The bending angle BA at which the mux clock wirings ME1 to ME6 are bent may be 90 degrees or more and less than 180 degrees.

The multiplexer MUX1 and MUX2 are formed along the curved section of the pixel active array (A / A) by forming the bending angles BA to be bent at 90 degrees or more and less than 180 degrees, Can be routed while minimizing the empty space of the bezel area BZ.

The mux clock wirings ME1 to ME6 can be routed close to the circular shape as the bending angle BA to be bending becomes larger. As the mux clock wirings ME1 to ME6 are routed close to the circular shape, the deviation of the spacing distance from the data routing wiring is reduced. The bezel area BZ has an interval margin that can reduce the separation distance between the mux clock wirings ME1 to ME6 and the data routing wiring by a deviation of the separation distance in which the mux clock wirings ME1 to ME6 are reduced I have. The bezel area BZ further reduces the spacing distance by the generated spacing margin at the spacing distance between the mux clock wires ME1 to ME6 and the data routing wiring so that the bezel area BZ is wasted Can be reduced.

Thus, the bezel areas BZ are routed close to the substantially circular shape of the mux clock wirings ME1 to ME6 so that data routing wiring arranged after the multiplexers MUX1 and MUX2, The portion VDD, the reference voltage line portion Vref, the GIP circuit 120, and the low potential line portion Vss can be easily designed in a circular shape in correspondence thereto.

13 shows various banding shapes of the Mux clock wiring and the data routing wiring.

13, the MUX clock wiring 161 and the data routing wiring 111 can be divided into a curved type or a stair type depending on the banding angle at which they are bent.

13 (a) and 13 (b), when the Mux clock wirings 161 are formed in a curved type, the data routing wirings 111 corresponding to the curved type (FIG. 13 (a)) or A step type (Fig. 13 (b)), or the like. 13 (c) and 13 (d), when the mux clock wirings 161 are formed in the step type, the data routing wiring 111 corresponds to the curved type A step type (Fig. 13 (d)), or the like. The bezel region BZ in which the mux clock wiring 161 or the data routing wiring 111 is disposed has an interval margin that can reduce the separation distance between the mux clock wirings 161 and the data routing wiring 111. [

If the data routing wiring 111 and the MUX clock wirings 161 are formed in the same type, the deviation of the spacing distance therebetween is reduced. The bezel region BZ has an interval margin that can reduce the distance between the mux clock wiring 161 and the data routing wiring 111 as the deviation of the spacing distance is reduced.

The bezel area BZ can further reduce the space wasted in the bezel area BZ by further reducing the spacing distance between the mux clock wirings 161 and the data routing wiring 111 by the generated spacing margin. Thus, the separation distance between the MUX clock wiring 161 and the data routing wiring 111 can be minimized to the allowable range in which no short circuit occurs between the MUX clock wiring 161 and the data routing wiring 111. Therefore, the bezel area BZ can reduce the waste of space, thereby effectively reducing the overall width of the bezel area BZ.

Also, although the data routing wiring 111 and the MUX clock wirings 161 are formed in different types, the bezel area BZ can have an interval margin that can reduce the separation distance therebetween. However, when the data routing wiring 111 and the mux clock wirings 161 are of different types, the bead area BZ is a type in which the data routing wiring 111 and the mux clock wirings 161 are of different types Is smaller than the interval margin. Accordingly, it is preferable that the data routing wiring 111 and the MUX clock wirings 161 are formed in the same type.

14 is a diagram showing the outermost contacts of the GIP circuit 120 according to the embodiment of the present invention.

Referring to FIG. 14, a pixel active array (A / A) includes a curve section having a center C of a circle.

The GIP circuit 120 includes a shift register. A shift register includes stages that are connected in a dependent manner. The GIP circuit 120 includes the outermost contacts Om1 and Om2. The outermost contacts Om1 and Om2 are the contacts located farthest from the center C of the circle in the GIP circuit 120. [ The outermost contacts Om1 and Om2 may be disposed in each of the stages.

The lengths W1 and W2 measured between the center C of the circle located in the active area A / A and the outermost contacts disposed on the stages are substantially .

The outermost contacts Om1 and Om2 of the stage include a first outermost contact Om1 and a second outermost contact Om1. And the second outermost contact Om2 is disposed apart from the first outermost contact Om1. The first length W1 is defined as a length measured between the center C of the circle and the first outermost contact Om1 and the second length W2 is defined as the length measured between the center C of the circle and the second outermost contact (Om2).

When the first length W1 and the second length W2 are included within a predetermined error range, the first length W1 and the second length W2 may be said to be the same. Here, the error range is preferably within 5%.

When the first length W1 and the second length W2 have the same length within a predetermined error range, the shape connecting the outermost contacts Om1 and Om2 of the stage may be formed to be substantially circular have. The GIP circuit 120 is arranged close to the circular shape along the curve section of the pixel active area A / A so that the low potential line part Vss Line (B), which is adjacent to the GIP circuit 120 in the bezel area BZ, , 114 are reduced. The bezel region BZ has an interval margin that can reduce the separation distance between the GIP circuit 120 and the low potential line portion (Vss Line) 114 as the deviation of the spacing distance is reduced. The distance between the GIP circuit 120 and the low potential line portion (Vss Line) 114 is set to a permissible range where no short circuit occurs between the low potential line portion (Vss Line) 114 adjacent to the GIP circuit 120 As much as possible. Accordingly, the bezel area BZ easily secures and reduces surplus space, thereby effectively reducing the overall width.

In addition, when the first length W1 and the second length W2 have the same length within a predetermined error range, the shape connecting the outermost contact points Om1 and Om2 of the stage is formed substantially close to a circle The low potential line portion 114 disposed along the edge of the GIP circuit 120 can also be routed uniformly. It is possible to protect the GIP circuit 120 from moisture or the like that can be penetrated from the outside by forming an organic film on the low potential line portion 114 which is uniformly routed.

Alternatively, when the first length W1 and the second length W2 have different lengths out of the predetermined error range, the shape connecting the outermost contacts Om1 and Om2 of the stage is relatively angular It can be formed close to many polygons. The GIP circuit 120 is disposed in a polygonal shape along the curve section of the pixel active area A / A so that a low potential line part Vss Line, which is adjacent to the GIP circuit 120 in the bezel area BZ, 114 is increased. The bezel area BZ has an increased vacancy space between the GIP circuit 120 and the low potential line part (Vss line) 114 as the deviation of the spacing distance is increased. Thus, there is a limit in reducing the overall width of the bezel area BZ.

As described above, the length measured between the center C of the circle located in the active area (A / A) and the outermost contacts Om1 and Om2 disposed on the stages is set in advance The width of the bezel area BZ can be reduced and the degree of freedom of design can be improved.

15 is a view showing a relationship between the width of the high-potential line portion and the width of the reference voltage line portion and the width of the reference voltage line portion disposed in the upper and lower hemispheres according to the embodiment of the present invention.

Referring to FIG. 15, the release display panel (PNL) 110 can be divided into upper half and lower half.

The upper half of the mold active area (Pixel Array A / A), the upper half of the bezel area BZ and the upper half of the mold release display panel (PNL) 110, Array, A / A), a lower hemisphere of the bezel area BZ, and a lower hemisphere of the display panel (PNL) 110.

The width SP1 of the high potential line portion 112 disposed in the upper half of the bezel region BZ is equal to the width SP21 of the reference voltage line portion Vref Line 113 disposed in the upper half portion of the bezel region BZ, . The high potential line portion 112 is disposed only in the upper half portion. The reference voltage line portion (Vref Line) 113 is formed to have a width SP21 that is smaller than the width SP1 of the high potential line portion 112 in the upper half region arranged in parallel with the high potential line portion 112. [ As described above, by forming the width SP21 of the reference voltage line portion Vref Line 113 smaller than the width SP1 of the high potential line portion 112 in the upper half region, it is possible to reduce the width of the bezel region BZ, Both the upper line portion (VDD Line) 112 and the reference voltage line portion 113 can be arranged.

The width SP21 of the reference voltage line portion Vref Line 113 disposed in the upper half of the bezel region BZ is equal to the width of the reference voltage line portion Vref Line 113 disposed in the lower half of the bezel region BZ, Is smaller than the width SP22. Since the high potential line portion 112 is not disposed in the lower hemisphere, the high voltage line portion 112 can be included in the bezel region BZ having a constant width even if the width of the reference voltage line portion Vref Line 113 is increased.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: mold release display device 110: mold release display panel
111: data routing wiring 112: high potential line portion
113: Reference voltage line section 114: Low potential line section
115: AP switch circuit 116: dummy capacitor
117: high potential equal potential input portion 118: reference voltage equal potential input portion
120: gate driver circuit (GIP circuit) 140: data driving circuit (SIC)
140a: Flexible circuit board 160: Multiplexer (MUX)
161: multiplexer (mux) clock wiring 162: multiplexer (mux) switch
180:

Claims (10)

A plurality of pixels in which scan lines and data lines are defined by being intersected with each other, and a deformed active region including a curved portion having a center (C) of the circle and a bezel region disposed outside the deformed active region Display panel;
And a multiplexer arranged to be distributed along the curved line of the mold active region on the bezel region and to distribute the supplied data voltage to the data lines by time division. The method according to claim 1,
The multiplexer comprising: multiplexer switches for time-dividing the data voltage in response to a mux control signal and distributing the time-divided data voltage to the data line;
And a multiplexer clock wiring electrically connected to the multiplexer switches and supplying the mux control signal to each of the multiplexer switches
Wherein a bending angle at which the multiplexer clock wiring is bent is 90 degrees or more and less than 180 degrees. 3. The method of claim 2,
A data routing wiring arranged to be spaced apart from the multiplexer clock wiring banded on the bezel region and supplying a data voltage output from the data driving circuit to the pixels;
A high potential line portion disposed along an edge of the data routing wiring and supplying a high potential power supply voltage output from the power generating portion to the pixel; And
And a reference voltage line unit arranged along an edge of the high potential line part and receiving a reference voltage lower than the high potential power supply voltage from the power generating unit and supplying the reference voltage to the pixel. 3. The method of claim 2,
And a gate driving circuit arranged along an edge of the reference voltage line part and supplying a scan pulse to the scan lines,
Wherein a length between the center (C) of the circle and the first and second outermost contacts spaced out of the outermost contacts of the gate driving circuit is the same within a predetermined error range. 5. The method of claim 4,
And a low potential line portion disposed along an edge of the gate driving circuit and supplying a low potential power supply voltage lower than the reference voltage to the pixel from the power generating portion. The method according to claim 1,
And the data routing wiring and the multiplexer are disposed in the upper half of the mold release display panel. The method according to claim 6,
And an AP switch circuit disposed between the mold active region and the gate driving circuit and electrically connected to the scan lines and the data lines to operate to check lighting of the pixels,
And the AP switch circuit is disposed in a lower half of the release active area. The method according to claim 6,
Wherein the width of the high potential line portion disposed in the upper half of the bezel region is larger than the width of the reference voltage line portion disposed in the upper half portion of the bezel region. 9. The method of claim 8,
Wherein a width of the reference voltage line portion disposed in a top half of the bezel region is smaller than a width of the reference voltage line portion disposed in a bottom half of the bezel region. 5. The method of claim 4,
And the high-potential line portion is disposed along the data routing wiring while maintaining a predetermined gap with the data routing wiring.

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