KR20170057113A - Multi input power manager - Google Patents

Abstract

According to the present invention, a multi-input power manager comprises: a first to an n^th (n is a natural number larger than one) maximum power tracking circuit to receive first to n^th power from the outside, and control voltages of a first to an n^th voltage by a first to an n^th reference voltage based on the first to the n^th power; a first to an n^th capacitor configured to store the first to the n^th power by control of the first to the n^th maximum power tracking circuit, and connected to the first to the n^th node; a first to an n^th transmission switch connected to the first to the n^th node, and configured to output power stored in the first to the n^th capacitor as output power in response to a first to an n^th switching signal; and a transmission switch control circuit to activate the first switching signal to turn on a first switch connected to the first node if the first reference voltage of the first node is reached.

Description

[0001] MULTI INPUT POWER MANAGER [

The present invention relates to a power harvesting system, and more particularly to a multiple input power manager.

BACKGROUND ART [0002] With the recent miniaturization of electronic devices, battery life or battery capacity included in electronic devices has become a problem. In order to solve such a problem, recently, an energy harvesting power conversion system is being developed. Energy harvesting power conversion systems are used to implement increased battery life or battery-less systems in a variety of small or low power application environments, such as wireless sensor networks. In an energy harvesting power conversion system, the maximum output power is the biggest issue. That is, a maximum power follow-up (MPPT) technique is used to maximize the available energy capacity to continuously deliver the energy required by the load or to store the maximum energy in the energy storage.

In particular, since multiple input source structures receive energy from a plurality of energy source sources, they can output large power when summing the energy from each of the plurality of energy source sources. However, when simultaneously outputting the energy received from each energy source source, a separate power conversion device is required for each energy source source. Since separate power conversion devices require a large area, multiple input source structures are difficult to apply to small devices.

It is an object of the present invention to provide a multiple input power manager for efficiently using multiple input power.

A multiple input power manager according to an embodiment of the present invention receives first to n-th (where n is a natural number greater than 1) powers from the outside, and generates first to n-th powers based on the first to n- n th maximum power follow-up circuits for controlling the voltages of the n nodes to the first through the n th reference voltages, respectively, the first through the n th maximum power follow- N-th input capacitors connected to the first to the n-th nodes, respectively, and connected to each of the first to the n-th nodes, wherein the first to n- N-th transfer capacitors configured to output power stored in each of the first to n < th > input capacitors as output power in response to the first to n-th input capacitors when the first reference voltage of the first node , The first node And a transfer switch control circuit for activating the first transfer switching signal so that the first switch is turned on.

In an embodiment, the transfer switch control circuit deactivates the second to the n-th switching signals so that the second to the n-th transfer switches are turned off when the first switching signal is activated.

In one embodiment, when the voltage at the first node coupled to the first turn-on transfer switch reaches a first minimum voltage, the transfer switch control circuit switches the first transfer switch such that the first transfer switch is turned off, Deactivates the signal.

As an embodiment, after the first transfer switch is turned off, the transfer switch control circuit may be configured such that the transfer switch connected to the node having a voltage that reaches the corresponding one of the second to the n < th & The first to n < th > switching signals are generated.

In an embodiment, the first maximum power follower circuit includes a first voltage ratio controller for receiving the first power and determining the first reference voltage based on the received first power, A first internal capacitor configured to charge the first power according to a control, a first internal switch coupled between the first internal capacitor and the first node, a first internal capacitor coupled between the first reference voltage and the first internal capacitor, And a first control circuit configured to control the first internal switch based on a comparison result of the first comparator.

In an embodiment, each of the first to the n-th reference voltages is different from each other.

In an embodiment, at least two of the first to n-th powers are power provided from the same power source, and at least two of the first to the n-th reference voltages are equal to each other.

In an embodiment, the transfer switch control circuit activates the first switching signal and deactivates the first switching signal after a predetermined time elapses.

In an embodiment, the transfer switch control circuit activates the first switching signal and deactivates the first switching signal when any one of the second to the n-th nodes reaches a corresponding reference voltage.

As an embodiment, the transfer switch control circuit generates the first to the n-th switching signals so that the transfer switch connected to any one of the nodes is turned on after the transfer switch control circuit deactivates the first switching signal.

In an embodiment, each of the first to the n-th reference voltages indicates a voltage at which the first to n-th powers become the maximum power.

A multiple input power manager according to an exemplary embodiment of the present invention includes a first maximum power follower circuit for receiving a first power and following a maximum power of the first power, A first transfer switch operative in response to a first switching signal and coupled between the first input capacitor and the output node, a second transfer switch coupled between the first input capacitor and the output node for receiving a second power to follow the maximum power of the second power A second maximum power follow-up circuit, a second input capacitor for storing the second power in accordance with the control of the second maximum power follow-up circuit, and a second switching circuit operating in response to a second switching signal between the second input capacitor and the output node And a comparison result of a first reference voltage from the first maximum power follow-up circuit and a voltage of the first input capacitor, and a second comparison result of the second maximum voltage follow- And a transfer switch control circuit for generating the first and second switching signals based on a comparison result of a second reference voltage from the power follower circuit and a voltage of the second input capacitor, 1 and the voltages of the second input capacitors reach a corresponding reference voltage, the first and second switching signals are activated so that the transfer switch connected to any one of the input capacitors is turned on.

In an embodiment, the first and second reference voltages are different from each other.

In an embodiment, the first maximum power follow-up circuit includes a first voltage ratio controller for receiving the first power and determining the first reference voltage at which the first power received is at maximum power, A first switch coupled between the first internal capacitor and the first input capacitor, a first comparator comparing the voltages of the first reference voltage and the first internal capacitor, and a second internal capacitor coupled between the first internal capacitor and the first internal capacitor, And a first control circuit for controlling the first switch based on a result of the first comparator.

As an embodiment, the second maximum power follow-up circuit includes a second voltage ratio controller for receiving the second power and determining the second reference voltage at which the received second power is at maximum power, A second switch coupled between the second internal capacitor and the second input capacitor, a second comparator comparing the voltages of the second reference voltage and the second internal capacitor, and a second comparator coupled between the first internal capacitor and the second internal capacitor, And a second control circuit for controlling the second switch based on the result of the second comparator.

According to the present invention, the multiple input power manager outputs the multiple input powers in a time interleaved manner, so that power can be used without waste from each of the multiple power sources, and the power from each of the plurality of power sources Power can be efficiently used. Thus, a multiple input power manager with improved efficiency and reduced cost is provided.

1 is a block diagram illustrating an energy multiple input power management system in accordance with an embodiment of the present invention.
FIG. 2 is a detailed view of the multiple input power manager of FIG. 1. FIG.
FIG. 3 is a diagram showing the first maximum power follow-up circuit of FIG. 2. FIG.
FIG. 4 is a detailed circuit diagram of the power transmission circuit of FIG. 2. FIG.
5 is an exemplary illustration of the transfer switch control circuit of FIG.
6 is an exemplary graph illustrating the operation of the multiple input power manager of FIG.
FIG. 7 is a graph for explaining another embodiment of the multiple input power manager of FIG. 2. FIG.
FIG. 8 is a graph for explaining another embodiment of the multiple input power manager of FIG. 2. FIG.
FIG. 9 is a circuit diagram illustrating an exemplary power converter of FIG. 1;

In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, details such as detailed configurations and structures are provided merely to assist in an overall understanding of embodiments of the present invention. Modifications of the embodiments described herein may be made by those skilled in the art without departing from the spirit and scope of the invention. Moreover, descriptions of well-known functions and structures are omitted for clarity and brevity. The terms used in the present specification are defined in consideration of the functions of the present invention and are not limited to specific functions. Definitions of terms may be determined based on the description in the detailed description.

Modules in the following figures or detailed description may be shown in the drawings or may be connected to others in addition to the components described in the detailed description. The connections between the modules or components may be direct or non-direct, respectively. The connections between the modules or components may be a communication connection or a physical connection, respectively.

1 is a block diagram illustrating an energy multiple input power management system in accordance with an embodiment of the present invention. Referring to Figure 1, a multiple input power management system 100 may include a plurality of power sources 101-10n, a multiple input power manager 110, a power converter 120, and a power store 130 have.

The plurality of power sources 101 to 10n may output the first to the n-th powers PWR1 to PWRn, respectively. For example, each of the plurality of power sources 101 to 10n can convert physical energy such as sunlight, vibration, rotational power, heat, etc. into electrical energy to output the first to n-th powers PWR1 to PWRn have. That is, each of the plurality of power sources 101 to 10n may be the same energy source or different energy sources. Illustratively, each of the plurality of power sources 101-10n may be a power generator such as a solar cell, a piezoelectric element, a solar cell, a small generator, and the like.

The multi-input power manager 110 receives the first to n-th powers PWR1 to PWRn from the first to Nth power sources 101 to 10n, And can provide the output power PWR_out to the power converter 120 by managing the n-th powers PWR1 to PWRn. For example, the multiple input power manager 110 may store each of the first through n-th powers PWR1 through PWRn in different energy reservoirs (e.g., capacitors), respectively, It is possible to output the electric powers PWR1 to PWRn as the output electric power PWR_out.

As a more detailed example, the multiple input power manager 110 stores each of the first through n-th powers PWR1 through PWRn in different energy reservoirs (e.g., capacitors), respectively, The first to n-th powers PWR1 to PWRn may be output as the output power PWR_out in the order that they reach the reference voltage. That is, the multiple input power manager 110 can provide the output power PWR_out without wasting the powers PWR1 to PWRn from the plurality of power sources 101 to 10n.

The power converter 120 may receive the output power PWR_out from the multiple input power manager 110 and convert the received output power PWR_out to output the converted power PWR_con. The power converter 120 may include at least one of a variety of power conversion devices such as a DC-to-DC converter, an AC-to-DC converter, a DC-to-AC converter,

The power store 130 may receive the converted power PWR_con and store the received converted power PWR_con. The power storage 130 may include a power storage medium such as a battery, a capacitor, and the like.

As described above, the multiple input power manager 110 according to the present invention outputs a plurality of input powers in a time-interleaved manner, so that power can be used without waste from each of the plurality of power sources.

FIG. 2 is a detailed view of the multiple input power manager of FIG. 1. FIG. 1 and 2, the multiple input power manager 110 includes first to nth maximum power followers MPPT1 to MPPTn, first to nth input capacitors CIN1 to CINn, Circuit < / RTI >

Each of the first to nth maximum power follow-up circuits MPPT1 to MPPTn receives the first to n-th powers PWR1 to PWRn from the first to nth power sources 101 to 10n, It is possible to control the voltages of the first to n < th > nodes N1 to Nn such that the received and received powers are respectively maximum. For example, the first to n-th maximum power follow-up circuits MPPT1 to MPPTn may be configured such that the voltages of the first to the n-th nodes N1 to Nn are the first to the n-th reference voltages VR1 to VRn, The first to n-th input capacitors CIN1 to CINn may store the first to Nth powers PWR1 to PWRn. Illustratively, each of the first to n-th reference voltages VR1 to VRn may indicate a voltage level at which each of the first to n-th powers PWR1 to PWRn can be supplied with the maximum power.

The power transfer circuit 111 receives the first to the n-th reference voltages VR1 to VRn from the first to the n-th maximum power follow-up circuits MPPT1 to MPPTn, The power stored in any one of the first to n-th input capacitors CIN1 to CINn is output as the output power PWR_out based on the voltages of the first to n-th nodes N1 to Nn, Can be output. Illustratively, the power transfer circuit 111 may successively output the powers stored in the first to n-th input capacitors CIN1 to CINn based on the time interleaving scheme.

FIG. 3 is a diagram showing the first maximum power follow-up circuit of FIG. 2. FIG. Illustratively, referring to Fig. 3, the first maximum power follow-up circuit MPPT1 is described, but the scope of the present invention is not limited thereto. The second to nth maximum power follow-up circuits MPPT2 to MPPTn may also have a structure similar to that of the first maximum power follow-up circuit MPPT1 shown in Fig.

2 and 3, the first maximum power follow-up circuit MPPT1 includes a first voltage ratio controller VRC1, a first comparator COMP1, a first control circuit CC1, and a first internal capacitor CS1 ).

The first voltage ratio controller VRC1 may generate a first reference voltage VR1 corresponding to the first power source 101. [ The first power PWR1 is maximally provided by a factor such as a type of the first power source 101 or an impedance between the first power source 101 and the first voltage ratio controller VRC The possible voltage levels can be changed. The first voltage ratio controller VRC may determine a first reference voltage VR1 at which the first power PWR1 may be maximally provided.

The first comparator COMP1 receives the first reference voltage VR1 from the first voltage ratio controller VRC1 and the first reference voltage VR1 and the voltage VS1 of the first internal capacitor CS1 Can be compared. The first comparator COMP1 may provide the comparison result to the first control circuit CC1.

The first control circuit (CC1) can control the first internal switch (SSW1) in response to the comparison result from the first comparator (COMP1). For example, when the voltage of the first internal capacitor SC1 is higher than the first reference voltage VR1, the first control circuit CC1 turns off the first internal switch SSW1, When the voltage of the first switch SC1 is lower than the first reference voltage VR1, the first control circuit CC1 can turn on the first internal switch SSW1. The voltage of the first node N1 (that is, the charging voltage of the first input capacitor CIN1) can be raised to the first reference voltage VR1 by the switching control operation of the first control circuit CC1.

As described above, the first maximum power follow-up circuit MPPT1 can adjust the charge voltage of the first input capacitor CIN1 so that the input first power PWR1 can be supplied as maximum power. Illustratively, the first maximum power follow-up circuit MPPT1 described with reference to FIG. 3 is exemplary and the first maximum power follow-up circuit MPPT1 may be implemented based on various well known algorithms.

FIG. 4 is a detailed circuit diagram of the power transmission circuit of FIG. 2. FIG. 2 and 4, the power transfer circuit 111 includes a transfer switch control circuit TSCC and first to Nth transfer switches TSW1 to TSWn.

Each of the first to Nth transfer switches TSW1 to TSWn is connected to the first to Nth nodes N1 to Nn. Each of the first to Nth transfer switches TSW1 to TSWn may operate under the control of the switch control circuit TSCC.

The transfer switch control circuit TCSS receives the first to Nth reference voltages VR1 to VRn from the first to Nth maximum power follow-up circuits MPPT1 to MPPTn, The first to Nth transfer switches TSW1 to TSWn are controlled based on the comparison result by comparing the voltages of the first to Nth nodes N1 to Nn and the voltages VR1 to VRn of the first to Nth nodes N1 to Nn, 1 to nth switching signals SS1 to SSn.

For example, the voltage of the first node N1 may first reach the first reference voltage VR1. In this case, the switch control circuit TSCC can turn on the first transfer switch TSW1 so that the power stored in the first input capacitor CIN1 is output as the output power PWR_out.

Illustratively, while the first transfer switch TSW1 remains in the turn-on state, the other transfer switches (e.g., second through n th transfer switches TSW2 through TSWn) .

Illustratively, the transfer switch control circuit TSCC turns on the first transfer switch TSW1 when the power of the first node N1 has dropped to a certain level (for example, to a predetermined minimum level) Off. Then, the transfer switch control circuit TSCC can turn on the transfer switch corresponding to the node that has reached the corresponding reference voltage.

As a more detailed example, each of the first to n-th maximum power follow-up circuits MPPT1 to MPPTn includes first to n-th nodes N1 to Nn so that the first to n-th powers PWR1 to PWRn are maximized, ≪ / RTI > At this time, depending on the type or characteristics of the power source and the capacitances of the first to n-th input capacitors CIN1 to CINn, the voltage of each of the first to the n-th nodes N1 to Nn reaches the time Can be different.

The transfer switch control circuit TSCC firstly sets the reference voltage VR1 to VRn based on the comparison results of the voltages of the first to Nth nodes N1 to Nn and the first to Nth reference voltages VR1 to VRn, The first to n-th switching signals SS1 to SSn may be controlled so that the power of the input capacitor connected to the reached node can be output to the power converter 120. [

At this time, if one switch is turned on, the remaining switches will remain in the turn-off state. For example, the voltage of the first node N1 may first reach the target voltage (i.e., the first reference voltage VR1). In this case, the transfer switch control circuit TSCC can output the first switching signal SS1 at a logic high level. The first transfer switch TSW1 is turned on and the power stored in the first capacitor C1 is supplied to the power converter 120 via the first transfer switch SW1 in response to the logic high first switching signal SS1, ). ≪ / RTI > At this time, the voltage of the second node N2 may reach the second reference voltage VR2 while the first transfer switch TSW1 is in the turn-on state. In this case, since the first transfer switch TSW1 is in the turn-on state, the second transfer switch TSW2 will remain in the turn-off state. Thereafter, after the first transfer switch TSW1 is turned off, the second transfer switch TSW2 may be turned on.

Illustratively, when the voltage of the first node N1 drops below the minimum voltage, or when a predetermined time has elapsed since the first transfer switch TSW1 was turned on, The first transfer switch TSW1 may be turned off when any one of the nodes has reached the corresponding reference voltage.

Illustratively, the amount of power provided through any one switch while the one of the switches is turned on may be greater than the amount of power charged into the corresponding capacitor. That is, the speed at which power is supplied to the power converter 120 may be faster than the speed at which the corresponding capacitor is charged.

As described above, the multiple input power manager 110 according to the embodiment of the present invention receives and stores each of a plurality of powers through a separate maximum power follower circuit, and the voltage level of the stored power is set to a corresponding reference voltage To the power converter 120 based on the arriving order. Thus, in a multiple input power system, using a single power converter, multiple powers can be used without waste of multiple powers. Thus, a power system with improved efficiency is provided.

5 is an exemplary illustration of the transfer switch control circuit of FIG. The transfer switch control circuit TSCC includes first to Nth comparators CP1 to CPn and a time-interleave controller TIC. Each of the first to Nth comparators CP1 to CPn receives the voltages of the first to Nth reference voltages VR1 to VRn and the first to Nth nodes N1 to Nn, And the comparison result can be outputted.

The time-interleave controller TIC receives the comparison result from each of the first to Nth comparators CP1 to CPn and outputs the first to Nth switch signals SS1 to SSn based on the received comparison result. can do. Illustratively, the time-interleave controller TIC may output the first to Nth switch signals SS1 to SSn according to the embodiment of the present invention described above.

Illustratively, the first to Nth comparators CP1 to CPn may have a hysteresis characteristic. For example, the first comparator CP1 may output a signal of logic high when the voltage of the first node N1 is higher than the first reference voltage VR1. The first comparator CP1 outputs a logic low signal when the voltage of the first node N1 becomes the first minimum voltage lower than the first reference voltage VR1 after outputting the signal of logic high . That is, the first comparators CP1 to CPn may have a hysteresis characteristic. The second to Nth comparators CP2 to CPn may also have characteristics similar to the first comparator CP1.

As described above, the multiple input power manager 110 according to the embodiment of the present invention receives and stores each of a plurality of powers through a separate maximum power follower circuit, and the voltage level of the stored power is set to a corresponding reference voltage To the power converter 120 based on the arriving order. Thus, in a multiple input power system, using a single power converter, multiple powers can be used without waste of multiple powers. Thus, a power system with improved efficiency is provided.

6 is an exemplary graph illustrating the operation of the multiple input power manager of FIG. Illustratively, for the sake of brevity of the drawing, each graph is depicted. That is, the graph shown in FIG. 6 is schematic, and the actual voltage or waveform of the signal may be different from that shown in FIG.

The X-axes of the graphs shown in FIG. 6 indicate time, the Y-axes respectively indicate the voltage of the first node N1, the voltage of the second node N2, the voltage of the third node N3, And indicates the level of the switching signals SS1, SS2, and SS3.

Referring to FIGS. 2 to 6, the first to third maximum power follow-up circuits MPPT1 to MPPT3 are connected to the first to third nodes N1 to N3 so that the first to third powers PWR1 to PWR3 are maximized. To N3 can be controlled. For example, as shown in FIG. 3, the first maximum power follow-up circuit MPPT1 receives the first power PWR1 so that the voltage of the first node N1 becomes the first reference voltage VR1 The first input capacitor CIN1 can be charged. Similarly, the second and third maximum power follow-up circuits MPPT2 and MPPT3 receive the second and third powers PWR2 and PWR3, respectively, and the voltages of the second and third nodes N2 and N3 The second and third input capacitors CIN2 and CIN3 to be the second and third reference voltages VR2 and VR2. Illustratively, as described above, the first to third reference voltages VR1 to VR3 may be different values depending on the type or characteristic of the power source.

At the first time point t1, the voltage of the first node N1 may reach the first reference voltage VR1. In this case, as described above, the transfer switch control circuit (TSCC) controls the first switching capacitor (TSCC) so that power can be supplied to the power converter (120) from the first input capacitor The signal SS1 can be activated. In response to the activated first switching signal SS1, the first transfer switch TSW1 is turned on and the power of the first input capacitor C1 is turned on via the first transfer switch TSW1 turned on, (Not shown).

Illustratively, while the first transfer switch TSW1 is in the turn-on state, the first transfer switch TSW1 is connected to the first input capacitor CIN1 by the first maximum power follower circuit MPPT1, The amount of power supplied to the power converter 120 may be greater. That is, as shown in FIG. 6, while the first transfer switch TSW1 is in the turn-on state, the voltage of the first node N1 may be lowered.

At the second time point t2, the voltage of the first node N1 may be lowered to the first minimum voltage VM1. In this case, the transfer switch control circuit TSCC deactivates the first switching signal SS1, and in response to the deactivated first switching signal SS1, the first transfer switch TSW1 is turned off. Illustratively, the first minimum voltage VM1 may be a predetermined voltage by the first maximum power follow-up circuit MPPT1.

Illustratively, the transfer switch control circuit TSCC controls the first to n th switching signals SS1 to SSn so that the first to nth transfer switches TSW1 to TSWn do not overlap each other and turn on . For example, as shown in FIG. 6, the voltage of the third node N3 may reach the third reference voltage VR3 during the time from the first time point t1 to the second time point t2 . Since the first transfer switch TSW1 is in the turned-on state during the period from the first time point t1 to the second time point t2, the transfer switch control circuit TSCC controls the third transfer switch TSW3 to turn- The third switching signal SS3 may not be activated.

At the second time point t2 the transfer switch control circuit TSCC activates the third switching signal SS3 so that the third transfer switch TSW3 is turned on since the first switching signal SS1 has been turned off, can do. The third switching signal SS3 may be activated from the second time point t2 to the third time point t3. The voltage at the third node N3 is lowered to the third minimum voltage VM3 and the transfer switch control circuit TSCC is responsive to the third switching voltage V3 at the third point of time t3, The signal SS3 can be deactivated. Illustratively, the third minimum voltage VM3 may be a predetermined voltage by the third maximum power follow-up circuit MPPT3.

Subsequent operations operate similar to those described above. For example, the first node N1 may reach the first reference voltage VR1 for a time from the second time point t2 to the third time point t3. Since the third switching signal SS3 is active in this period, the third switching signal SS3 is deactivated and the first switching signal SS1 is activated at the third time point t3.

The first switching signal SS1 maintains the active state from the third time point t3 to the fourth time point t4. In this section, the voltage of the second node N2 can reach the second reference voltage VR2, and the voltage of the third node N3 can reach the third reference voltage VR3. At a fourth point in time t4, the control logic circuit 112 deactivates the first switching signal SS1 and supplies the switching signal SS1 corresponding to the node (i.e., the second node N2) (I.e., the second switching signal SS2).

The second switching signal SS2 is activated for the time from the fourth time point t4 to the fifth time point t5 and the second switching signal SS2 is activated for the time period from the fifth time point t5 to the sixth time point t6 The third switching signal SS3 is activated during the period from the seventh time t7 to the seventh time t7 and the first switching signal SS1 is activated during the time from the sixth time t6 to the seventh time t7, The second switching signal SS2 is activated for a time period up to the time point t8.

As described above, the multiple input power manager 110 according to the present invention receives a plurality of powers from a plurality of power sources through a plurality of maximum power follow-up circuits, and the voltage of the capacitor storing each power is supplied to the reference voltage Based on the order of arrival, the output power can be output. Thus, multiple powers can be used without wasting power, thus providing a multiple input power system with improved efficiency.

FIG. 7 is a graph for explaining another embodiment of the multiple input power manager of FIG. 2. FIG. For the sake of brevity, a detailed description of the components described above is omitted. The embodiment shown in Fig. 7 differs from the embodiment shown in Fig. 6 in that the switch is turned on for a predetermined time.

For example, referring to FIG. 2 to FIG. 7, at the eleventh time point t11, the voltage of the first node N1 may reach the first reference voltage VR1. In this case, the transfer switch control circuit TSCC activates the first switching signal SS1. At this time, unlike the embodiment of FIG. 6, the embodiment of FIG. 7 activates the first switching signal SS1 for a predetermined time. That is, in the embodiment of FIG. 6, when the node voltage reaches the minimum voltage, the activated switching signal is deactivated, while in the embodiment of FIG. 7, the switching signal is activated for a predetermined time.

The voltage of the third node N3 may reach the third reference voltage VR3 between the eleventh time point t11 and the twelfth time point t12. Similarly to the above description, at the twelfth time point t12, the first switching signal SS1 is inactivated and the third switching signal SS3 is activated. Likewise, the third switching signal SS3 is activated for the time from the twelfth viewpoint t12 to the thirteenth viewpoint t13 (i.e., a predetermined time).

Thereafter, the operation is performed similar to that described above. For example, the first switching signal SS1 is activated during the time from the 13th time point t13 to the 14th time point t14 (i.e., the predetermined time), and the first switching signal SS1 is activated from the 14th time point t14 to the 15th time point the third switching signal SS3 is activated during the time from the fifteenth time point t15 to the tenth time point t15 (i.e., the predetermined time) The switching signal SS2 is activated and the first switching signal SS1 is activated for the time from the 16th time point t16 to the 17th time point t17 (i.e., the predetermined time) The third switching signal SS3 is activated during the time from the 18th viewpoint t18 to the 18th viewpoint t18 (i.e., the predetermined time), and the time from the 18th viewpoint t18 to the 19th viewpoint t19 The first switching signal SS1 is activated during the period from the nineteenth time point t19 to the twentieth time point t20 (i.e., the predetermined time) 2 switching signal SS2 is activated.

4, the multiple input power manager 110 according to the present invention receives a plurality of powers from a plurality of power sources through a plurality of maximum power follower circuits, The output power can be output based on the order in which the voltage of the capacitor storing the voltage reaches the reference voltage. At this time, the multiple input power manager 110 can output one power as output power for a predetermined time. Thus, multiple powers can be used without wasting power, thus providing a multiple input power system with improved efficiency.

FIG. 8 is a graph for explaining another embodiment of the multiple input power manager of FIG. 2. FIG. For the sake of brevity, a detailed description of the components described above is omitted. The embodiment shown in Fig. 8 differs from the embodiments shown in Figs. 6 and 7 in that when any one of a plurality of nodes reaches a corresponding reference voltage, the switching signal corresponding to any one of the nodes .

For example, referring to FIGS. 2 to 8, at the 31st time point t31, the voltage of the first node N1 may reach the first reference voltage VR1. In this case, the transfer switch control circuit TSCC activates the first switching signal SS1. Thereafter, at the 32nd time point t32, the voltage of the third node N3 may reach the third reference voltage VR3. In this case, the transfer switch control circuit TSCC deactivates the first switching signal SS1, regardless of the predetermined time or the minimum voltage, unlike that described with reference to Figs. 6 and 7, and the third switching signal SS3). At the thirty-third time point t33, the voltage of the first node N1 reaches the first reference voltage VR1, and accordingly, the control logic circuit 112 deactivates the third switching signal SS3, Thereby activating the switching signal SS1. After this, the operation proceeds similarly.

For example, at the 34th time point t34, the voltage of the third node N3 reaches the third reference voltage VR3, so that the transfer switch control circuit TSCC outputs the first switching signal SS1 And activates the third switching signal SS3. At the 35th time point t35 the voltage of the first node N1 reaches the first reference voltage VR1 and accordingly the transfer switch control circuit TSCC deactivates the third switching signal SS3, 1 switching signal SS1. At the tenth time t36, the voltage of the second node N2 reaches the second reference voltage VR2, so that the transfer switch control circuit TSCC deactivates the switching signal SS1, Thereby activating the switching signal SS2. At the 37th time point t37, the voltage of the third node N3 reaches the third reference voltage VR3, so that the transfer switch control circuit TSCC deactivates the second switching signal SS2, 3 Activates the switching signal (SS3). At time t38, the voltage of the first node N1 reaches the first reference voltage VR1, so that the transfer switch control circuit TSCC deactivates the third switching signal SS3, 1 switching signal SS1.

As described above, according to the embodiment of FIG. 5, the multiple input power manager 110 according to the present invention receives a plurality of powers from a plurality of power sources through a plurality of maximum power follower circuits, The output voltage can be output based on the order in which the voltage of the capacitor reaching the reference voltage. Thus, multiple powers can be used without wasting power, thus providing a multiple input power system with improved efficiency.

Illustratively, the embodiments described with reference to Figs. 6 to 8 are illustrative for clearly explaining the technical idea of the present invention, and the technical idea of the present invention is not limited thereto. The graphs shown in FIGS. 3 to 5 are graphical graphs. Depending on the actual power source, the power environment, and the system configuration, the slope, shape, and waveform of the graph may be variously modified.

FIG. 9 is a circuit diagram illustrating an exemplary power converter of FIG. 1; Referring to FIGS. 1 and 9, the power converter 120 may include an inductor L, a first transistor TR1, a second transistor TR2, and a control circuit 121.

One end of the inductor L1 receives the output power PWR_out from the multiple input power manager 110 and the other end is connected to the second node N2. One end of the first transistor TR1 is connected to the second node N2, the other end is connected to the ground terminal, and the gate electrode receives a control signal from the control circuit 121. [ One end of the second transistor TR2 is connected to the second node N2 and the other end is connected to the power storage 130. The gate terminal receives a control signal from the control circuit 121. [

The power converter 120 may perform the same operation as the buck-converter. For example, the control circuit 121 may turn on the first transistor TR1. At this time, the second transistor TR2 is in a turn-off state. When the first transistor TR1 is turned on, the output power PWR_out from the multiple input power manager 110 can be accumulated in the inductor L. [ After a predetermined time has elapsed, the control circuit 121 may turn off the first transistor TR1 and turn on the second transistor TR2. At this time, the power stored in the inductor L is supplied to the power storage 130 as the converted power PWR_con through the second transistor TR2.

Illustratively, a diode D may be coupled between the second node N2 and the power storage 130 instead of the second transistor TR2. That is, when the first transistor TR1 is turned off, the voltage stored in the inductor L increases the voltage of the second node N2. As a result, the diode D is turned on. At this time, the power stored in the inductor L may be supplied to the power storage 130 via the diode D.

Illustratively, the control circuit 121 may be included in the control logic circuit 112 shown in FIG.

Illustratively, the power converter 120 shown in FIG. 6 is exemplary and the scope of the invention is not so limited. For example, the power converter 120 shown in FIG. 6 has a buck-converter structure, but the scope of the present invention is not limited thereto, and the power converter 120 according to the present invention A buck converter, a boost converter, a buck-boost converter, a DC chopper, and the like.

Although the multiple input power manager 110 and the power converter 120 are illustrated as separate blocks, the scope of the present invention is not limited thereto, and the multiple input power manager 110 and the power converter 120 One device, one module, or one package.

Illustratively, the first control circuit CC1 of FIG. 3 (or the control circuits included in other maximum power follower circuits), the transfer switch control circuit (TSCC) of FIG. 4, or the time-interleave controller TIC) may be implemented as one control logic circuit or one control logic module.

As described above, according to the embodiment of the present invention, by using the time interleaving scheme to provide power from a plurality of power sources to the power storage, power can be efficiently used from a plurality of power sources without waste of power . Further, according to the embodiment of the present invention, since only one converter is used, miniaturization of the power harvesting system is possible.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the claims.

100: Multiple input power management system
101 to 10n: first to Nth power sources
110: Multiple input power manager
MPPT1 to MPPTn: First to n < th > maximum power followers
COMP1 to COMPn: The first to n < th >
TSW1 to TSWn: First to nth transfer switches
TSCC: Transfer switch control circuit

Claims (15)

(N is a natural number greater than 1) powers from the outside, and applying voltages of the first to the n-th nodes based on the first to the n-th powers to first to n-th First to n < th > maximum power follow-up circuits for controlling with voltages;
N-th input capacitors connected to the first to the n-th nodes, respectively, and the first to the n-th maximum power follow-up circuits, respectively, field;
N) input capacitors connected to the first to the n-th nodes and outputting, as output power, the power stored in each of the first to the n-th input capacitors in response to the first to the n-th transfer switching signals, N th transfer switches; And
The first to the n-th reference voltages, and the first to the n-th nodes, and generates the first to the n-th switching signals according to the comparison result, And a transfer switch control circuit for activating the first transfer switching signal so that when the first reference voltage is reached, the first switch connected to the first node is turned on. The method according to claim 1,
Wherein the transfer switch control circuit deactivates the second to the n-th switching signals so that the second to the n-th transfer switches are turned off when the first switching signal is activated. The method according to claim 1,
When the voltage of the first node connected to the turned-on first transfer switch reaches a first minimum voltage, the transfer switch control circuit deactivates the first switching signal so that the first transfer switch is turned off Multiple Input Power Management. The method of claim 3,
After the first transfer switch is turned off, the transfer switch control circuit controls the transfer switch so that the transfer switch connected to the node having the voltage which has reached the corresponding one of the second to the n-th nodes is turned on, 1 to n < th > switching signals. The method according to claim 1,
The first maximum power follow-up circuit
A first voltage ratio controller receiving the first power and determining the first reference voltage based on the received first power;
A first internal capacitor configured to charge the first power under the control of the first voltage ratio controller;
A first internal switch coupled between the first internal capacitor and the first node;
A first comparator configured to compare the first reference voltage and the voltage of the first internal capacitor; And
And a first control circuit configured to control the first internal switch based on a comparison result of the first comparator. The method according to claim 1,
Wherein each of the first to n < th > reference voltages is different. The method according to claim 1,
Wherein at least two of said first through n-th powers are powers provided from the same power source, and at least two of said first through n-th reference voltages are identical to each other. The method according to claim 1,
Wherein the transfer switch control circuit activates the first switching signal and deactivates the first switching signal after a predetermined time elapses. The method according to claim 1,
Wherein the transfer switch control circuit activates the first switching signal and deactivates the first switching signal when any one of the second to the nth nodes reaches a corresponding reference voltage. 10. The method of claim 9,
Wherein the transfer switch control circuit generates the first to the n-th switching signals such that after the first switching signal is deactivated, the transfer switch connected to any one of the nodes is turned on. The method according to claim 1,
Wherein each of the first to n < th > reference voltages indicates a voltage at which each of the first to n < th > A first maximum power follower circuit receiving the first power and following the maximum power of the first power;
A first input capacitor for storing the first power according to the control of the first maximum power follow-up circuit;
A first transfer switch operating in response to a first switching signal, the first transfer switch coupled between the first input capacitor and the output node;
A second maximum power follower circuit for receiving the second power and following the maximum power of the second power;
A second input capacitor for storing the second power according to the control of the second maximum power follow-up circuit;
A second transfer switch operating in response to a second switching signal and coupled between the second input capacitor and the output node; And
A comparison result of a first reference voltage from the first maximum power follow-up circuit and a voltage of the first input capacitor and a comparison result of a second reference voltage and a voltage of the second input capacitor from the second maximum power follow- And a transfer switch control circuit for generating the first and second switching signals based on the first and second switching signals,
The transfer switch control circuit controls the first and second input capacitors so that when any one of the voltages of the first and second input capacitors reaches a corresponding reference voltage, the transfer switch connected to any one of the input capacitors is turned- 2 multi-input power manager activating a switching signal. 13. The method of claim 12,
Wherein the first and second reference voltages are different. 13. The method of claim 12,
Wherein the first maximum power follow-
A first voltage ratio controller receiving the first power and determining the first reference voltage at which the received first power is at maximum power;
A first internal capacitor charging the power from the first voltage ratio controller;
A first switch coupled between the first internal capacitor and the first input capacitor;
A first comparator for comparing the first reference voltage and the voltage of the first internal capacitor; And
And a first control circuit for controlling the first switch based on a result of the first comparator. 15. The method of claim 14,
Wherein the second maximum power follow-
A second voltage ratio controller receiving the second power and determining the second reference voltage at which the received second power is at maximum power;
A second internal capacitor charging electric power from the second voltage ratio controller;
A second switch coupled between the second internal capacitor and the second input capacitor;
A second comparator for comparing the voltage of the second reference capacitor and the voltage of the second internal capacitor; And
And a second control circuit for controlling the second switch based on a result of the second comparator.

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