KR20170055582A - Direct transfer printing method and transfer medium used for the method - Google Patents

Abstract

According to one aspect of the present invention, provided is a method of manufacturing a semiconductor device by transferring an electrode layer patterned on a transfer substrate directly onto a receiver substrate through a printing process. The method comprises: a step of preparing a flexible transfer substrate; a step of forming a metal oxide layer on the transfer substrate; a step of forming an electrode pattern having micrometer-sized gaps on the metal oxide layer using a patterning process including a photolithography process; a step of aligning the silicon nanowires between the electrodes of the electrode pattern; a step of forming a layer of adhesive material on a rigid or flexible receiver substrate provided with a semiconductor element; and a step of separating the electrode pattern of the transfer substrate and the silicon nanowires from the transfer substrate, and transferring the electrode pattern and the silicon nanowires to the adhesive material of the receiver substrate by contacting the transfer substrate on which the silicon nanowires are arranged with the receiver substrate and applying a predetermined pressure.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a direct transfer printing method and a transfer medium used in the method. ≪ RTI ID = 0.0 >

The present invention relates to direct transfer printing, and more particularly, to a method of manufacturing a device by direct transfer printing using a photolithography process and a transfer medium used in the method.

A flexible device manufacturing method is known (for example, Publication No. 10-2011-72033).

BACKGROUND OF THE INVENTION Over the past several decades, many nanostructures, including nanoparticles, nanowires, nanotubes, and nanosheets, have been found to be effective in the field of field effect transistors (FETs), photosensors, solar cells, biosensors, Have been studied as building blocks for the same nanoelectronic devices.

In particular, nanomaterials are attracted to the most attractive for use in plastic electronic devices due to their suitability for printing on plastic substrates and their mechanical flexibility, and enable large-area fabrication at low cost. As such research, development of micro / nano fabrication and transfer printing techniques of nanomaterials is proceeding.

Polydimethylsiloxane (PDMS) is commonly used as a stamp to transfer nanomaterials to printed electronic device applications in order to transfer the nanomaterials to a plastic substrate, since the PDMS is soft and resilient and conformal contact ) To enable accurate transfer at the desired location. Currently, photolithography and PDMS mediation transfer techniques are widely used to manufacture devices based on nanomaterials. However, during the transfer process, photolithography can not be used on PDMS because the photoresist, developer and stripper are solutions containing organic solvents, which causes the PDMS to swell. Therefore, forming a pattern having features with sub-micron dimensions on the PDMS through photolithography remains a challenge.

Disclosure of Invention Technical Problem [8] In order to solve the problems of the prior art, the present invention provides a method of manufacturing a semiconductor device using direct transfer, And a method of manufacturing a semiconductor device by direct transfer printing using the transfer medium.

According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device by transferring a patterned electrode layer on a transfer substrate directly onto a receiver substrate through a printing process. The method includes: preparing a flexible transfer substrate; Forming a metal oxide layer on the transfer substrate; Forming an electrode pattern having micrometer-sized gaps on the metal oxide layer using a patterning process including a photolithography process; Aligning the silicon nanowires between the electrodes of the electrode pattern; Forming a layer of tacky material on a rigid or flexible receiver substrate provided with a semiconductor element; Separating the electrode pattern of the transfer substrate and the silicon nanowires from the transfer substrate by transferring the electrode pattern of the transfer substrate to the adhesive material of the receiver substrate by applying a predetermined pressure while bringing the transfer substrate with the silicon nanowires aligned into contact with the receiver substrate, .

In one embodiment, the flexible transfer substrate is held on a rigid substrate, and in the transfer step, the transfer substrate can be brought into contact with the receiver substrate while being separated from the rigid substrate.

In one embodiment, a PI or PET substrate can be used as the flexible transfer substrate.

In one embodiment, Au may be used as the electrode, and Al ₂ O ₃ , Nb ₂ O _5, or ZnO may be used as the metal oxide layer.

In one embodiment, in the step of forming the electrode pattern, the electrode interval of the electrode pattern may be 2 占 퐉 or less.

In one embodiment, the silicon nanowires may be aligned between the electrodes through an electrophoretic (DEP) process.

In one embodiment, the electrode pattern includes a source electrode and a drain electrode, and the semiconductor element may include a gate electrode and a gate dielectric.

In one embodiment, PVP may be used as the adhesive material of the receiver substrate.

In one embodiment, PVP may be spin coated on the receiver substrate followed by baking.

According to another aspect of the present invention, there is provided a method of manufacturing a transfer substrate for transferring an electrode pattern onto a receiver substrate through a direct printing process, the method comprising: preparing a flexible transfer substrate; Forming a metal oxide layer on the transfer substrate; Forming an electrode pattern having micrometer-sized gaps on the metal oxide layer using a patterning process including a photolithography process; And aligning the silicon nanowires between the electrodes of the electrode pattern.

According to another aspect of the present invention, there is provided a transfer substrate for use in transferring an electrode pattern to a receiver substrate through a direct printing process, wherein the transfer substrate is a flexible substrate made of PET or PI, A metal oxide layer formed on the substrate; An Au electrode pattern formed on the metal oxide layer using a patterning process including a photolithography process so as to have an interval of 2 mu m or less; And silicon nanowires arranged between the electrodes of the electrode pattern.

In the transfer substrate, the transfer substrate may be configured to be held on a hard substrate and to be detached from the hard substrate at the time of transfer to the receiver substrate.

In the transfer substrate, an Al ₂ O ₃ layer may be used as the metal oxide layer.

According to the present invention, a metal oxide layer (most preferably, an Al ₂ O ₃ layer) is used in place of PDMS in a transfer substrate including a transfer medium. This metal oxide layer can withstand the organic solvent in the photolithography process. Therefore, when PDMS is used, it is possible to realize an electrode gap that is not realized, that is, an electrode gap of 2 μm or less, It can be transferred to a semiconductor element substrate such as a FET.

1 is a diagram showing a manufacturing process of a Si nanowire FET using a direct printing method. As shown in _{Fig, Al 2 O 3, Nb 2} O 5, ZnO, NiOx, also water and de-Io on the metal oxide layer of WO ₃ The contact angle of methane and the surface energy of each layer calculated by the Owen-wendt model are also shown. 1C is an OM image of an Au electrode transferred from the PDMS and Al ₂ O ₃ , Nb ₂ O ₅ , ZnO, NiOx, and WO ₃ layers to the PVP adhesive layer.
FIG. 2 is AFM images (a to f) of PDMS and Al ₂ O ₃ , Nb ₂ O ₅ , ZnO, NiOx and WO ₃ on the PI substrate and FIG. 2g shows RMS defects of PDMS and five metal oxides Show.
3 (a) is a SEM sectional view of the Si nanowire etched for 2.5 hours, and the inserting drawing is an enlarged view of the circle portion. b is an OM image of the Si nanowire and Au electrode transferred to the PVP adhesive layer, and the insertion drawing shows Si nanowires aligned on the Au electrode before transfer. c is a SEM cross-sectional view of the Si nanowire and the Au electrode partly embedded in the PVP, and d and e are graphs showing the transfer characteristics and the output characteristics of the Si nanowire FET. and f is a graph showing changes in mobility and threshold voltage as a function of channel length.
4a shows a statistical diameter distribution of synthesized Si nanowires for FET fabrication, b is a SEM image showing a rough surface of a cylindrical Si nanowire, and c shows monocrystalline properties in the < 100 > SEM image.
5 is an OM image of Si nanowires placed between Au electrodes on ZnO (a) and Nb ₂ O ₅ (b) by a DEP process.
6 is an OM image of an Au electrode formed on an Al ₂ O ₃ transfer medium by photolithography with an electrode gap distance of 1.767 μm (a), 2.604 μm (b), and 3.442 μm (c).
7 (a) is a photograph of a Si nanowire FET on a bending tester, b to d indicate the bending radius (b), the number of bending cycles in the vertical direction with a strain of 0.57% (c) Lt; RTI ID = 0.0 &gt; FET &lt; / RTI &gt;
8A and 8B show changes in IV (a) and capacitance (b) as a function of the number of bending cycles, and c shows the transfer characteristics of the Si nanowire FET as a function of the bending cycle in the parallel direction Fig.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, a description of a technical process well known in the art, for example, a specific process for manufacturing an FET and its structure and operation, a dielectrophoretic (DEP) alignment process and the like will be omitted. Even if these explanations are omitted, those skilled in the art will readily understand the characteristic configuration of the present invention through the following description.

The present invention suggests a direct printing method for fabricating a device using a metal-oxide transfer layer instead of a conventional transfer medium such as polydimethylsiloxane (PDMS). The metal oxide is not damaged by the organic solvent. Therefore, an electrode having an interval of 2 mu m or less can be formed on the metal-oxide transfer layer through photolithography. In order to determine the metal oxide suitable for use as the transfer layer, the surface energies of the various metal oxides were measured and the Au layer deposited on these oxides was transferred onto poly (vinylphenol) (PVP). In order to verify the suitability of the method of the present invention, the Si nanowires aligned by an electrophoretic (DEP) alignment process and Au source-drain electrodes on the transfer layer were transferred onto a PVP coated flexible substrate. Based on the transfer experiment and the DEP process, it was confirmed that Al ₂ O ₃ is the optimal transfer layer. Finally, Si nanowire field effect transistors (FETs) were fabricated on rigid Si substrates and flexible polyimide films. As the channel length decreased from 3.442 ㎛ to 1.767 ㎛, the mobility of the FET on the Si substrate increased from 127.61 ± 37.64 cm ² / V · s to 181.60 ± 23.73 cm ² / V · s. In addition, the flexible Si nanowire FET manufactured by the method of the present invention showed improved electrical characteristics as the bending cycle was increased. Hereinafter, the characteristic configuration of the present invention will be described in more detail.

In the present invention, a metal-oxide transfer layer is proposed as a candidate for replacing PDMS in order to overcome the shortcomings of the PDMS described in the prior art. As is well known, metal-oxides are widely available and can be prepared in a variety of ways. In this invention, we present five different metal oxides _{(Al 2 O 3, Nb 2} O 5, ZnO, NiOx, WO 3). Although there are many kinds of metal oxides, the present inventors used the most common materials. However, the method of the present invention is also applicable to other oxides. Also, through the method of the present invention, the phase of the metal oxide can be easily controlled, which helps to control the morphology and surface energy. The most important parameter for the transfer medium is surface energy. Thus, if a metal oxide layer is applicable, the layer can be easily optimized as a transfer layer. The metal oxide is not damaged by the organic solvent, and allows a small interval of micropatterns to be formed on the transfer medium through photolithography.

FIG. 1A schematically illustrates a process for fabricating a Si nanowire FET using a direct printing method with a thin inorganic metal-oxide layer. In order to verify whether the metal oxide layer can be applied as a transfer medium for the Au electrode, surface characteristics of the metal oxide and the PDMS were compared and the surface characteristics were studied. Five different metal oxides _{(Al 2 O 3, Nb 2} O 5, ZnO, NiOx, WO 3) were laminated through a RF magnetron sputtering.

To evaluate the surface energy, contact angles of water and diiodomethane were measured for metal oxide and PDMS. The contact angle depends not only on the surface energy of the material, but also on the surface roughness. If the surface is rough, the droplet for the contact angle measurement spreads across the surface and reduces the contact angle. In this case, the surface energy is greater than the actual value. The RMS roughness of the PDMS was 0.48 nm, and the RMS roughness of the metal oxide was 0.2-0.4 nm (FIG. 2). This shows that all metal oxides have a sufficiently smooth surface, minimizing the effect of surface roughness on surface energy. The contact angles of water and diiodomethane were 110.71 ± 4.10 °, 69.14 ± 2.52 °, 64.41 ± 2.60 °, and 35.2 ± 1.92 ° for PDMS, Al ₂ O ₃ , Nb ₂ O ₅ , ZnO, NiOx and WO ₃ , 68.48 占 0.88 占 28.39 占 0.81 占 and 69.03 占 1.99 占 32.23 占 1.35 占 113.83 占 1.02 占 35.77 占 0.72 占 38.80 占 3.19 占 23.2 占 1.79 占 (Fig. Based on these values, the surface energy was calculated using the following Owen-Wendt model (Figure 1c)

및

는 액체의 표면 에너지의 분산 항목 및 극성 항목이고,

및

는 금속 산화물 층의 표면 에너지의 분산 항목 및 극성 항목이다.

및

의 값은 물과 디이오도메탄에 대하여, 각각, 22.85 dynes/cm, 50.3 dynes/cm 및 48.5 dynes/cm, 2.3 dynes/cm 이다. PDMS는 24.62 dynes/cm의 가장 낮은 표면 에너지를 나타내었다. Al₂O₃, Nb₂O₅, ZnO의 표면 에너지는 45.63±0.72-47.00±0.45 dynes/cm이었고, WO₃는 61.68 dynes/cm의 가장 큰 표면 에너지를 나타내었다. 이는, 본 발명에서 사용된 금속 산화물 중에서, Al₂O₃, Nb₂O₅, ZnO가 전사층으로서 사용될 수 있음을 나타낸다. 45.63±0.72-47.00±0.45 dynes/cm의 표면 에너지를 갖는 Al₂O₃, Nb₂O₅, ZnO의 경우, Au 층이 폴리(비닐페놀)(PVP) 기판 위로 전사될 수 있는데(도 1c의 삽입 도면 참조), 이는 낮은 표면 에너지를 갖는 PDMS의 경우와 유사하고, Au와의 점착성(adhesion)이 낮다는 것을 보여준다. 다른 한편으로, 50 dynes/cm 이상의 표면 에너지를 갖는 NiOx, WO₃ 막의 경우, Au 전극을 PVP 층 위로 스탬프시킬 수 없는데, 이들 사이의 점착성이 강하기 때문이다(도 1c의 삽입 도면 참조).? _L is the surface energy of the droplet,? _S is the surface energy of the metal oxide layer,? Is the surface energy of the metal oxide layer,

And

Is the item of dispersion and polarity of the surface energy of the liquid,

And

Are the items of dispersion and polarity of the surface energy of the metal oxide layer.

And

Are 22.85 dynes / cm, 50.3 dynes / cm and 48.5 dynes / cm and 2.3 dynes / cm, respectively, for water and diiodomethane. PDMS showed the lowest surface energy of 24.62 dynes / cm. The surface energies of Al ₂ O ₃ , Nb ₂ O ₅ and ZnO were 45.63 ± 0.72-47.00 ± 0.45 dynes / cm and WO ₃ showed the largest surface energy of 61.68 dynes / cm. This indicates that among the metal oxides used in the present invention, Al ₂ O ₃ , Nb ₂ O ₅ and ZnO can be used as the transfer layer. In the case of Al ₂ O ₃ , Nb ₂ O ₅ , ZnO with surface energies of 45.63 ± 0.72-47.00 ± 0.45 dynes / cm, an Au layer can be transferred onto the poly (vinyl phenol) (PVP) substrate ), Which is similar to that of PDMS with low surface energy and shows a low adhesion to Au. On the other hand, in the case of a NiOx, WO ₃ film having a surface energy of 50 dynes / cm or more, the Au electrode can not be stamped onto the PVP layer because of the strong adhesion therebetween (see the inset of FIG.

Si nanowire FETs were fabricated on rigid Si and flexible polyimide (PI) substrates by direct printing process using metal oxide stamps as described above, and Al ₂ O ₃ , Nb ₂ O ₅ , and ZnO were transferred Media. First, a Si nanowire was synthesized from a boron-doped p-type Si wafer through a metal-assisted etching method. The average diameter and length of these nanowires were 130 nm and 100 탆, respectively (Figs. 3A and 4A). Due to the high aspect ratio of 780, the Si nanowires were warped like hair (Fig. 3A), indicating flexibility due to their nanoscale size, compared to hard Si films. The Si nanowire has a rough surface and is a single crystal growing along the <100> direction (FIGS. 4B and 4C). Through the electrophoretic (DEP) alignment process, Si nanowires were aligned on the patterned Au electrodes on the metal oxide layer using standard photolithography. Next, the Si nanowire and the Au electrode were transferred onto the PVP-coated substrate with the gate electrode (Au) and the gate insulating layer (Al ₂ O ₃ ). In terms of surface energy, ZnO and Nb ₂ O ₅ may be suitable as the transfer layer, but due to their semiconducting properties they are not suitable for the DEP alignment process (FIG. 5). A strong electric field must be generated between the electrodes to align the Si nanowires perpendicular to the Au electrodes using a DEP process that requires insulating material. Thus, Al ₂ O ₃ with a large bandgap (8.8 eV) and a large dielectric constant (9.0-10.1) can be the metal oxide material that is optimal for the present process (FIG. Si nanowires aligned between the Au electrodes on the surface of the Al ₂ O ₃ layer were pressed onto the target substrate provided with the PVP layer by pressing the Al ₂ O ₃ stamp at a predetermined pressure. Since the adhesion between Au and Al ₂ O ₃ was sufficiently weak, Au electrodes were also stamped with Si nanowires (FIG. 3 b) and the exposed areas of the Si nanowires were embedded in the PVP layer (FIG. 3 c).

These inorganic stamps enable the formation of source and drain electrodes with narrower spacing compared to PDMS stamps because inorganic stamps are not damaged by the organic solvent used in conventional photolithographic techniques. Within the limited range of applications utilized in the present invention, electrodes with spacing of 1,767 μm, 2.604 μm, and 3.442 μm could be patterned on the Al ₂ O ₃ layer (ie, micrometer size, preferably less than 2 μm , And a stamping was performed to fabricate a Si-nanowire FET having a back-gated configuration (FIG. 6). Figures 3d and 3e show the transfer (I _DS -V _G ) curves and output (I _DS -V _DS ) curves for FETs with a channel length of 1.767 μm. The value of I _DS increased with increasing negative V _G and saturated with increasing negative V _DS because of the typical p-type channel behavior and good ohmic contact between the Au electrode and the Si nanowire. . The on / off current ratio and the field effect mobility (μ _h ) were 1.2 × 10 ⁷ and 176.94 cm ² / Vs, respectively. As the channel length decreased from 3.442 μm to 1.767 μm, the mobility increased from 127.61 ± 37.64 cm ² / Vs to 181.60 ± 23.73 cm ² / Vs (FIG. 3F). This improved mobility increases the contact area between the Au electrode and the Si nanowire as the Si nanowires used in the present invention have the same length and as the electrode spacing decreases, This is because the contact resistance decreases. In addition, the Si nanowires synthesized through the metal assisted etching method have a rough surface, and the carrier is captured by surface defects. Thus, the reduction of the channel length reduces the charge collection site, thereby increasing the mobility. In addition, since the Si nanowires have similar conduction characteristics including surface charge, the threshold voltage remains unchanged regardless of the channel length.

To demonstrate the applicability of the method of the present invention to flexible electronic devices, Si nanowire FETs were fabricated on PI substrates (Figure 7a) through direct printing using an Al ₂ O ₃ layer as the transfer medium. Figures 7b and 7c show transfer curves of Si nanowire FETs as a function of bending strain (bending radius) and bending cycle. The transfer curves showed no large current fluctuations over the range of bending strain up to 0.85% and the mobility was estimated to be 192.46 ± 7.74 cm ² / Vs. When the bending strain exceeded 1.71%, the transfer curve deteriorated and the mobility decreased to 176.32 cm ² / Vs. In addition, the value and mobility of I _{DS in} the transfer curve gradually increased from 0.57% strain to a maximum of 8,000 bending cycles. After 10,000 bending cycles, the device was irreversibly damaged.

A typical flexible device degrades its electrical properties as the bending cycle increases. On the other hand, the flexible Si nanowire FET manufactured by the method of the present invention exhibited improved electrical properties as the bending cycle was increased. After performing 8,000 bending cycles with a 0.57% strain, the transfer current increased 266% compared to the pre-bend current at -30V gate voltage (Figure 7c). The Si nanowires bonded on the Au electrode through the DEP process are in physical contact with the Au electrode by van der Waals forces. The contact properties were improved during the bending test by friction between the Si nanowires and the surface of the Au electrode, thereby increasing the mobility. 8A shows that the current increases as the bending cycle increases. Nonlinear IV curves originate from the electron-transporting nature of porous Si nanowires. Another possible reason for the improved transfer current can be explained by the increased capacitance of the gate insulator depending on the number of bending cycles (Fig. 8B). After 8,000 bend cycles, the capacitance of the metal-insulator-metal (MIM) structure increased by 12.58%, as shown in Figure 8B. The PVP polymer chains are aligned at each bend, increasing the capacitance. The capacitance value was compensated, and the transistor mobility before the bend test was 188.09 ± 11.59 cm ² / Vs. This value increased to 345.54 ± 10.16 cm ² / Vs after 8,000 bending cycles (FIG. 7d). However, the present inventors have found that the stress caused by bending is concentrated at the interface between the Si nanowire and the PVP, and since the Si nanowire is buried in the PVP in the flexible device, the capacitance of the device is further increased compared to that of the MIM structure think. To demonstrate this hypothesis, the flexible elements were bent in a parallel direction. As a result, the transfer current increased by 195% as the bending cycle increased (FIG. 8C). This result implies that the increase in capacitance depends not only on the direction of bending but also on the alignment direction of the buried Si nanowires.

In summary, the present inventors studied the surface energy of a metal oxide layer used as a transfer layer for an Au electrode, and conducted a transfer experiment to determine the most suitable metal oxide layer. It was determined that Al ₂ O ₃ , Nb ₂ O ₅ , and ZnO having a surface energy of less than 50 dynes / cm were suitable materials. In particular, Al ₂ O ₃ , which has a large dielectric constant and helps form a strong electric field between the Au electrodes, has been selected as the transfer layer because the DEP process is applied to align the Si nanowires. To demonstrate the suitability of the method of the present invention, FETs comprising Si nanowires were fabricated on PVV coated substrates and flexible PI substrates via direct printing with Al ₂ O ₃ as the transfer layer. On a rigid Si substrate, the mobility of the FET was 1.767 at a channel length of 3.442 μm. ㎛, it increased linearly from 127.61 ± 37.64 cm ² / V · s to 181.60 ± 23.73 cm ² / V · s. This is because the number of carriers trapped on the rough surface of the Si nanowire decreases and the contact area between the Si nanowire and the Au electrode increases. In the case of a flexible Si nanowire FET, the electrical properties were maintained over a bending strain range of 0.85%, and the deterioration of the current started at a bending strain of 1.71% or more. Also, after 8,000 bend tests at 0.57% strain in the vertical direction, the transfer current of the flexible FET increased 266% at -30V gate voltage. The reason for this phenomenon is not only an increase in the capacitance of the gate insulator during the bending test but also an improvement in the contact characteristics between the Si nanowire and the Au electrode.

<Explanation of Experiment>

Flexible PI  Preparation of a metal oxide layer on a substrate

As a transfer medium for the direct printing, was used for five different metal oxides _{(Al 2 O 3, Nb 2} O 5, ZnO, NiOx, WO 3). The flexible PI substrate having a thickness of 15 mu m was cleaned by sonication in acetone, methanol and deionized water for 10 minutes, respectively, and then dried with nitrogen gas. All metal oxide films were laminated on the PI substrate by radio frequency (RF) magnetron sputtering at a working pressure of 10 mTorr and a radio frequency (RF) power of 150 W. [ The thickness of the laminated film was about 20 nm. For comparison, SYLGARD? 184 Silicone elastomer curing agent and SYLGARD? The silicone elastomer base was mixed in a volume ratio of 1:10 and baked at 75 占 폚 for 1 hour to prepare 5 mm thick PDMS as a conventional transfer medium. The contact angles of water and diimomethane on PDMS and Al ₂ O ₃ , Nb ₂ O ₅ , ZnO, NiOx and WO ₃ were measured using a contact angle analyzer (phoenix 300 plus SEO Co., Ltd.). The surface roughness of the metal oxide layer was measured using an atomic force microscope (AFM) (MFP-3D, Asylum research).

Using a metal oxide film Au  Direct transfer printing of electrode pattern

An electrode pattern having an interval of 1.767, 2.604 and 3.442 탆 was formed on the PDMS with a metal oxide film (Al ₂ O ₃ , Nb ₂ O ₅ , ZnO, NiOx, WO ₃ ) by photolithography and subsequent electron beam evaporation. As a receiver substrate, a 10% PVP solution with a crosslinking agent, namely poly (melamine-co-formaldehyde) in propylene glycol mono-methyl ether acetate, was added to the Si substrate for 5 seconds at 500 rpm and for 10 seconds at 1500 rpm. The substrate coated with the step spin-coated PVP was prepared, and then the substrate was lightly baked at 150 캜 for 10 minutes. The transfer medium having the Au electrode pattern was contacted with the PVP-coated substrate under a pressure of 26.7 g / cm &lt; 2 &gt;, and then heated to 170 DEG C at a temperature raising rate of 3.34 DEG C / min. Finally, the transfer medium was peeled off and the Au electrode pattern was left on the PVP-coated substrate.

Hard or by direct transfer printing Flexible On the substrate Si Nanowire  FET formation

A DEP process was used to align the Si nanowires between the Au electrodes on the Al ₂ O ₃ transfer medium. Si nanowires were prepared from the boron doped p-type Si (100) wafers having a resistivity of 1-10 OMEGA cm, as described above, by a metal assisted etching method. The synthesized Si nanowires were dispersed in a solution composed of dilute hydrazine (0.05%) and ethanol to yield 7 × 10 ⁸ NWs / mL. A 4-μL droplet was suspended on the Au electrode interval, and then a direct current bias (amplitude of 10 Vpp, frequency of 1 kHz and pulse width of 500 μs) was applied for 5 seconds to arrange a plurality of Si nanowires Respectively. For the fabrication of Si nanowire FETs, p-doped Si substrate with thermally grown 300 nm thick SiO ₂ layer and 10 μm thick PI substrate was used. The Ti / Au gate electrode was deposited on the PI substrate by electron beam evaporation and the Al ₂ O ₃ layer was deposited as the gate dielectric on the gate electrode. For direct transfer printing, the PVP layer was coated on the substrate by two-step spin coating under the same conditions as the receiver substrate. A Si nanowire and Au electrodes arranged on the surface of Al ₂ O ₃ layer, Al ₂ O ₃ stamped by a press into a 26.7 g / cm3 pressure was attached over the PVP-coated substrate, followed by 170 to 3.34 ℃ / min heating rate of Lt; 0 &gt; C. After the transfer medium was peeled off, the device was baked at 175 占 폚 for 1 hour. The morphology of Si nanowires and the structure of Si nanowires embedded in PVP were observed using a field emission scanning microscope (JSM-7001, Jeol). IV characteristics were measured using a probe station (Desert Cryogenics, model TTP4) and an Agilent semiconductor parameter analyzer (B1500A).

Although the present invention has been described with reference to the embodiment, the present invention is not limited to the above embodiment. That is, the embodiment can be variously modified and modified within the scope of the following claims, and these are also within the scope of the present invention.

For example, in the above embodiment, a PI substrate laminated on a glass substrate has been described as a transfer substrate including a transfer medium (metal oxide, most preferably Al ₂ O ₃ layer). Here, the glass substrate is a substrate for holding PI, and at the time of actual transfer, the PI substrate is removed from the glass substrate and transferred. That is, since the glass substrate is a rigid substrate, the force is not applied uniformly when the pressure is applied during the transfer, so the transfer process is carried out while being separated.

Further, the substrate is not limited to the PI substrate. That is, a substrate made of a material other than PI can be used as long as it is flexible. For example, a PET substrate may be used instead of PI.

In the above embodiment, PVP was spin-coated on the semiconductor element substrate. This PVP is also a little sticky by soft baking, and it also acts as a gate insulator. Instead of such PVP, any material having appropriate tackiness can be used.

In the above embodiment, Si and PI substrates are exemplified as the semiconductor element substrates, but any of the substrates that can be coated with the sticking material, for example, PVP can be used.

Claims (18)

A method of manufacturing a semiconductor device by transferring a patterned electrode layer on a transfer substrate directly to a receiver substrate through a printing process,
Preparing a flexible transfer substrate;
Forming a metal oxide layer on the transfer substrate;
Forming an electrode pattern having micrometer-sized gaps on the metal oxide layer using a patterning process including a photolithography process;
Aligning the silicon nanowires between the electrodes of the electrode pattern;
Forming a layer of tacky material on a rigid or flexible receiver substrate provided with a semiconductor element;
Separating the electrode pattern of the transfer substrate and the silicon nanowires from the transfer substrate by transferring the electrode pattern of the transfer substrate to the adhesive material of the receiver substrate by applying a predetermined pressure while bringing the transfer substrate with the silicon nanowires aligned into contact with the receiver substrate,
&Lt; / RTI &gt; The manufacturing method of a semiconductor device according to claim 1, wherein the flexible transfer substrate is held on a rigid substrate, and in the transfer step, the transfer substrate contacts the receiver substrate while being separated from the rigid substrate Way. The method of manufacturing a semiconductor device according to claim 1, wherein a PI or PET substrate is used as said flexible transfer substrate. The method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein Au is used as the electrode and Al ₂ O ₃ , Nb ₂ O _5, or ZnO is used as the metal oxide layer. 5. The method of manufacturing a semiconductor device according to claim 4, wherein, in the step of forming the electrode pattern, the electrode interval of the electrode pattern is 2 占 퐉 or less. 5. The method of claim 4, wherein the silicon nanowires are aligned between the electrodes through an electrophoretic (DEP) process. 5. The method of claim 4, wherein the electrode pattern comprises a source electrode and a drain electrode, wherein the semiconductor element comprises a gate electrode and a gate dielectric. The method of manufacturing a semiconductor device according to claim 7, wherein PVP is used as a sticking material of the receiver substrate. 9. The method according to claim 8, wherein baking treatment is performed after spin-coating PVP on the receiver substrate. A method for manufacturing a transfer substrate for transferring an electrode pattern onto a receiver substrate through a direct printing process,
Preparing a flexible transfer substrate;
Forming a metal oxide layer on the transfer substrate;
Forming an electrode pattern having micrometer-sized gaps on the metal oxide layer using a patterning process including a photolithography process;
Aligning the silicon nanowires between the electrodes of the electrode pattern;
And transferring the transfer substrate. 11. The method of claim 10, wherein the flexible transfer substrate is held on a rigid substrate. The transfer substrate manufacturing method according to claim 10, wherein a PI or PET substrate is used as the transfer substrate. The transfer substrate manufacturing method according to any one of claims 10 to 12, wherein Au is used as an electrode of the electrode pattern, and Al ₂ O ₃ , Nb ₂ O _5, or ZnO is used as the metal oxide layer . The method according to claim 13, wherein, in the step of forming the electrode pattern, the electrode interval of the electrode pattern is 2 占 퐉 or less. 15. The method of claim 14, wherein the silicon nanowires are aligned between the electrodes through an electrophoretic (DEP) process. A transfer substrate for use in transferring an electrode pattern onto a receiver substrate through a direct printing process,
The transfer substrate is a flexible substrate made of PET or PI,
A metal oxide layer formed on the transfer substrate;
An Au electrode pattern formed on the metal oxide layer using a patterning process including a photolithography process so as to have an interval of 2 mu m or less;
The silicon nanowires arranged between the electrodes of the electrode pattern
Wherein the transfer substrate comprises a first substrate and a second substrate. 17. The transfer substrate according to claim 16, wherein the transfer substrate is held on a rigid substrate and is configured to be detached from the rigid substrate at the time of transfer to the receiver substrate. The transfer substrate according to claim 16, wherein an Al ₂ O ₃ layer is used as the metal oxide layer.

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