KR102126526B1 - Organic semiconductor device using nano structure and method for comprising the same - Google Patents
Organic semiconductor device using nano structure and method for comprising the same Download PDFInfo
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- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/80—Constructional details
- H10K10/82—Electrodes
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- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
- H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
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Abstract
본 발명은 제 1전극, 유전층, 유기 반도체층 및 일면이 음각 및 양각의 패턴으로 형성된 제 2전극이 순차적으로 적층된 유기 반도체 소자 및 이의 제조방법에 관한 것이다.The present invention relates to an organic semiconductor device in which a first electrode, a dielectric layer, an organic semiconductor layer, and a second electrode formed on one surface in an intaglio and embossed pattern are sequentially stacked and a method for manufacturing the same.
Description
본 발명은 나노 구조를 이용한 유기 반도체 소자 및 이의 제조방법에 관한 것으로, 보다 자세하게는 제 1전극, 유전층, 유기 반도체층 및 음각 및 양각의 패턴이 형성된 제 2전극이 순차적으로 적층된 유기 반도체 소자 및 이의 제조방법에 관한 것이다.The present invention relates to an organic semiconductor device using a nanostructure and a method for manufacturing the same, more specifically, an organic semiconductor device in which a first electrode, a dielectric layer, an organic semiconductor layer, and a second electrode on which negative and embossed patterns are formed are sequentially stacked. It relates to a manufacturing method.
최근, 유연하고 구부릴 수 있으며 깨지지 않는 플렉서블(flexible) 평판 표시장치에 대한 관심이 고조되면서, 플렉서블 평판 표시장치에 적합한 스위칭 소자의 개발이 더욱 중요해지고 있다.2. Description of the Related Art Recently, as interest in flexible flat panel displays that are flexible, bendable, and unbreakable has increased, the development of switching elements suitable for flexible flat panel displays has become more important.
현재 액정 디스플레이(Liquid Crystal Display, LCD)에 주로 사용되는 비정질 실리콘(amorphous-Si) 박막 트랜지스터는 구성요소가 모두 무기물로 이루어져 있다. 특히, 채널로 작용하는 활성층이 무기물로 이루어져 있기 때문에 구부리거나 휘어지게 되면, 박막 트랜지스터에 기계적 응력(stress)이 발생한다. 이러한 기계적 응력으로 인하여 크랙(crack)이 발생하며, 그로 인해 반도체 소자가 정상적으로 작동하지 않는 치명적인 문제점이 있다.Currently, an amorphous silicon (amorphous-Si) thin film transistor mainly used in a liquid crystal display (LCD) is composed of all inorganic components. Particularly, when the active layer serving as a channel is made of an inorganic material and is bent or bent, mechanical stress occurs in the thin film transistor. Due to this mechanical stress, a crack occurs, and thus there is a fatal problem that the semiconductor device does not operate normally.
따라서, 종래의 실리콘 기반의 박막 트랜지스터 대신 유기 반도체(organic semiconductor, OSC)를 활용한 유기 박막 트랜지스터(Organic Thin Film Transistor, OTFT)가 근래 들어 많은 관심을 받고 있다.Accordingly, an organic thin film transistor (OTFT) using an organic semiconductor (OSC) instead of a conventional silicon-based thin film transistor has recently attracted much attention.
상기 박막 트랜지스터는 소스/드레인 영역과, 이 소스/드레인 영역의 사이에 형성된 채널 영역을 갖는 유기 반도체층을 가지며, 이 유기 반도체층과 절연되어 상기 채널 영역에 대응되는 영역에 위치하는 게이트 전극과, 상기 소스/드레인 영역에 각각 접촉되는 소스/드레인 전극을 갖는다.The thin film transistor has a source/drain region and an organic semiconductor layer having a channel region formed between the source/drain regions, a gate electrode positioned in a region corresponding to the channel region insulated from the organic semiconductor layer, And source/drain electrodes respectively contacting the source/drain regions.
상기 유기 박막 트랜지스터는 실리콘 박막 트랜지스터(Si-TFT)와 구조적으로 거의 동일한 형태로서, 채널이 형성되는 영역에 실리콘(Si) 대신 유기물질을 사용한다는 차이점이 있다. 유기 박막 트랜지스터는 제작 공정 면에서 실리콘 박막 트랜지스터에 비하여 간단하고 비용이 저렴하다는 장점이 있다. 또한, 유기 박막 트랜지스터는 대부분의 구성요소가 유기물로 이루어지기 때문에, 구부리거나 휘어져도 크랙이 발생하거나 깨질 가능성이 매우 작은 장점이 있다.The organic thin film transistor has a structure that is substantially the same as that of the silicon thin film transistor (Si-TFT), and has a difference that an organic material is used instead of silicon (Si) in a region in which a channel is formed. The organic thin film transistor has the advantage of being simple and inexpensive compared to the silicon thin film transistor in terms of manufacturing process. In addition, since most of the organic thin film transistors are made of organic materials, there is a very small possibility of cracking or breaking even when bent or bent.
또한, 일반적으로 상기 유기물질은 그 하부에 양극을 형성하고, 그 상부에 음극을 형성하여 외부의 인가된 전압에 의하여 구동이 가능한데, 상기 유기물질의 물리적 특성 즉, 표면의 형태, 결정도 및 표면 입자들의 조밀도(Packing density)에 의하여 유기 발광 표시 패널의 발광효율이 영향을 받는다. 특히, 유기박막 트랜지스터는 기존의 고체 실리콘 트랜지스터로써 실현할 수 없는 플렉서블 디스플레이, 스마트카드, RF 태그 등 응용분야의 핵심소자로 활용될 수 있기 때문에 활발한 연구가 수행되고 있다.In addition, in general, the organic material may be driven by an externally applied voltage by forming an anode on its lower part and a cathode on its upper part. Physical properties of the organic material, that is, surface shape, crystallinity and surface The luminous efficiency of the organic light emitting display panel is affected by the packing density of the particles. In particular, active research has been conducted because the organic thin film transistor can be used as a core device in applications such as a flexible display, a smart card, and an RF tag that cannot be realized as a conventional solid silicon transistor.
유기 나노와이어는 유연하고 저렴하며 넓은 면적의 전기 전자 소자, 예를 들면 유연한 디스플레이, 무선 주파수 인식 장치(RFIDs), 스마트카드, 메모리, 태양전지, 센서 등에 대해 큰 잠재력을 갖고 있다.Organic nanowires have great potential for flexible, inexpensive and large-area electrical and electronic devices, such as flexible displays, radio frequency identification devices (RFIDs), smart cards, memory, solar cells and sensors.
그러나 대면적의 응용을 위한 적절한 패터닝 정렬 기술이 부족하다는 문제가 남아있으며, 예를 들어 유기 나노와이어를 원하는 배향 및 특정 위치에 개개의 나노와이어를 컨트롤하기 어려운 문제가 있다.However, there remains a problem of lack of proper patterning alignment technology for application of a large area, for example, it is difficult to control individual nanowires at a specific position and desired orientation of the organic nanowires.
따라서, 본 발명에서는 기판에 유기 나노와이어를 패터닝하는 것이 아닌, 기판 자체에 나노 구조를 갖는 전극을 제조하여 이를 포함하는 유기 반도체 소자를 제공하고자 하였다.Therefore, in the present invention, rather than patterning the organic nanowires on the substrate, an electrode having a nanostructure on the substrate itself was prepared to provide an organic semiconductor device including the same.
본 발명은 유기 반도체층과 접촉하는 제 2 전극의 표면이 음각 및 양각의 패턴으로 교대로 새겨진 나노 구조물인 유기 반도체 소자를 제공하는 것을 목적으로 한다.An object of the present invention is to provide an organic semiconductor device having a nanostructure in which the surface of the second electrode contacting the organic semiconductor layer is alternately engraved in an intaglio and embossed pattern.
또한, 본 발명은 상기 나노 구조물을 지닌 제 2전극으로 인하여 높은 효율을 얻을 수 있는 유기 반도체 소자를 제공하는 것을 목적으로 한다.In addition, an object of the present invention is to provide an organic semiconductor device capable of obtaining high efficiency due to the second electrode having the nanostructure.
또한, 본 발명은 상기 유기 반도체 소자의 제조방법을 제공하는 것을 목적으로 한다.In addition, an object of the present invention is to provide a method for manufacturing the organic semiconductor device.
상기 목적을 달성하기 위하여,In order to achieve the above object,
본 발명은 제 1전극, 유전층, 유기 반도체층 및 제 2전극이 순차적으로 적층된 유기 반도체 소자로,The present invention is an organic semiconductor device in which a first electrode, a dielectric layer, an organic semiconductor layer, and a second electrode are sequentially stacked.
상기 유기 반도체층과 접촉하는 제 2전극의 일면이 음각 및 양각의 패턴이 교대로 새겨진 나노 구조물인 것을 특징으로 하는 유기 반도체 소자를 제공한다.Provided is an organic semiconductor device characterized in that one surface of the second electrode contacting the organic semiconductor layer is a nano structure in which intaglio and embossed patterns are alternately engraved.
또한, 본 발명은In addition, the present invention
(1)기판 상에 제 1전극을 형성하는 단계;(1) forming a first electrode on the substrate;
(2)상기 제 1전극 상부에 유전층을 형성하는 단계;(2) forming a dielectric layer over the first electrode;
(3)상기 유전층 상부에 유기 반도체막을 형성하는 단계; 및(3) forming an organic semiconductor film on the dielectric layer; And
(4)상기 유기 반도체막 상부에 제 2전극을 형성하는 단계를 포함하는 유기 반도체 소자 제조방법으로,(4) A method of manufacturing an organic semiconductor device, comprising forming a second electrode on the organic semiconductor film.
상기 유기 반도체 소자는 상기 본 발명의 유기 반도체 소자를 포함하는 것을 특징으로 하는 유기 반도체 소자 제조방법을 제공한다.The organic semiconductor device provides an organic semiconductor device manufacturing method comprising the organic semiconductor device of the present invention.
본 발명의 유기 반도체 소자는 제 2전극의 나노 구조물로 인하여 표면 저항을 낮출 수 있어 효율이 매우 우수한 장점을 지니고 있다.The organic semiconductor device of the present invention has the advantage of being very efficient because it can lower the surface resistance due to the nanostructure of the second electrode.
도 1은 본 발명의 유기 반도체 소자를 나타낸 것이다.
도 2는 측면에서 바라본 제 2전극을 나타낸 것이다.
도 3은 위에서 바라본 제 2전극을 나타낸 것이다.
도 4는 제 2전극의 양각이 사각형 형태로 떨어져 있는 것을 위에서 바라본 도면이다.
도 5는 제 2전극의 양각이 삼각형 형태로 떨어져 있는 것을 위에서 바라본 도면이다.
도 6은 제 2전극의 양각 간격이 불규칙한 것을 위에서 바라본 도면이다.
도 7은 제 2전극의 측면 SEM 사진이다.
도 8은 실험예 1의 결과를 나타낸 그래프이다.1 shows an organic semiconductor device of the present invention.
2 shows the second electrode as viewed from the side.
3 shows a second electrode as viewed from above.
4 is a view as viewed from above that the embossing of the second electrode is separated in a square shape.
5 is a view as viewed from above that the embossing of the second electrode is separated in a triangular shape.
6 is a view as viewed from above that the embossed spacing of the second electrode is irregular.
7 is a side SEM photograph of the second electrode.
8 is a graph showing the results of Experimental Example 1.
이하, 본 발명을 보다 자세히 설명한다.Hereinafter, the present invention will be described in more detail.
본 발명은 제 1전극, 유전층, 유기 반도체층 및 제 2전극이 순차적으로 적층된 유기 반도체 소자로,The present invention is an organic semiconductor device in which a first electrode, a dielectric layer, an organic semiconductor layer, and a second electrode are sequentially stacked.
상기 유기 반도체층과 접촉하는 제 2전극의 일면이 음각 및 양각의 패턴이 교대로 새겨진 나노 구조물인 것을 특징으로 하는 유기 반도체 소자에 관한 것이다.It relates to an organic semiconductor device characterized in that one surface of the second electrode in contact with the organic semiconductor layer is a nanostructure in which intaglio and embossed patterns are alternately engraved.
본 발명의 유기 반도체 소자의 제 2전극은 유기 반도체층과 접촉하는 일면의 구조가 음각 및 양각의 패턴이 교대로 새겨진 나노 구조를 지니고 있는 것이 특징이다. 제 2전극의 일면을 나노 구조로 개질함으로써 표면 저항이 낮아져 제 2전극에서 유기 반도체층으로 전자의 이동이 용이해져 유기 반도체 소자의 효율을 증가시킬 수 있다. 이 때 전자는 나노 크기의 음각 및 양각의 패턴을 인식하지 못하며, 그로 인하여 전자의 이동이 더욱 용이해질 수 있다.The second electrode of the organic semiconductor device of the present invention is characterized in that the structure of one surface in contact with the organic semiconductor layer has a nano structure in which engraved and embossed patterns are alternately engraved. By modifying one surface of the second electrode with a nano-structure, the surface resistance is lowered, and the transfer of electrons from the second electrode to the organic semiconductor layer is facilitated, thereby increasing the efficiency of the organic semiconductor device. At this time, the electrons do not recognize the nano-sized intaglio and embossed patterns, and as a result, the electrons may be more easily moved.
상기 제 2전극의 음각 및 양각의 패턴은 10 내지 200nm의 간격으로 교대로 구성되었으며, 바람직하게는 10 내지 50nm의 간격으로 구성되었다.The intaglio and embossed patterns of the second electrode were alternately formed at intervals of 10 to 200 nm, and preferably at intervals of 10 to 50 nm.
상기 패턴 간격이 10nm 미만이면 제 2전극의 제조가 어렵고, 200nm를 초과하면 나노구조로 인한 효과를 얻기 어렵다.If the pattern spacing is less than 10 nm, it is difficult to manufacture the second electrode, and if it exceeds 200 nm, it is difficult to obtain an effect due to the nanostructure.
또한, 상기 양각의 높이는 10 내지 200 nm이며, 바람직하게는 30 내지 100nm이다. 상기 음각 및 양각의 높이는 상기 범위에서 전하주입시 접촉저항이 감소하여 유기 반도체 소자의 효율이 증가될 수 있다. In addition, the height of the embossing is 10 to 200 nm, preferably 30 to 100 nm. The intaglio and embossed heights may decrease the contact resistance during charge injection in the above range, thereby increasing the efficiency of the organic semiconductor device.
상기 양각은 원기둥 모양으로 돌출되었으며, 돌출된 양각은 서로 사각(도 4) 또는 삼각형의 형태(도 5)로 규칙적인 간격으로 떨어져 있을 수 있으며, 서로의 간격이 불규칙적(도 6)일 수도 있다.The embossing is projected in a cylindrical shape, and the protruding embossing may be spaced apart at regular intervals in a square shape (FIG. 4) or a triangular shape (FIG. 5), and may be irregular in space (FIG. 6).
상기 제 1전극은 산화인듐주석(Indium Tin Oxide, ITO), 산화인듐아연(Indium Zinc Oxide, IZO), 산화인듐주석아연(Indium Tin Zinc Oxide, ITZO), 산화알루미늄아연(Al doped Zinc Oxide, AZO), 산화갈륨아연(Gallium Zinc Oxide, GZO), 알루미늄(Al), n 도핑된 실리콘 및 Au-Si로 이루어진 군으로부터 선택되는 1종을 포함한다.The first electrode is indium tin oxide (ITO), indium zinc oxide (Indium Zinc Oxide, IZO), indium tin zinc oxide (Indium Tin Zinc Oxide, ITZO), aluminum oxide (Al doped Zinc Oxide, AZO ), gallium zinc oxide (Gallium Zinc Oxide, GZO), aluminum (Al), n doped silicon and Au-Si.
상기 유전층은 파릴렌(parylene), 에폭시(epoxy), 폴리이미드(polyimide), 폴리아미드(polyamide), 폴리비닐클로라이드(polyvinylchloride), 벤조사이클로부텐(benzocyclobutene), 폴리비닐알코올(polyvinylalcohol), 폴리비닐페놀(polyvinylphenol), 사이클로펜텐(cyclopentene) 및 산화규소(SiO2)로 이루어진 군으로부터 선택되는 1종을 포함한다.The dielectric layer is parylene, epoxy, polyimide, polyamide, polyvinylchloride, benzocyclobutene, polyvinylalcohol, polyvinylphenol (polyvinylphenol), cyclopentene (cyclopentene) and silicon oxide (SiO 2 ).
상기 유기 반도체층은 유기 물질이 도포된 층으로, 상기 유기 물질은 펜타센(pentacene), 팁스-펜타센(6,13-Bis(triisopropylsilylethynyl)pentacene, TIPS-pentacene), 테트라센(tetracene), 안트라센(anthracene), 나프탈렌(naphthalene), 알파-6-티오펜(alpha-6-thiopene), 알파-4-티오펜(alpha-6-thiopene), 페릴렌(perylene), 루브렌(rubrene), 코로넨(coronene), 페릴렌테트라카르복실릭디안하이드라이드(perylene tetracarboxylic dianhydride), 페릴렌테트라카르복실릭디이미드(perylene tetracarboxylic diimide), 폴리티오펜(polythiopene), 폴리파라페닐렌비닐렌(polyparavinylene), 폴리파라페닐렌(polyparaphenylene), 폴리플로렌(polyfulorene) 및 폴리티오펜비닐렌(polythiopenevinylene)으로 이루어진 군으로부터 선택되는 1종 이상을 포함하며, 바람직하게는 팁스-펜타센(TIPS-pentacene)을 포함한다.The organic semiconductor layer is a layer coated with an organic material, and the organic material is pentacene, tips, pentacene (6,13-Bis (triisopropylsilylethynyl)pentacene, TIPS-pentacene), tetracene, anthracene (anthracene), naphthalene, alpha-6-thiopene, alpha-4-thiophene, perylene, rubrene, coro Coronene, perylene tetracarboxylic dianhydride, perylene tetracarboxylic diimide, polythiopene, polyparaphenylene vinylene , Polyparaphenylene (polyparaphenylene), polyfluorene (polyfulorene) and polythiophene vinylene (polythiopenevinylene) contains at least one selected from the group consisting of, preferably, TIPS-pentacene (TIPS-pentacene) Includes.
상기 유기 물질은 용액 상태이며, 스핀코팅법, 슬릿코팅법, 드럽캐스팅법, 딥캐스팅법, 잉크젯법, 프린팅법 및 임프린트법으로 이루어진 군으로부터 선택되는 1종 이상의 방법으로 도포될 수 있다. 상기의 방법으로 유기 물질을 도포한 후, 가열 및 건조 과정을 거쳐 유기 반도체층이 형성 된다.The organic material is in a solution state, and may be applied by one or more methods selected from the group consisting of spin coating, slit coating, drum casting, deep casting, inkjet, printing and imprint. After applying the organic material by the above method, an organic semiconductor layer is formed through a heating and drying process.
상기 제 2전극은 금(Au), 은(Ag), 백금(Pt), 크롬(Cr), 티타늄(Ti), 구리(Cu), 알루미늄(Al), 탄탈륨(Ta), 몰리브덴(Mo), 텅스텐(W), 니켈(Ni) 및 팔라듐(Pd)으로 이루어진 군으로부터 선택되는 1종 이상을 포함하며, 바람직하게는 금을 포함한다.The second electrode is gold (Au), silver (Ag), platinum (Pt), chromium (Cr), titanium (Ti), copper (Cu), aluminum (Al), tantalum (Ta), molybdenum (Mo), Tungsten (W), nickel (Ni) and palladium (Pd), and at least one selected from the group consisting of, preferably contains gold.
또한, 상기 유기 반도체 소자는 바람직하게는 유기 트랜지스터일 수 있다.Further, the organic semiconductor device may be preferably an organic transistor.
또한, 본 발명은 In addition, the present invention
(1)기판 상에 제 1전극을 형성하는 단계;(1) forming a first electrode on the substrate;
(2)상기 제 1전극 상부에 유전층을 형성하는 단계;(2) forming a dielectric layer over the first electrode;
(3)상기 유전층 상부에 유기 반도체막을 형성하는 단계; 및(3) forming an organic semiconductor film on the dielectric layer; And
(4)상기 유기 반도체막 상부에 제 2전극을 형성하는 단계를 포함하는 유기 반도체 소자 제조방법으로,(4) A method of manufacturing an organic semiconductor device, comprising forming a second electrode on the organic semiconductor film.
상기 유기 반도체 소자는 상기 본 발명의 유기 반도체 소자를 포함하는 것을 특징으로 하는 유기 반도체 소자 제조방법에 관한 것이다.The organic semiconductor device relates to an organic semiconductor device manufacturing method comprising the organic semiconductor device of the present invention.
상기 제 2전극은 유기 반도체층과 접촉하는 일면의 구조가 음각 및 양각의 패턴이 교대로 새겨진 나노 구조를 지니고 있다. 상기 나노 구조로 인하여 제 2전극의 표면 저항이 낮아져 제 2전극에서 유기 반도체층으로 전자의 이동이 용이해져 유기 반도체 소자의 효율이 증가할 수 있다. 이 때 전자는 나노 크기의 음각 및 양각의 패턴을 인식하지 못하며, 그로 인하여 전자의 이동이 더욱 용이해질 수 있다.The second electrode has a nano structure in which the structure of one surface in contact with the organic semiconductor layer is engraved with alternating intaglio and embossed patterns. Due to the nano-structure, the surface resistance of the second electrode is lowered, and thus the transfer of electrons from the second electrode to the organic semiconductor layer is facilitated, thereby increasing the efficiency of the organic semiconductor device. At this time, the electrons do not recognize the nano-sized intaglio and embossed patterns, and as a result, the electrons may be more easily moved.
상기 제 2전극의 제조방법은 본 발명에서 특별히 한정하는 것은 아니며, 사출 성형 등 당 업계에 공지된 방법들이 사용될 수 있다.The manufacturing method of the second electrode is not particularly limited in the present invention, and methods known in the art, such as injection molding, may be used.
이하에서, 실시예를 통하여 본 발명을 보다 상세히 설명한다. 그러나, 하기의 실시예는 본 발명을 더욱 구체적으로 설명하기 위한 것으로서, 본 발명의 범위가 하기의 실시예에 의하여 한정되는 것은 아니다.Hereinafter, the present invention will be described in more detail through examples. However, the following examples are intended to illustrate the present invention more specifically, but the scope of the present invention is not limited by the following examples.
실시예 1. 유기 반도체 소자 제조Example 1. Organic semiconductor device manufacturing
20mg/mL의 팁스-펜타센(6,13-Bis(triisopropylsilylethynyl)pentacene) 유기반도체 시료에 1,2,3,4-테트라하이드로나프탈렌 무수물(1,2,3,4-tetrahydronaphtalene, anhydrous 99%)을 혼합하여 팁스-펜타센 용액을 제조하였다.1,2,3,4-tetrahydronaphthalene anhydride (1,2,3,4-tetrahydronaphtalene, anhydrous 99%) in 20mg/mL tip-pentacene (6,13-Bis(triisopropylsilylethynyl)pentacene) organic semiconductor sample Was mixed to prepare a tip-pentacene solution.
그 후, 포토리소방법을 이용하여 유리 기판 위에 제 2전극인 Au의 나노 패턴을 100nm 간격을 갖게 제조하였다. 상기 Au 층 위에 상기 팁스-펜타센을 스핀코팅 방법으로 도포하고, 100℃에서 5분 동안 가열하여 용액을 증발시켜 유기 반도체 층을 제작하였다. 상기 유기 반도체 층 상부에 스핀코팅 방법으로 Cytop을 도포하고, 90℃에서 20분 동안 가열하여 유전체 박막을 형성하였다. 상기 유전체 박막 상부에 Al 층을 진공 열증착기를 이용하여 적층시켜 유기 반도체 소자를 제조하였다.Thereafter, a nano pattern of Au, which is a second electrode, was formed on the glass substrate using a photolitho method with a spacing of 100 nm. The tips-pentacene was coated on the Au layer by a spin coating method, and heated at 100° C. for 5 minutes to evaporate the solution to prepare an organic semiconductor layer. Cytop was applied by spin coating on the organic semiconductor layer, and heated at 90° C. for 20 minutes to form a dielectric thin film. An Al layer was deposited on the dielectric thin film using a vacuum thermal evaporator to manufacture an organic semiconductor device.
비교예 1. 유기 반도체 소자 제조Comparative Example 1. Organic semiconductor device manufacturing
패턴이 없는 Au를 사용한 것을 제외하고는 상기 실시예 1과 동일하게 실시하여 유기 반도체 소자를 제조하였다.An organic semiconductor device was manufactured in the same manner as in Example 1, except that Au without a pattern was used.
실험예 1. 유기 반도체 소자의 전류-전압 측정Experimental Example 1. Current-voltage measurement of an organic semiconductor device
상기 실시예 1 및 비교예 1에서 제조한 유기 반도체 소자의 전류-전압을 측정하였다(도 8).The current-voltage of the organic semiconductor device manufactured in Example 1 and Comparative Example 1 was measured (FIG. 8).
제 2전극에 나노패턴이 없는 비교예 1의 유기 반도체 소자는 전압이 증가하여도 전류의 증가가 보이지 않았으나, 제 2전극에 100nm 간격으로 나노패턴이 형성된 실시예 1의 유기 반도체 소자는 전압이 증가할수록 전류가 증가하는 결과를 보였다.The organic semiconductor device of Comparative Example 1 without a nanopattern on the second electrode did not show an increase in current even when the voltage increased, but the voltage increased in the organic semiconductor device of Example 1 in which nanopatterns were formed at 100 nm intervals on the second electrode. The more it showed, the more the current increased.
상기 결과를 통하여, 본 발명의 유기 반도체 소자는 제 2전극에 나노패턴이 형성됨으로써, 유기 반도체 소자의 효율이 증가된다는 것을 알 수 있다.Through the above results, it can be seen that the efficiency of the organic semiconductor device is increased by forming a nano pattern on the second electrode of the organic semiconductor device of the present invention.
Claims (9)
기판 상에 형성되며, 일면에 나노패턴이 형성된 상기 제 2전극;
상기 제 2전극 상에 형성된 상기 유기 반도체층;
상기 유기 반도체층 상에 형성된 상기 유전층;
상기 유전층 상에 형성된 상기 제 1전극을 포함하며,
상기 유기 반도체층과 접촉하는 제 2전극의 일면은 음각 및 양각의 패턴이 교대로 새겨진 나노 구조물로, 상기 제 2전극의 음각 및 양각의 패턴은 10 내지 200 nm의 간격으로 교대로 이루어지고, 상기 제 2전극의 양각 패턴의 높이는 10 내지 200 nm인 것으로서, 전자가 상기 음각 및 양각의 패턴을 인식하지 못하여 전자의 이동이 용이해지고, 표면 저항을 감소시켜 상기 유기 반도체 소자의 효율을 향상시키는 것을 특징으로 하는 유기 반도체 소자.An organic semiconductor device in which a first electrode, a dielectric layer, an organic semiconductor layer, and a second electrode are sequentially stacked,
A second electrode formed on a substrate and having a nano pattern on one surface;
The organic semiconductor layer formed on the second electrode;
The dielectric layer formed on the organic semiconductor layer;
It includes the first electrode formed on the dielectric layer,
One surface of the second electrode in contact with the organic semiconductor layer is a nano structure in which engraved and embossed patterns are alternately engraved, and engraved and embossed patterns of the second electrode are alternately formed at intervals of 10 to 200 nm. The height of the embossed pattern of the second electrode is 10 to 200 nm, and electrons do not recognize the intaglio and embossed patterns, thereby facilitating the movement of electrons and improving the efficiency of the organic semiconductor device by reducing surface resistance. An organic semiconductor device.
(2)상기 제 1전극 상부에 유전층을 형성하는 단계;
(3)상기 유전층 상부에 유기 반도체막을 형성하는 단계; 및
(4)상기 유기 반도체막 상부에 제 2전극을 형성하는 단계를 포함하는 유기 반도체 소자 제조방법으로,
상기 유기 반도체 소자는 상기 청구항 1 내지 5 및 8항 중 어느 한 항의 유기반도체 소자를 포함하는 것을 특징으로 하는 유기 반도체 소자 제조방법.(1) forming a first electrode on the substrate;
(2) forming a dielectric layer over the first electrode;
(3) forming an organic semiconductor film on the dielectric layer; And
(4) A method of manufacturing an organic semiconductor device, comprising forming a second electrode on the organic semiconductor film.
The organic semiconductor device is an organic semiconductor device manufacturing method characterized in that it comprises the organic semiconductor device of any one of claims 1 to 5 and 8.
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