KR20170044568A - Gate driving circuit and display device having them - Google Patents

Abstract

The present invention relates to a gate actuator circuit which includes a plurality of stages. A k^th stage (k is a positive integer) among the plurality thereof receives a clock signal, a (k-1)^th carry signal from a (k-1)^th stage, a (k+1)^th carry signal from a (k+1)^th stage, a carry signal from a (k+2)^th stage, first ground voltage, and second ground voltage, and also outputs a k^th carry signal and a k^th gate signal. The clock signal is a pulse signal in which high voltage and third ground voltage periodically occur, wherein the third ground voltage has lower level of voltage than the first ground voltage and the second ground voltage.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate driver circuit and a display device including the gate driver circuit.

The present invention relates to a gate driving circuit integrated on a display panel and a display device including the same.

The display device includes a plurality of gate lines, a plurality of data lines, a plurality of gate lines, and a plurality of pixels connected to the plurality of data lines. The display device includes a gate driving circuit for providing gate signals to a plurality of gate lines and a data driving circuit for outputting data signals to a plurality of data lines.

The gate driving circuit includes a shift register including a plurality of driving stage circuits (hereinafter, driving stages). The plurality of driving stages output gate signals corresponding to the plurality of gate lines, respectively. Each of the plurality of driving stages includes a plurality of transistors that are connected to each other.

When the frequency of the gate signal output from the gate driving circuit is the same, the horizontal period becomes longer when the size of the display panel becomes larger. As one horizontal period becomes longer, a delay of the gate signal occurs, which may result in deterioration of the display image quality.

An object of the present invention is to provide a gate drive circuit with improved reliability.

It is an object of the present invention to provide a display device including a gate drive circuit with improved reliability.

In order to achieve the above object, the gate drive circuit of the present invention includes a plurality of stages. The kth stage of the plurality of stages includes a clock signal, a (k-1) th carry signal from the (k-1) th stage, a k + A first ground voltage and a second ground voltage, and outputs a k-th gate signal and a k-th carry signal, wherein the clock signal is a pulse signal periodically showing a high voltage and a third ground voltage, The ground voltage has a voltage level lower than the first ground voltage and the second ground voltage.

In this embodiment, the kth stage of the plurality of stages outputs the high voltage of the clock signal as the kth gate signal in response to the signal of the first node during the kth clock period, And discharging the kth gate signal to the third ground voltage of the clock signal in response to the signal of the first node during a first clock period.

In this embodiment, the k-th stage among the plurality of stages further includes a second output unit for outputting the clock signal as the k-th carry signal in response to the signal of the first node.

In this embodiment, the kth stage of the plurality of stages further includes a first pull down portion for discharging the kth gate signal to the first ground voltage in response to the carry signal to the (k + 1) th carry signal .

In this embodiment, a k-th stage of the plurality of stages is connected to the first node in response to the clock signal, the (k-1) -th carry signal, and the (k + 2 ground voltage, an inverter unit providing the clock signal to a second node, discharging the second node to the second ground voltage in response to the signal of the first node, A first discharging unit for discharging the first node to the second ground voltage in response to a signal of the second node, a first discharging unit for discharging the k < th > carry signal to the second grounding voltage in response to the signal of the second node, And a third discharging unit discharging the kth gate signal to the first ground voltage in response to the signal of the second node.

In this embodiment, the kth stage of the plurality of stages further includes a second pull down portion for discharging the kth carry signal to the second ground voltage in response to the (k + 1) th carry signal.

In this embodiment, the first ground voltage and the second ground voltage are different voltage levels.

In this embodiment, a k-th stage of the plurality of stages is connected to the first node in response to the clock signal, the (k-1) -th carry signal, and the (k + 2 ground voltage, an inverter section providing the clock signal to a second node, and a second node in response to the signal of the second node, the first node and the second node being coupled to the second ground voltage, A second discharging section for discharging the kth carry signal to the second grounding voltage in response to the signal of the second node, a second discharging section for discharging the kth carry signal to the second grounding voltage in response to the signal of the second node, And a second pull-down unit for discharging the k-th carry signal to the second ground voltage in response to the (k + 2) -th carry signal, and a third pull- The.

In this embodiment, the kth stage of the plurality of stages includes a fourth discharging portion for discharging the first node to the second ground voltage in response to the (k + 2) th carry signal and a fourth discharging portion for discharging the first node to the second ground voltage, And a first pull-down section for discharging the k-th gate signal to the second ground voltage in response to the carry signal in the second carry signal.

In this embodiment, the fourth discharge section includes a first discharge transistor connected between the first node and the fourth node, the first discharge transistor including a control electrode connected to the (k + 2) th carry signal, And a second discharge transistor connected between the node and the second ground voltage and including a control electrode connected to the fourth node.

A display device according to another aspect of the present invention includes: a display panel including a plurality of pixels connected to a plurality of gate lines and a plurality of data lines, a plurality of driving stages for outputting gate signals to the plurality of gate lines And a data driving circuit for driving the plurality of data lines. The kth stage of the plurality of stages includes a clock signal, a (k-1) th carry signal from the (k-1) th stage, a k + A first ground voltage, and a second ground voltage, and outputs a k-th gate signal and a k-th carry signal. The clock signal is a pulse signal periodically showing a high voltage and a third ground voltage, and the third ground voltage has a voltage level lower than the first ground voltage and the second ground voltage.

In this embodiment, the display panel includes a display region in which the plurality of pixels are arranged, and a non-display region adjacent to the display region, and the gate drive circuit is integrated in the non-display region.

In this embodiment, the kth stage of the plurality of stages outputs the high voltage of the clock signal as the kth gate signal in response to the signal of the first node during the kth clock period, And discharging the kth gate signal to the third ground voltage of the clock signal in response to the signal of the first node during a first clock period.

In this embodiment, the k-th stage among the plurality of stages further includes a second output unit for outputting the clock signal as the k-th carry signal in response to the signal of the first node.

In this embodiment, the kth stage of the plurality of stages further includes a first pull down portion for discharging the kth gate signal to the first ground voltage in response to the carry signal to the (k + 1) th carry signal And the display device.

In this embodiment, a k-th stage of the plurality of stages is connected to the first node in response to the clock signal, the (k-1) -th carry signal, and the (k + 2 ground voltage, an inverter unit providing the clock signal to a second node, discharging the second node to the second ground voltage in response to the signal of the first node, A first discharging unit for discharging the first node to the second ground voltage in response to a signal of the second node, a first discharging unit for discharging the k < th > carry signal to the second grounding voltage in response to the signal of the second node, And a third discharging unit discharging the kth gate signal to the first ground voltage in response to a signal of the second node.

In this embodiment, the kth stage of the plurality of stages further includes a second pull down portion for discharging the kth carry signal to the second ground voltage in response to the (k + 1) th carry signal.

In this embodiment, the first ground voltage and the second ground voltage are different voltage levels.

In this embodiment, the display device controls the gate driving circuit and the data driving circuit in response to a control signal and a video signal provided from the outside, and outputs the clock signal, the first ground voltage, And a drive controller for generating the first ground voltage and the third ground voltage.

In this embodiment, the pulses of the clock signal correspond to the plurality of gate lines, respectively, and the voltage level of the third ground voltage of each of the pulses of the clock signal corresponds to the order of the pulses in one frame do.

In this embodiment, when the gate signals are sequentially output in the order of the stages far from the stage adjacent to the drive controller among the plurality of stages, the voltage of the third ground voltage of each of the pulses of the clock signal The level is gradually lowered in accordance with the order of the pulses in the one frame.

The gate driving circuit having such a configuration can quickly discharge the gate signal by changing the voltage level of the clock signal. Therefore, the reliability of the gate drive circuit is improved. Also, the gate drive circuit can perform a stable operation without using some of the transistors for discharging the first node, the gate signal, and the carry signal. Therefore, the circuit area of the gate driving circuit can be reduced.

1 is a plan view of a display device according to an embodiment of the present invention.
2 is a timing diagram of signals of a display device according to an embodiment of the present invention.
3 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.
4 is a cross-sectional view of a pixel according to an embodiment of the present invention.
5 is a block diagram of a gate driving circuit according to an embodiment of the present invention.
6 is a circuit diagram of a driving stage according to an embodiment of the present invention.
7 is a timing chart for explaining the operation of the k-th driving stage shown in Fig.
8 is a circuit diagram of a driving stage according to another embodiment of the present invention.
9 is a circuit diagram of a driving stage according to another embodiment of the present invention.
10 is a circuit diagram of a driving stage according to another embodiment of the present invention.
11 is a block diagram of a gate driving circuit according to another embodiment of the present invention.
12 is a circuit diagram of the driving stage shown in Fig.
13 is a circuit diagram of a driving stage according to another embodiment of the present invention.
14 is a block diagram of a gate driving circuit according to another embodiment of the present invention.
15 is a circuit diagram of the driving stage shown in Fig.
FIG. 16 is a view showing an exemplary delay time of gate signals output from the gate driving circuit shown in FIG. 1. FIG.
17 is a block diagram showing an exemplary structure of the drive controller shown in Fig.
FIG. 18 is a timing diagram exemplarily showing clock signals generated in the clock and voltage generator shown in FIG. 17 and gate signals generated in the gate drive circuit shown in FIG.
FIG. 19 is a timing chart for another embodiment of the clock signals generated in the clock and voltage generator shown in FIG. 17 and the gate signals generated in the gate drive circuit shown in FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a display device according to an embodiment of the present invention. 2 is a timing diagram of signals of a display device according to an embodiment of the present invention.

1 and 2, a display device according to an embodiment of the present invention includes a display panel DP, a gate driving circuit 100, a data driving circuit 200, and a driving controller 300.

The display panel DP is not particularly limited and includes, for example, a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, An electrowetting display panel, and the like. In this embodiment, the display panel DP is described as a liquid crystal display panel. Meanwhile, the liquid crystal display device including the liquid crystal display panel may further include a polarizer, a backlight unit, and the like not shown.

The display panel DP includes a first substrate DS1, a second substrate DS2 spaced apart from the first substrate DS1, and a liquid crystal layer LCL disposed between the first substrate DS1 and the second substrate DS2. ). The display panel DP includes a display area DA in which a plurality of pixels PX ₁₁ to PX _nm are arranged and a non-display area NDA surrounding the display area DA.

The display panel DP includes a plurality of gate lines GL1 to GLn disposed on the first substrate DS1 and a plurality of data lines DL1 to DLm crossing the gate lines GL1 to GLn do. The plurality of gate lines GL1 to GLn are connected to the gate driving circuit 100. [ The plurality of data lines DL1 to DLm are connected to the data driving circuit 200. 1, only a part of a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm are shown.

1, only a part of a plurality of pixels PX ₁₁ to PX _{nm is} shown. The plurality of pixels PX ₁₁ to PX _nm are connected to corresponding gate lines of the plurality of gate lines GL1 to GLn and corresponding data lines of the plurality of data lines DL1 to DLm, respectively.

The plurality of pixels PX ₁₁ to PX _nm may be divided into a plurality of groups according to a color to be displayed. The plurality of pixels PX ₁₁ to PX _nm may display one of the primary colors. The primary colors may include red, green, blue and white. However, the present invention is not limited thereto, and the main color may further include various colors such as yellow, cyan, and magenta.

The gate drive circuit 100 and the data drive circuit 200 receive a control signal from the drive controller 300. The drive controller 300 may be mounted on the main circuit board MCB. The drive controller 300 receives image data and control signals from an external graphic controller (not shown). The control signal is a signal for distinguishing the frame intervals Ft-1, Ft and Ft + 1 from the vertical synchronization signal Vsync and the horizontal intervals HP, that is, the horizontal synchronization signal Hsync ), And a data enable signal and a clock signal that are at a high level only during an interval in which data is output to indicate an area where data is input.

The gate driving circuit 100 generates a gate control signal based on a control signal (hereinafter referred to as a gate control signal) received via the signal line GSL from the driving controller 300 during the frame periods Ft-1, Ft and Ft + And generates the signals G1 to Gn and outputs the gate signals G1 to Gn to the plurality of gate lines GL1 to GLn. The gate signals G1 to Gn may be sequentially output in correspondence with the horizontal intervals HP. The gate drive circuit 100 can be formed simultaneously with the pixels PX ₁₁ to PX _nm through the thin film process. For example, the gate driving circuit 100 may be mounted in an OSD (Oxide Semiconductor TFT Gate Driver circuit) in the non-display area NDA.

1 illustrates an example of one gate driving circuit 100 connected to the left ends of a plurality of gate lines GL1 to GLn. In one embodiment of the invention, the display device may comprise two gate drive circuits. One of the two gate driving circuits may be connected to the left ends of the plurality of gate lines GL1 to GLn and the other may be connected to the right ends of the plurality of gate lines GL1 to GLn. Further, one of the two gate drive circuits may be connected to the odd gate lines and the other to the even gate lines.

 The data driving circuit 200 generates gradation voltages according to image data provided from the driving controller 300 based on a control signal (hereinafter, a data control signal) received from the driving controller 300. The data driving circuit 200 outputs the gradation voltages to the plurality of data lines DL1 to DLm as the data voltages DS.

 The data voltages DS may comprise positive data voltages having a positive value for the common voltage and / or negative data voltages having a negative value. Some of the data voltages applied to the data lines DL1 to DLm during the respective horizontal intervals HP may have a positive polarity and the other may have a negative polarity. The polarity of the data voltages DS may be reversed according to the frame periods Ft-1, Ft, Ft + 1 to prevent deterioration of the liquid crystal. The data driving circuit 200 may generate inverted data voltages in units of frames in response to the inverted signal.

 The data driving circuit 200 may include a flexible circuit board 220 on which the driving chip 210 and the driving chip 210 are mounted. The data driving circuit 200 may include a plurality of driving chips 210 and a flexible circuit board 220. The flexible circuit board 220 electrically connects the main circuit board MCB and the first board DS1. The plurality of driving chips 210 provide data signals corresponding to corresponding ones of the plurality of data lines DL1 to DLm.

FIG. 1 exemplarily shows a data carrier circuit 200 of a tape carrier package (TCP: Tape Carrier Package) type. In another embodiment of the present invention, the data driving circuit 200 may be disposed on the non-display area NDA of the first substrate DS1 by a chip on glass (COG) method.

3 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. 4 is a cross-sectional view of a pixel according to an embodiment of the present invention. Each of the plurality of pixels PX ₁₁ to PX _nm shown in FIG. 1 may have the equivalent circuit shown in FIG.

As shown in FIG. 3, the pixel PX _ij includes a pixel thin film transistor TR (hereinafter referred to as a pixel transistor), a liquid crystal capacitor Clc, and a storage capacitor Cst. Hereinafter, the transistor means a thin film transistor. In one embodiment of the present invention, the storage capacitor Cst may be omitted.

The pixel transistor TR is electrically connected to the i-th gate line GLi and the j-th data line DLj. The pixel transistor TR outputs a pixel voltage corresponding to the data signal received from the jth data line DLj in response to the gate signal received from the i-th gate line GLi.

The liquid crystal capacitor Clc charges the pixel voltage output from the pixel transistor TR. The arrangement of the liquid crystal directors included in the liquid crystal layer (LCL, see FIG. 4) changes in accordance with the amount of charge charged in the liquid crystal capacitor Clc. Light incident on the liquid crystal layer is transmitted or blocked depending on the arrangement of liquid crystal directors.

The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc. The storage capacitor Cst maintains the arrangement of the liquid crystal director for a predetermined period.

4, the pixel transistor TR includes a control electrode GE connected to the i-th gate line GLi (see FIG. 3), an activating portion AL superimposed on the control electrode GE, A first electrode SE connected to the line DLj (see FIG. 3), and a second electrode DE disposed apart from the first electrode SE.

The liquid crystal capacitor Clc includes a pixel electrode PE and a common electrode CE. The storage capacitor Cst includes a portion of the storage line STL overlapping the pixel electrode PE and the pixel electrode PE.

An i-th gate line GLi and a storage line STL are disposed on one surface of the first substrate DS1. And the control electrode GE is branched from the i-th gate line GLi. The i-th gate line GLi and the storage line STL may be formed of a metal such as aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), tantalum (Ta) Metals, alloys thereof, and the like. The i-th gate line GLi and the storage line STL may include a multilayer structure, for example, a titanium layer and a copper layer.

A first insulating layer 10 covering the control electrode GE and the storage line STL is disposed on one surface of the first substrate DS1. The first insulating layer 10 may include at least one of an inorganic material and an organic material. The first insulating layer 10 may be an organic film or an inorganic film. The first insulating layer 10 may include a multilayer structure, such as a silicon nitride layer and a silicon oxide layer.

An activating part (AL) overlapping the control electrode (GE) is disposed on the first insulating layer (10). The activation part AL may include a semiconductor layer and an ohmic contact layer. A semiconductor layer is disposed on the first insulating layer 10, and an ohmic contact layer is disposed on the semiconductor layer.

A second electrode DE and a first electrode SE are disposed on the activation part AL. The second electrode DE and the first electrode SE are disposed apart from each other. Each of the second electrode DE and the first electrode SE partially overlaps the control electrode GE.

A second insulating layer 20 covering the activating part AL, the second electrode DE and the first electrode SE is disposed on the first insulating layer 10. The second insulating layer 20 may include at least one of an inorganic material and an organic material. The second insulating layer 20 may be an organic film or an inorganic film. The second insulating layer 20 may include a multilayer structure, such as a silicon nitride layer and a silicon oxide layer.

Although the pixel transistor TR having a staggered structure is shown as an example in Fig. 1, the structure of the pixel transistor TR is not limited thereto. The pixel transistor TR may have a planar structure.

A third insulating layer (30) is disposed on the second insulating layer (20). The third insulating layer 30 provides a flat surface. The third insulating layer 30 may include an organic material.

A pixel electrode PE is disposed on the third insulating layer 30. [ The pixel electrode PE is connected to the second electrode DE through the second insulating layer 20 and the contact hole CH passing through the third insulating layer 30. [ An alignment film (not shown) covering the pixel electrode PE may be disposed on the third insulating layer 30. [

A color filter layer CF is disposed on one surface of the second substrate DS2. A common electrode CE is disposed on the color filter layer CF. A common voltage is applied to the common electrode CE. And has a different value from the common voltage and the pixel voltage. An alignment film (not shown) covering the common electrode CE may be disposed on the common electrode CE. Another insulating layer may be disposed between the color filter layer CF and the common electrode CE.

The pixel electrode PE and the common electrode CE, which are disposed with the liquid crystal layer LCL therebetween, form a liquid crystal capacitor Clc. A part of the pixel electrode PE and the storage line STL arranged with the first insulating layer 10, the second insulating layer 20 and the third insulating layer 30 interposed therebetween is connected to the storage capacitor Cst ). The storage line STL receives a storage voltage different from the pixel voltage. The storage voltage may have the same value as the common voltage.

On the other hand, the cross section of the pixel PX _ij shown in Fig. 3 is only one example. 3, at least one of the color filter layer CF and the common electrode CE may be disposed on the first substrate DS1. In other words, the liquid crystal display panel according to the present embodiment can be used in a VA (Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, IPS (in-plane switching) mode or Fringe- And a switching mode.

5 is a block diagram of a gate driving circuit according to an embodiment of the present invention.

As shown in Fig. 5, the gate drive circuit 100 includes a plurality of drive stages SRC1 to SRCn and dummy drive stages SRCn + 1 and SRCn + 2. The plurality of driving stages SRC1 to SRCn and the dummy driving stage SRCn + 1 have a dependent connection relationship operating in response to the carry signal output from the previous stage and the carry signal output from the next stage.

Each of the plurality of driving stages SRC1 to SRCn receives a first clock signal CKV / second clock signal CKVB, a first ground voltage VSS1 and a second ground signal VSS2 from the driving controller 300 shown in Fig. And receives the voltage VSS2. The driving stage SRC1 and the dummy driving stages SRCn + 1 and SRCn + 2 further receive the start signal STV.

In this embodiment, the plurality of driving stages SRC1 to SRCn are connected to the plurality of gate lines GL1 to GLn, respectively. The plurality of driving stages SRC1 to SRCn provide gate signals to the plurality of gate lines GL1 to GLn, respectively. In one embodiment of the present invention, the gate lines connected to the plurality of driving stages SRC1 to SRCn may be odd gate lines or even gate lines among the gate lines.

Each of the plurality of driving stages SRC1 to SRCn and the dummy driving stages SRCn + 1 and SRCn + 2 includes input terminals IN1, IN2 and IN3, an output terminal OUT, a carry terminal CR, Terminal CT, a clock terminal CK, a first ground terminal V1 and a second ground terminal V2.

The output terminal OUT of each of the plurality of driving stages SRC1 to SRCn is connected to a corresponding one of the plurality of gate lines GL1 to GLn. The gate signals generated from the plurality of driving stages SRC1 to SRCn are provided to a plurality of gate lines GL1 to GLn through an output terminal OUT.

The carry terminal CR of each of the plurality of driving stages SRC1 to SRCn is electrically connected to the first input terminal IN1 of the driving stage next to the driving stage. The carry terminal CR of each of the plurality of drive stages SRC1 to SRCn is connected to previous drive stages. For example, the carry terminal CR of the k-th driving stage among the driving stages SRC1 to SRCn is connected to the second input terminal IN2 of the (k-1) -th driving stage and the third input terminal IN3 ). The carry terminals CR of each of the plurality of drive stages SRC1 to SRCn and the dummy drive stages SRCn + 1 and SRCn + 2 output a carry signal.

The first input terminal IN1 of each of the plurality of driving stages SRC2 to SRCn and the dummy driving stages SRCn + 1 and SRCn + 2 receives the carry signal of the driving stage before the corresponding driving stage. For example, the first input terminal IN1 of the kth driving stages SRCk receives the carry signal of the (k-1) th driving stage SRCk-1. The first input terminal IN1 of the first driving stage SRC1 of the plurality of driving stages SRC1 to SRCn is connected to the vertical start signal STV ).

The second input terminal IN2 of each of the plurality of driving stages SRC1 to SRCn receives the carry signal from the carry terminal CR of the driving stage next to the driving stage. The third input terminal IN3 of each of the plurality of driving stages SRC1 to SRCn receives the carry signal of the next driving stage of the corresponding driving stage. For example, the second input terminal IN2 of the kth driving stage SRCk receives the carry signal output from the carry terminal CR of the (k + 1) th driving stage SRCk + 1. The third input terminal IN3 of the kth driving stage SRCk receives the carry signal output from the carry terminal CR of the (k + 2) th driving stage SRCk + 2. In another embodiment of the present invention, the second input terminal IN2 of each of the plurality of driving stages SRC1 to SRCn may be electrically connected to the output terminal OUT of the driving stage next to the driving stage. The third input terminal IN3 of each of the plurality of driving stages SRC1 to SRCn may be electrically connected to the output terminal OUT of the next driving stage.

The second input terminal IN2 of the driving stage SRCn disposed at the terminal receives the carry signal output from the carry terminal CR of the dummy stage SRCn + 1. The third input terminal IN3 of the driving stage SRCn receives the carry signal output from the carry terminal CR of the dummy stage SRCn + 2.

The clock terminal CK of each of the plurality of driving stages SRC1 to SRCn receives either the first clock signal CKV or the second clock signal CKVB. The clock terminals CK of the odd-numbered driving stages SRC1, SRC3, ..., SRCn-1 of the plurality of driving stages SRC1 to SRCn can receive the first clock signal CKV, respectively . The clock terminals CK of the even-numbered driving stages SRC2, SRC4, ..., SRCn among the plurality of driving stages SRC1 to SRCn can receive the second clock signal CKVB, respectively. The first clock signal CKV and the second clock signal CKVB may be signals having different phases.

The first ground terminal V1 of each of the plurality of driving stages SRC1 to SRCn receives the first ground voltage VSS1. The second ground terminal V2 of each of the plurality of driving stages SRC1 to SRCn receives the second ground voltage VSS2. The first ground voltage VSS1 and the second ground voltage VSS2 have different voltage levels and the second ground voltage VSS2 has a level lower than the first ground voltage VSS1.

In one embodiment of the present invention, each of the plurality of driving stages SRC1 to SRCn includes an output terminal OUT, a first input terminal IN1, a second input terminal IN2, One of the first ground terminal IN3, the carry terminal CR, the control terminal CT, the clock terminal CK, the first ground terminal V1 and the second ground terminal V2 may be omitted, . For example, either the first ground terminal V1 or the second ground terminal V2 may be omitted. In this case, each of the plurality of driving stages SRC1 to SRCn receives only one of the first ground voltage VSS1 and the second ground voltage VSS2. Also, the connection relationship of the plurality of drive stages SRC1 to SRCn may be changed.

6 is a circuit diagram of a driving stage according to an embodiment of the present invention.

FIG. 6 exemplarily shows k (k is a positive integer) driving stage SRCk among the plurality of driving stages SRC1 to SRCn shown in FIG. Each of the plurality of driving stages SRC1 to SRCn shown in FIG. 5 may have the same circuit as the kth driving stage SRCk.

6, the kth driving stage SRCk includes a first output unit 110, a second output unit 120, a controller 130, an inverter unit 140, a first discharging unit 150, A second discharging unit 160, a third discharging unit 170, a first pull down unit 180, and a second pull down unit 190.

The first output unit 110 outputs the kth gate signal Gk and the second output unit 120 outputs the kth carry signal CRk. The first pull down unit 180 pulls down the output terminal OUT to the first ground voltage VSS1 connected to the first ground terminal V1. The second pull down unit 190 pulls down the carry terminal CR to the second ground voltage VSS2 connected to the second ground terminal V2. The controller 130 controls the operations of the first output unit 110 and the second output unit 120.

The concrete configuration of the k-th driving stage SRCk is as follows.

The first output unit 110 includes a first output transistor TR1 and a capacitor C. The first output transistor TR1 includes a first electrode connected to the clock terminal CK, a control electrode connected to the first node N1, and a second electrode outputting the kth gate signal Gk.

 The second output portion 120 includes a second output transistor TR15. The second output transistor TR15 includes a first electrode connected to the clock terminal CK, a control electrode connected to the first node N1, and a second electrode for outputting the k-th carry signal CRk.

SRCn-1) and the clock terminal (CK) of the dummy driving stage (SRCn + 1) of the driving stages (SRC1 to SRCn) Lt; / RTI > receives the first clock signal CKV. The other driving stages SRC2, SRC4, ..., SRCn of the driving stages SRC1 to SRCn and the clock terminal CK of the dummy driving stage SRCn + 2 receive the second clock signal CKVB . The clock signal CKV and the clock signal CKVB are complementary signals. That is, the first clock signal CKV and the second clock signal CKVB may have a phase difference of 180 degrees.

The controller 130 controls the first output transistor TR1 and the second output transistor TR1 in response to the (k-1) -th carry signal CRk-1 received from the previous driving stage SRCk-1 to the first input terminal IN1. (TR2) is turned on. The control unit 130 responds to the (k + 2) -th carry signal CRk + 2 received from the next driving stage SRCk + 2 to the third input terminal INT3 to output the first output transistor TR1 and the second output transistor TR1 in response to the (k + (TR2) is turned off.

The controller 130 includes a fourth transistor and a sixth transistor TR4 and TR6. The fourth transistor TR4 includes a first electrode connected to the first input terminal IN1, a second electrode connected to the first node N1, and a control electrode connected to the first input terminal IN1. The sixth transistor TR6 includes a first electrode connected to the first node N1, a second electrode connected to the second ground terminal V2, and a control electrode connected to the third input terminal IN3.

The inverter unit 140 transfers the clock signal CKV from the clock terminal CK to the second node N2. The inverter unit 140 includes transistors TR7, TR8, TR12, and TR13. The seventh transistor T7 includes a first electrode connected to the clock terminal CK, a second electrode connected to the second node N2, and a control electrode connected to the third node N3. The twelfth transistor TR12 includes a first electrode connected to the clock terminal CK, a second electrode connected to the third node N3, and a control electrode connected to the clock terminal CK. The eighth transistor TR8 includes a first electrode connected to the second node N2, a second electrode connected to the first ground terminal V1, and a control electrode connected to the carry terminal CR. The thirteenth transistor TR13 includes a first electrode connected to the third node N3, a second electrode connected to the first ground terminal V1, and a control electrode connected to the carry terminal CR.

The first discharge section 150 discharges the second node N2 to the second ground terminal V2 in response to the signal of the first node N1 and outputs the second node N2 in response to the signal of the second node N3 And discharges the first node N1 to the second ground terminal V2. The first discharging unit 150 includes a fifth transistor TR5 and a tenth transistor TR10. The fifth transistor TR5 includes a first electrode connected to the second node N2, a second electrode connected to the second ground terminal V2, and a control electrode connected to the first input terminal IN1. The tenth transistor TR10 includes a first electrode connected to the first node N1, a second electrode connected to the second ground terminal V2, and a control electrode connected to the second node N2.

The second discharge section 160 discharges the carry terminal CR to the second ground terminal V2 in response to the signal of the second node N2. The second discharge unit 160 includes a first electrode connected to the carry terminal CR, a second electrode connected to the second ground terminal V2, and a control electrode connected to the second node N2. TR11).

The third discharge section 170 discharges the output terminal OUT to the first ground terminal V2 in response to the signal of the second node N2. The third discharging unit 170 includes a third transistor M3 including a first electrode connected to the output terminal OUT, a second electrode connected to the first ground terminal V1, and a control electrode connected to the second node N2. TR3).

The first pull down unit 180 discharges the output terminal OUT to the first ground terminal V1 in response to the (k + 1) -th carry signal CRk + 1 received via the second input terminal IN2 . The first pull-down unit 180 includes a first electrode connected to the output terminal OUT, a second electrode connected to the first ground terminal V1, and a control electrode connected to the second input terminal IN2. TR2.

The second pull down unit 190 discharges the carry terminal CR to the second ground terminal V2 in response to the (k + 1) th carry signal CRk + 1 received via the second input terminal IN2 . The second pulldown unit 190 includes a seventeenth transistor 171 including a first electrode connected to the carry terminal CR, a second electrode connected to the second ground terminal V2, and a control electrode connected to the second input terminal IN2. TR17).

7 is a timing chart for explaining the operation of the k-th driving stage shown in Fig.

Referring to FIGS. 6 and 7, the first clock signal CKV and the second clock signal CKVB have the same frequency and different phases. Each of the first clock signal CKV and the second clock signal CKVB is a pulse signal in which the high voltage VH and the third ground voltage VSS3 periodically appear. The third ground voltage VSS3 of the first clock signal CKV and the second clock signal CKVB has a voltage level lower than the first ground voltage VSS1 and the second ground voltage VSS2.

When the (k-1) -th carry signal CRk-1 transitions to the high level in the (k-1) -th clock period (k-1), the transistor TR4 is turned on and the voltage level of the first node N1 rises do. When the first clock signal CKV transits to the high voltage VH level in the kth clock period k, the first output transistor TR1 is turned on, so that the voltage of the first node N1 is lowered to the capacitor C, Lt; / RTI > At this time, the k-th gate signal Gk is outputted through the output terminal OUT. When the second output transistor TR2 is turned on by the boosted voltage of the first node N1, the kth carry signal CRk is output via the carry terminal CR.

When the first clock signal CKV transits to the third ground voltage VSS3 level in the (k + 1) -th clock period (k + 1), the kth gate signal Gk of the output terminal OUT becomes the first clock signal CKV) to the third ground voltage VSS3 level.

When the (k + 1) th carry signal (CRk + 1) transits to the high level, the second transistor T2 in the first pull down unit 180 is turned on and the kth gate signal Gk of the output terminal OUT is turned on. Is discharged to the first ground voltage VSS1. When the seventeenth transistor T17 in the second pull-down unit 190 is turned on in response to the (k + 1) th carry signal CRk + 1 of the high level, the kth carry signal CRk of the carry terminal CR is And discharged to the second ground voltage VSS2.

On the other hand, the fifth transistor TR5 is turned on while the (k-1) -th carry signal CRk-1 is at the high level ) Level. if the k-1-th carry signal CRk-1 is at the low level, the k-th carry signal CRk is at the low level, and the first clock signal CKV is at the high level in the (k + (N2) transits to the high level. When the second node N2 is at the high level, the third transistor TR3 is turned on and the output terminal OUT can be maintained at the first ground voltage VSS1. Likewise, if the second node N2 is at a high level, the eleventh transistor TR11 may be turned on and the carry terminal CR may be maintained at the second ground voltage VSS2.

the kth gate signal Gk of the output terminal OUT during the (k + 1) -th clock period (k + 1) has the third ground voltage Vcc1 of the first clock signal CKV, which is a voltage level lower than the first ground voltage VSS1 (VSS3), no separate transistor for discharging the k-th gate signal Gk of the output terminal OUT is required. Therefore, the circuit area of each of the plurality of drive stages SRC1 to SRCn can be reduced. Furthermore, since the kth gate signal Gk can be discharged with the third ground voltage VSS3, which is a voltage level lower than the first ground voltage VSS1, the discharge speed of the gate signal Gk is improved. Therefore, the delay of the gate signal can be minimized even if the size of the display panel DP shown in Fig. 1 becomes larger and the horizontal period becomes longer, which improves the reliability of the gate driving circuit 100. [

8 is a circuit diagram of a driving stage according to another embodiment of the present invention.

The driving stage ASRCk shown in Fig. 8 has a configuration similar to the driving stage SRCk shown in Fig. 6, but does not include the first pull down portion 180 and the second pull down portion 190. [

7, the kth clock signal Gk of the output terminal OUT during the (k + 1) -th clock period (k + 1) is set to the third ground voltage VSS3 of the first clock signal CKV Can be discharged. Accordingly, the first pull down unit 180 for discharging the kth clock signal Gk of the output terminal OUT to the first ground voltage VSS1 during the (k + 1) -th clock period (k + 1) have. Likewise, the kth carry signal CRk of the carry terminal CR may be discharged to the third ground voltage VSS3 of the first clock signal CKV. Accordingly, the second pull down unit 190 for discharging the kth carry signal CRk of the carry terminal CR to the second ground voltage VSS2 during the (k + 1) -th clock period (k + 1) have.

The driving stage ASRCk shown in FIG. 8, in which the first pull down portion 180 and the second pull down portion 190 shown in FIG. 6 are omitted, has a further reduced circuit area than the driving stage SRCk shown in FIG. . The stage ASRCk shown in FIG. 8 includes the fifth transistor TR5, but may not include the fifth transistor TR5 to reduce the circuit area.

9 is a circuit diagram of a driving stage according to another embodiment of the present invention.

The driving stage BSRCk shown in Fig. 9 has a structure similar to the driving stage SRCk shown in Fig. 6, but does not include the first pull down portion 180. [

7, the kth clock signal Gk of the output terminal OUT during the (k + 1) -th clock period (k + 1) is set to the third ground voltage VSS3 of the first clock signal CKV Can be discharged. Accordingly, the first pull down unit 180 for discharging the kth clock signal Gk of the output terminal OUT to the first ground voltage VSS1 during the (k + 1) -th clock period (k + 1) have.

However, the driving stage BSRCk shown in FIG. 9 may further include a second pull down portion 190 in the driving stage ASRCk shown in FIG. 8 to further stabilize the off voltage level of the k-th carry signal CRk have. The driving stage BSRCk shown in Fig. 9 in which the first pull down portion 180 shown in Fig. 6 is omitted can be reduced in circuit area than the driving stage SRCk shown in Fig.

10 is a circuit diagram of a driving stage according to another embodiment of the present invention.

The driving stage CSRCk shown in FIG. 10 has a configuration similar to that of the driving stage SRCk shown in FIG. 6, but further includes a third pull down portion 200.

Referring to FIG. 10, the third pull down unit 200 discharges the first node N1 to the second ground voltage VSS2 in response to the (k + 1) th carry signal CRk + 1. The third pull down unit 200 includes a ninth transistor TR9 and a sixteenth transistor TR16. The ninth transistor TR9 includes a first electrode connected to the first node N1, a second electrode connected to the fourth node N4, and a control electrode connected to the second input terminal IN2. The sixteenth transistor TR16 includes a first electrode connected to the fourth node N4, a second electrode connected to the second ground terminal V2, and a control electrode connected to the fourth node N4.

11 is a block diagram of a gate driving circuit according to another embodiment of the present invention.

The gate driving circuit 100_1 shown in Fig. 11 has a structure similar to that of the gate driving circuit 100 shown in Fig. 5, but a plurality of driving stages DSRC1 to DSRCn and dummy driving stages DSRCn + 1 and DSRCn + 2 do not include the third input terminal IN3.

The second input terminal IN2 of each of the plurality of driving stages SRC1 to SRCn receives the carry signal output from the next stage. For example, the second input terminal IN2 of the kth driving stage DSRCk is electrically connected to the carry terminal CR of the (k + 2) th driving stage DSRCk + 2. The second input terminal IN2 of each of the dummy driving stages DSRCn + 1, DSRCn + 2 receives the vertical start signal STV.

12 is a circuit diagram of the driving stage shown in Fig.

The driving stage DSRCk shown in Fig. 12 has a structure similar to the driving stage CSRCk shown in Fig. 10, in which the first pull down portion 180 and the second pull down portion 190 are connected to the (k + 2) CRk + 2).

The driving stage DSRCk does not include an input terminal for receiving the (k + 1) -th carry signal CRk + 1 and a signal line for transmitting the (k + 1) -th carry signal CRk + 1, The circuit area of the driving circuit 100_1 can be reduced.

13 is a circuit diagram of a driving stage according to another embodiment of the present invention.

The driving stage ESRCk shown in FIG. 13 has a configuration similar to the driving stage DSRCk shown in FIG. 12, but does not include the first pull down portion 180 and the third pull down portion 200.

7, the kth clock signal Gk of the output terminal OUT during the (k + 1) -th clock period (k + 1) is set to the third ground voltage VSS3 of the first clock signal CKV Can be discharged. Accordingly, the first pull down unit 180 for discharging the kth clock signal Gk of the output terminal OUT to the first ground voltage VSS1 during the (k + 1) -th clock period (k + 1) have.

Since the driving stage ESRCk does not include the first pull down portion 180 shown in Fig. 12, the circuit area can be reduced more than the driving stage DSRCk shown in Fig.

14 is a block diagram of a gate driving circuit according to another embodiment of the present invention.

The gate drive circuit 100_2 shown in FIG. 14 includes a plurality of drive stages SSRC1 to SSRCn and dummy drive stages (not shown). The plurality of driving stages SSRC1 to SSRCn and the dummy driving stages have a dependent connection relationship operating in response to a carry signal outputted from the previous stage and a carry signal outputted from the next stage.

Each of the plurality of driving stages SSRC1 to SSRCn receives either one of the first clock signals CKV1 to CKV6 and the second clock signals CKVB1 to CKVB6 from the driving controller 300 shown in Fig. And receives the ground voltage VSS1 and the second ground voltage VSS2. The driving stages SSRC1 to SSRC6 further receive the start signal STV.

Each of the plurality of driving stages SSRC1 to SSRCn and the dummy driving stages includes input terminals IN1 and IN2, an output terminal OUT, a carry terminal CR, a control terminal CT, a clock terminal CK, And includes a first ground terminal (V1) and a second ground terminal (V2).

15 is a circuit diagram of the driving stage shown in Fig.

The driving stage SSRCk shown in FIG. 15 has a configuration similar to the driving stage ASRCk shown in FIG. 8, in which the first input terminal IN1 receives the (k-6) th carry signal CRk-6, The second input terminal IN2 receives the (k + 8) th carry signal CRk + 8.

The driving stage SSRCk is connected to an input terminal for receiving the (k + 1) -th carry signal CRk + 1 and a signal for transmitting the (k + 1) -th carry signal CRk + 1 in comparison with the driving stage SRCk shown in Fig. Line, the circuit area of the gate driving circuit 100_2 shown in Fig. 14 can be reduced.

FIG. 16 is a view showing an exemplary delay time of gate signals output from the gate driving circuit shown in FIG. 1. FIG.

1 and 16, the gate driving circuit 100 includes a vertical synchronizing signal STV, a first clock signal CKV, and a second clock signal CLK received from the driving controller 300 through a signal line GSL, (G1 to Gn) based on the clock signal CKVB.

The delay curve DLY_G1 of the gate signal G1 and the delay curve DLY_Gn of the gate signal Gn when the voltage level of the low level of each of the first clock signal CKV and the second clock signal CKVB are the same You can tell the difference. That is, the delay of the gate signal Gn provided to the n-th gate line GLn remote from the drive controller 300 is smaller than the gate signal G1 provided to the first gate line GL1 adjacent to the drive controller 300 The time is longer. This is due to the delay time and the voltage level of the first clock signal CKV and the second clock signal CKVB provided from the drive controller 300 shown in FIG. 1 to the gate drive circuit 100.

For example, when the voltage level of the low level of each of the first clock signal CKV and the second clock signal CKVB is -11.5 V, the delay time of the gate signal G1 provided to the first gate line GL1 is 0 ns , and the delay time of the gate signal Gn provided to the n-th gate line GLn is 0.15 ns. That is, the delay time of the gate signal Gn provided to the n-th gate line GLn is longer when the voltage levels of the first clock signal CKV and the second clock signal CKVB are the same.

17 is a block diagram showing an exemplary structure of the drive controller shown in Fig.

Referring to FIG. 17, the drive controller 300 includes a drive controller 300, a timing controller 310, and a clock and voltage generator 320. The timing controller 310 receives the image data RGB and the control signal CTRL and generates a data control signal CONT and a data signal DATA to be provided to the data driving circuit 200 shown in FIG. And outputs a start signal STV to be supplied to the inverter 100. [ The data control signal CONT may include a data enable signal DE.

The clock and voltage generator 320 receives the start enable signal DEV included in the start signal STV and the data control signal CONT from the timing controller 310 and outputs the first clock signal CKV, Generates a clock signal (CKVB), a first ground voltage (VSS1), and a second ground voltage (VSS2). The first ground voltage VSS1 and the second ground voltage VSS2 generated by the clock and voltage generator 320 may be at different voltage levels. The clock and voltage generator 320 may be implemented as a PMIC (power management integrated circuit) and mounted on the main circuit board MCB shown in FIG.

The clock and voltage generator 320 generates a first clock signal CKV and a second clock signal CKVB in response to the start signal STV and the data enable signal DE from the timing controller 310, Can be changed. That is, the clock and voltage generator 320 can change the voltage level of the low level of each of the first clock signal CKV and the second clock signal CKVB according to the position of the gate lines GL1 through GLn.

FIG. 18 is a timing diagram exemplarily showing clock signals generated in the clock and voltage generator shown in FIG. 17 and gate signals generated in the gate drive circuit shown in FIG.

5, 17 and 18, the clock and voltage generator 320 starts generating the first clock signal CKV and the second clock signal CKVB in response to the start signal STV. The clock and voltage generator 320 counts the number of pulses of the first clock signal CKV and counts the number of pulses of the first clock signal CKV and the second clock signal CKVB in accordance with the pulse count value within one frame Ft And changes the voltage level of the third ground voltage VSS3. For example, the gate lines GL1 to GLn may be divided into p groups. The clock and voltage generator 320 generates the third ground voltage VSS3 of each of the first clock signal CKV and the second clock signal CKVB corresponding to the first group of gate lines GL1 to GLi- VSS3_V1. The clock and voltage generator 320 generates the third ground voltage VSS3 of each of the first clock signal CKV and the second clock signal CKVB corresponding to the second group of gate lines GLi to GLi- VSS3_V2. The clock and voltage generator 320 sets the third ground voltage VSS3 of each of the first clock signal CKV and the second clock signal CKVB corresponding to the last pth group of gate lines GLh to GLn to VSS3_Vp .

The third ground voltage VSS3 of the first clock signal CKV and the second clock signal CKVB has a relation of VSS3_V1> VSS3_V2> ....> VSS3_Vp. As a result, the gate signal Gn provided to the n-th gate line GLn far from the drive controller 300 is greater than the gate signal G1 provided to the first gate line GL1 adjacent to the drive controller 300 The discharge rate can be improved. Accordingly, even if the delay of the gate signals G1 to Gn according to the positions of the gate lines GL1 to GLn increases due to the increase of the size of the display panel DP shown in FIG. 1, it can be compensated.

In another embodiment, when the main circuit board MCB and the drive controller 300 shown in FIG. 1 are arranged adjacent to the last gate line GLn, the first clock signal CKV shown in FIG. 18 and the first clock signal CKV shown in FIG. It is preferable that the voltages corresponding to the low level of the second clock signal CKVB have a relationship of VSS3_V1 <VSS3_V2 <.... <VSS3_Vp.

FIG. 19 is a timing chart for another embodiment of the clock signals generated in the clock and voltage generator shown in FIG. 17 and the gate signals generated in the gate drive circuit shown in FIG.

In the timing chart shown in Fig. 18, the low level periods of the first clock signal CKV and the second clock signal CKVB are maintained at constant voltages VSS3_V1, VSS3_V2, and VSS3_Vp. 19, the low level interval of the first clock signal CKV and the second clock signal CKVB is set at a predetermined voltage VSS3_V1, VSS3_V2, and VSS3_Vp corresponding to the gate lines GL1 to GLn Is changed to the first ground voltage VSS1.

Voltages corresponding to the low level of the first clock signal CKV and the second clock signal CKVB have a relationship of VSS3_V1> VSS3_V2> ....> VSS3_Vp. As a result, the gate signal Gn provided to the n-th gate line GLn far from the drive controller 300 is greater than the gate signal G1 provided to the first gate line GL1 adjacent to the drive controller 300 The discharge rate can be improved. Therefore, even if the delay of the gate signals G1 to Gn according to the positions of the gate lines GL1 to GLn increases due to the increase of the size of the display panel DP shown in FIG. 1, it can be compensated.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible. In addition, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, and all technical ideas which fall within the scope of the following claims and equivalents thereof should be interpreted as being included in the scope of the present invention .

DP: display panel DS1: first substrate
DS2: second substrate 100: gate drive circuit
200: Data driver circuit MCB: Main circuit board
SRC1 to SRCn: driving stage 110: first output section
120: second output unit 130:
140: inverter section 150: first discharge section
160: second dispatcher 170: third dispatcher
180: first pull down part 190: second pull down part
200: Third pull-down section

Claims (20)

A gate drive circuit comprising a plurality of stages, comprising:
Wherein k (k is a positive integer) stage of the plurality of stages includes:
The k + 1 th carry signal from the (k + 1) th stage, the k + 1 th carry signal from the k + 1 th stage, the k + 2 th carry signal from the k + A second ground voltage, a kth gate signal, and a kth carry signal,
Wherein the clock signal is a pulse signal periodically showing a high voltage and a third ground voltage, and the third ground voltage has a voltage level lower than the first ground voltage and the second ground voltage. The method according to claim 1,
Wherein the k &lt; th &gt; stage of the plurality of stages comprises:
outputting the high voltage of the clock signal to the kth gate signal in response to a signal of the first node during a kth clock period and outputting the high voltage of the kth gate signal during a kth And a first output for discharging the gate signal to the third ground voltage of the clock signal. 3. The method of claim 2,
Wherein the k &lt; th &gt; stage of the plurality of stages comprises:
And a second output unit for outputting the clock signal as the k-th carry signal in response to the signal of the first node.
3. The method of claim 2,
Wherein the k &lt; th &gt; stage of the plurality of stages comprises:
And a first pull-down unit for discharging the k-th gate signal to the first ground voltage in response to the carry signal to the (k + 1) -th carry signal.
The method according to claim 1,
Wherein the k &lt; th &gt; stage of the plurality of stages comprises:
A control unit for providing either the clock signal or the second ground voltage to the first node in response to the clock signal, the k-1-th carry signal, and the (k + 1) -th carry signal;
An inverter for providing the clock signal to a second node;
A first node responsive to the k-th carry signal for discharging the second node to the second ground voltage, and responsive to the signal of the second node for discharging the first node to the second ground voltage, A discharge portion;
A second discharging unit for discharging the k-th carry signal to the second ground voltage in response to the signal of the second node; And
And a third discharging unit discharging the k-th gate signal to the first ground voltage in response to the signal of the second node.
6. The method of claim 5,
Wherein the k &lt; th &gt; stage of the plurality of stages comprises:
And a second pull down unit for discharging the k-th carry signal to the second ground voltage in response to the (k + 1) -th carry signal.
3. The method of claim 2,
Wherein the first ground voltage and the second ground voltage are at different voltage levels.
3. The method of claim 2,
Wherein the k &lt; th &gt; stage of the plurality of stages comprises:
A control unit for providing either the clock signal or the second ground voltage to the first node in response to the clock signal, the k-1-th carry signal, and the (k + 1) -th carry signal;
An inverter for providing the clock signal to a second node;
A first discharging unit for discharging the first node and the second node to the second ground voltage in response to the (k-1) th carry signal;
A second discharging unit discharging the kth carry signal to the second grounding voltage in response to the signal of the second node;
A third discharging portion for discharging the kth gate signal to the first grounding voltage in response to the signal of the second node,
And a second pull-down unit for discharging the k-th carry signal to the second ground voltage in response to the (k + 2) -th carry signal.
9. The method of claim 8,
Wherein the k &lt; th &gt; stage of the plurality of stages comprises:
A fourth discharging unit discharging the first node to the second ground voltage in response to the (k + 2) th carry signal; And
And a first pull-down unit for discharging the kth gate signal to the second ground voltage in response to the carry signal in the (k + 2) th carry signal.
10. The method of claim 9,
Wherein the fourth discharging unit comprises:
A first discharge transistor coupled between the first node and the fourth node and including a control electrode coupled to the (k + 2) th carry signal; And
And a second discharge transistor connected between the fourth node and the second ground voltage and including a control electrode coupled to the fourth node.
A display panel including a plurality of pixels each connected to a plurality of gate lines and a plurality of data lines;
A gate driving circuit including a plurality of stages for outputting gate signals to the plurality of gate lines; And
And a data driving circuit driving the plurality of data lines,
Wherein k (k is a positive integer) stage of the plurality of stages includes:
Th stage, a (k + 1) th carry signal from the k + 1 &lt; th &gt; stage, a carry signal from the (k + 2) &lt; th &gt; stage, a first ground voltage and a second ground voltage And outputs a k-th gate signal and a k-th carry signal,
Wherein the clock signal is a pulse signal periodically showing a high voltage and a third ground voltage, and the third ground voltage has a voltage level lower than the first ground voltage and the second ground voltage.
12. The method of claim 11,
In the display panel,
A display region in which the plurality of pixels are arranged; And
And a non-display area adjacent to the display area,
And the gate driving circuit is integrated in the non-display region.
12. The method of claim 11,
Wherein the k &lt; th &gt; stage of the plurality of stages comprises:
outputting the high voltage of the clock signal to the kth gate signal in response to a signal of the first node during a kth clock period and outputting the high voltage of the kth gate signal during a kth And a first output (TR1) for discharging a gate signal to the third ground voltage of the clock signal.
14. The method of claim 13,
Wherein the k &lt; th &gt; stage of the plurality of stages comprises:
And a second output unit for outputting the clock signal as the k-th carry signal in response to the signal of the first node.
14. The method of claim 13,
Wherein the k &lt; th &gt; stage of the plurality of stages comprises:
And a first pull-down unit for discharging the k-th gate signal to the first ground voltage in response to the carry signal in the (k + 1) -th carry signal.
16. The method of claim 15,
Wherein the k &lt; th &gt; stage of the plurality of stages comprises:
A control unit for providing either the clock signal or the second ground voltage to the first node in response to the clock signal, the k-1-th carry signal, and the (k + 1) -th carry signal;
An inverter for providing the clock signal to a second node;
A first node responsive to the k-th carry signal for discharging the second node to the second ground voltage, and responsive to the signal of the second node for discharging the first node to the second ground voltage, A discharge portion;
A second discharging unit discharging the kth carry signal to the second grounding voltage in response to the signal of the second node; And
And a third discharging unit for discharging the kth gate signal to the first ground voltage in response to the signal of the second node.
16. The method of claim 15,
Wherein the k &lt; th &gt; stage of the plurality of stages comprises:
And a second pull-down unit for discharging the k-th carry signal to the second ground voltage in response to the (k + 1) -th carry signal.
12. The method of claim 11,
And a driving circuit for controlling the gate driving circuit and the data driving circuit in response to a control signal and a video signal provided from the outside, and for driving the clock signal, the first ground voltage, the second ground voltage and the third ground voltage Further comprising a controller.
19. The method of claim 18,
The pulses of the clock signal corresponding to the plurality of gate lines, respectively,
Wherein a voltage level of the third ground voltage of each of the pulses of the clock signal corresponds to an order of the pulses in one frame.
20. The method of claim 19,
When the gate signals are sequentially output in the order of stages far from the stage adjacent to the drive controller among the plurality of stages, the voltage level of the third ground voltage of each of the pulses of the clock signal is And gradually decreases in accordance with the order of the pulses.

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