KR20170042204A - Method of forming semiconductor devices including conductive contacts on source/drains - Google Patents

Abstract

Disclosed are methods to form a semiconductor device, including forming a plurality of pin-shaped channels on a substrate, forming a gate structure intersecting the plurality of pin-shaped channels, and forming a source/drain adjacent to one side of the gate structure. According to the present invention, the source/drain is able to intersect the plurality of pin-shaped channels and is able to be electrically connected to the plurality of pin-shaped channels. Moreover, the methods form a metal layer on the upper surface of the source/drain and form a conductive contact on the metal layer facing the source/drain. The conductive contact has a first length in the longitudinal direction of the metal layer and the first length is smaller than a second length of the metal layer in the longitudinal direction of the metal layer.

Description

Methods for forming semiconductor devices, including conductive contacts on source / drains,

The concepts of the present invention generally relate to the field of electronic devices, and more particularly to semiconductor devices.

Parasitic resistance and capacitance can degrade the performance of semiconductor devices. As the scale is reduced, the parasitic resistance and capacitance can be increased and it may be necessary to reduce the parasitic resistance and capacitance for the high performance of the semiconductor devices.

The present invention provides methods for forming semiconductor devices with low parasitic resistance and low parasitic capacitance.

A method of forming a semiconductor device includes forming a plurality of fin-shaped channels on a substrate, forming a gate structure across the plurality of pin-shaped channels, and forming a source / To form a drain. The source / drain may traverse the plurality of pin-shaped channels and may be electrically connected to the plurality of pin-shaped channels. The method may also include forming a metal layer on the upper surface of the source / drain and forming a conductive contact on the metal layer opposite the source / drain. The conductive contact may have a first length along the length of the metal layer and the first length may be less than a second length of the metal layer along the length of the metal layer.

According to various embodiments, forming the metal layer includes forming an insulating layer on the gate structure and the source / drain, forming an opening extending along the insulating layer and exposing at least a portion of the source / And forming the metal layer on the source / drain.

In various embodiments, the second length of the metal layer along the length of the metal layer may be greater than the distance between two adjacent ones of the plurality of pin-shaped channels.

In various embodiments, the insulating layer may comprise a first insulating layer, wherein forming the gate structure includes forming a dummy gate structure across the plurality of fin-shaped channels, Forming a second insulating layer on the sides, and replacing the dummy gate structure with a gate insulating layer and a gate electrode. The gate electrode may comprise a metal.

In various embodiments, the insulating layer may comprise a first insulating layer, wherein forming the conductive contact includes forming a second insulating layer on the metal layer in the opening, Forming a contact opening extending along and exposing the metal layer, and forming the conductive contact in the contact opening.

According to various embodiments, the metal layer may comprise a silicide layer and / or a stacked layer. The stacked layers may include a stack comprising a dielectric layer and a metal layer, or a stack comprising a rare earth or alkaline earth metal layer, a metal layer and a capping layer.

In various embodiments, forming the source / drain and metal layer may include forming the insulating layer on the plurality of fin-shaped channels and the gate structure, extending along the insulating layer, Forming an opening exposing the fin-shaped channels, performing an epitaxial growth process using the plurality of fin-shaped channels exposed by the opening as a seed layer to form the source / drain in the opening, and And forming a metal layer on the source / drain.

A method of forming a semiconductor device includes forming a plurality of fin-shaped channels on a substrate, forming a gate structure across the plurality of fin-shaped channels, forming source / drain regions adjacent to one side of the gate structure Can be formed. The source / drain may traverse a plurality of pin-shaped channels and may be electrically connected to a plurality of pin-shaped channels. The method may also include forming a metal layer on the upper surface of the source / drain and forming a conductive contact on the metal layer opposite the source / drain. The conductive contacts may overlap less vertically than all of the plurality of pin shaped channels.

In various embodiments, the metal layer is vertically superimposed on a first number of the plurality of pin-shaped channels, the first number of the plurality of pin-shaped channels overlapping vertically with the conductive contact, Can be greater than two.

According to various embodiments, the metal layer may vertically overlap with all of the plurality of pin shaped channels.

In various embodiments, forming the metal layer and the conductive contact includes forming a first insulating layer on the gate structure and the source / drain, extending through the first insulating layer and forming the source / Forming an opening to expose, forming the metal layer on the source / drain, forming a second insulating layer on the metal layer in the opening, extending through the second insulating layer, Forming a contact opening exposing the layer, and forming the conductive contact in the contact opening.

According to various embodiments, forming the gate structure includes forming a dummy gate structure across the plurality of fin-shaped channels, forming a third insulating layer on the sides of the dummy gate structure, And replacing the dummy gate structure with a gate insulating layer and a gate electrode. The gate electrode may comprise a metal.

According to various embodiments, the metal layer may comprise a silicide layer and / or a stacked layer. The stacked layers may include a stack comprising a dielectric layer and a metal layer, or a stack comprising a rare earth or alkaline earth metal layer, a metal layer, and a capping layer.

A method of forming a semiconductor device includes forming a plurality of fin-shaped channels on a substrate, forming a gate structure across the plurality of fin-shaped channels, forming source / drain regions adjacent to one side of the gate structure Lt; / RTI > The source / drain may be electrically connected to the plurality of pin-shaped channels across the plurality of pin-shaped channels. The method may also include forming a conductive contact on the upper surface of the source / drain. The conductive contact may have a first length along the length of the source / drain, and the first length may be shorter than the second length of the source / drain along the length of the source / drain.

According to various embodiments, the conductive contact may vertically overlap only a portion of the plurality of pin-shaped channels.

In various embodiments, the method may further comprise forming a metal layer between the source / drain and the conductive contact. The metal layer may have a third length along the length of the source / drain, and the third length may be greater than the first length of the conductive contact.

According to various embodiments, the method may further comprise forming a metal layer between the source / drain and the conductive contact. Forming the metal layer and the conductive contact includes forming a first insulating layer on the gate structure and the source / drain, forming an opening extending along the first insulating layer and exposing the source / drain Forming a metal layer on the source / drain; forming a second insulating layer on the metal layer in the opening; forming a contact opening extending along the second insulating layer and exposing the metal layer; Lt; / RTI > And forming the conductive contact within the contact opening. The conductive contact may be in contact with the metal layer.

According to various embodiments, forming the gate structure includes forming a dummy gate structure across the plurality of fin-shaped channels, forming a third insulating layer on the sides of the dummy gate structure, And replacing the dummy gate structure with the gate insulating layer and the gate electrode. The gate electrode may comprise a metal.

In various embodiments, the metal layer may comprise a silicide layer and / or a stacked layer. The stacked layers may include a stack of dielectric layers and metal layers or a stack comprising a rare earth or alkaline earth metal layer, a metal layer, and a capping layer.

According to the concept of the present invention, the present invention can form semiconductor devices with low parasitic resistance and low parasitic capacitance, and deterioration of the metal layer can be reduced.

1 is a perspective view showing a semiconductor device according to some embodiments of the inventive concepts.
Figure 2 is a flow chart illustrating the process of forming a semiconductor device, in accordance with some embodiments of the concepts of the present invention.
3 is a flow chart illustrating the steps of forming a semiconductor device, in accordance with some embodiments of the concepts of the present invention.
FIGS. 4-8 are perspective views, and FIGS. 9 and 10 are cross-sectional views showing intermediate structures provided in the process of forming a semiconductor device according to some embodiments of the concepts of the present invention.
11 is a flow chart illustrating the steps of forming a semiconductor device according to some embodiments of the inventive concepts.
12 and 13 are perspective views showing intermediate structures provided in the process of forming a semiconductor device according to some embodiments of the concepts of the present invention.
14-17 are perspective views of semiconductor devices according to some embodiments of the concepts of the present invention.
Figures 18 and 19 are block diagrams illustrating examples of electronic systems including semiconductor devices according to some embodiments of the inventive concepts.

Embodiments of the inventive concepts provide methods of forming semiconductor devices with low parasitic resistance and low parasitic capacitance. The methods can include reducing the parasitic resistance by forming a metal layer on the source / drain, and reducing the parasitic capacitance by forming a contact that vertically overlaps only a portion of the metal layer. According to embodiments by the concepts of the present invention, the metal layer can be formed after a high temperature process (e.g., gate replacement process) is completed, so that deterioration of the metal layer can be reduced.

Hereinafter, methods and elements according to embodiments of the concepts of the present invention will be described more specifically with reference to the accompanying drawings. The figures illustrate these methods and exemplary embodiments of semiconductor devices and intermediate structures.

1 is a perspective view showing a semiconductor device according to some embodiments of the inventive concepts. Referring to FIG. 1, a semiconductor device 10 may include a separation layer 110 and pin structures 120 on a substrate 100. The pin structures 120 may extend along a first direction. As shown in FIG. 1, pin structures 120 may be buried in isolation film 110. In some embodiments, the pin structures 120 may protrude above the isolation layer 110. Although four pin structures 120 are shown in FIG. 1, the semiconductor device 10 can be understood to include four or more pin structures 120.

The substrate 100 may be formed of one or more of silicon, germanium, silicon germanium, gallium arsenide, gallium arsenide, silicon carbide, silicon germanium carbide and / Or indium phosphide (InP). The substrate 100 can be, for example, a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The isolation layer 110 may comprise an insulating material such as, for example, silicon oxide. The pin structures 120 may be formed of, for example, silicon, germanium, silicon germanium, gallium arsenide, gallium arsenide, silicon carbide, silicon germanium carbide, ) And / or indium phosphide (InP). The pin structures 120 need not include the same materials as the substrate 100.

The semiconductor device 10 may also include a gate structure 148 on the pin structures 120. The gate structure 148 may extend along a second direction different from the first direction. In some embodiments, the first direction may be perpendicular to the second direction, and each of the first direction and the second direction may be parallel to a plane defined by the lower surface of the substrate 100. The pin structures 120 under the gate structure 148 may provide non-planar channels (e.g., channels in the form of pins). As shown in FIG. 1, the gate structure 148 may have a gate-gated structure formed using, for example, a metal gate replacement process. Gate spacers 134 may be disposed on the sides of gate structure 148.

The gate structure 148 may include a gate insulating layer 140 and a gate electrode 146. The gate electrode 146 may comprise a stack of two layers including first and second gate electrodes 142 and 144. The first gate electrode 142 may be conformally formed on the gate insulating film 140 and the second gate electrode 144 may fill the gap formed by the first gate electrode 142. The first gate electrode 142 may include one of titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), and tantalum carbide (TaC). The second gate electrode 144 may comprise tungsten (W) or aluminum (Al). In some embodiments, the gate electrode 146 may comprise two or more layers.

The source / drain 130 may be formed adjacent the side of the gate structure 148. The source / drain 130 may include an integrated structure (not shown) having a plurality of individual source / drain regions formed on the fin structures 120 and extending beyond the fin structures 120 to contact one another merged structure. The source / drain 130 may traverse the pin structures 120 and may contact the upper surfaces of the pin structures 120. The source / drain 130 may vertically overlap with all of the pin structures 120 (e.g., four pin structures). The expression "one element A" (or similar expressions) that vertically overlaps one element B described herein means that at least one vertical line intersecting elements A and B is perpendicular to the bottom surface of the substrate 100 Can be understood as meaning to do.

The individual source / drain regions of the source / drain 130 may generally have a diamond-shaped cross-section, as shown in Fig. Thus, as described below, the contact area between the source / drain 130 and the metal layer 132 can be increased. The cross section of the portions of the source / drain 130 can be understood to have various shapes.

In some embodiments, the source / drain 130 may include a metal having a resistivity lower than the resisvivity of the metal contained within the pin structures 120, thereby reducing the parasitic resistance of the source / . The reduced parasitic resistance of the source / drain can increase the current delivered to the semiconductor device 10. The source / drain 130 may include, for example, doped Si, silicon germanium (SiGe), or silicon carbide (SiC).

In some embodiments, the source / drain 130 may include a stressor material that increases the channel mobility of the semiconductor device 10, so that the current delivered to the semiconductor device 10 . When the appropriate stress is applied to the channel (such as, for example, including materials with different lattice constants), the mobility of the carriers may be increased and the amount of current delivered to the semiconductor device 10 may be increased. For example, a stressor material having a lattice constant greater than the substrate 100 of the P-type transistor (e.g., silicon germanium when the substrate 100 is silicon) may apply compressive stress to the channel of the P-type transistor , The current can be increased. A stressor material having a lattice constant that is less than the lattice constant of the substrate 100 of the N-type transistor (e.g., silicon carbide when the substrate 100 is silicon) can apply tensile stress to the channel of the N-type transistor , The current can be increased.

The semiconductor device 10 may include a metal layer 132 on the source / drain 130. The metal layer 132 may contact the upper surface of the source / drain 130. The metal layer may extend in a second direction and may vertically overlap with all (e.g., four pin structures) of pin structures 120, as shown in FIG. In some embodiments, the metal layer 132 may have a length along the second direction, and the length may be similar or substantially equal to the length of the source / drain 130 along the second direction. In some embodiments, the length of the metal layer 132 along the second direction may be less than the length along the second direction of the source / drain 130.

The thickness of the metal layer 132 may be determined in consideration of parasitic capacitance and parasitic resistance. It can be seen that as the thickness of the metal layer 132 is increased, the parasitic capacitance between the source / drain 130 and the gate structure 148 is increased. Further, it can be understood that as the thickness of the metal layer 132 is reduced, the sheet resistance of the source / drain 130 is increased. In some embodiments, metal layer 132 may be a reacted metal-semiconductor compound layer formed by reaction of a metal with a material contained in a silicide layer or source / drain 130. As an example, the metal layer 132 may be formed of a material selected from the group consisting of nickel-silicon-germanium (NiSi (Ge), titanium germanium-silicide, nickel- Carbide alloys, Ti-Si alloys, Ni-semiconductor alloys, Ni-Pt-semiconductor alloys, Co-semiconductor alloys, alloys or Ta-semiconductor alloys. The thickness of the silicide layer may be less than about 20 [nm], and the sheet resistance may be less than about 40 [ohm / sq].

In some embodiments, the metal layer 132 is a stack stack of layers (including the top surface of the source / drain 130) of layers comprising an insulating layer and a metal layer, forming a metal-insulator-semiconductor (MIS) can do. The insulating layer of the MIS contact may comprise, by way of example, titanium oxide (TiOx) or zinc oxide (ZnO), and may have a thickness of about 1 [nm]. The metal layer of the MIS contact can be made of a metal such as nickel, titanium, tantalum, tantalum nitride, titanium nitride, titanium carbide, tungsten, And may include titanium (TiAl), ruthenium (Ru), aluminum (Al), lanthanum (La), cobalt (Co), platinum (Pt), palladium (Pd), molybdenum (Mo) In some embodiments, when the gate structure 148 is the gate of an N-type transistor, the metal layer 132 may be an interfacial layer, a low resistance layer (e.g., a titanium film), and a capping layer Titanium layer). ≪ / RTI > The interface layer may comprise a thin rare earth or alkaline earth metal layer. The capping layer can reduce or prevent oxidation of the low resistance layer.

The semiconductor device 10 may include a contact 150 on the metal layer 132. The contact 150 may contact the metal layer 132. The contact 150 may be either vertically overlapped with any one of the pin structures 120 or less than one or more of the pin structures 120 under the source / They can be superimposed vertically. Thus, the contact 150 has a length along the second direction, which may be shorter than the length of the metal layer 132 along the second direction. Although the contact 150 is illustrated in FIG. 1 as providing the contact 150 on the source / drain 130 of the edge portion of the source / drain 130 along the second direction, Drain 130, as shown in FIG. The contact 150 may comprise, by way of example, a semiconductor material and / or a metal. The metal may be at least one selected from the group consisting of nickel (Ni), titanium (Ta), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium carbide (TiC), tungsten (W), aluminum titanium , Aluminum (Al), lanthanum (La), cobalt (Co), platinum (Pt), palladium (Pd), molybdenum (Mo) or alloys thereof. An insulating layer (not shown) may be formed on the upper surface of the source / drain 130, metal layer 132, and the contact 150 may penetrate the insulating layer.

Although Figure 1 illustrates source / drain 130, metal layer 132 and contact 150 formed on one side of gate structure 148, source / drain 130, metal layer 132, And contact 150 may be formed on both sides of gate structure 148. [ 1, the semiconductor device 10 may also be formed on the source / drain 130 and the gate structure 148 to form insulating layers surrounding the contact 150 (e.g., 1, second, and third insulating layers 152, 154, 156). The insulating layers may expose the top surface of the contact 150.

Figure 2 is a flow chart illustrating the process of forming a semiconductor device, in accordance with some embodiments of the concepts of the present invention. Referring to FIG. 2, the processes may include forming pin-shaped channels on the substrate (block 100) and forming the source / drain (block 200). The processes may further include forming a metal gate structure on the fin shaped channels (block 300) and forming a metal layer on the source / drain (block 400). The processes may further include forming an insulating layer on the metal layer (block 500) and forming a contact in the insulating layer (block 600).

Figure 3 is a flow chart illustrating the process of forming a semiconductor device, in accordance with some embodiments of the inventive concepts. FIGS. 4-8 are perspective views, and FIGS. 9 and 10 are cross-sectional views showing intermediate structures provided in the process of forming a semiconductor device according to some embodiments of the concepts of the present invention.

Referring to FIGS. 3 and 4, preliminary pin structures 120P may be formed on the substrate 100 (block 100). The spare pin structures 120P may be provided spaced apart from each other, each of which may be provided in a line shape. A separation layer 110 may be formed on the substrate 100. A dummy gate structure 145 may be formed on the preliminary pin structures 120P and isolation layer 110 (block 110). Portions of the preliminary pin structures 120P under the dummy gate structure 145 may provide finned channels. The dummy gate structure 145 may extend in a direction different from the direction in which the spare pin structures 120P extend. The dummy gate structure 145 may include a dummy gate insulating layer 141 and a dummy gate electrode 143. The dummy gate insulating layer 141 may include silicon oxide, and the dummy gate electrode 143 may include polysilicon. Gate spacers 134 may be formed in each of the sides of the dummy gate structure 145. Gate spacers 134 may be provided by forming a spacer layer and then performing an etch process. The gate spacers 134 may comprise silicon nitride, aluminum nitride, silicon oxynitride, or silicon carbide.

Referring to FIGS. 3 and 5, the upper portions of the pre-fin structures 120P exposed by the dummy gate structure 145 may be selectively removed to form the pin structures 120. Referring to FIG. The regions exposed by the dummy gate structure 145 may be understood as source / drain regions. The upper portions of the spare fin structures 120P may be removed by any suitable etching process. The top surfaces of the pin structures 120 of the source / drain regions may be at substantially the same level as the top surface of the isolation layer 110. In some embodiments, the top surfaces of the pin structures 120 of the source / drain regions may be at a different level than the top surface of the isolation layer 110. In one example, the top surfaces of the pin structures 120 may be lower than the top surface of the isolation layer 110.

A source / drain 130 may be formed on the pin structures 120 (block 200). The source / drain 130 may be formed using an epitaxial growth process with the fin structures 120 as seed layers. The epitaxial growth process may proceed until the individual source / drain regions grown from the respective pin structures 120 are merged with each other and epitaxially grown to form a single structure. The source / drain 130 may comprise, for example, doped Si, silicon germanium (SiGe), or silicon carbide (SiC).

Referring to FIG. 6, a first insulating layer 152 may be formed on the structure shown in FIG. 5 (block 210). The first insulating layer 152 may be formed by depositing and planarizing an insulating layer. The first insulating layer 152 may expose the upper surface of the dummy gate electrode 143.

3 and 7, in one example, using the metal gate replacement process, the dummy gate insulating layer 141 and the dummy gate electrode 143 may be replaced by a gate insulating layer 140 and a gate electrode 146 And may form a gate structure 148 (block 300). The dummy gate insulating layer 141 and the dummy gate electrode 143 can be removed by any suitable etching process, wet and / or dry etch process, and the trench defined by the opposing sidewalls of the gate spacers 134 . Thereafter, the gate insulating layer 140 and the gate electrode 146 may be formed in the trench.

The gate insulating layer 140 may comprise an insulating material such as, for example, silicon dioxide. In some embodiments, the gate insulating layer 140 has a higher dielectric constant than a silicon oxide film such as, for example, hafnium oxide (HfO2), lanthanum oxide (La2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2O5) May include a high dielectric constant material having a high dielectric constant. The gate insulating layer 140 may be formed conformally on the sidewalls and bottom surface of the trench, and may be formed using, for example, an atomic layer deposition (ALD) method. The gate electrode 146 may include first and second gate electrodes 142 and 144. The first gate electrode 142 may be conformally formed on the gate insulating layer 140 and the second gate electrode 144 may fill the space formed by the first gate electrode 142. The first gate electrode 142 may include any one of titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), and tantalum carbide (TaC). The second electrode 144 may include tungsten (W) or aluminum (Al).

Referring to FIGS. 3 and 8, a second insulating layer 154 may be formed on the first insulating layer 152 and the gate structure 148 (block 310). The portions of the first and second insulating layers 152 and 154 are etched until the source / drain 130 is exposed so that the opening 132T is formed in the first and second insulating layers 152 and 154 (Block 320). The opening 132T may be provided in a line shape and the length of the opening 132T along the second direction may be greater than the distance between adjacent pin structures 120 along the second direction. In some embodiments, the opening 132T may be provided in a line shape and the length of the opening 132T along the second direction may be similar or substantially equal to the length of the source / drain 130 along the second direction can do. The opening 132T may expose the upper surface of the source / drain 130.

Referring to FIGS. 3 and 9, a metal layer 132 may be formed on the upper surface of the source / drain 130 exposed by the opening 132T (block 400). The metal layer 132 may be a stacked layer comprising a silicide layer or a metal layer. In some embodiments, the metal layer 132 may be a silicide layer and may be formed by a self-aligning process. The self-aligning process may include forming a thin metal layer on the structures (including the top surface of the source / drain 130) shown in FIG. Thereafter, the thin metal layer may thermally react with the source / drain 130 to form a metal semiconductor compound film. A portion of the unreacted metal layer can be selectively removed.

According to some embodiments of the inventive concept, deterioration of the silicide layer in the metal layer 132 may be reduced since the metal layer 132 is formed after the gate electrode 146 is formed. Metal gate replacement processes require high temperature processes. The high temperature process can result in severe degradation of the silicide layer (e.g., agglomeration resulting in the formation of a discontinuous layer) and can result in high sheet resistance. According to some embodiments, the metal gate replacement process may be performed prior to forming the metal layer 132, and the metal layer 132 may be formed using metals having low thermal stability.

In some embodiments, the metal layer 132 may comprise a metal layer formed by a directional deposition process (e.g., a PVD process). The metal layer 132 on the sidewalls of the opening 132T may then be removed so that a metal layer is left at the bottom of the opening 132T. Using a directional deposition process, the metal layer deposited underneath opening 132T may be thicker than the metal layer deposited on the sidewalls of opening 132T. Thus, the metal layer on the sidewall of the opening 132T can be completely removed while a portion of the metal layer under the opening 132T remains.

Referring to FIGS. 3 and 10, a third insulating layer 156 may be formed in the opening 132T (block 500-1). The third insulating layer 156 may fill the opening 132T. A contact 150 may be formed in the third insulating layer 156 (block 600-1). Forming the contact 150 can include forming a contact opening in the third insulating layer 156 and forming conductive materials within the contact opening. The contact 150 may extend along the third insulating layer 156 and the metal layer 132 may contact.

11 is a flow chart illustrating the steps of forming a semiconductor device according to some embodiments of the inventive concepts. 12 and 13 are perspective views showing intermediate structures provided in the process of forming a semiconductor device according to some embodiments of the concepts of the present invention.

11 and 12, preliminary pin structures 120P and dummy gate structure 145 may be formed on the substrate shown in FIG. 4 (blocks 100 and 110). A first insulating layer 152 may be formed on the structure shown in FIG. 4 (block 210).

11 and 13, the dummy gate insulating layer 141 and the dummy gate electrode 143 may be replaced with a gate insulating layer 140 and a gate electrode 146 to form a gate structure (block 300 ). A second insulating layer 154 may be formed on the first insulating layer 152 and the gate structure 148 (block 310). Portions of the first and second insulating layers 152 and 154 may be etched to form openings 132T in the first and second insulating layers 152 and 154 (block 320). The opening 132T may expose the upper surfaces of the preliminary pin structures 120P. The opening 132T may be line-shaped.

By removing the upper portions of the pre-fin structures 120P exposed by the opening 132T, the pin structures 120 can be formed. A source / drain 130 may be formed on the pin structures 120 (block 200). A metal layer 132 may be formed on the upper surface of the source / drain 130 (block 400). The final structure may be the same as the structure of FIG.

Referring again to FIG. 10, a third insulating layer 156 may be formed within the opening 132T (block 500-1). The third insulating layer 156 may fill the opening 132T. A contact 150 may be formed in the third insulating layer 156 (block 600-1). The contact 150 may extend through the third insulating layer 156 and may contact the metal layer 132.

14-17 are perspective views of semiconductor devices according to some embodiments of the concepts of the present invention.

14, the semiconductor device 20 may have a structure similar to the semiconductor device 10 of FIG. 1 except for the contact 150-1. As shown in FIG. 14, the contact 150-1 may vertically overlap the two pin structures 120 under the source / drain 130.

15, a semiconductor device 30 includes a plurality of contacts 150 that vertically overlap a portion of the isolation layer 110 between the portions of the two pin structures 120 and the two pin structures 120 -2).

As shown in FIG. 16, the semiconductor device 40 may include two contacts 150 and 150-3. The two contacts 150 and 150-3 may have other shapes (e.g., shapes having different widths in a first direction or a second direction).

In some embodiments, the semiconductor device 50 is vertically stacked with one or more fin structures 120 and has a first direction that is greater than the width of the metal layer 132 along the first direction as shown in FIG. And may include a contact 150-4 having a small width.

Although not shown in Figures 14-17, the semiconductor devices 20,30, 40,50 are also formed on the source / drain 130 and the gate structure 148 and the contacts 150-1, 150-2, 150- (E.g., first, second, and third insulating layers 152, 154, 156 of FIG. 10) surrounding the first, second, and third insulating layers 3, 150-4. The insulating layers may expose the top surfaces of the contacts 150-1, 150-2, 150-3, and 150-4.

18 is a block diagram illustrating an example of an electronic system including a semiconductor device according to some embodiments of the concepts of the present invention. 18, the electronic system 1100 may include a controller 1110, an input / output circuit 1120, a memory element 1130, an interface circuit 1140, and a data bus 1150. The controller 1110, the input / output circuit 1120, the memory element 1130, and the interface circuit 1140 can communicate with each other via the data bus 1150. The data bus 1150 may correspond to a path through which electrical signals are transmitted. The controller 1110, the input / output circuit 1120, the memory element 1130, and / or the interface circuit 1140 may include semiconductor devices according to some embodiments of the inventive concepts.

The controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller, or another logic device. Another logic element may have a similar function to either a microprocessor, a digital signal processor, or a microcontroller. The input / output circuit 1120 may include a keypad, a keyboard, and / or a display unit. Memory element 1130 may store data and / or instructions. The interface circuit 1140 can transmit electrical data to the communication network and receive electrical data from the communication network. The interface circuit 1140 may operate over the air or cable. In one example, the interface circuit 1140 may comprise an antenna for wireless communication or a transceiver for cable communication. The electronic system 1100 may further include a fast DRAM device and / or a fast ES RAM device that functions as a cache memory to enhance the operation of the controller 1110.

The electronic system 1100 may be provided in a personal digital assistant (PDA), a mobile computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card, or other electronic products. Other electronic products can receive and transmit information wirelessly.

19 is a block diagram illustrating an example of an electronic system including semiconductor devices according to some embodiments of the inventive concepts. Referring to FIG. 19, electronic system 1200 may include at least one of the semiconductor devices according to some embodiments of the inventive concepts. The electronic system 1200 may include a mobile device or a computer. In one example, electronic system 1200 includes a memory system 1210, a processor 1220, a random access memory (RAM) element 1230, and a user interface unit 1240, Communication can be performed. The processor 1220 may execute the program and control the electronic system 1200. The RAM device 1230 may be used as an operational memory. In one example, the processor 1220 and the RAM element 1230 may each comprise semiconductor elements according to some embodiments of the inventive concepts. Alternatively, the processor 1220 and the RAM device 1230 may be included in a single package. The user interface unit 1240 can be used to input data to and output data from the electronic system 1200. Memory system 1210 may store code for operation of processor 1220 or data generated by processor 1220 or data output from an external system. Memory system 1210 may include a controller and a memory device.

The electronic system 1200 may be used as a mobile system, a personal computer, an industrial computer, or logic systems that perform various functions. As an example, the mobile system may be one of a personal digital assistant (PDA), a mobile computer, a web tablet, a mobile phone, a wireless phone, a laptop computer, a memory card, a digital music player, and information transmission / reception systems. When the electronic system 1100 performs wireless communications, the electronic system 1100 can be used as a communication interface protocol for third generation communication systems such as CDMA, GSM, NADC, E-TDMA, WCDMA, or CDMA 200.

BRIEF DESCRIPTION OF THE DRAWINGS To the best of our knowledge, embodiments in accordance with the concepts of the present invention have been described with reference to the drawings and accompanying drawings, which illustrate exemplary embodiments. The inventive concepts, however, may be embodied in various other forms, and are not limited to the embodiments described herein. On the contrary, the embodiments can provide the concept of the present invention completely, and the scope of the invention can be fully conveyed to those skilled in the art. The elements described through the drawings and specification may be referred to by way of reference numerals. The expression "and / or" used herein may include one or more combinations of items in the associated list.

It is to be understood that the first, second, and other terms are used herein to describe various elements, but such elements are not limited to these terms. These terms are only used to distinguish one element from another. In one example, the first element can be used as the second element, and likewise, the second element can be used as the first element, without being limited by the scope of the concepts of the present invention.

In the specification, when an element is referred to as being "coupled" or "connected" or "phase" to another element, an element can be directly coupled to, coupled to, Or intermediate elements. Alternatively, when an element is described as being "directly coupled" or "directly connected" or "directly on" another element, the intermediate element may not be involved. Other words used to describe the relationship between elements should be interpreted in the same way (eg, "directly in between" versus "between", "directly adjacent" versus "adjacent", etc.) )

Relative terms such as "below" or "above" or "upper" or " lower " or "horizontal" or "vertical" Can be used to describe the relationship with the region. It will be appreciated that these terms, in addition to the orientations shown in the Figures, are intended to include other orientations of the semiconductor device.

The terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the invention. The singular terms used herein may be considered to include plural forms unless the context clearly indicates otherwise. The terms "comprise," "comprise," "includes," and / or "including," as used in the specification, may be understood to be descriptive of the stated features, elements, and / , But does not limit the presence or addition of one or more other features, elements, components, and / or groups thereof.

Embodiments of the concepts of the present invention are described herein with reference to schematic perspective views and cross-sectional views of ideal embodiments (and intermediate structures) of the inventive concepts. The thicknesses of the layers and regions of the figures may be exaggerated for clarity. In addition, variations from the shapes of the figures, e.g., manufacturing methods and / or tolerances, can be expected. Accordingly, embodiments of the present invention are not to be construed as limited to the specific features described herein, and may include various variations thereof, e.g., a manufacturing process.

The functions / operations described in the flowchart blocks may be understood to include some optional completions, leaving the order described in the flow chart. In one example, two blocks shown in succession may in fact be performed substantially concurrently, and the sequences may be performed inversely according to their associated functions / operations. In addition, the functions and / or block diagrams of a given block of flowcharts can be divided into functions and / or block diagrams of a plurality of blocks and / or two or more blocks of flowcharts, have. As a result, other blocks may be added or inserted between the illustrated blocks, and blocks / operations may be omitted as long as they are not limited within the scope of the inventive concepts.

As understood in its entirety, the elements and methods of forming elements in accordance with various embodiments described herein may include microelectronic components such as integrated circuits. A plurality of elements in accordance with various embodiments described herein may be integrated into the same microelectronic device. Thus, the perspective view (s) and section (s) depicted herein may be simulated along two directions, and in a microelectronic device, the two directions need not be perpendicular to each other. Thus, in a top view of a microelectronic device, elements in accordance with various embodiments described herein may include a two-dimensional pattern based on the functionality of a plurality of elements and / or microelectronic elements comprising the array .

Devices according to various embodiments described herein may be disposed between other devices depending on the functionality of the microelectronic device. In addition, the microelectronic devices according to the various embodiments described herein can be simulated along a third direction perpendicular to two different directions, thereby providing three-dimensional integrated circuits.

Thus, the perspective (s) and section (s) described herein can support a plurality of elements described herein. For example, it may be a structure extending in two different directions when viewed in a plane and / or a structure extending in three different directions in terms of perspective. In one example, a single source / drain, device / structure depicted in a cross-sectional view of a device / structure includes a plurality of source / drains and transistor structures (or memory cell structures, gate structures, / RTI > can be shown in plan view of the device / structure.

All embodiments may be combined in any manner and / or combination.

In the drawings and specification, there have been disclosed typical embodiments in accordance with the concepts of the present invention, and although specific terms are employed, they are used for generic and specific purposes only and are not intended to limit the purpose or intent of the invention, Can basically be set by the claims that follow.

Claims (20)

A method of forming a semiconductor device comprising:
Forming a plurality of fin-shaped channels on the substrate;
Forming a gate structure across the plurality of fin-shaped channels;
Forming a source / drain adjacent to one side of the gate structure;
Forming a metal layer on the upper surface of the source / drain; And
Forming a conductive contact on the metal layer opposite the source / drain,
Wherein the source / drain traverses the plurality of pin-shaped channels and is electrically connected to the plurality of pin-shaped channels,
Wherein the conductive contact has a first length along a longitudinal direction of the metal layer and the first length is less than a second length of the metal layer along the longitudinal direction of the metal layer.
The method according to claim 1,
The metal layer is formed by:
Forming an insulating layer on the gate structure and the source / drain;
Forming an opening through the insulating layer and exposing at least a portion of the source / drain; And
And forming the metal layer on the source / drain.
3. The method of claim 2,
Wherein the second length of the metal layer along the longitudinal direction of the metal layer is greater than the distance between two adjacent ones of the plurality of pinned channels.
3. The method of claim 2,
Wherein the insulating layer includes a first insulating layer,
The gate structure is formed by:
Forming a dummy gate structure across the plurality of fin-shaped channels;
Forming a second insulating layer on the sides of the dummy gate structure; And
And replacing the dummy gate structure with a gate insulating layer and a gate electrode, wherein the gate electrode comprises a metal.
3. The method of claim 2,
Wherein the insulating layer includes a first insulating layer,
Forming the conductive contact comprises:
Forming a second insulating layer on the metal layer in the opening;
Forming a contact opening through the second insulating layer and exposing the metal layer; And
And forming the conductive contact within the contact opening.
The method according to claim 1,
The metal layer comprises a stack of silicide layers and / or layers,
Wherein the stack of layers comprises a stack comprising an insulating layer and a metal layer, or a stack comprising a rare earth or alkaline earth metal layer, a metal layer and a capping layer.
The method according to claim 1,
Forming the source / drain and the metal layer comprises:
Forming an insulating layer on the plurality of fin-shaped channels and the gate structure;
Forming an opening through the insulating layer and exposing the plurality of fin-shaped channels;
Performing an epitaxial growth process using the plurality of fin-shaped channels exposed by the opening as a seed layer to form a source / drain in the opening; And
And forming the metal layer on the source / drain.
A method of forming a semiconductor device comprising:
Forming a plurality of fin-shaped channels on the substrate;
Forming a gate structure across the plurality of fin-shaped channels;
Forming a source / drain adjacent to one side of the gate structure;
Forming a metal layer on the upper surface of the source / drain; And
Forming a conductive contact on the metal layer opposite the source / drain,
Wherein the source / drain traverses the plurality of pin-shaped channels and is electrically connected to the plurality of pin-shaped channels, the conductive contacts overlapping less vertically than all of the plurality of pin-shaped channels.
9. The method of claim 8,
Wherein the metal layer is vertically superimposed on a first number of the plurality of pinned channels and the first number is greater than a second number of the plurality of pinned channels vertically overlapping the conductive contact.
10. The method of claim 9,
Wherein the metal layer is vertically overlapped with all of the plurality of pin-shaped channels.
9. The method of claim 8,
Wherein the conductive contact is vertically overlapped with only a portion of the metal layer along the length of the metal layer.
9. The method of claim 8,
The metal layer and the conductive contact are formed by:
Forming a first insulating layer on the gate structure and the source / drain;
Forming an opening through the first insulating layer and exposing the source / drain;
Forming the metal layer on the source / drain;
Forming a second insulating layer on the metal layer in the opening;
Forming a contact opening through the second insulating layer and exposing the metal layer; And
And forming the conductive contact within the contact opening.
13. The method of claim 12,
The gate structure is formed by:
Forming a dummy gate structure across the plurality of fin-shaped channels;
Forming a third insulating layer on the sides of the dummy gate structure; And
And replacing the dummy gate structure with a gate insulating layer and a gate electrode, wherein the gate electrode comprises a metal.
9. The method of claim 8,
The metal layer comprises a stack of silicide layers and / or layers,
Wherein the stack of layers comprises a stack comprising an insulating layer and a metal layer, or a stack comprising a rare earth or alkaline earth metal layer, a metal layer, and a capping layer.
A method of forming a semiconductor device comprising:
Forming a plurality of fin-shaped channels on the substrate;
Forming a gate structure across the plurality of fin-shaped channels;
Forming a source / drain adjacent to one side of the gate structure;
Forming a conductive contact on the upper surface of the source / drain,
Wherein the source / drain traverses the plurality of pin-shaped channels and is electrically connected to the plurality of pin-shaped channels,
Wherein the conductive contact has a first length along the length of the source / drain and the first length is less than the second length of the source / drain along the length of the source / drain.
16. The method of claim 15,
Wherein the conductive contact vertically overlaps only a portion of the plurality of pin-shaped channels.
16. The method of claim 15,
Further comprising forming a metal layer between the source / drain and the conductive contact,
Wherein the metal layer has a third length along the length of the source / drain and the third length is greater than the first length of the conductive contact.
16. The method of claim 15,
Further comprising forming a metal layer between the source / drain and the conductive contact,
The metal layer and the conductive contact are formed by:
Forming a first insulating layer on the gate structure and the source / drain;
Forming an opening through the first insulating layer and exposing the source / drain;
Forming the metal layer on the source / drain;
Forming a second insulating layer on the metal layer in the opening;
Forming a contact opening through the second insulating layer and exposing the metal layer; And
And forming the conductive contact within the contact opening, wherein the conductive contact is in contact with the metal layer.
19. The method of claim 18,
The gate structure is formed by:
Forming a dummy gate structure across the plurality of fin-shaped channels;
Forming a third insulating layer on the sides of the dummy gate structure; And
And replacing the dummy gate structure with the gate insulating layer and the gate electrode, wherein the gate electrode comprises a metal.
16. The method of claim 15,
The metal layer comprises a stack of silicide layers and / or layers,
Wherein the stack of layers comprises a stack of a dielectric layer and a metal layer, or a stack comprising a rare earth or alkaline earth metal layer, a metal layer, and a capping layer.

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