KR20190038282A - Method of manufacturing a semiconductor device and a semiconductor device - Google Patents

Abstract

The present invention relates to a manufacturing method of a semiconductor device and a semiconductor device. The manufacturing method of a semiconductor device comprises the steps of: forming a first semiconductor layer having a first composition over a semiconductor substrate; and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, the second semiconductor layer, and the third semiconductor layer are patterned to form a fin structure. A part of the third semiconductor layer is removed thereby forming a nanowire including the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, the second semiconductor layer, and the third semiconductor layer include different materials.

Description

Technical Field [0001] The present invention relates to a method of manufacturing a semiconductor device,

This application claims priority of U.S. Provisional Patent Application No. 62 / 565,339, filed September 29, 2017, the entire contents of which are incorporated herein by reference.

The present disclosure relates to a method of fabricating semiconductor integrated circuits, and more particularly to a method of fabricating semiconductor integrated circuits, and more particularly to a method of fabricating semiconductor integrated circuits, And semiconductor devices. ≪ RTI ID = 0.0 > [0002] < / RTI >

As the semiconductor industry moves to nanometer technology process nodes in pursuit of higher device density, higher performance, and lower cost, the challenges from both manufacturing and design issues are addressed by the use of finFETs and gate- Have led to the development of three-dimensional designs such as multi-gate field effect transistors (FETs) that include all-around (GAA) FETs. In FinFETs, the gate electrode is adjacent to three sides of the channel region, and a gate dielectric layer is interposed therebetween. Because the gate structure surrounds the pin on three sides, the transistor essentially has three gates that control the current through the pin or channel region. Unfortunately, on the fourth side, the bottom portion of the channel is remote from the gate electrode and is therefore not under closed gate control. In contrast, in a GAA FET, all sides of the channel region are surrounded by a gate electrode, which allows a more complete depletion in the channel region, a more abrupt threshold current swing (SS) and a smaller drain induced barrier degradation (DIBL, drain induced barrier lowering). As transistor dimensions continue to shrink to technology nodes below 10-15 nm, further improvements in GAA FETs are required.

The present disclosure is best understood by reading the following detailed description in conjunction with the accompanying drawings. In accordance with standard practice in the industry, it is emphasized that the various features are not drawn to scale and are used for illustrative purposes only. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.
Figure 1 shows an isometric view of a GAA FET semiconductor device showing one of the stages of the manufacturing process according to an embodiment of the present disclosure.
Figure 2 shows a cross-sectional view of one of the various stages of fabricating a semiconductor FET device in accordance with embodiments of the present disclosure.
Figure 3 shows a cross-sectional view of one of the various stages of fabricating a semiconductor FET device according to embodiments of the present disclosure.
Figure 4 shows a cross-sectional view of one of the various stages of fabricating a semiconductor FET device in accordance with embodiments of the present disclosure.
Figure 5 shows a cross-sectional view of one of the various stages of fabricating a semiconductor FET device in accordance with embodiments of the present disclosure.
Figures 6A, 6B, and 6C show cross-sectional views of stages of various stages for fabricating semiconductor FET devices in accordance with embodiments of the present disclosure.
Figure 7 shows a cross-sectional view of one of the various stages of fabricating a semiconductor FET device according to embodiments of the present disclosure.
Figure 8 shows a cross-sectional view of one of the various stages of fabricating a semiconductor FET device according to embodiments of the present disclosure.
Figure 9 shows a cross-sectional view of one of the various stages of fabricating a semiconductor FET device in accordance with embodiments of the present disclosure.
Figures 9A, 9B and 9C show one of the various stages of fabricating a semiconductor FET device according to embodiments of the present disclosure. 10A is a cross-sectional view taken along the gate electrode in the X-direction (line AA in FIG. 1). 10B is a cross-sectional view taken along the pin structure in the Y-direction (line BB in FIG. 1).
11A-11D illustrate one of the various stages of fabricating a semiconductor FET device according to embodiments of the present disclosure. 11A is a cross-sectional view taken along the gate electrode in the X-direction (line AA in FIG. 1). 11B is a cross-sectional view taken along the pin structure in the Y-direction (line BB in FIG. 1). 11C is a cross-sectional view taken along the line CC of FIG. 11D is a cross-sectional view taken along line DD of FIG.
12A-12D illustrate one of the various stages of fabricating a semiconductor FET device according to embodiments of the present disclosure. 12A is a cross-sectional view taken along the gate electrode in the X-direction (line AA in FIG. 1). 12B is a cross-sectional view taken along the pin structure in the Y-direction (line BB in FIG. 1). 12C is a cross-sectional view taken along line CC of FIG. 12D is a cross-sectional view taken along the line DD of FIG. Figure 12E is a cross-sectional view taken along line BB of Figure 1 of yet another embodiment.
13A-13D show one of the various stages of fabricating a semiconductor FET device according to embodiments of the present disclosure. 13A is a cross-sectional view taken along the gate electrode in the X-direction (line AA in FIG. 1). 13B is a cross-sectional view taken along the pin structure in the Y-direction (line BB in FIG. 1). 13C is a cross-sectional view taken along the line CC of FIG. 13D is a cross-sectional view taken along the line DD of FIG. FIG. 13E is a cross-sectional view taken along line CC of FIG. 1, and FIG. 13F is a cross-sectional view taken along line BB of FIG. 1 of still another embodiment.
14A-14D show one of the various stages of fabricating a semiconductor FET device according to embodiments of the present disclosure. 14A is a cross-sectional view taken along the gate electrode in the X-direction (line AA in FIG. 1). 14B is a cross-sectional view taken along the pin structure in the Y-direction (line BB in FIG. 1). Fig. 14C is a cross-sectional view taken along line CC of Fig. 14D is a cross-sectional view taken along the line DD of FIG. FIG. 14E is a cross-sectional view taken along line CC of FIG. 1, and FIG. 14F is a cross-sectional view taken along line BB of FIG. 1 of still another embodiment.
15A-15D show one of the various stages of fabricating a semiconductor FET device according to embodiments of the present disclosure. 15A is a cross-sectional view taken along the gate electrode in the X-direction (line AA in FIG. 1). 15B is a cross-sectional view taken along the fin structure in the Y-direction (line BB in FIG. 1). 15C is a cross-sectional view taken along line CC of FIG. 15D is a cross-sectional view taken along line DD of FIG. FIG. 15E is a cross-sectional view taken along line CC of FIG. 1, and FIG. 15F is a cross-sectional view taken along line BB of FIG. 1 of still another embodiment. 15G is a detailed cross-sectional view of the pin structure of FIG. 15A.
16A-16D show one of the various stages of fabricating a semiconductor FET device according to embodiments of the present disclosure. 16A is a cross-sectional view taken along the gate electrode in the X-direction (line AA in FIG. 1). 16B is a cross-sectional view taken along the pin structure in the Y-direction (line BB in FIG. 1). 16C is a cross-sectional view taken along line CC of FIG. 16D is a cross-sectional view taken along the line DD of FIG. FIG. 16E is a cross-sectional view taken along line CC of FIG. 1, and FIG. 16F is a cross-sectional view taken along line BB of FIG. 1 of still another embodiment.
17A-17D illustrate one of the various stages of fabricating a semiconductor FET device according to embodiments of the present disclosure. 17A is a cross-sectional view taken along the gate electrode in the X-direction (line AA in FIG. 1). 17B is a cross-sectional view taken along the pin structure in the Y-direction (line BB in FIG. 1). Fig. 17C is a cross-sectional view taken along line CC of Fig. 17D is a cross-sectional view taken along line DD of FIG. FIG. 17E is a cross-sectional view taken along line CC of FIG. 1, and FIG. 17F is a cross-sectional view taken along line BB of FIG. 1 of still another embodiment.
18A-18D show one of the various stages of fabricating a semiconductor FET device according to embodiments of the present disclosure. 18A is a cross-sectional view taken along the gate electrode in the X-direction (line AA in FIG. 1). 18B is a cross-sectional view taken along the pin structure in the Y-direction (line BB in FIG. 1). 18C is a cross-sectional view taken along the line CC of FIG. 18D is a cross-sectional view taken along line DD of FIG. FIG. 18E is a cross-sectional view taken along line CC of FIG. 1, and FIG. 18F is a cross-sectional view taken along line BB of FIG. 1 of still another embodiment.

It should be understood that the following inventions provide many different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely illustrative, and not intended to be limiting. For example, the dimensions of the elements are not limited to the ranges or values disclosed, but may depend on the process conditions and / or the desired characteristics of the device. In addition, the formation of the first feature on the second feature or on the second feature in the following description may include embodiments in which the first feature and the second feature are formed in direct contact, And embodiments in which additional features may be formed interposing between the first feature and the second feature such that the second feature may not be in direct contact. The various features may be optionally shown at different scales for simplicity and clarity.

Also, spatially relative terms such as "under", "under", "under", "above", "above" and the like refer to one element Element or feature may be used herein for ease of description. Spatially relative terms are intended to include different orientations of the device upon use or operation in addition to the orientations shown in the Figures. The device may be oriented in other ways (which may be rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly. In this specification, the phrase "one of A, B, and C" refers to "A, B, and / or C Means one element from A, one element from B (A, B, C, A and B; A and C; B and C; or A, B and C) , But does not mean one element from C.

In this disclosure, a method for fabricating a GAA FET and a stacked channel FET is provided. Note that in this disclosure, the source and the drain are used interchangeably and the structure is substantially the same.

Figure 1 shows an isometric view of a GAA FET semiconductor device showing one of the stages of the manufacturing process according to an embodiment of the present disclosure. One or more gate electrodes 100 extending in the X-direction are disposed on one or more pin structures 35 extending in the Y-direction. The X-direction is substantially perpendicular to the Y-direction. The pin structures 35 are formed on the semiconductor substrate 10. The lower portion of the fin structure 35 is embedded in an isolation layer 45 and the gate electrode 100 surrounds the semiconductor nanowires 20. [

Figures 2 to 18F illustrate exemplary sequential processes for fabricating GAA FETs in accordance with embodiments of the present disclosure. Additional operations may be provided before, during and after the processes illustrated in Figures 2 to 18f, and some of the operations described below for the additional embodiments of the method may be replaced or eliminated . The order of operations / processes may be interchangeable.

Figure 2 shows a cross-sectional view of one of the various stages of fabricating a semiconductor FET device in accordance with embodiments of the present disclosure. As shown in Fig. 2, a semiconductor substrate 10 is provided. In some embodiments, the substrate 10 includes at least a single crystal semiconductor layer on its surface portion. The substrate 10 may include single crystal semiconductor materials such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaPb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. In certain embodiments, the substrate 10 is comprised of crystalline Si.

The substrate 10 may include one or more buffer layers (not shown) in its surface region. The buffer layers may act to gradually change the lattice constant from the lattice constant of the substrate to the lattice constant of the source / drain regions. The buffer layers may be epitaxially grown single crystal semiconductor materials such as (but not limited to) Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, / RTI >

As shown in FIG. 2, impurity ions (dopants) 12 are implanted into the silicon substrate 10 to form a well region. Ion implantation is performed to prevent punch-through effects. Substrate 10 may include various regions suitably doped with impurities (e.g., p-type or n-type conductivity). The dopants 12 are, for example, boron (BF2) for n-type FinFETs and phosphorous for p-type FinFETs.

Then, as shown in FIG. 3, a first semiconductor layer 15 is formed on the substrate 10. In some embodiments, the first semiconductor layer 15 is formed of a first semiconductor material. In some embodiments, the first semiconductor material comprises a first group IV element and a second group IV element. Group IV elements are selected from the group consisting of C, Si, Ge, Sn and Pb. In some embodiments, the first IV group element is Si and the second IV group element is Ge. In certain embodiments, the first semiconductor material is Si _1-x Ge _x , where 0.3 ≦ x ≦ 0.9, and in other embodiments 0.4 ≦ x ≦ 0.7.

As shown in FIG. 4, a second semiconductor layer 20 is formed on the first semiconductor layer 15 thereafter. In some embodiments, the second semiconductor layer 20 is formed of a second semiconductor material. In some embodiments, the second semiconductor material comprises a first group IV element and a second group IV element. In some embodiments, the first IV group element is Si and the second IV group element is Ge. In some embodiments, the amounts of the first IV group element and the second IV group element in the first semiconductor material are different from those in the second semiconductor material. In some embodiments, the amount of Ge in the first semiconductor material exceeds the amount of Ge in the second semiconductor material. In certain embodiments, the second semiconductor material is Si _1-y Ge _y , where 0.1 ≤ y ≤ 0.5, x> y, and in other embodiments 0.2 ≤ y ≤ 0.4.

Next, another first semiconductor layer 15 is formed on the second semiconductor layer 20, as shown in Fig. Another first semiconductor layer 15 is formed of the same material as described above with reference to Fig. The third semiconductor layer 25 is formed on another first semiconductor layer 15. In some embodiments, the third semiconductor layer 25 is made of a Group IV element. In some embodiments, the third semiconductor layer 25 is made of the same material as the substrate 10.

The first semiconductor layer 15, the second semiconductor layer 20 and the third semiconductor layer 25 are made of materials having different lattice constants in some embodiments and may be made of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP. In some embodiments, the first semiconductor layers 15, the second semiconductor layer 20, and the third semiconductor layers 25 are made of different materials. In one embodiment, the first semiconductor layers 15 are made of Si _1-x Ge _x , where 0.3 ≦ x ≦ 0.7 and the second semiconductor layer 20 is made of Si _1-y Ge _y , where 0.2? Y? 0.5, x> y, and the third semiconductor layer 25 is made of Si.

In some embodiments, the thickness of the first semiconductor layer 15 is about 0.5 nm to about 5 nm, the thickness of the second semiconductor layer 20 is about 3 nm to about 20 nm, the thickness of the third semiconductor layer 25 ) Is from about 2 nm to about 18 nm. In other embodiments, the thickness of the first semiconductor layer 15 is about 0.5 nm to about 2 nm, the thickness of the second semiconductor layer 20 is about 5 nm to about 15 nm, the thickness of the third semiconductor layer 25 ) Is from about 3 nm to about 12 nm. In some embodiments, the thickness of the second semiconductor layer 20 exceeds the thickness of the third semiconductor layer 25 and the thickness of the third semiconductor layer 25 exceeds the thickness of the first semiconductor layer 15 do.

The first semiconductor layer 15, the second semiconductor layer 20 and the third semiconductor layer 25 may be formed by one or more epitaxial or epitaxial (epi) processes. The epitaxy processes may be performed by CVD deposition techniques (e.g., VPE, and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / Or other suitable processes.

Next, in some embodiments, additional first semiconductor layers (A) 15, second semiconductor layers (B) 20, and third semiconductor layers (C) 25 are formed as shown in FIG. 6A Are stacked together in a repeating sequence ABAC. Although the three repetitive sequences ABAC of the semiconductor layers are shown in Fig. 6A, the number of repetitive sequences is not limited to three, but may be as small as one (each layer), and in some embodiments, two to ten iterations A sequence ABAC is formed. In other embodiments, repeated sequences of ACAB are formed, as shown in FIG. 3B. By adjusting the number of stacked layers, the driving current of the GAA FET device can be adjusted.

In some embodiments in which the substrate 10 is made of a material different from the third semiconductor layers 25, the bottom semiconductor layer formed on the substrate 10 is a third semiconductor layer (C) 25. After formation of the initial layer of the third semiconductor layer (C) 25, the first semiconductor layer (A) 15, the second semiconductor layer (B) 20, Repeating sequences ABAC of the layer (A) 15 and the third semiconductor layer (C) 25 are formed.

In some embodiments, as shown in Figure 7, a mask layer 30 is formed over the topmost semiconductor layer. The mask layer 30 includes a first mask layer 32 and a second mask layer 35. The first mask layer 32 is a pad oxide layer of silicon oxide that can be formed by thermal oxidation or chemical vapor deposition (CVD). The second mask layer 16B may be formed by CVD including low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD, atomic layer deposition), or other suitable process. The mask layer 30 is patterned into a mask pattern by using patterning operations including photolithography and etching.

Next, as shown in FIG. 8, the stacked layers of the first, second and third semiconductor layers 15, 20, 25 are patterned by using the patterned mask layer 16 so that the stacked layers And is formed of pin structures 35 extending in the Y direction. 8, the two pin structures 35 are arranged in the X direction. However, the number of pin structures is not limited to two, but may be as few as one or three or more. In some embodiments, one or more dummy pin structures are formed on both sides of the fin structures 35 to improve pattern fidelity in patterning operations. As shown in FIG. 8, the fin structures 35 have top portions configured by laminated semiconductor layers 15, 20, 25 and well portions 40.

The width W1 along the X direction of the upper portion of the pin structure is in the range of about 5 nm to about 40 nm in some embodiments and in the range of about 10 nm to about 30 nm in other embodiments. In some embodiments, the height H1 along the Z direction of the fin structure ranges from about 100 nm to about 200 nm.

The stacked fin structure 35 may be patterned by any suitable method. For example, structures may be patterned using one or more photolithographic processes including dual patterning or multiple patterning processes. Generally, a dual patterning or multiple patterning process combines the photolithography and self-aligning processes to allow patterns to be produced having smaller pitches than can be achieved, for example, using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithographic process. Spacers are formed with the patterned sacrificial layer using a self-aligning process. The sacrificial layer is then removed and the remaining spacers can then be used to pattern the stacked fin structure 35.

After the pin structures 35 are formed, a layer of insulating material comprising at least one layer of insulating material is formed on the substrate such that the pin structures are fully embedded in the insulating layer. The insulating material for the insulating layer may be silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine doped silicate glass (FSG, fluorine) formed by low pressure chemical vapor deposition (LPCVD), plasma CVD, -doped silicate glass, or a low-k dielectric material. The annealing operation may be performed after formation of the insulating layer. Then, a planarization operation such as a chemical mechanical polishing (CMP) method and / or an etch-back method is performed so that the upper surface of the uppermost third semiconductor layer 25 is removed from the insulating material layer Exposed. In some embodiments, the fin liner layer 50 is formed over the fin structures prior to forming the insulating material layer. The fin liner layer 50 is made of Si ₃ N ₄ or a silicon nitride based material (e.g., SiON, SiCN or SiOCN).

In some embodiments, the fin liner layers 50 include a first fin liner layer formed on the sidewalls of the lower end of the fin structures 35 and the substrate 10, and a second fin liner layer < RTI ID = 0.0 > Layer. In some embodiments, each of the liner layers has a thickness of from about 1 nm to about 20 nm. In some embodiments, the first fin liner layer comprises silicon oxide and has a thickness of from about 0.5 nm to about 5 nm, and the second fin liner layer comprises silicon nitride and has a thickness of from about 0.5 nm to about 5 nm. The liner layer may be deposited through one or more processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD), but any acceptable process may be used.

9, the insulating material layer is recessed to form the isolating insulation layer 45, so that the upper portions of the pin structures 35 are exposed. With this operation, the pin structures 35 are electrically isolated from each other by an isolating insulation layer 45, also referred to as Shallow Trench Isolation (STI).

In the embodiment shown in FIG. 9, the insulating material layer 45 is recessed until the upper portion of the well region 40 is exposed. In other embodiments, the upper portion of the well region 40 is not exposed.

After the isolation insulating layer 45 is formed, a sacrificial (dummy) gate structure 52 is formed, as shown in FIGS. 10A and 10B. 10A is a cross-sectional view taken along the gate electrode in the X-direction (line A-A). 10B is a cross-sectional view taken along the pin structure in the Y-direction (line B-B). FIGS. 10A-C illustrate the structure after the sacrificial gate structure 52 is patterned over exposed pin structures 35. FIG. A sacrificial gate structure 52 is formed over a portion of the pin structures 35 which will be the channel region. The sacrificial gate structure 52 defines the channel region of the GAA FET. The sacrificial gate structure 52 includes a sacrificial gate dielectric layer 55 and a sacrificial gate electrode layer 60. The sacrificial gate dielectric layer 55 comprises at least one layer of an insulating material such as a silicon oxide-based material. In one embodiment, silicon oxide formed by CVD is used. In some embodiments, the thickness of the sacrificial gate dielectric layer 55 ranges from about 1 nm to about 5 nm.

A sacrificial gate structure 52 is formed by first blanket depositing a sacrificial gate dielectric layer over the fin structures. The sacrificial gate electrode layer is then blanket deposited over the sacrificial gate dielectric layer and over the fin structures such that the fin structure is completely buried in the sacrificial gate electrode layer. The sacrificial gate electrode layer includes silicon such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate electrode layer ranges from about 100 nm to about 200 nm. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, PVD, ALD, or other suitable process including LPCVD and PECVD. Subsequently, a mask layer 62 is formed on the sacrificial gate electrode layer. The mask layer 62 includes a pad silicon nitride layer 65 and a silicon oxide mask layer 70.

10A and 10B, a patterning operation is performed on the mask layer 62, and the sacrificial gate electrode layer 60 is patterned with the sacrificial gate electrode 52. Next, as shown in FIGS. The sacrificial gate structure 52 includes a sacrificial gate dielectric layer 55, a sacrificial gate electrode layer 60 (e.g., polysilicon), and a silicon nitride pad layer 65 and a silicon oxide mask layer 65 And a mask layer 62. By patterning the sacrificial gate structure, the stacked layers of the first, second and third semiconductor layers are partially exposed on both sides of the sacrificial gate structure to define the source / drain (S / D) regions. In the present disclosure, the source and the drain are used interchangeably and their structures are substantially the same. 10A and 10B, one sacrificial gate structure 52 is formed, but the number of sacrificial gate structures is not limited to one. In some embodiments, two or more sacrificial gate structures are arranged in the Y direction of the pin structures. In certain embodiments, one or more dummy sacrificial gate structures are formed on both sides of the sacrificial gate structures to enhance pattern fidelity.

After the sacrificial gate structure 52 is formed, a cover layer 75 of insulating material is conformally exposed over the exposed fin structures 35 and the sacrificial gate structure 52, as shown in Figs. 11A-11D. . 11A is a cross-sectional view taken along the gate electrode in the X-direction (line A-A in FIG. 1). 11B is a cross-sectional view taken along the pin structure in the Y-direction (line B-B in FIG. 1). Fig. 11C is a cross-sectional view taken along the line C-C in Fig. 11D is a cross-sectional view taken along line D-D in FIG. The cover layer 75 is deposited conformally, which is formed to have substantially the same thickness on each of the vertical surfaces, such as the sidewalls, the horizontal surfaces, and the top portion of the sacrificial gate structure. In some embodiments, the cover layer 75 has a thickness in the range of about 2 nm to about 20 nm, and in other embodiments, the cover layer 75 has a thickness in the range of about 5 nm to about 15 nm.

In some embodiments, the cover layer 75 includes a first cover layer and a second cover layer. The first cover layer may comprise a low-k dielectric material such as SiOC and / or SiOCN, or any other suitable dielectric material, and the second cover layer 53 may comprise Si ₃ N ₄ , SiON, and SiCN, or And any other suitable dielectric material. The first cover layer and the second cover layer are made of different materials in some embodiments, which can be selectively etched. The first cover layer and the second cover layer may be formed by ALD or CVD, or any other suitable method.

12A to 12D, in some embodiments, the cover layer 75 is removed to remove the cover layer 75 formed over the source / drain regions and the silicon oxide mask layer 70, And then the upper portion of the substrate 10 and the third semiconductor layers 25 in the source / drain regions are removed to the upper surface of the isolating insulating layer 45. [ 12A is a cross-sectional view taken along the gate electrode in the X-direction (line AA in FIG. 1). 12B is a cross-sectional view taken along the pin structure in the Y-direction (line BB in FIG. 1). 12C is a cross-sectional view taken along line CC of FIG. 12D is a cross-sectional view taken along the line DD of FIG. The third semiconductor layers 25 and the upper portion of the substrate are removed using a suitable etching operation. For example, the third semiconductor layers 25 are Si, and the first and second case where the semiconductor layers (15, 20) is a Ge or SiGe, the third semiconductor layers 25 are ammonium hydroxide (NH ₄ OH) Such as, but not limited to, tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions. . In some embodiments, the third semiconductor layers 25 are removed when forming a p-type pFET.

As shown in FIG. 12C, the cover layer 75 and the sacrificial gate dielectric layer 55 are completely removed from the source / drain regions using suitable lithography and etching techniques.

In other embodiments, the pin structures of the source / drain regions are recessed to the top surface of the isolation dielectric layer 45, as shown in Figure 12E. In other words, all of the first, second and third semiconductor layers and the upper portion of the substrate 10 in the source / drain regions are removed. 12E is a cross-sectional view taken along line B-B in FIG. The pin structures are recessed by a recess etch operation using suitable etchants in some embodiments. In some embodiments, the recess etch operation is a dry etch operation. In some embodiments, the pin structures are recessed in the source / drain regions when forming an n-type pFET.

Subsequently, a source / drain epitaxial layer 80 is formed, as shown in Figures 13a-d. Figure 13a is a cross-sectional view taken along the gate electrode in the X-direction (line A-A in Figure 1). Figure 13B is a cross-sectional view taken along the pin structure in the Y-direction (line B-B in Figure 1). 13C is a cross-sectional view taken along line C-C of FIG. 13D is a cross-sectional view taken along the line D-D in Fig.

The source / drain epitaxial layer 80 comprises one or more layers of Si, SiP, SiC and SiCP for an n-channel FET or Si, SiGe, Ge for a p-channel FET. In the case of a P-channel FET, boron (B) may also be included in the source / drain. The source / drain epitaxial layers 80 are formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE). As shown in FIG. 13C, in some embodiments, the source / drain epitaxial layers 80 grow around the pin structures, the grown epitaxial layers are integrated over the isolation insulating layer 45, (82). The source / drain epitaxial layer 80 is formed in contact with the cover layer 75 disposed on the sides of the sacrificial gate structure 52 as shown in FIG. 13D.

In some embodiments, the source / drain epitaxial layer 80 has a diamond-like, hexagonal, other polygonal, or semi-circular cross-section.

Figures 13E and 13F illustrate another embodiment in which the source / drain epitaxial layer 80 is formed on the structure of Figure 12E. FIG. 13E is a cross-sectional view taken along line C-C of FIG. 1, and FIG. 13F is a cross-sectional view taken along line B-B of FIG.

Subsequently, an interlayer dielectric (ILD) layer 85 is formed, as shown in Figures 14A-14D. Figure 14A is a cross-sectional view taken along the gate electrode in the X-direction (line A-A in Figure 1). 14B is a cross-sectional view taken along the pin structure in the Y-direction (line B-B in FIG. 1). 14C is a cross-sectional view taken along the line C-C of FIG. Fig. 14D is a cross-sectional view taken along the line D-D in Fig.

The materials for the ILD layer 85 include compounds including Si, O, C and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers can be used for the ILD layer 85. After the ILD layer 85 is formed, a planarization operation such as chemical mechanical polishing (CMP) is performed to expose the upper portion of the sacrificial gate electrode layer 60. CMP also removes a portion of mask layer 62 and cover layer 75 that covers the top surface of sacrificial gate electrode layer 60.

Figs. 14E and 14F illustrate another embodiment in which the ILD layer 85 is formed on the structures of Figs. 13E and 13F. Fig. 14E is a cross-sectional view taken along line C-C of Fig. 1, and Fig. 14F is a cross-sectional view taken along line B-B of Fig.

The sacrificial gate electrode layer 60 and the sacrificial gate dielectric layer 55 are then removed to form a gate space 90 in which the channel regions of the pin structures are exposed, as shown in Figures 15A-15D. 15A is a cross-sectional view taken along the gate electrode in the X-direction (line A-A in FIG. 1). 15B is a cross-sectional view taken along the pin structure in the Y-direction (line B-B in FIG. 1). Fig. 15C is a cross-sectional view taken along the line C-C of Fig. 15D is a cross-sectional view taken along the line D-D in FIG.

The ILD layer 85 protects the S / D structures 80 during removal of the sacrificial gate structures. The sacrificial gate structures can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer 60 is polysilicon and the ILD layer 85 is silicon oxide, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution is used to selectively remove the sacrificial gate electrode layer 60 Can be used. Thereafter, the sacrificial gate dielectric layer 55 is removed using plasma dry etch and / or wet etch.

Fig. 15E is a cross-sectional view taken along line C-C in Fig. 1, and Fig. 15F is a cross-sectional view taken along line B-B in Fig. 1 of another embodiment where the sacrificial gate electrode layer 60 and sacrificial gate dielectric layer of Fig.

15G is a detailed cross-sectional view of a pin structure according to an embodiment of the present disclosure; In one embodiment, as shown in FIG. 15G, the first semiconductor layer 15 is comprised of Si _0.5 Ge _0.5 having a thickness (Z) of about 0.5 nm to about 5 nm. The second semiconductor layer 20 is made of Si _0.7 Ge _0.3 having a thickness (B) of about 3 nm to about 20 nm. The third semiconductor layer 25 is made of Si having a thickness (A) of about 2 nm to about 18 nm. The thicknesses A, B, and Z are related by B > A > Z.

After the sacrificial gate structure is removed, the third semiconductor layers 25 in the pin structures are removed to form first semiconductor layers (not shown) sandwiching the second semiconductor layers 20, as shown in FIGS. 16A- 15). ≪ / RTI > 16A is a cross-sectional view taken along the gate electrode in the X-direction (line A-A in FIG. 1). 16B is a cross-sectional view taken along the pin structure in the Y-direction (line B-B in FIG. 1). Fig. 16C is a cross-sectional view taken along line C-C of Fig. 16D is a cross-sectional view taken along the line D-D in Fig.

The third semiconductor layers 25 may be removed or etched using an etchant that selectively etches the first semiconductor layer 25 with respect to the first and second semiconductor layers 15,20. Third and semiconductor layers 25 are Si first and a second case where the semiconductor layers (15, 20) is a Ge or SiGe, the third semiconductor layers 25 are ammonium hydroxide (NH ₄ OH), tetramethylammonium Can be selectively removed using a wet etchant such as, but not limited to, hydroxides (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions. If the third semiconductor layer 25 is Si and the substrate 10 is a silicon substrate, etching of the third semiconductor layer 25 also removes a portion of the pin structure underlying the lowermost first semiconductor layer 15. When the third semiconductor layer 25 and the substrate 10 are made of different materials, in some embodiments, a pin (not shown) underlying the lowermost first semiconductor layer 25, in order to provide the structure shown in Figures 16A and 16B, An additional etching operation is performed to remove a portion of the structure. In other embodiments, when the third semiconductor layer 25 and the substrate 10 are made of different materials, an initial third semiconductor layer 25 is formed on the substrate 10, as shown in Figure 6C, Which is removed with the other third semiconductor layers 25 to provide the structure shown in Figures 16A and 16B.

Figs. 16E and 16F show another embodiment in which the third semiconductor layers 25 are removed from the structure of Fig. 15F. Fig. 16E is a cross-sectional view taken along line C-C of Fig. 1, and Fig. 16F is a cross-sectional view taken along line B-B of Fig.

In some embodiments, a combination of dry etch techniques and wet etch techniques is used to remove the third semiconductor layer 25.

In yet another embodiment, the first and second semiconductor layers 15,20 are removed by using suitable etching techniques and nanowires of the third semiconductor layer 25 are obtained.

Although the cross-sectional shapes of the semiconductor nanowires 15 and 20 in the channel region are shown as being rectangular, any polygonal shape (triangle, diamond, etc.), polygonal shape with rounded edges, circular or elliptical .

After the semiconductor nanowires of the first and second semiconductor layers 15 and 20 are formed, as shown in FIGS. 17A to 17D, the respective channel layers (the wires of the first and second semiconductor layers 15 and 20) Gate dielectric layer 95 is formed around gate dielectric layer 95 and gate electrode layer 100 is formed on gate dielectric layer 95. 17A is a cross-sectional view taken along the gate electrode in the X-direction (line A-A in FIG. 1). 17B is a cross-sectional view taken along the pin structure in the Y-direction (line B-B in FIG. 1). Fig. 17C is a cross-sectional view taken along line C-C of Fig. 17D is a cross-sectional view taken along the line D-D in Fig.

17E and 17F illustrate another embodiment in which the gate dielectric layer 95 and the gate electrode layer 100 are formed on the structure of FIG. 16F. 17E is a cross-sectional view taken along line C-C of FIG. 1, and FIG. 17F is a cross-sectional view taken along line B-B of FIG.

In certain embodiments, the gate dielectric layer 95 comprises one or more layers of dielectric materials such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high k dielectric materials include, but are not limited to, HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO ₂ -Al ₂ O ₃ ) Materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 95 includes an interfacial layer formed between the channel layers and the dielectric material.

The gate dielectric layer 95 may be formed by CVD, ALD, or any suitable method. In one embodiment, a gate dielectric layer 95 is formed using a highly conformal deposition process, such as ALD, to ensure formation of a gate dielectric layer having a uniform thickness around each channel layer. In some embodiments, the thickness of the gate dielectric layer 95 ranges from about 1 nm to about 6 nm. In some embodiments, a gate dielectric layer 95 is also formed on the exposed source / drain epitaxial layers 80.

A gate electrode layer 100 is formed on the gate dielectric layer 95 to surround each channel layer. The gate electrode 100 may be formed of any suitable material such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, , ≪ / RTI > and / or combinations thereof.

The gate electrode layer 100 may be formed by CVD, ALD, electroplating, or other suitable method. A gate electrode layer is also deposited on top of the ILD layer 85. The gate dielectric layer and the gate electrode layer formed over the ILD layer 85 are then planarized by using, for example, CMP until the top surface of the ILD layer 85 is exposed. In some embodiments, after the planarization operation, the gate electrode layer is recessed and a cap insulation layer (not shown) is formed over the recessed gate electrode. The cap insulating layer comprises at least one layer of a silicon nitride-based material, such as Si ₃ N ₄ . The cap insulating layer may be formed by depositing an insulating material and then performing a planarization operation.

In certain embodiments of the disclosure, one or more work function adjustment layers (not shown) are interposed between the gate dielectric layer 95 and the gate electrode 100. The work function adjustment layers are composed of a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC or a conductive material such as two or more layers of these materials. In the case of an n-channel FET, at least one of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi is used as a work function adjusting layer, and TiAlC, Al, TiAl, TaN , At least one of TaAlC, TiN, TiC and Co is used as a work function adjusting layer. The work function adjustment layer may be formed by ALD, PVD, CVD, e-beam evaporation or other suitable process. In addition, the work function adjustment layer can be formed separately for the n-channel FET and the p-channel FET, which can use different metal layers.

In other embodiments, the first semiconductor layers 15 disposed on both sides of the second semiconductor layer 20 are removed prior to forming the gate dielectric layer 95 and the gate electrode layer 100, 18A to 18D. The first semiconductor layer 15 can be removed by a suitable etching operation such as wet etching using HF: HNO3: H2O. 18A is a cross-sectional view taken along the gate electrode in the X-direction (line A-A in FIG. 1). Figure 18b is a cross-sectional view taken along the pin structure in the Y-direction (line B-B in Figure 1). 18C is a cross-sectional view taken along line C-C of FIG. 18D is a cross-sectional view taken along line D-D in Fig. The first semiconductor layers 15 disposed on both sides of the second semiconductor layer 20 are removed only in the channel region by using a suitable etching technique. Thus, in this embodiment, the first semiconductor layers remain in the first source / drain regions 80.

18E and 18F show that pin structures in the source / drain regions are recessed to the top surface of the isolating insulation layer 45 and source / drain regions 80 are formed in the recesses < RTI ID = 0.0 >Lt; RTI ID = 0.0 > embodiment. ≪ / RTI > 18E is a cross-sectional view taken along line C-C of FIG. 1, and FIG. 18F is a cross-sectional view taken along line B-B of FIG.

Then, contact holes (not shown) may be formed in the ILD layer 85 by using dry etching. In some embodiments, the upper portion of the S / D epitaxial layer 80 is etched. In some embodiments, a silicide layer is formed over the S / D epitaxial layer 80. The silicide layer includes at least one of WSi, CoSi, NiSi, TiSi, MoSi, and TaSi. Then, a conductive material (not shown) is formed in the contact holes. The conductive material includes at least one of Co, Ni, W, Ti, Ta, Cu, Al, TiN and TaN. It should be appreciated that the GAA FETs may undergo additional CMOS processes to form various features such as contacts / vias, interconnect metal layers, dielectric layers, passivation layers, and the like.

In some embodiments shown in Figures 18A-18F, each of the plurality of nanowires 20 has a greater distance in the nanowire stacking direction than each of the plurality of nanowires 15,20 in Figures 17A-17F .

In certain embodiments, the semiconductor device is an n-type GAA FET. In other embodiments, the semiconductor device is a p-type GAA FET. In some embodiments, one or more n-type GAA FETs and one or more p-type GAA FETs are provided on the same substrate 10.

In embodiments of the disclosure, the first semiconductor layer disposed on either side of the second semiconductor layer protects the second semiconductor layer during etching to remove the third semiconductor layer in the channel region. In some embodiments, the first SiGe semiconductor layer having a higher Ge concentration than the second SiGe semiconductor layer has high resistance to the etchant used to remove the third semiconductor layer of Si, so that the third semiconductor layer etching operation While protecting the second SiGe semiconductor layer from thinning. Semiconductor devices formed in accordance with the present disclosure have an improved process window of nanowire release etch leading to higher device yield.

In order that those aspects of the disclosure may be better understood by those skilled in the art, the features of the various embodiments have been outlined above. Those skilled in the art will readily appreciate that the present invention can be readily applied by those skilled in the art to the disclosure of the present invention as a basis for designing or modifying other processes and structures for performing the same purposes of the presently disclosed embodiments or examples and / It should be noted that Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that various changes, substitutions, and modifications may be effected therein by those skilled in the art without departing from the spirit and scope of the disclosure. .

An embodiment of the disclosure is a method of fabricating a semiconductor device comprising forming a first semiconductor layer having a first composition on a semiconductor substrate and forming a second semiconductor layer having a second composition over the first semiconductor layer . Another first semiconductor layer having a first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed on another first semiconductor layer. The first semiconductor layers, the second semiconductor layer, and the third semiconductor layer are patterned to form a fin structure. A part of the third semiconductor layer is removed to form a nanowire including the second semiconductor layer, and a conductive material surrounding the nanowire is formed. The first semiconductor layers, the second semiconductor layer, and the third semiconductor layer include different materials. In the embodiment, by repeating the step of forming the first semiconductor layer, the step of forming the second semiconductor layer, the step of forming the other first semiconductor layer, and the step of forming the third semiconductor layer, A stack of one semiconductor layers, second semiconductor layers, another first semiconductor layers, and third semiconductor layers is formed. In an embodiment, a sacrificial gate structure is formed over the fin structure prior to removing a portion of the third semiconductor layer. In an embodiment, before removing a portion of the third semiconductor layer, a portion of the fin structure that is not covered by the sacrificial gate structure is removed to form the source / drain space. In an embodiment, source / drain regions are formed in the source / drain space. In an embodiment, when forming the nanowire, a portion of the semiconductor substrate is removed. In an embodiment, the third semiconductor layer and the semiconductor substrate are formed of the same material. In an embodiment, the same material is silicon. In an embodiment, the first semiconductor material is Si _1-x Ge _x and the second semiconductor material is Si _1-y Ge _y , where x> y.

In another embodiment of the present disclosure, a method of fabricating a semiconductor device includes providing a semiconductor substrate (A), a second semiconductor layer (B), and a third semiconductor layer (C) And forming a fin structure thereon. The first semiconductor layers, the second semiconductor layers, and the third semiconductor layers comprise different materials. The sacrificial gate structure defines a gate region over the fin structure. The third semiconductor layers are removed from the source / drain regions of the fin structure that is not covered by the sacrificial gate structure. Source / drain epitaxial layers are formed in the source / drain regions. The sacrificial gate structure is removed, and the third semiconductor layers are removed from the gate region. A gate electrode structure is formed in the gate region, and the gate electrode structure surrounds the first and second semiconductor layers. In an embodiment, when the third semiconductor layers are removed, a portion of the semiconductor substrate is removed. In an embodiment, the third semiconductor layer and the semiconductor substrate are formed of the same material. In an embodiment, the same material is a Group IV element. In an embodiment, the first semiconductor material is Si _1-x Ge _x and the second semiconductor material is Si _1-y Ge _y , where x> y. In the embodiment, 0.3? X? 0.9 and 0.1? Y? 0.5. In an embodiment, the first semiconductor layers and the second semiconductor layers are epitaxially formed and during the epitaxial operation, the Ge concentration is increased to form the first semiconductor layer, and the Ge concentration to form the second semiconductor layer is . In an embodiment, the thickness of the second semiconductor layer exceeds the thickness of the third semiconductor layer.

In an embodiment of the present disclosure, a method of fabricating a semiconductor device includes forming a first fin structure and a second fin structure, wherein the first semiconductor layer and the second semiconductor structure are formed in both the first fin structure and the second fin structure, Layers are alternately stacked. A first sacrificial gate structure is formed over the first fin structure and a second sacrificial gate structure is formed over the second fin structure. A first passivation layer is formed over the second fin structure and the second sacrificial gate structure. The first semiconductor layers in the source / drain regions of the first fin structure that are not covered by the first sacrificial gate structure are removed to form a first source / drain space. A first source / drain epitaxial layer is formed in the first source / drain space to form the first structure. A second passivation layer is formed over the second fin structure and the second sacrificial gate structure. The second semiconductor layers in the source / drain regions of the second fin structure not covered by the second sacrificial gate structure are removed to form a second source / drain space. The second source / drain epitaxial layer in the second source / drain space is removed to form the second structure. The first sacrificial gate structure and the first semiconductor layer in the first gate region are removed to form the first gate space. The second sacrificial gate structure and the second semiconductor layer in the second gate region are removed to form the second gate space. A first gate electrode structure and a second gate electrode structure are formed in the first gate space and the second gate space, respectively. The first semiconductor layer comprises a first sub-layer and second sub-layers disposed on both sides of the first sub-layer, the first sub-layer being formed of an alloy comprising a first group IV element and a second group IV element And the second sub-layer is formed of an alloy comprising the first IV group element and the second IV group element. The amounts of the first IV group element and the second IV group element are different in the first sub-layer and the second sub-layer. In an embodiment, the first IV group element is Si and the second IV group element is Ge. In an embodiment, the composition of the first sub-layer is Si _1-y Ge _y , where 0.1 ≤ y ≤ 0.5 and the composition of the second sub-layer is Si _1-x Ge _x , where 0.3 ≤ x ≤ 0.9.

In an embodiment of the present disclosure, a semiconductor device includes at least one semiconductor nanowire disposed over a semiconductor substrate, and a gate structure surrounding at least one semiconductor nanowire. Source / drain structures are disposed on semiconductor substrates on both sides of the gate structure. The at least one semiconductor nanowire includes two opposing first layers of a first semiconductor material sandwiching a layer of a second semiconductor material different from the first semiconductor material. In an embodiment, the first semiconductor material comprises a first group IV element and a second group IV element, the second semiconductor material comprises a first group IV element and a second group IV element, and the first group IV element and / The amount of the second IV group element is different in the first semiconductor material and the second semiconductor material. In an embodiment, the first IV group element is Si and the second IV group element is Ge. In an embodiment, the first semiconductor material is Si _1-x Ge _x , the second semiconductor material is Si _1-y Ge _y , and x> y. In the embodiment, 0.3? X? 0.9 and 0.1? Y? 0.5. In an embodiment, the thickness of the first layers is 0.5 nm to 2 nm and the thickness of the second layers is 3 nm to 15 nm. In an embodiment, the source / drain structures surround at least one nanowire. In an embodiment, insulating sidewalls are disposed between the source / drain structures and the gate structure. In an embodiment, the gate structure includes a high-k dielectric layer and a metal gate electrode layer.

In an embodiment of the present disclosure, a semiconductor device includes a plurality of semiconductor wires arranged in a stack arranged in a first direction on a substrate, the first direction extending substantially perpendicular to the main surface of the substrate. The first source / drain region is in contact with the ends of the first semiconductor wires. A gate dielectric layer is disposed on and surrounds each channel region of the first semiconductor wires. A gate electrode layer is disposed on the gate dielectric layer and surrounds each channel region. The at least one semiconductor nanowire includes two opposing first layers comprised of a first semiconductor material sandwiching a second layer of a second semiconductor material different from the first semiconductor material, Are arranged along the first direction. In an embodiment, the first semiconductor material comprises a first group IV element and a second group IV element, the second semiconductor material comprises a first group IV element and a second group IV element, and the first group IV element and / The amount of the second IV group element is different in the first semiconductor material and the second semiconductor material. In an embodiment, the first IV group element is Si and the second IV group element is Ge. In an embodiment, the first semiconductor material is Si _1-x Ge _x , the second semiconductor material is Si _1-y Ge _y , and x> y. In an embodiment, the thickness of the first layers is 0.5 nm to 2 nm and the thickness of the second layer is 3 nm to 15 nm. In an embodiment, the source / drain structures surround each of the nanowires. In an embodiment, insulating sidewalls are included between the source / drain regions and the gate electrode layer.

In an embodiment of the present disclosure, a semiconductor device includes a first nanowire structure and a second nanowire structure, wherein both the first nanowire structure and the second nanowire structure extend along a first direction and extend in a first direction And a plurality of nanowires stacked along a second direction that is substantially perpendicular. The first and second gate electrodes are disposed over the first and second nanowire structures, respectively, and the first and second electrodes surround the nanowires of the first and second nanowires, respectively. The first nanowires comprise a first semiconductor layer comprising a first semiconductor material and second sublayers comprising a second semiconductor material and disposed on opposite sides of the first sublayer. The second nanowires are composed of a third semiconductor material, and the first, second and third semiconductor materials are different materials. In an embodiment, the first semiconductor material is an alloy comprising a first IV group element and a second IV group element, the second semiconductor material is an alloy comprising a first IV group element and a second IV group element, The semiconductor material is one of a first IV group element and a second IV group element and the amounts of the first IV group element and the second IV group element are different in the first semiconductor material and the second semiconductor material. In an embodiment, the first IV group element is Si and the second IV group element is Ge. In an embodiment, the composition of the first semiconductor material is Si _1-y Ge _y , where 0.1 ≤ y ≤ 0.5 and the composition of the second semiconductor material is Si _1-x Ge _x , where 0.3 ≤ x ≤ 0.9.

In an embodiment of the present disclosure, a method of manufacturing a semiconductor device includes the steps of disposing a first semiconductor layer, a first second semiconductor layer, a third semiconductor layer, a second second semiconductor layer, and a second first semiconductor layer in this order To form a pin structure including the pin structure. A sacrificial gate structure is formed that includes a sacrificial gate dielectric layer and a sacrificial gate electrode layer overlying the fin structure. Source and drain regions are formed over the fin structure on either side of the sacrificial gate structure. An interlayer dielectric layer is formed over the source / drain regions. The sacrificial gate structure is removed. The first semiconductor layers and the second semiconductor layers are removed from the channel region of the device to form the nanowires of the third semiconductor layer. A high-k gate dielectric layer and a metal gate electrode surrounding the nanowires in the channel region are formed.

It is to be understood that not all advantages are necessarily discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may provide different advantages.

Examples

1. A method of manufacturing a semiconductor device,

Forming a first semiconductor layer having a first composition on a semiconductor substrate;

Forming a second semiconductor layer having a second composition over the first semiconductor layer;

Forming another first semiconductor layer having the first composition on the second semiconductor layer;

Forming a third semiconductor layer having a third composition on the another first semiconductor layer;

Patterning the first semiconductor layers, the second semiconductor layer, and the third semiconductor layer to form a fin structure;

Removing a portion of the third semiconductor layer to form a nanowire including the second semiconductor layer; And

Forming a conductive material surrounding the nanowire

/ RTI >

Wherein the first semiconductor layers, the second semiconductor layer, and the third semiconductor layer comprise different materials.

Example 2 [0050] In Example 1,

The step of forming the first semiconductor layer, the step of forming the second semiconductor layer, the step of forming the another first semiconductor layer, and the step of forming the third semiconductor layer are repeated in order, Wherein a stack of one semiconductor layers, second semiconductor layers, another first semiconductor layers, and third semiconductor layers is formed.

Example 3 In Example 1,

Further comprising forming a sacrificial gate structure over the fin structure prior to removing a portion of the third semiconductor layer.

Example 4 [0060] In Example 3,

Further comprising removing a portion of the fin structure not covered by the sacrificial gate structure to form a source / drain space prior to removing a portion of the third semiconductor layer.

Example 5 In Example 4,

And forming source / drain regions in the source / drain space.

Example 6 In Example 1,

Further comprising removing a portion of the semiconductor substrate when forming the nanowire.

[Example 7]

Wherein the third semiconductor layer and the semiconductor substrate are formed of the same material.

Example 8 [0141] In the same manner as in Example 7,

Wherein the same material is silicon.

[Example 9] In Example 1,

Wherein the first semiconductor material is Si _1-x Ge _x and the second semiconductor material is Si _1-y Ge _y , where x> y.

Embodiment 10. A method of manufacturing a semiconductor device,

Forming a fin structure on a semiconductor substrate on which the first semiconductor layers (A), the second semiconductor layers (B), and the third semiconductor layers (C) are stacked in a repeating sequence ABAC, The layers, and the third semiconductor layers comprise different materials;

Forming a sacrificial gate structure defining a gate region over the fin structure;

Removing the third semiconductor layers from the source / drain regions of the fin structure not covered by the sacrificial gate structure;

Forming source / drain epitaxial layers in the source / drain regions;

Removing the sacrificial gate structure;

Removing the third semiconductor layers from the gate region; And

Forming a gate electrode structure within the gate region, the gate electrode structure including a first and a second semiconductor layers,

≪ / RTI >

Example 11 [0141] In Example 10,

Further comprising removing a portion of the semiconductor substrate when removing the third semiconductor layers.

Example 12 [0141] In the same manner as in Example 10,

Wherein the third semiconductor layer and the semiconductor substrate are formed of the same material.

13. The method according to embodiment 12,

Wherein the same material is a Group IV element.

Example 14 [0141] In the same manner as in Example 10,

Wherein the first semiconductor material is Si _1-x Ge _x , the second semiconductor material is Si _1-y Ge _y , and the third semiconductor material is silicon, wherein x> y. Way.

Example 15. In Example 14,

0.3? X? 0.9, and 0.1? Y? 0.5.

[Example 16]

Wherein the first and second semiconductor layers are epitaxially formed and during the epitaxial operation the Ge concentration is increased to form the first semiconductor layer and the Ge concentration to form the second semiconductor layer is Wherein the semiconductor device is reduced in thickness.

[Example 17] In Example 10,

Wherein the thickness of the second semiconductor layer exceeds the thickness of the third semiconductor layer.

Embodiment 18. In a semiconductor device,

At least one semiconductor nanowire disposed on a semiconductor substrate;

A gate structure surrounding the at least one semiconductor nanowire; And

Source / drain structures disposed on the semiconductor substrate on either side of the gate structure

/ RTI >

Wherein the at least one semiconductor nanowire comprises two opposing layers comprised of the first semiconductor material that sandwich a layer of a second semiconductor material different from the first semiconductor material.

[Example 19]

Wherein the first semiconductor material comprises a first group IV element and a second group IV element and the second semiconductor material comprises the first group IV element and the second group IV element and wherein the first group IV element And wherein the amount of the second group IV element is different in the first semiconductor material and the second semiconductor material.

20. The process of embodiment 19,

Wherein the first group IV element is Si and the second group IV element is Ge.

Claims (10)

A method of manufacturing a semiconductor device,
Forming a first semiconductor layer having a first composition on a semiconductor substrate;
Forming a second semiconductor layer having a second composition over the first semiconductor layer;
Forming another first semiconductor layer having the first composition on the second semiconductor layer;
Forming a third semiconductor layer having a third composition on the another first semiconductor layer;
Patterning the first semiconductor layers, the second semiconductor layer, and the third semiconductor layer to form a fin structure;
Removing a portion of the third semiconductor layer to form a nanowire including the second semiconductor layer; And
Forming a conductive material surrounding the nanowire
/ RTI >
Wherein the first semiconductor layers, the second semiconductor layer, and the third semiconductor layer comprise different materials. The method according to claim 1,
The step of forming the first semiconductor layer, the step of forming the second semiconductor layer, the step of forming the another first semiconductor layer, and the step of forming the third semiconductor layer are repeated in order, Wherein a stack of one semiconductor layers, second semiconductor layers, another first semiconductor layers, and third semiconductor layers is formed. The method according to claim 1,
Further comprising forming a sacrificial gate structure over the fin structure prior to removing a portion of the third semiconductor layer. The method of claim 3,
Further comprising removing a portion of the fin structure not covered by the sacrificial gate structure to form a source / drain space prior to removing a portion of the third semiconductor layer. 5. The method of claim 4,
And forming source / drain regions in the source / drain space. The method according to claim 1,
Further comprising removing a portion of the semiconductor substrate when forming the nanowire. The method according to claim 1,
Wherein the third semiconductor layer and the semiconductor substrate are formed of the same material. The method according to claim 1,
Wherein the first semiconductor material is Si _1-x Ge _x and the second semiconductor material is Si _1-y Ge _y , where x> y. A method of manufacturing a semiconductor device,
Forming a fin structure on a semiconductor substrate on which the first semiconductor layers (A), the second semiconductor layers (B), and the third semiconductor layers (C) are stacked in a repeating sequence ABAC, The semiconductor layers, and the third semiconductor layers comprise different materials;
Forming a sacrificial gate structure defining a gate region over the fin structure;
Removing the third semiconductor layers from the source / drain regions of the fin structure not covered by the sacrificial gate structure;
Forming source / drain epitaxial layers in the source / drain regions;
Removing the sacrificial gate structure;
Removing the third semiconductor layers from the gate region; And
Forming a gate electrode structure within the gate region, the gate electrode structure including a first and a second semiconductor layers,
≪ / RTI > A semiconductor device comprising:
At least one semiconductor nanowire disposed on a semiconductor substrate;
A gate structure surrounding the at least one semiconductor nanowire; And
Source / drain structures disposed on the semiconductor substrate on either side of the gate structure
/ RTI >
Wherein the at least one semiconductor nanowire comprises two opposing layers comprised of the first semiconductor material that sandwich a layer of a second semiconductor material different from the first semiconductor material.

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