KR20170037203A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
KR20170037203A
KR20170037203A KR1020150136448A KR20150136448A KR20170037203A KR 20170037203 A KR20170037203 A KR 20170037203A KR 1020150136448 A KR1020150136448 A KR 1020150136448A KR 20150136448 A KR20150136448 A KR 20150136448A KR 20170037203 A KR20170037203 A KR 20170037203A
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KR
South Korea
Prior art keywords
bank
signal
local line
line
column
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KR1020150136448A
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Korean (ko)
Inventor
김기업
Original Assignee
에스케이하이닉스 주식회사
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Priority to KR1020150136448A priority Critical patent/KR20170037203A/en
Publication of KR20170037203A publication Critical patent/KR20170037203A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and is a technique for reducing an operating current of a semiconductor device. According to the present invention, an upper bank connected to an upper local line for inputting and outputting data of an upper mat, a lower bank connected to a lower local line for inputting and outputting data of the lower mat, an upper local line and a lower local line corresponding to a selection signal And a selection control unit for generating a selection signal corresponding to the bank active signal and the row address.

Description

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and is a technique for reducing an operating current of a semiconductor device.

It is common that a semiconductor device is composed of a plurality of memory banks, and an individual memory bank is composed of a set of memory cells. A region in which a memory bank is located in a semiconductor device is referred to as a core region, and an area between memory banks constituted by input / output lines for a memory bank is referred to as a ferry region.

The data transmitted from the ferry area is input into the core area through the write driver located at the boundary of the core area, and the data to be output to the ferry area is output through the input / output (IO) sense amplifier located at the boundary of the core area.

A data bus for transferring data input through a data input / output pin DQ to a core region is generally referred to as a global input / output line (GIO). The data line bus in the core region connected to the write driver and / or the input / output sense amplifier and connected to the core region is referred to as a local input / output line (LIO).

The local input / output line has a plurality of local input / output line pairs having mutually opposite logical values at the time of activation and maintaining the same pre-charge voltage at the time of inactivation. Also, one local input / output line pair is connected to one specified write driver and input / output sense amplifier.

The data input and output as one pair of local input / output lines is data for accessing memory cells defined by a specific range of addresses. That is, it is possible to judge which data is input / output through which local input / output line pair by referring to the address corresponding to the data.

In order to drive a word line at a high speed and perform data input / output operations at a high speed in accordance with a large capacity and a high speed of a semiconductor device, particularly a dynamic random access memory, a local input / output line pair and a global input / output line pair hierarchical input / Dirham is becoming common.

The present invention has a feature that the operation current can be reduced by separating and activating the banks into specific units.

A semiconductor device according to an embodiment of the present invention includes: an upper bank connected to an upper local line for inputting and outputting data of an upper mat; A lower bank connected to a lower local line for inputting / outputting data of the lower mat; A bank separator selectively connecting the upper local line and the lower local line in response to the selection signal; And a selection control unit for generating a selection signal corresponding to the bank active signal and the address of the row.

According to another aspect of the present invention, there is provided a semiconductor device comprising: an upper bank connected to an upper local line for inputting / outputting data of an upper mat; A lower bank connected to a lower local line for inputting / outputting data of the lower mat; A bank separator selectively connecting the upper local line and the lower local line in response to the selection signal; A selection control unit for generating a selection signal corresponding to the bank active signal and the row address; A column controller for generating a column select signal for selecting a column line of the upper bank and the lower bank and supplying a variable power to the column line depending on whether the upper bank and the lower bank are selected; And a precharging unit for selectively precharging the upper local line and the lower local line.

According to another aspect of the present invention, there is provided a semiconductor device including: an upper bank connected to an upper local line for inputting and outputting data of an upper mat; A lower bank connected to a lower local line for inputting / outputting data of the lower mat; A bank separator selectively connecting the upper local line and the lower local line in response to the selection signal; A selection control unit for generating a selection signal corresponding to the bank active signal and the row address; An upper precharging unit for precharging the upper local line when only the lower bank is operated corresponding to the selection signal; And a precharge unit for precharging the upper local line and the lower local line when the upper bank and the lower bank operate in response to the selection signal.

The present invention provides an effect of dividing and activating banks into specific units and controlling the driving power of the column lines to reduce the operating current of the semiconductor device.

It will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. .

1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention;
2 is a detailed circuit diagram of the selection control unit of FIG.
3 is a detailed circuit diagram of the power supply control unit of FIG.
4 and 5 are operation timing diagrams for explaining the operation of the semiconductor device according to the embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention.

The embodiment of the present invention includes an upper bank UBK, a lower bank DBK, a bank separator 140, a selection controller 150, an upper prechain 160, a precharger 170, a sense amplifier 180, A light driver 190, and a column controller YCON. The column controller YCON includes a column decoder 200 and a power controller 210.

The semiconductor device is divided into a plurality of banks and driven. Here, one single bank is divided into an upper bank UBK and a lower bank DBK, and a lower bank DBK is disposed in a lower region of the upper bank UBK.

The upper bank UBK includes a plurality of matrices MAT0 to MATn / 2, a column selection unit 100, and a connection unit 110. [ The lower bank DBK includes a plurality of matrices MAT0 to MATn / 2 + 1 to MATn, a column selection unit 120, and a connection unit 130. [

The upper bank UBK includes a plurality of matrices MAT0 to MATn / 2 formed of a plurality of memory cells. The lower bank DBK includes a plurality of matrices MAT0 to MATn / 2 + 1 to MATn, each of which is composed of a plurality of memory cells.

That is, the memory cell array is divided into a plurality of sets of unit memory cell mat MAT0 to MATn. A plurality of matrices MAT0 to MATn are arranged in the row direction and the column direction to form a plurality of matrices (matte blocks) and a plurality of matrices. Each of the plurality of mats MAT0 to MATn includes a plurality of memory cells in an area where the word lines and the bit lines BL and BLB cross each other.

The upper bank UBK and the lower bank DBK are separated and operated by the bank separator 140. That is, when the bank separator 140 is connected, both the upper bank UBK and the lower bank DBK operate. When the bank separator 140 is disconnected, only the lower bank DBK operates.

The column selection unit 100 of the upper bank UBK selectively controls the connection between the bit lines BL and BLB and the segment lines SIO and SIOB corresponding to the column selection signal YI. The column selection unit 100 includes NMOS transistors N1 to N4, which are a plurality of switching elements. The NMOS transistors N1 to N4 are connected between the bit lines BL and BLB and the segment lines SIO and SIOB, and the column select signal YI is applied through the gate terminal.

The connection unit 110 selectively controls connection between the segment lines SIO and SIOB and the upper local lines LIOU and LIOBU corresponding to the connection control signals IOSW <0: n / 2>. The connection control signal IOSW < 0: n / 2 > is provided in the same manner as the number of mats MAT0 to MATn / 2 of the upper bank UBK and is controlled by a control signal for connecting each mat MAT0 to MATn / 2 to the upper local lines LIOU and LIOBU to be.

The connection unit 110 includes NMOS transistors N5 to N8 which are a plurality of switching elements. The NMOS transistors N5 to N8 are connected between the segment lines SIO and SIOB and the upper local lines LIOU and LIOBU, and a connection control signal IOSW < 0: n / 2 >

In addition, the column selection unit 120 of the lower bank DBK selectively controls the connection between the bit lines BL and BLB and the segment lines SIO and SIOB corresponding to the column selection signal YI. The column selection unit 120 includes NMOS transistors N9 to N12, which are a plurality of switching elements. The NMOS transistors N9 to N12 are connected between the bit lines BL and BLB and the segment lines SIO and SIOB, and the column select signal YI is applied through the gate terminal.

The connection unit 130 selectively controls connection between the segment lines SIO and SIOB and the lower local lines LIOD and LIOBD corresponding to the connection control signal IOSW <n / 2 + 1: n>. The connection control signals IOSW <n / 2 + 1: n> are provided in the same manner as the mat matrices MATn / 2 + 1 ~ MATn of the lower bank DBK and the matrices MATn / 2 + 1 ~ MATn are connected to the lower local lines LIOD and LIOBD As shown in FIG.

The connection unit 130 includes NMOS transistors N13 to N16 which are a plurality of switching elements. The NMOS transistors N13 to N16 are connected between the segment lines SIO and SIOB and the lower local lines LIOD and LIOBD, and the connection control signal IOSW <n / 2 + 1: n> is applied through the gate terminal.

The bank separator 140 is connected between the upper local lines LIOU and LIOBU of the upper bank UBK and the lower local lines LIOD and LIOBD of the lower bank DBK. The bank separator 140 selectively separates the upper local lines LIOU and LIOBU of the upper bank UBK and the lower local lines LIOD and LIOBD of the lower bank DBK corresponding to the selection signal UDSEL.

The bank separator 140 includes NMOS transistors N7 and N8. The NMOS transistors N7 and N8 are connected between the upper local lines LIOU and LIOBU and the lower local lines LIOD and LIOBD, and the selection signal UDSEL is applied through the gate terminal.

In addition, the selection control unit 150 generates a selection signal UDSEL for separating the upper bank UBK and the lower bank DBK in response to the bank active signal BANKACT and the row address XADD_M, and outputs the selection signal UDSEL to the bank separation unit 140.

For example, when the selection signal UDSEL is activated, the bank separation unit 140 is activated and becomes a connection state. Then, the upper local lines LIOU and LIOBU of the upper bank UBK and the lower local lines LIOD and LIOBD of the lower bank DBK are connected and operated.

On the other hand, when the selection signal UDSEL is inactivated, the bank separator 140 is inactivated and turned off. Then, the upper local lines LIOU and LIOBU of the upper bank UBK and the lower local lines LIOD and LIOBD of the lower bank DBK are interrupted and operated.

In this case, the upper local lines LIOU and LIOBU of the upper bank UBK and the lower local lines LIOD and LIOBD of the lower bank DBK are separated from each other, thereby reducing the load on the local input / output line, thereby reducing the current consumed.

The upper precharge section 160 precharges the upper local lines LIOU and LIOBU in a state in which the upper bank UBK and the lower bank DBK are separated from each other. The precharge section 170 precharges the upper local lines LIOU and LIOBU and the lower local lines LIOD and LIOBD in the connected state of the upper bank UBK and the lower bank DBK.

The sense amplifier 180 includes an input / output sense amplifier IOSA and senses and amplifies output data of the lower local lines LIOD and LIOBD. Here, the sense amplifier 180 may include a latch unit, a bit line equalizing unit, and the like. The write driver 190 drives data input from the outside during the read operation and outputs the data to the lower local lines LIOD and LIOBD.

The number of Burst Length and data (DQ) input / output lines may be different depending on the type and structure of the semiconductor device. The number of column lines to be selected may vary depending on the burst length of the semiconductor device and the number of data input / output lines.

The column control unit YCON generates a column selection signal YI for selecting the column line of the upper bank UBK and the lower bank DBK and supplies a variable power to the column line depending on whether the upper bank UBK and the lower bank DBK are selected.

The column decoder 200 of the column control unit YCON decodes the column address corresponding to the power supply signal VDDY and generates a column selection signal YI for selecting a column line. The column selection signals YI are activated in different numbers by an externally inputted column address. Accordingly, the data of the sense amplifier selected by the column selection signal YI among the sense amplifiers of the mat selected at the time of the read / write command can be input / output.

The semiconductor device includes matters MAT0 to MATn provided with a word line (WL), a bit line (BL), and memory cells, a memory cell belonging to the mat MAT0 to MATn, As a means for writing or reading.

In this semiconductor device, the output signal of the Row Decoder, which receives the address of the R0 address, selects the word line WL. The column select signal YI outputted from the column decoder 200 drives the NMOS transistors N1 to N4 and N9 to N12 serving as switches for connecting the bit lines BL and BLB of the corresponding column group to the segment lines SIO and SIOB.

Data is read from the selected cell through the sense amplifier 180 or data is stored in the selected cell through the write driver 190.

Also, the power control unit 210 varies the power supplied to the column decoder 200 according to the bank active signal BANKACT and the row address XADD_M. Accordingly, even if the loading of the local input / output line is variable, the consumed current can be reduced.

That is, the power control unit 210 selects either the power supply VDD1Y or the power supply VDD2Y according to the bank active signal BANKACT and the row address XADD_M, and outputs the power supply signal VDDY. Here, the power source VDD2Y has a voltage level lower than the power source VDD1Y.

In the case of a semiconductor device, the length of the local input / output line is determined according to the density and the configuration of the bank. The data of the local input / output line is driven or sensed by the write driver 190 or the sense amplifier 180 to input / output data.

At this time, the operation characteristics of the local input / output line and the current usage amount in the read / write operation are determined according to the length of the local input / output line of the unit bank. However, as the density of the memory increases, the size of the unit bank increases.

In addition, when the size of the unit bank is increased to increase the chip size of the memory, the length of the local input / output line is increased. In this case, the operation characteristics of the local input / output line are lowered and the current for driving the local input / output line is increased.

It is possible to increase the power level of the column decoder in order to prevent the deterioration of characteristics as the length of the local input / output line increases. However, when the power level of the column decoder is increased, the current consumption is increased.

Accordingly, the embodiment of the present invention can separate a single bank into an upper bank UBK and a lower bank DBK, thereby reducing current consumption. According to an embodiment of the present invention, power consumption can be reduced by selectively controlling the power supplied to the column decoder 200 through the power control unit 210 according to whether the upper bank UBK and the lower bank DBK operate.

2 is a detailed circuit diagram of the selection control unit 150 of FIG.

The selection control unit 150 generates the selection signal UDSEL corresponding to the address of the row address XADD_M when activating the bank active signal BANKACT.

Here, the bank active signal BANKACT is a signal for activating the bank. And, the row address XADD_M is an address corresponding to the most significant bit of the row address. The selection signal UDSEL is a signal enabled by the most significant bit of the row address XADD_M, and has information on the mat MAT0 to MATn provided in the bank.

For example, when the row address XADD_M is enabled, both the upper bank UBK and the lower bank DBK operate. When the row address XADD_M is disabled, only the lower mat DBK operates with the bank separator 140 as a reference.

The selection control unit 150 includes a NAND gate ND1 for NANDing the bank active signal BANKACT and the row address XADD_M. The NAND gate ND1 performs a NAND operation on the bank active signal BANKACT and the row address XADD_M to output the select signal UDSEL.

The selection control unit 150 outputs the selection signal UDSEL at a low level when both the bank active signal BANKACT and the row address XADD_M are activated to the high level. That is, when the corresponding bank is active and the error address occurs at half or less of a single bank, the selection signal UDSEL becomes low level.

In this case, the bank separator 140 is disconnected so that the upper local lines LIOU and LIOBU of the upper bank UBK and the lower local lines LIOD and LIOBD of the lower bank DBK are separated from each other. Then, only the lower bank DBK operates, and the read or write operation is performed by the connection control signal IOSW <n / 2 + 1: n>.

Accordingly, only half of the lower local lines LIOD and LIOBD operate in the read or write operation, thereby reducing the load on the local input / output lines, thereby reducing current consumption.

At this time, the upper bank UBK which is not operated separately from the lower bank DBK is precharged by the upper prechach unit 160. That is, the upper precharge section 160 precharges the upper local lines LIOU and LIOBU of the upper bank UBK.

The selection control unit 150 activates the selection signal UDSEL to a high level when both the bank active signal BANKACT and the row address XADD_M are at a low level or at least one of them is a low level.

In this case, the bank separation unit 140 is connected to the selection signal UDSEL. Accordingly, the upper bank UBK and the lower bank DBK are connected to operate in a single bank unit.

3 is a detailed circuit diagram of the power supply control unit 210 of FIG.

The power control unit 210 includes a combining unit 211 and a power selection unit 212.

Here, the combination unit 211 outputs the power-on enable signals YDD1YEN and YDD2YEN by combining the bank active signal BANKACT and the row address XADD_M.

The combination unit 211 includes a plurality of NAND gates ND2 and ND3 and a plurality of inverters IV1 to IV3.

NAND gate ND2 performs a NAND operation on the row address XADD_M inverted by the bank active signal BANKACT and the inverter IV1. The inverter IV2 inverts the output of the NAND gate ND2 and outputs a power enable signal YDD1YEN.

Then, the NAND gate ND3 performs a NAND operation on the bank active signal BANKACT and the row address XADD_M. The inverter IV3 inverts the output of the NAND gate ND3 and outputs a power enable signal YDD2YEN.

The power source selection unit 212 selects the power source VDD2Y or the power source VDD1Y corresponding to the power enable signals YDD1YEN and YDD2YEN, and outputs the power source signal VDDY. The power source selection unit 212 includes NMOS transistors N17 and N18 which are pull-down driving elements.

Here, the NMOS transistor N17 is connected between the power supply VDD1Y application terminal and the output terminal of the power supply signal VDDY, and the power supply enable signal YDD1YEN is applied through the gate terminal. The NMOS transistor N18 is connected between the power supply VDD2Y supply terminal and the output terminal of the power supply signal VDDY, and the power supply enable signal YDD2YEN is applied through the gate terminal.

When the loading of the local input / output line is reduced during the read operation and the charge sharing increases, the pre-charge current may increase. Accordingly, the embodiment of the present invention varies the power supplied to the column decoder 200 so that the upper local lines LIOU, LIOBU, lower local lines LIOD, and LIOBD have the same operation swing width.

4 and 5 are operation timing diagrams for explaining the operation of the semiconductor device according to the embodiment of the present invention.

When the active command ACT is externally applied in response to the clock CLK, the row address XADD is input. When the active command ACT is applied and a predetermined time is delayed, the bank active signal BANKACT is activated.

For example, when the upper bank UBK is active, the bank active signal BANKACT becomes a high level, and the row address XADD_M is input to the low level as shown in FIG. That is, when the row address XADD_M corresponds to the upper bank UBK (for example, n / 2-3) of a single bank, the row address XADD_M is input to the low level.

Then, the selection signal UDSEL is activated to a high level to connect the bank separator 140. Then, the power-on enable signal YDD1YEN becomes a high level, and the power-on enable signal YDD2YEN becomes a low level.

Thus, the NMOS transistor N17 is turned on and the power supply signal VDDY is output to the power supply VDD1Y level. That is, when both the upper bank UBK and the lower bank DBK are operated, the power supply signal VDDY is supplied at the voltage level of the power supply VDD1Y higher than the power supply VDD2Y.

On the other hand, when only the lower bank DBK is active, the bank active signal BANKACT becomes high level, and the row address XADD_M transits to the high level as shown in Fig. That is, when the row address XADD_M corresponds to the lower bank UBK (for example, n / 2 + 3) of a single bank, the row address XADD_M is input to the high level.

Then, the selection signal UDSEL is inactivated to a low level, and the bank separator 140 is interrupted. Then, the power-on enable signal YDD2YEN becomes a high level, and the power-on enable signal YDD1YEN becomes a low level.

As a result, the NMOS transistor N18 is turned on and the power supply signal VDDY is output to the power supply VDD2Y level. That is, when the lower bank DBK operates, the power supply signal VDDY is supplied at the voltage level of the power supply VDD2Y lower than the power supply VDD1Y.

Depending on whether both the upper bank UBK and the lower bank DBK operate or only the lower bank DBK operates, the loading value on the local input / output line is changed. The power supply level supplied to the column decoder 200 is varied in order to have the same operation characteristics in response to the change of the loading value.

That is, when the column selection signal YI is activated, both the column selection unit 100 of the upper bank UBK and the column selection unit 120 of the lower bank DBK operate. In the structure in which the upper bank UBK and the lower bank DBK are separated from each other, when only the lower bank DBK is operated, current consumption becomes larger when the column selecting unit 100 of the upper bank UBK operates.

Accordingly, in the embodiment of the present invention, when both the upper bank UBK and the lower bank DBK operate, the driving voltage is increased by supplying a high voltage power VDD1Y to the column decoder 200. When only the lower bank DBK is operated, the column decoder 200 ) To supply a low-voltage power supply VDD2Y to reduce current consumption.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. It is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents. .

Claims (20)

An upper bank connected to an upper local line for inputting / outputting data of the upper mat;
A lower bank connected to a lower local line for inputting / outputting data of the lower mat;
A bank separator for selectively connecting the upper local line and the lower local line in response to a selection signal; And
And a selection control unit for generating the selection signal in correspondence with the bank active signal and the row address. The method according to claim 1,
Wherein the upper bank and the lower bank are divided into an upper region and a lower region in a single bank. The apparatus of claim 1, wherein the upper bank
A plurality of upper mats connected to bit lines;
A first column selector for selectively connecting the bit line and the segment line in response to a column select signal; And
And a first connection unit for selectively connecting the segment line and the upper local line in response to a connection control signal. The apparatus of claim 1, wherein the lower bank
A plurality of bottom mats connected to the bit lines;
A second column selector for selectively connecting the bit line and the segment line in response to a column select signal; And
And a second connection unit for selectively connecting the segment line and the lower local line in response to the connection control signal. The apparatus of claim 1, wherein the bank separator
And a plurality of NMOS transistors connected between the upper local line and the lower local line to receive the selection signal through a gate terminal. The method according to claim 1,
When the selection signal is activated, the bank separator is connected to operate both the upper bank and the lower bank,
And when the selection signal is inactivated, the bank separator is interrupted to operate the lower bank. The method according to claim 1,
And wherein the row address is the most significant bit. The apparatus of claim 1, wherein the selection control unit
When the row address is disabled when the bank active signal is activated, the selection signal is activated to connect the bank separator,
And when the row address is enabled at the time of activation of the bank active signal, the selection signal is inactivated and the bank separator is interrupted. The apparatus of claim 1, wherein the selection control unit
And a NAND gate for NANDing the bank active signal and the ROO address to output the select signal. The method according to claim 1,
Further comprising an upper precharge unit for precharging the upper local line when the selection signal is activated and only the lower bank is operated. The method according to claim 1,
Further comprising: a column controller for generating a column select signal for selecting a column line of the upper bank and the lower bank, and supplying a variable power source to the column line. 12. The apparatus of claim 11, wherein the column controller
A column decoder for generating a selection signal for selecting a column line of the upper bank and the lower bank; And
And a power controller for supplying variable power to the column decoder depending on whether the upper bank and the lower bank are selected. 13. The apparatus of claim 12, wherein the power control unit
Supplies a first power source to the column decoder when both the upper bank and the lower bank are selected and supplies a second power source lower than the first power source to the column decoder when only the lower bank is selected. . 13. The apparatus of claim 12, wherein the power control unit
A combination unit for outputting a first power supply enable signal and a second power supply enable signal by combining a bank active signal and a row address; And
And a power supply selector for supplying a first power supply or a second power supply lower than the first power supply in response to the first power supply enable signal and the second power supply enable signal. 15. The apparatus of claim 14,
The first power enable signal is activated when the bank active signal is activated and the Roo address is disabled,
And the second power-on signal is activated when the bank active signal is activated and the row address is enabled. The method according to claim 1,
A precharging unit for precharging the upper local line and the lower local line;
A sense amplifier for sensing and amplifying data of the lower local line; And
Further comprising: a write driver for driving external data to apply data to the lower local line. An upper bank connected to an upper local line for inputting / outputting data of the upper mat;
A lower bank connected to a lower local line for inputting / outputting data of the lower mat;
A bank separator for selectively connecting the upper local line and the lower local line in response to a selection signal;
A selection control unit for generating the selection signal corresponding to the bank active signal and the row address;
A column controller for generating a column select signal for selecting a column line of the upper bank and the lower bank and supplying a variable power to the column line depending on whether the upper bank and the lower bank are selected; And
And a precharge unit for selectively precharging the upper local line and the lower local line. 18. The method of claim 17,
When the selection signal is activated, the bank separator is connected to operate both the upper bank and the lower bank,
And when the selection signal is inactivated, the bank separator is interrupted to operate the lower bank. An upper bank connected to an upper local line for inputting / outputting data of the upper mat;
A lower bank connected to a lower local line for inputting / outputting data of the lower mat;
A bank separator for selectively connecting the upper local line and the lower local line in response to a selection signal;
A selection control unit for generating the selection signal corresponding to the bank active signal and the row address;
An upper precharging unit for precharging the upper local line when only the lower bank is operated corresponding to the selection signal; And
And a precharge unit for precharging the upper local line and the lower local line when the upper bank and the lower bank operate in response to the selection signal. 20. The method of claim 19,
When the selection signal is activated, the bank separator is connected to operate both the upper bank and the lower bank,
And when the selection signal is inactivated, the bank separator is interrupted to operate the lower bank.
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