KR20170020045A - Mixed voltage neutral point clamped type multi-level inverter having no dead-time - Google Patents

Abstract

The present invention relates to an MNPC-type multi-level inverter, comprising: a multi-level power supply unit to which at least one voltage source is connected; A first switching unit which forms an input node between at least one voltage source and is connected to a first line and a second line branched from the input node, respectively, to switch the output voltage of the power supply unit; And the output node of the first line and the output line of the second line are respectively branched to the first output line and the second output line so that the forward output current and the reverse output current have different paths from each other, And a second switching unit for preventing the first switching unit and the power supply unit from being short-circuited when the output voltage is switched by the switching of the first switching unit and the second switching unit.
The multi-level inverter having this circuit configuration has an effect that it can be driven without a dead time.

Description

MIXED VOLTAGE NEUTRAL POINT CLAMPED TYPE MULTI-LEVEL INVERTER HAVING NO DEAD-TIME "

The present invention relates to a multi-level inverter of a mixed voltage neutral point clamped (MNPC) type, and more particularly to a multi-level inverter capable of switching an output voltage without dead time.

Figure 1 below shows a conceptual diagram of a multilevel inverter that generates an AC output voltage waveform from a series connected DC input power supply.

[Figure 1]

[Figure 1] is a conceptual diagram showing a phase of a 5-level inverter in which four voltage sources are connected in series as an example of a multi-level inverter. As shown in Figure 1, the multilevel inverter has a circuit configuration that can output one of several stages of DC input voltage (V1, V2, V3, V4, V5) to the output like a multiplexer used in signal processing . The SPMT switch (Single-Pole Multiple-Through Switch) changes the contact point in a predetermined cycle in a predetermined cycle and finally generates an output voltage of the AC waveform.

Several types of multi-level inverters conceptually expressed in [Figure 1] have been proposed depending on the circuit configuration method. N-level multilevel inverters with a common arbitrary N level have a Neutral Point Clamped (NPC) scheme, which was first proposed in the early 1990s, and thereafter various types of multi-level inverter configurations that have improved the disadvantages of the NPC scheme. T-type Neutral Poined Clamped (MNPPC), Advanced Neutral Poined Clamped (ANPC), and Cascade.

The following [Figure 2] shows a MNPC-type multilevel inverter, which is a half-bridge circuit configuration of a 5-level inverter.

[Figure 2]

2, the half-bridge 5-level inverter consists of 8 IGBT power semiconductor switches (Q1 ~ Q8) and 8 power semiconductor diodes (D1 ~ D8). Diodes connected in parallel to Q2 to Q7 except diodes D1 and D8 connected in parallel with IGBT semiconductor switches (Q1 to Q8) do not substantially affect the operation of the circuit and can be omitted. Generally, an IGBT It is shown in the circuit diagram because it actually exists as a diode that is inserted automatically when it is produced.

Table 1 below shows the switching table of the 5-level MNPC inverter shown in [Fig. 2] above.

[Table 1]

In Table 1, a value of 0 indicates the off state of the IGBT switch, and a value of 1 indicates the on state of the IGBT switch. Looking at the switching logic in [Table 1], four IGBT switches always operate in the ON state. In this case, the Q1 switch operates complementarily with the Q5 switch, the Q2 switch operates complementarily with the Q6 switch, the Q3 switch operates complementarily with the Q7 switch, and the Q4 switch operates complementarily with the Q8 switch Is controlled.

For example, when the Q1, Q2, Q3 and Q4 switches are turned on and the Q5, Q6, Q7 and Q8 switches are turned off, the output point Po is connected to P1, and the output voltage Vo is switched to V1. When Q1, Q2, Q3 and Q4 are turned on at the same time, the reverse voltage is applied to D2, D3 and D4 due to the Q1 switch turned on, so that no current flows even though Q2, Q3 and Q4 are turned on.

Is a forward direction that flows from P1 to Po

Current flows through the Q1 switch,

Is in the reverse direction from Po to P1

Current flows through D1.

To switch the output voltage from V1 to V2, the control method of the switch is to turn off the Q1 switch and turn on the Q5 switch at the same time. At this time, when the Q5 switch is turned on, Po is connected to P2, so that the Q1 switch or the D1 diode

The current is changed to flow through the Q2 switch or the Q5 switch. The process of changing the path through which the current flows in this way is called commutation.

Theoretically, there is no problem that the Q1 switch is turned on while the Q1 switch is turned off at the same time, but in a practical case, a serious problem may occur. If the process of turning off the switch Q1 is delayed a little, a situation may occur in which the switch Q5 is turned on while the switch Q1 is still on. In this case, short-circuiting of the DC power source occurs along the path leading to P1-Q1-Q5-D5-P2, causing inverter damage due to excessive current.

The solution to this problem is to control the Q5 switch to turn on after a certain time interval ensuring that the Q1 switch is completely off. That is, the Q1 switch is turned off at a predetermined time, but the Q5 switch is slightly delayed. The delay time when the turn-on time of the IGBT switch that is turned on during the turn-on and turn-off of the two IGBT switches is slightly delayed is referred to as a dead time.

Therefore, the dead time in the conventional inverter is one of the matters to be considered in designing the gating signal generating circuit of the actual inverter. During the dead time, the output voltage is not determined according to the switching table in [Table 1] but is determined according to the direction of the output current.

For example, during the transition of the output voltage from V1 to V2, the output voltage during the dead time is V1 or V2 depending on the direction of the output current. In the process of converting the output voltage from V1 to V2, only the Q2, Q3 and Q4 switches are on during the dead time. At this time,

Is greater than 0 (referred to as positive direction), current flows in the direction of P2-D2-Q2-Po,

Is less than 0 (referred to as reverse direction), current flows in the direction of Po-D1-P1.

Accordingly,

Is 0 or more

Becomes V2,

Is a reverse direction with 0 or less

Becomes V1. This is because the Q3 switch and the Q4 switch are not turned on during the dead time because the reverse voltage is applied to the D3 diode and the D4 diode even if the Q3 switch is on.

In the operation of the inverter, the dead time is essential for the safe operation of the inverter. However, since the output voltage waveform of the inverter is distorted, the harmonics of the output voltage waveform are increased, the efficiency of the inverter is decreased, and the control performance is deteriorated.

In addition, the dead time has a problem of reducing the fundamental wave size of the output voltage waveform and lowering the utilization rate of the DC input voltage. When a high-voltage large-capacity system such as a multi-level inverter is constructed, a relatively long dead time is required for a low-voltage small-capacity inverter for safe operation. In this situation, it is desirable that the dead time of the inverter be as short as possible and ultimately it is best to remove it.

There are a number of prior art devices and methods for compensating the inverter output distortion caused by the dead time (Korean Patent Laid-Open No. 10-2013-0081353, etc.). However, the prior art to date has a limitation in not disclosing a control method or a circuit diagram that can ultimately eliminate dead time.

Korean Patent Publication No. 10-2014-0081353

The present invention intends to provide a multilevel inverter having a circuit diagram capable of operating without a dead time in an MNPC type multilevel inverter. In particular, the present invention aims to provide a multi-level inverter capable of stably switching the output voltage without dead time by controlling the semiconductor switch in consideration of the direction of the output current, without shorting the power supply when the output voltage is switched.

The present invention also provides a multi-level inverter having no dead time that can be extended to N-level regardless of the number of phases or the number of voltage levels in the MNPC type.

The present invention relates to an MNPC-type multi-level inverter, comprising: a multi-level power supply unit to which at least one voltage source is connected; A first switching unit which forms an input node between at least one voltage source and is connected to a first line and a second line branched from the input node, respectively, to switch the output voltage of the power supply unit; And the output node of the first line and the output line of the second line are respectively branched to the first output line and the second output line so that the forward output current and the reverse output current have different paths from each other, And a second switching unit for preventing the first switching unit and the power supply unit from being short-circuited when the output voltage is switched by the switching of the first switching unit and the second switching unit.

Preferably, the first switching unit according to the present invention is such that the first diode and the first semiconductor switch are connected in series so as to be positively biased in the first line, and the second diode and the second semiconductor switch are biased in the reverse direction in the second line They can be connected in series.

Preferably, the multi-level inverter according to the present invention further includes a control unit for controlling the second semiconductor switch to be off when the output current is positive and to turn off the first semiconductor switch when the output current is reverse can do.

Preferably, the second switching unit according to the present invention further comprises: a third semiconductor switch provided in the first output line and biased in the positive direction; A third diode having an input terminal connected to the voltage source and an output terminal connected to the output node of the first output line; A fourth semiconductor switch provided on the second output line and biased in the reverse direction; And a fourth diode having an input coupled to the output node of the second output line and an output coupled to the voltage source.

Preferably, the third semiconductor switch according to the present invention may be connected between one end (P1) of the power supply part and the output node of the first output line.

Preferably, the third diode according to the present invention may be connected between the other end (P5) of the power supply unit and the output node of the first output line.

Preferably, the fourth semiconductor switch according to the present invention may be connected between the other end (P5) of the power supply unit and the output node of the second output line.

Preferably, the fourth diode according to the present invention may be connected between one end (P1) of the power supply part and the output node of the second output line.

Preferably, the multi-level inverter according to the present invention may further include an inductor unit connected to an output terminal of the second switching unit to limit a short-circuit current.

Preferably, the inductor unit according to the present invention comprises: a first inductor connected in series with the output terminal of the first output line; And a second inductor connected in series with the output terminal of the second output line.

Preferably, the multi-level inverter according to the present invention may further include a third inductor connected in series between the inductor unit and the load to remove harmonics of the output current supplied to the load.

Further, the present invention provides an MNPC-type multi-level inverter comprising: a multi-level power supply unit to which at least one voltage source is connected; A first switching unit connected in parallel with a second semiconductor switch (Q5) biased in the opposite direction to a first semiconductor switch (Q2) in which a current outputted from the power supply unit is biased in a forward direction; A third semiconductor switch Q1 connected between one end P1 of the power supply unit and the first semiconductor switch Q2 and a fourth semiconductor switch Q8 connected between the other end P5 of the power supply unit and the second semiconductor switch Q5, And a second switching unit having a first switching unit and a second switching unit.

Preferably, the multilevel inverter according to the present invention controls the first semiconductor switch Q2 and the third semiconductor switch Q1 when the output current is forward, and the second semiconductor switch Q5 and the second semiconductor switch Q2 when the output current is reverse. The fourth semiconductor switch Q8 is controlled so that the output voltage can be stably switched without having a dead time.

Preferably, the second switching unit according to the present invention includes an output terminal of the first semiconductor switch Q2,

A first output line forming a first output line; And the output terminal of the second semiconductor switch (Q5) and the output node

The third semiconductor switch Q1 may be connected to the first output line and the fourth semiconductor switch Q8 may be connected to the second output line.

According to the present invention, in the MNPC-type multilevel inverter, since the output current in the forward direction and the output current in the reverse direction flow in different paths of the second switching unit, the switching unit, the first switching unit, And the circuit of the switching unit is not short-circuited.

In this case, if the control unit controls the semiconductor switch in accordance with the direction of the output current, no interval is required in the process of switching the output voltage. Therefore, the multi-level inverter having this circuit configuration has an effect that it can be driven without a dead time.

Also, according to the present invention, it is possible to expand the circuit configuration of the first switching unit and the second switching unit irrespective of the number of the configuration or the number of voltage sources. Therefore, there is an advantage that it can be widely applied to MNPC type inverters without dead time.

Thus, according to the present invention, there is an advantage that the distortion of the output voltage waveform can be eliminated, the utilization ratio of the DC voltage is increased, and the harmonic component of the output voltage waveform can be reduced. Further, according to the present invention, the linearity of the inverter is increased, the control performance and reliability are remarkably improved, and the life of the inverter can be expected to be improved.

1 shows a circuit diagram of a multi-level inverter of a half bridge configuration according to an embodiment of the present invention.
Fig. 2 shows an equivalent circuit when the output current of the multi-level inverter according to the embodiment of the present invention is forward.
FIG. 3 is a graph showing the output current of the multi-level inverter according to the embodiment of the present invention

) Is the reverse direction.
4 illustrates a half bridge configuration in which a multi-level inverter according to an embodiment of the present invention is extended to an arbitrary N-level inverter.
5 shows a three-phase circuit configuration of a 5-level inverter according to an embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to or limited by the exemplary embodiments. Like reference numerals in the drawings denote members performing substantially the same function.

The objects and effects of the present invention can be understood or clarified naturally by the following description, and the purpose and effect of the present invention are not limited by the following description. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

1 shows a circuit diagram of a multi-level inverter 1 in a half bridge configuration according to an embodiment of the present invention. 1, the multilevel inverter 1 may include a power supply unit 10, a first switching unit 30, a second switching unit 50, and an inductor unit 70.

The power supply unit 10 may be connected to one or more voltage sources in series. An input node may be formed between the voltage source and the voltage source by the first switching unit 30, which will be described later. Hereinafter, a node formed between a voltage source and a voltage source is referred to as an input node.

In this embodiment, FIG. 1 shows a five-level inverter in which four DC voltage sources are connected. Since four DC voltage sources are provided, a total of five input nodes can be formed. This is an example of five levels of the power supply unit 10, and the level of the inverter according to the number of voltage sources can be expanded to the same principle.

The input node may be a P1 node to which the V1 voltage is applied, a P2 node to which the V2 voltage is applied, a P3 node to which the V3 voltage is applied, a P4 node to which the V4 voltage is applied, and a P5 node to which the V5 voltage is applied. Each DC voltage source provided in the power supply unit 10 has a voltage difference between the P1 node and the P5 node

Respectively.

The input nodes P1, P2, P3, P4, and P5 to which the power of five levels are inputted are connected to the output nodes (first, second, third,

or

). Accordingly, the multi-level inverter 1 can continuously output the DC voltage as the AC voltage waveform by continuously switching V1 or V2 or V3 or V4 or V5.

The first switching unit 30 forms an input node P2 between at least one voltage source and the semiconductor switches Q2 and Q5 are connected to the first line and the second line branched from the input node P2, The output voltage of the inverter 10 can be switched.

The first switching unit 30 may be connected in parallel with the first semiconductor switch Q2 whose current is biased in the forward direction and the second semiconductor switch Q5 which is biased in the opposite direction. In this embodiment, the semiconductor switch of the first switching unit 30 may be provided as an IGBT switch.

The plurality of first switching units 30 may be connected between the voltage source and the voltage source. 1, three first switching units 30 may be connected to form the input nodes P2, P3 and P4 between the four voltage sources. Hereinafter, for convenience of explanation, the first switching unit 30 forming the P2 node will be used as a reference.

The first switching unit 30 may be connected in series so that the first diode D2 and the first semiconductor switch Q2 are biased in the positive direction to the first line. The first switching unit 30 may be connected in series so that the second diode D5 and the second semiconductor switch Q5 are biased in the opposite direction to the second line.

In this specification, the terms forward and reverse are used to distinguish the direction in which current flows. In the forward direction,

Direction. That is, the forward current

. On the other hand,

The current flowing in the direction of the power source unit 10 is referred to as a current. That is, the reverse current

.

In this specification, the first and second ordinal expressions are used to distinguish a plurality of semiconductor switches and diodes. In other words, in this specification, the first switching unit 30 connected to the P2 input node is exemplarily described, and the Q3 and Q4 semiconductor switches connected to the first line by the same principle can be understood as the first semiconductor switch Q2, The Q6 and Q7 semiconductor switches connected to the two lines can be understood as the second semiconductor switch Q5.

The second switching unit 50 is connected to the output node of the first line and the output node of the second line,

,

) To form a forward output current (

) And the reverse output current (

May be branched to the first output line and the second output line so as to flow in different paths. Accordingly, when the output voltage is switched by the switching of the third semiconductor switch Q1 or the fourth semiconductor switch Q8, the second switching unit 50 is turned off when the first switching unit 30 and the power supply unit 10 are short- Can be prevented.

The second switching unit 50 is connected between the output terminal of the first semiconductor switch Q2 and the output node

) And the output terminal of the second semiconductor switch (Q5) and the output node

To the second output line forming the second output line.

The second switching unit 50 includes a third semiconductor switch Q1 connected between one end P1 of the power supply unit 10 and the first semiconductor switch Q2 and the other end P5 of the power supply unit 10, And a fourth semiconductor switch Q8 connected between the first and second semiconductor switches Q5 and Q5. The second switching unit 50 may include a third diode D8 and a fourth diode D1. In this embodiment, the third and fourth semiconductor switches Q1 and Q8 may be provided as IGBT switches.

The second switching unit 50 branches the output point of the first switching unit 30 to thereby divide the path of the current due to the switching. The current flowing through the second switching unit 50 is the output of the first output line

Node and the output terminal of the second output line

Lt; / RTI > node.

In this specification, an output node (

,

Is a node to which the voltages of the input nodes P1, P2, P3, P4 and P5 are applied in accordance with the switching, and this means the output terminal of the second switching unit 30. Or a point where the first switching unit 30 and the second switching unit 50 are connected in circuit.

According to the circuit configuration of the second switching unit 50, the dead time is not generated in the multilevel inverter 1 according to the present embodiment. The fact that the dead time is not generated when the semiconductor switches Q1 to Q8 are switched by the first switching unit 30 and the second switching unit 50 according to the present embodiment will be described later in conjunction with switching of the control unit.

The second switching unit 50 may include a third semiconductor switch Q1, a fourth semiconductor switch Q8, a third diode D8 and a fourth diode D1.

The third semiconductor switch Q1 is provided in the first output line and biased in the positive direction. The third semiconductor switch Q1 is connected between one end P1 of the power supply unit 10 and the output node of the first output line

). ≪ / RTI > The third diode D8 has an input terminal connected to the voltage source and an output terminal connected to the output node of the first output line

.

That is, the third semiconductor switch Q1 and the third diode D8 are connected to the upper and lower ends of the first output line, respectively, irrespective of the number of the first switching units 30. Therefore, even if a higher level expansion occurs in the power supply unit 10,

, The third semiconductor switch Q1 and the third diode D8 are connected to each other. Therefore, the second switching unit 50 has a structure capable of expanding the circuit.

The fourth semiconductor switch Q8 is provided on the second output line and can be biased in the reverse direction. The fourth semiconductor switch Q8 is connected to the other end P5 of the power supply section 10 and the output node

). ≪ / RTI > The fourth diode D1 has an input terminal connected to the output node of the second output line

And the output terminal may be connected to the voltage source.

That is, the fourth semiconductor switch Q8 and the fourth diode D1 are connected to each other at the lower end and the upper end of the second output line irrespective of the number of the first switching units 30. FIG. Therefore, even if a higher level expansion occurs in the power supply unit 10,

And the fourth switch Q8 is connected to the fourth diode D1 and the fourth semiconductor switch Q8. Therefore, the second switching unit 50 has a structure capable of expanding the circuit.

The multilevel inverter 1 according to the present embodiment controls the first semiconductor switch Q2 and the third semiconductor switch Q1 when the output current is forward and the second semiconductor switch Q5 when the output current is reverse. And the fourth semiconductor switch (Q8) are controlled and have no dead time. The switching table of the related control unit will be described later.

The inductor unit 70 is connected to the output terminal of the second switching unit 50

,

) To limit the short-circuit current. The inductor unit 70 can limit the short circuit current of the circuit that may occur in the commutation process. The circuit diagram according to the present embodiment may cause a short circuit in the course of switching the direction of the current. The inductor unit 70 is connected to the output terminal of the first output line

And the output terminal of the second output line

And prevents the short circuit of the circuit which may be generated in switching between the forward direction and the reverse direction of the output current.

The inductor unit 70 includes a first inductor

) And the second inductor

). The first inductor

Is connected to the output terminal of the first output line

) Connected in series. The second inductor

Is connected to the output terminal of the second output line

) Connected in series.

The first inductor

) And the second inductor

Regardless of the level expansion of the power supply unit 10 or the first switching unit 30, the output terminal of the first output line

And the output terminal of the second output line

Respectively. Therefore, the inductor unit 70 has a structure capable of expanding the circuit.

In this embodiment, the multilevel interverter 1 includes a third inductor

). The third inductor

Is connected between the inductor unit 70 and the load (

) Connected in series between the load (

) Of the output current (

) Can be removed.

Although not shown in FIG. 1, the multilevel inverter 1 may further include a controller for controlling the first switching unit 30 and the second switching unit 50. In this circuit configuration, the control section can switch the semiconductor switches Q1 to Q8 without a dead time.

In this case, the control unit according to the present embodiment, unlike the conventional case,

) To detect the output current (

The semiconductor switches Q1 to Q8 are operated. At this time, the control unit outputs the output current

) Is forward (

), The second semiconductor switch Q5 is turned off, and the output current (

) Is in the reverse direction

), The first semiconductor switch Q2 can be controlled to be turned off.

More precisely, the control unit controls the output current

) Is forward (

), The second semiconductor switches Q5, Q6, Q7 and the fourth semiconductor switch Q8 are controlled to be always OFF. In addition,

) Is in the reverse direction

), The first semiconductor switches Q2, Q3, and Q4 and the third semiconductor switch Q1 are always kept in the OFF state.

The switching table of the control unit is shown in Table 2 below. Hereinafter, the switching control of the controller and the switching of the output voltage without a dead time will be described in detail with reference to Table 2 below.

[Table 2]

The multilevel inverter 1 according to FIG. 1 is controlled by the second switching unit 50 to output the output current

) Can be divided into a forward direction and a reverse direction. Figure 2 shows the output current

) Is the forward direction.

Figure 2 shows the output current

The first switching unit 30 has the first diode D2, D3, and D4 and the first semiconductor switch Q2, Q3, and Q4 in the first line. The second switching unit 50 omits the second output line because only the first output line connected to the first line is interpreted.

end. Output Current (

) Is the forward direction.

> 0)

Referring to FIG. 2 and [Table 2], the output current

) Is a positive current having a positive value, the output node

The semiconductor switches Q5, Q6, Q7 and Q8 to all the gates connected to the reverse current

) Becomes zero. In this state, the output current

)

And

Is determined according to the switching states of the third semiconductor switch Q1 and the first semiconductor switches Q2, Q3, and Q4. The principle that the output voltage is switched by the switching control in the control unit is as follows.

In FIG. 2, when the switches Q1, Q2, Q3, and Q4 are all turned on

Is supplied through Q1,

Is V1. This is because the reverse voltage is applied to the diodes D2, D3, D4 and D8 by the turned-on switch Q1, so that all the paths of D2, D3, D4 and D8 are cut off.

On the other hand, when Q1 is turned off (turn-off) and both Q2, Q3 and Q4 are turned on,

Is supplied via Q2

Is V2. This is because the reverse voltage is applied to the diodes D3 and D4 and the diode D8 by the turned-on switch Q2, and the paths of D3, D4 and D8 are cut off.

On the other hand, when the switches Q1 and Q2 are turned off and the switches Q3 and Q4 are both turned on,

Is supplied through Q3

Is V3. This is because the reverse voltage is applied to the diodes D4 and D8 by the turned-on switch Q3, so that the paths of D4 and D8 are all cut off.

On the other hand, when the switches Q1, Q2 and Q3 are turned off and the switch Q4 is turned on,

Is supplied through the switch Q4

Becomes V4. This is because the reverse voltage is applied to the diode D8 by the turned-on switch Q4 and the path of D8 is cut off.

On the other hand, when the switches Q1, Q2, Q3 and Q4 are all turned off,

Is supplied via D8

Becomes V5. This is because the switches Q1, Q2, Q3 and Q4 are all turned off, so that only diode D8 provides the only path for supplying the output current.

The commutation process of For example, in order to commutate the output voltage from V1 to V2, the control unit applies a turn-on gating signal to the switches Q1, Q2, Q3 and Q4 and then applies a turn-off signal to the switch Q1, The turn-on signal may be continuously applied to the switches Q2, Q3, and Q4.

Turning off the switch Q1 to convert the output voltage from V1 to V2 results in a current

Is immediately commutated to Q2, which is already given a turn-on gating signal, and the output voltage is immediately changed from V1 to V2. That is, the output voltage of V1 or V2 is determined depending on whether the switch Q1 is turned on or off while the switches Q2, Q3 and Q4 are turned on, and no dead time is required in the process of switching between the two voltages.

Figure 3 shows the output current

) Is the reverse direction. Referring to FIG. 3,

The first switching unit 30 has the second diode D5, D6, D7 and the second semiconductor switch Q5, Q6, Q7 in the second line, The second switching unit 50 omits the first output line because only the second output line connected to the second line is interpreted.

I. Output Current (

) In the reverse direction (

<0)

Is a reverse current having a negative value, the output node

When the semiconductor switches Q1, Q2, Q3, and Q4 connected to all the gates are turned off

Becomes zero. In this state, the output current

)

Current

Is determined according to the switching states of the second semiconductor switches (Q5, Q6, Q7) and the fourth semiconductor switch (Q8). The principle that the output voltage is switched by the switching control in the control unit is as follows.

3, when the switches Q5, Q6, Q7 and Q8 are all turned on,

Is introduced through Q8

Becomes V5. This is because a reverse voltage is applied to the diodes D1, D5, D6 and D7 by the turned-on switch Q8, and all the paths of D1, D5, D6 and D7 are cut off.

On the other hand, when the switch Q8 is turned off and the switches Q5, Q6 and Q7 are both turned on,

Is introduced through Q7

Becomes V4. This is because a reverse voltage is applied to the diodes D1, D5, and D6 by the turned-on switch Q7 to cut off the paths of D1, D5, and D6.

On the other hand, when the switches Q7 and Q8 are turned off and the switches Q5 and Q6 are both turned on,

Is supplied via Q6

Is V3. This is because the reverse voltage is applied to the diodes D1 and D5 by the turned-on switch Q6 and the paths of D1 and D5 are cut off.

On the other hand, when the switches Q6, Q7 and Q8 are turned off and the switch Q5 is turned on,

Is supplied through Q5,

Is V2. This is because the reverse voltage is applied to the diode D1 by the turned-on switch Q5, and the path of the diode D1 is cut off.

On the other hand, when the switches Q5, Q6, Q7 and Q8 are all turned off,

Is supplied through D1,

Is V1. This is because the switches Q5, Q6, Q7 and Q8 are both turned off, so that only diode D1 provides the only path for the output current to flow.

The commutation process of For example, in order to commutate the output voltage from V1 to V2, the control unit applies a turn-off signal to switches Q5, Q6, Q7 and Q8, The turn-off signal may be continuously applied to the switches Q6, Q7 and Q8.

When the switch Q5 is turned on to convert the output voltage from V1 to V2, a reverse voltage is applied to the diode D1 at the same time as the switch Q5 is turned on so that the path of D1 is cut off and the current is commutated immediately to Q5, To V2 immediately. That is, the output voltage of V2 or V1 is determined depending on whether the switch Q5 is turned on or off while the switches Q6, Q7 and Q8 are turned off, and no dead time is required in the process of switching between the two voltages.

As described above, the switching state of the [Table 2]

Is forward (

> 0) Controls the switches Q5, Q6, Q7 and Q8 to be in the off state regardless of the output voltage,

Is in the reverse direction (

<0) It can be seen that the switches Q1, Q2, Q3, and Q4 are controlled to be in an off state regardless of the output voltage.

The multi-level inverter 1 according to the present embodiment has the forward output current

And the reverse output current

Flows in different paths, and there is no risk of short circuit because the path of current switching is not overlapped. When the switch Q1 is in the forward direction and the switch Q5 is in the reverse direction, the control unit can switch the output voltage to either V1 or V2 depending on whether the switch Q5 is on or off. According to the control method of the control unit, no dead time is required during the voltage switching process in the circuit configuration.

4 shows a half bridge configuration in which a multi-level inverter 1 according to an embodiment of the present invention is extended to an arbitrary N-level inverter. 5 shows a three-phase circuit configuration of the 5-level inverter 1 according to the embodiment of the present invention.

4, 2 (N-1) IGBT semiconductor switches and 2 (N-1) power semiconductor diodes are provided to constitute an N-level inverter having N-1 DC voltage sources connected to the power supply unit 10 . Accordingly, even though the (N-2) number of the first switching units 30 are added in parallel, the second switching unit 50 increases the number of output nodes connected to the first switching unit 30 There is no change in circuit configuration.

The first inductor of the inductor unit 70

) And the second inductor

Are connected to only one of the first output line and the second output line, even if the level is extended. In this embodiment, the first inductor

) And the second inductor

) Can be designed to have the same value.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. will be. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by all changes or modifications derived from the scope of the appended claims and equivalents of the following claims.

1: Multi-level inverter
10:
30: First switching unit
50:
70: Inductor part

Claims (14)

In a multi-level inverter of the MNPC type,
A multi-level power supply unit to which at least one voltage source is connected;
A first switching unit for forming an input node between the at least one voltage source and a semiconductor switch connected to a first line and a second line branched from the input node to switch an output voltage of the power source unit; And
An output node of the first line and an output node of the second line are respectively branched into the first output line and the second output line so that the forward output current and the reverse output current flow in different paths, And a second switching unit for preventing the first switching unit and the power supply unit from being short-circuited when the output voltage is switched by the switching of the semiconductor switch,
Wherein the inverter has no dead time.
The method according to claim 1,
Wherein the first switching unit comprises:
A first diode and a first semiconductor switch are serially connected to bias the first line in a positive direction,
And the second diode and the second semiconductor switch are connected in series so as to be biased in the opposite direction to the second line.
3. The method of claim 2,
Further comprising a control section for controlling the second semiconductor switch to be off when the output current is positive and to turn off the first semiconductor switch when the output current is reverse.
The method according to claim 1,
Wherein the second switching unit comprises:
A third semiconductor switch provided on the first output line and biased in a positive direction;
A third diode having an input coupled to the voltage source and an output coupled to an output node of the first output line;
A fourth semiconductor switch provided on the second output line and biased in the reverse direction; And
And a fourth diode whose input end is connected to the output node of the second output line and whose output end is connected to the voltage source.
5. The method of claim 4,
Wherein the third semiconductor switch comprises:
And is connected between one end (P1) of the power supply unit and the output node of the first output line.
5. The method of claim 4,
Wherein the third diode comprises:
And the other end (P5) of the power supply unit and the output node of the first output line.
5. The method of claim 4,
Wherein the fourth semiconductor switch comprises:
And the other end (P5) of the power supply unit and the output node of the second output line.
5. The method of claim 4,
Wherein the fourth diode comprises:
And is connected between one end (P1) of the power supply unit and the output node of the second output line.
The method according to claim 1,
Further comprising an inductor unit connected to an output terminal of the second switching unit to limit a short-circuit current.
10. The method of claim 9,
The inductor unit includes:
A first inductor connected in series with an output of the first output line; And
And a second inductor connected in series with an output terminal of the second output line.
10. The method of claim 9,
And a third inductor connected in series between the inductor unit and the load to remove harmonics of an output current supplied to the load.
In a multi-level inverter of the MNPC type,
A multi-level power supply unit to which at least one voltage source is connected;
A first switching unit connected in parallel with a second semiconductor switch (Q5) biased in the opposite direction to a first semiconductor switch (Q2) in which the current output from the power supply unit is biased in a positive direction; And
A third semiconductor switch Q1 connected between the one end P1 of the power supply unit and the first semiconductor switch Q2 and a fourth semiconductor switch Q8 connected between the other end P5 of the power supply unit and the second semiconductor switch Q5. And a second switching unit having a first switching unit,
The first semiconductor switch Q2 and the third semiconductor switch Q1 are controlled when the output current is in the forward direction and the second semiconductor switch Q5 and the fourth semiconductor switch Q8 are controlled when the output current is in the reverse direction, Wherein the inverter has no time.
13. The method of claim 12,
Further comprising a control section for controlling the second semiconductor switch (Q5) to be off when the output current is forward and to turn off the first semiconductor switch (Q2) when the output current is reverse. Level inverter.
13. The method of claim 12,
Wherein the second switching unit comprises:
The output terminal of the first semiconductor switch Q2 and the output node

A first output line forming a first output line; And
The output terminal of the second semiconductor switch Q5 and the output node

) Formed on the first output line,
Wherein the third semiconductor switch (Q1) is connected to the first output line and the fourth semiconductor switch (Q8) is connected to the second output line.

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