CN116317653A - Converter method and system based on ANPC topology for reducing voltage stress - Google Patents

Converter method and system based on ANPC topology for reducing voltage stress Download PDF

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Publication number
CN116317653A
CN116317653A CN202310247315.5A CN202310247315A CN116317653A CN 116317653 A CN116317653 A CN 116317653A CN 202310247315 A CN202310247315 A CN 202310247315A CN 116317653 A CN116317653 A CN 116317653A
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switching tube
turned
switching
level
signals
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薛嘉丰
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Xi'an Shenghong Electric Co ltd
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Xi'an Shenghong Electric Co ltd
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Priority to CN202310247315.5A priority Critical patent/CN116317653A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/487—Neutral point clamped inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/083—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the ignition at the zero crossing of the voltage or the current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53873—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with digital control

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)

Abstract

The invention provides a commutation method based on an ANPC topology for reducing voltage stress, which comprises the steps of generating a driving signal; the switching-on and switching-off of the switching tube is controlled by using a driving signal, S2 is kept to be normally on and S3 and S4 are kept to be normally off in the positive half cycle, and S1, S5 and S6 are switched in the process of converting the voltage of the neutral end O from zero level to positive level or from positive level to zero level; in the negative half cycle, keeping S3 normally on, S1 and S2 normally off, and S4, S6 and S5 switch during the transition of the voltage at neutral terminal O from zero level to negative level or from negative level to zero level. The invention divides the stable state of the system in the whole modulation period into P and O of the positive half period and N and O of the negative half period, and the P and O+ are mutually switched in the positive half period during normal operation; at zero level O+ and O-switch to each other; the switching between O-and N in the negative half cycle makes the system state switching smoother, especially O+ switching to P and O-to N switching, and the risk of the voltage stress born by the inner tube is greatly reduced.

Description

Converter method and system based on ANPC topology for reducing voltage stress
Technical Field
The invention relates to the technical field of circuits, in particular to an ANPC topology-based current conversion method and system for reducing voltage stress.
Background
As the installed capacity of energy storage products on the market continues to increase, individual modules also tend to be high powered. Due to the insufficient IGBT capacity, the conventional three-level NPC (Neutral point clamped ) topology faces the problem of IGBT module out-of-stock. The ANPC topology can replace the NPC topology by using three two-level modules, so that the problem of IGBT backout is solved.
Fig. 1 is a single phase NPC topology, with a long commutation path always present due to the uncontrollability of D5 and D6. For example, when the system is operated under the inversion condition, i.e. when u >0, i >0, the system switches between paths S1, S2 and paths D5, S2, which is a short commutation path; when the system works under the rectifying working condition, namely when u >0, i <0, the system is switched between paths 'D2 and D1' and paths 'S3 and D6', which is a short commutation path, and particularly when paths 'S3 and D6' are switched to paths 'D2 and D1', the S3 is subjected to larger turn-off stress, and the risk is larger.
The ANPC (Active Neutral Point Clamped, active clamp three level topology) topology is based on an NPC (Neutral point clamped, neutral point clamp) topology with two power switching devices with antiparallel diodes replacing the original clamp diodes. The flow change control becomes more complex due to the two more degrees of freedom. The prior art is slightly modified on the basis of NPC topology commutation control, namely S5 and S6 are turned on when S2 and S3 are simultaneously turned on, and S5 and S6 are turned off when S2 and S3 are simultaneously turned off. Therefore, although the commutation method is simple and can be slightly modified on the basis of the original NPC commutation control program, the biggest advantage of the ANPC topology cannot be exerted, a plurality of long commutation paths exist, and IGBT voltage stress is large.
Based on this, a new solution is needed.
Disclosure of Invention
According to an aspect of the present invention, there is provided a converter method based on an ANPC topology for reducing voltage stress, the ANPC converter including 6 switching tubes S1 to S6, wherein each switching tube is antiparallel connected to a diode, a first switching tube S1 and a fourth switching tube S4 are respectively connected to a positive terminal P and a negative terminal N of a dc network, a connection point of a fifth switching tube S5 and a sixth switching tube S6 is connected to a neutral terminal O of the dc network, and a connection point of a second switching tube S2 and a third switching tube S3 is connected to an ac network, the modulation method including:
generating a drive signal;
the drive signal is used for controlling the turn-off of each switching tube, wherein,
in the positive half cycle, the second switching tube S2 is kept normally on, the third switching tube S3 and the fourth switching tube S4 are kept normally off, the first switching tube S1 is turned on in the process that the voltage of the neutral end O is converted from zero level to positive level, the fifth switching tube S5 is turned off before the first switching tube S1 is turned on, and the sixth switching tube S6 is turned off before the fifth switching tube S5 is turned off and is turned on after the first switching tube S1 is completely turned on; in the process that the voltage of the neutral end O is changed from the positive level to the zero level, the first switching tube S1 is turned off, and the fifth switching tube S5 is turned on after the first switching tube S1 is turned off;
in the negative half cycle, the third switching tube S3 is kept normally on, the first switching tube S1 and the second switching tube S2 are kept normally off, the fourth switching tube S4 is turned on in the process that the voltage of the neutral end O is converted from zero level to negative level, the sixth switching tube S6 is turned off before the fourth switching tube S4 is turned on, the fifth switching tube S5 is turned off before the sixth switching tube S6 is turned off, and the fourth switching tube S4 is turned on after being completely turned on; in the process of the voltage of the neutral end O changing from the negative level to the zero level, the fourth switching tube S4 is turned off, and the sixth switching tube S6 is turned on after the fourth switching tube S4 is turned off.
In the converter method for reducing voltage stress based on the ANPC topology, the modulation method further comprises the following steps:
when the positive half-cycle zero-crossing level is switched, the third switching tube S3 is turned on, and the second switching tube S2 is turned off before the third switching tube S3 is turned on;
when the negative half-cycle zero-crossing level is switched, the second switching tube S2 is turned on, and the third switching tube S3 is turned off before the second switching tube S2 is turned on.
In the converter method based on the ANPC topology for reducing voltage stress, when the current of the MOSFET at the high voltage side is smaller than a preset threshold value, the comparison result signal is at a high level.
In the method for reducing voltage stress based on ANPC topology, the step of generating a driving signal includes:
outputting 3 paths of PWM signals to the CPLD by the DSP;
outputting 18 paths of PWM control signals to a driving plate by the CPLD;
the drive board outputs 18 drive signals to control the turn-off of each switch tube.
In the converter method based on the ANPC topology for reducing voltage stress provided by the invention, the step of outputting 18 paths of PWM control signals to the driving plate by the CPLD comprises the following steps:
the CPLD comprises three groups of modules, and each group of modules expands 1-path PWM signals input by the DSP into 6-path PWM temporary signals with dead zones;
generating 6 paths of PWM formal signals through time sequence control;
and sending the 6 paths of PWM formal signals into a driving board to generate 6 paths of switching tube driving signals.
In the method for reducing voltage stress based on ANPC topology, the time sequence control comprises a start-up time sequence and a shut-down time sequence, wherein,
in the starting time sequence, a fifth switching tube S5 and a second switching tube S6 are firstly started at the same time, then a second switching tube S2 or a third switching tube S3 is started, and finally a first switching tube S1 or a fourth switching tube S4 is started;
in the shutdown sequence, the first switching tube S1 and the fourth switching tube S4 are turned off simultaneously, then the second switching tube S2 and the third switching tube S3 are turned off simultaneously, and finally the fifth switching tube S5 and the second switching tube S6 are turned off simultaneously.
According to another aspect of the present invention, there is also provided an ANPC topology-based converter system for reducing voltage stress, the ANPC converter including 6 switching tubes S1 to S6, wherein each switching tube is antiparallel connected to a diode, a first switching tube S1 and a fourth switching tube S4 are respectively connected to a positive terminal P and a negative terminal N of a dc network, a connection point of a fifth switching tube S5 and a sixth switching tube S6 is connected to a neutral terminal O of the dc network, and a connection point of a second switching tube S2 and a third switching tube S3 is connected to an ac network, the modulation system comprising:
the driving signal generation module is used for generating a driving signal;
a modulation module for controlling the on/off of each switching tube by using the driving signal, wherein,
in the positive half cycle, the second switching tube S2 is kept normally on, the third switching tube S3 and the fourth switching tube S4 are kept normally off, the first switching tube S1 is turned on in the process that the voltage of the neutral end O is converted from zero level to positive level, the fifth switching tube S5 is turned off before the first switching tube S1 is turned on, and the sixth switching tube S6 is turned off before the fifth switching tube S5 is turned off and is turned on after the first switching tube S1 is completely turned on; in the process that the voltage of the neutral end O is changed from the positive level to the zero level, the first switching tube S1 is turned off, and the fifth switching tube S5 is turned on after the first switching tube S1 is turned off;
in the negative half cycle, the third switching tube S3 is kept normally on, the first switching tube S1 and the second switching tube S2 are kept normally off, the fourth switching tube S4 is turned on in the process that the voltage of the neutral end O is converted from zero level to negative level, the sixth switching tube S6 is turned off before the fourth switching tube S4 is turned on, the fifth switching tube S5 is turned off before the sixth switching tube S6 is turned off, and the fourth switching tube S4 is turned on after being completely turned on; in the process of the voltage of the neutral end O changing from the negative level to the zero level, the fourth switching tube S4 is turned off, and the sixth switching tube S6 is turned on after the fourth switching tube S4 is turned off.
In the converter system for reducing voltage stress based on the ANPC topology provided by the present invention, the modulation module is further configured to:
when the positive half-cycle zero-crossing level is switched, the third switching tube S3 is turned on, and the second switching tube S2 is turned off before the third switching tube S3 is turned on;
when the negative half-cycle zero-crossing level is switched, the second switching tube S2 is turned on, and the third switching tube S3 is turned off before the second switching tube S2 is turned on.
In the converter system based on the ANPC topology for reducing voltage stress, which is provided by the invention, the driving signal generation module comprises a DSP, a CPLD and a driving board, wherein the DSP outputs 3 paths of PWM signals to the CPLD; outputting 18 paths of PWM control signals to a driving plate by the CPLD; the drive board outputs 18 drive signals to control the on/off of each switch tube.
In the converter system based on the ANPC topology for reducing voltage stress, the CPLD comprises three groups of modules, and each group of modules expands 1-path PWM signals input by the DSP into 6-path PWM temporary signals with dead zones; generating 6 paths of PWM formal signals through time sequence control; and sending the 6 paths of PWM formal signals into a driving board to generate 6 paths of switching tube driving signals.
In the converter system based on the ANPC topology for reducing voltage stress provided by the present invention, the second switching tube S2 and the third switching tube S3 are power frequency switching tubes.
The ANPC topology-based commutation method for reducing voltage stress has the following beneficial effects: according to the converter method based on the ANPC topology for reducing the voltage stress, the state at the zero level is divided into two types, and the stable state of the system in the whole modulation period is divided into P and O+ in the positive half cycle and N and O-in the negative half cycle, so that during normal operation, P and O+ are mutually switched in the positive half cycle; at zero level, O+ and O-switch to each other; in the negative half cycle, O-and N are mutually switched, so that the system state switching is smoother, especially the O+ switching to P and the O-switching to N are switched, and the risk of the voltage stress born by the inner tube is greatly reduced; meanwhile, by changing part of long commutation into short commutation, the control logic is simple and easy to realize.
Drawings
For a clearer description of an embodiment of the invention or of a technical solution in the prior art, the drawings that are needed in the description of the embodiment or of the prior art will be briefly described, it being obvious that the drawings in the description below are only embodiments of the invention, and that other drawings can be obtained, without inventive effort, by a person skilled in the art from the drawings provided:
FIG. 1 is a diagram illustrating a prior art single phase NPC topology;
FIG. 2 is a single-phase circuit topology of an ANPC converter in an embodiment of an ANPC topology-based commutation method for reducing voltage stress provided by the present invention;
FIG. 3 is a block diagram of the dead zone control logic of the CPLD;
FIG. 4 shows a power-on timing control and a power-off timing control;
FIG. 5 is an enlarged waveform diagram of the positive half cycle of an ANPC topology-based commutation method for reducing voltage stress according to the present invention;
FIG. 6 is an enlarged waveform diagram of the negative half cycle of an ANPC topology-based commutation method for reducing voltage stress according to the present invention;
fig. 7 is an enlarged waveform diagram of a full period of the ANPC topology-based commutation method for reducing voltage stress according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment provides a converter method based on an ANPC topology for reducing voltage stress, wherein, as shown in fig. 2, the ANPC converter single-phase topology comprises 6 switching tubes S1-S6, wherein, each switching tube is connected in anti-parallel with a diode, a first switching tube S1 and a fourth switching tube S4 are respectively connected with a positive electrode terminal P and a negative electrode terminal N of a direct current network, a connection point of a fifth switching tube S5 and a sixth switching tube S6 is connected with a neutral terminal O of the direct current network, and a connection point of a second switching tube S2 and a third switching tube S3 is connected with an alternating current network; the first switching tube S1 and the fifth switching tube S5 are packaged in the same switching tube packaging module, the second switching tube S2 and the third switching tube S3 are packaged in the same switching tube packaging module, and the fourth switching tube S4 and the sixth switching tube S6 are packaged in the same switching tube packaging module; the second switching tube S2 and the third switching tube S3 select power frequency IGBT modules, the first switching tube S1 and the fifth switching tube S5 select high-frequency IGBT modules, and the fourth switching tube S4 and the sixth switching tube S6 select high-frequency IGBT modules, so that the hardware cost can be saved maximally.
The embodiment of the invention discloses a modulation method suitable for an ANPC converter shown in fig. 2, which comprises the following steps:
step S1: generating a drive signal;
specifically, in one embodiment of the present invention, the DSP outputs 3 PWM signals to the CPLD; then, outputting 18 paths of PWM control signals to a driving board by the CPLD; finally, the drive board outputs 18 drive signals to control the turn-off of each switch tube.
Specifically, in this embodiment, the commutation control of the core is implemented by the CPLD, and mainly includes two parts: firstly, dead zone control is realized, and secondly, time sequence control is realized. Fig. 3 is a logic block diagram of dead zone control, in which there are three groups of three phases in the CPLD, respectively. Each group expands 1 PWM signal input by the DSP into 6 PWM temporary signals with dead zones, namely PWM1Temp, PWM2Temp, PWM3Temp, PWM4Temp, PWM5Temp, and PWM6Temp. The 6-path PWM temporary signals generate 6-path PWM formal signals PWM1, PWM2, PWM3, PWM4, PWM5 and PWM6 through time sequence control. And the 6 PWM formal signals are sent to a driving board to generate 6 switching tube driving signals. The timing control is a separator timing control and a shutdown timing control, as shown in fig. 4. In the starting time sequence, the fifth switching tube S5 and the second switching tube S6 are firstly turned on simultaneously, then the second switching tube S2 or the third switching tube S3 is turned on, and finally the first switching tube S1 or the fourth switching tube S4 is turned on; in the shutdown sequence, the first switching tube S1 and the fourth switching tube S4 are turned off simultaneously, then the second switching tube S2 and the third switching tube S3 are turned off simultaneously, and finally the fifth switching tube S5 and the second switching tube S6 are turned off simultaneously. Thus, the step of outputting 18 PWM control signals to the drive board by the CPLD includes:
the CPLD comprises three groups of modules, and each group of modules expands 1-path PWM signals input by the DSP into 6-path PWM temporary signals with dead zones; generating 6 paths of PWM formal signals through time sequence control; and sending the 6 paths of PWM formal signals into a driving board to generate 6 paths of switching tube driving signals. .
In the invention, because the commutation control is realized by adopting the combination of DSP and CPLD, 18 driving signals for driving can be expanded by only inputting 3 PWM signals.
Step S2: the driving signals are utilized to control the turn-off of each switching tube, wherein in the positive half cycle, the second switching tube S2 is kept to be normally on, the third switching tube S3 and the fourth switching tube S4 are kept to be normally off, and the first switching tube S1, the fifth switching tube S5 and the sixth switching tube S6 are switched in the process that the voltage of the neutral end O is changed from zero level to positive level or from positive level to zero level; in the negative half cycle, the third switching tube S3 is kept normally on, the first switching tube S1 and the second switching tube S2 are normally off, and the fourth switching tube S4, the sixth switching tube S6 and the fifth switching tube S5 switch in the process that the voltage of the neutral end O is changed from zero level to negative level or from negative level to zero level.
Specifically, in one embodiment of the present invention, four steady states (P, O +, O-, N) are defined as shown in Table 1 below.
Table 1 four steady states
State S1 S2 S3 S4 S5 S6
P
1 1 0 0 0 1
O+ 0 1 0 0 1 1
O- 0 0 1 0 1 1
N 0 0 1 1 1 0
As shown in table 1, in the positive half cycle (i.e., state P and state o+), the second switching tube S2 is kept normally on, the third switching tube S3 and the fourth switching tube S4 are normally off, and the first switching tube S1 and the fifth switching tube S5 are high-frequency complementary. In the practical application process, due to the difference of the switching tube driving circuit and the semiconductor device, one of the switching tubes which are complementarily turned on may not be turned off in time when the other switching tube is turned on due to inconsistent on/off switching speed, so in this embodiment, for the first switching tube S1 and the fifth switching tube S5 which are complementarily turned on, when the switching tube is turned on from the state o+ to the state P, the fifth switching tube S5 is turned off before the first switching tube S1 is turned on, and when the switching tube is turned off from the state P to the state o+, the fifth switching tube S5 is turned on after the first switching tube S1 is turned off, and by inserting dead time between the first switching tube S1 and the fifth switching tube S5, the short circuit can be avoided, wherein the length of the dead time is set according to the switching characteristics of the switching tubes. Further, in switching from the state o+ to the state P, in order to reduce the risk of voltage stress borne by the inner tube, the sixth switching tube S6 is turned off before the fifth switching tube S5 is turned off and turned on after the first switching tube S1 is completely turned on, wherein the off time of the sixth switching tube S6 is set according to the switching characteristics of the respective switching tubes. Therefore, as shown in fig. 3, in the process of the voltage at the neutral terminal O transitioning from zero level to positive level (i.e., transitioning from state o+ to state P), the first switching tube S1 is turned on, the fifth switching tube S5 is turned off before the first switching tube S1 is turned on, and the sixth switching tube S6 is turned off before the fifth switching tube S5 is turned off and turned on after the first switching tube S1 is completely turned on; during the transition of the voltage at the neutral terminal O from the positive level to the zero level (i.e., the transition from the state P to the state o+), the first switching tube S1 is turned off, and the fifth switching tube S5 is turned on after the first switching tube S1 is turned off.
As shown in table 1, in the negative half cycle (i.e., state N and state O-), the third switching tube S3 is kept normally on, the first switching tube S1 and the second switching tube S2 are normally off, and the fourth switching tube S4 and the sixth switching tube S6 are complemented with each other at high frequency. In the practical application process, because of the difference between the driving circuit of the switching tube and the semiconductor device, one of the switching tubes which are turned on complementarily may not be turned off in time when the other switching tube is turned on due to inconsistent on/off switching speed, so in this embodiment, for the fourth switching tube S4 and the sixth switching tube S6 which are turned on complementarily, when the switching tube is turned on from the state O-to the state N, the sixth switching tube S6 is turned off before the fourth switching tube S4 is turned on, and when the switching tube is turned on from the state N to the state O-is turned on, the sixth switching tube S6 is turned on after the fourth switching tube S4 is turned off, and by inserting dead time between the fourth switching tube S4 and the sixth switching tube S6, the short circuit can be avoided, wherein the length of the dead time is set according to the switching characteristics of the switching tubes. Further, in switching from state O-to state N, in order to reduce the risk of voltage stress borne by the inner tube, the fifth switching tube S5 is turned off before the sixth switching tube S6 is turned off and turned on after the fourth switching tube S4 is fully turned on, wherein the turn-off time of the fifth switching tube S5 is set according to the switching characteristics of the respective switching tubes. Therefore, as shown in fig. 4, in the process of the voltage of the neutral terminal O being changed from the zero level to the negative level, the fourth switching tube S4 is turned on, the sixth switching tube S6 is turned off before the fourth switching tube S4 is turned on, the fifth switching tube S5 is turned off before the sixth switching tube S6 is turned off and is turned on after the fourth switching tube S4 is completely turned on; in the process of the voltage of the neutral end O changing from the negative level to the zero level, the fourth switching tube S4 is turned off, and the sixth switching tube S6 is turned on after the fourth switching tube S4 is turned off.
Further, in the conventional control method, when the system is operating in the zero level state, the second switching tube S2, the third switching tube S3, the fifth switching tube S5, and the sixth switching tube S6 are turned on together. In the present application, the zero level state is divided into two types as shown in table 1: one is the state O+, namely the second switching tube S2, the fifth switching tube S5 and the sixth switching tube S6 are simultaneously turned on, and the third switching tube S3 is turned off; the other is the state O-, namely the third switching tube S3, the fifth switching tube S5 and the sixth switching tube S6 are simultaneously turned on, and the second switching tube S2 is turned off. In the practical application process, because of the difference between the driving circuit of the switching tube and the semiconductor device, one of the switching tubes which are complementarily turned on may not be turned off in time when the other switching tube is turned on due to inconsistent on/off switching speed, so in this embodiment, for the second switching tube S2 and the third switching tube S3 which are complementarily turned on in the zero state, when the state O-to the state o+, the third switching tube S3 is turned off before the second switching tube S2 is turned on, and when the state o+ to the state O-, the second switching tube S2 is turned off before the third switching tube S3 is turned on, short circuit can be avoided by inserting dead time between the second switching tube S2 and the third switching tube S3, wherein the length of the dead time is set according to the switching characteristics of the switching tubes. Therefore, as shown in fig. 5, when the positive half-cycle zero-crossing level is switched, the third switching tube S3 is turned on, and the second switching tube S2 is turned off before the third switching tube S3 is turned on; when the negative half-cycle zero-crossing level is switched, the second switching tube S2 is turned on, and the third switching tube S3 is turned off before the second switching tube S2 is turned on.
The system is characterized in that the state at zero level is divided into two types, and the stable state of the system in the whole modulation period is divided into P and O in the positive half period and N and O-in the negative half period, so that in normal operation, P and O+ are mutually switched in the positive half period; at zero level, O+ and O-switch to each other; in the negative half cycle, O-and N are mutually switched, so that the system state switching is smoother, especially the O+ switching to P and the O-switching to N are switched, and the risk of the voltage stress born by the inner tube is greatly reduced; meanwhile, by changing part of long commutation into short commutation, the control logic is simple and easy to realize.
Accordingly, the present invention also provides a modulation system for an ANPC converter as shown in fig. 2, the modulation system comprising: the driving signal generation module is used for generating a driving signal; the modulation module is used for controlling the turn-off of each switching tube by using the driving signal, wherein:
in the positive half cycle, the second switching tube S2 is kept normally on, the third switching tube S3 and the fourth switching tube S4 are kept normally off, the first switching tube S1 is turned on in the process that the voltage of the neutral end O is converted from zero level to positive level, the fifth switching tube S5 is turned off before the first switching tube S1 is turned on, and the sixth switching tube S6 is turned off before the fifth switching tube S5 is turned off and is turned on after the first switching tube S1 is completely turned on; in the process that the voltage of the neutral end O is changed from the positive level to the zero level, the first switching tube S1 is turned off, and the fifth switching tube S5 is turned on after the first switching tube S1 is turned off;
in the negative half cycle, the third switching tube S3 is kept normally on, the first switching tube S1 and the second switching tube S2 are kept normally off, the fourth switching tube S4 is turned on in the process that the voltage of the neutral end O is converted from zero level to negative level, the sixth switching tube S6 is turned off before the fourth switching tube S4 is turned on, the fifth switching tube S5 is turned off before the sixth switching tube S6 is turned off, and the fourth switching tube S4 is turned on after being completely turned on; in the process that the voltage of the neutral end O is changed from the negative level to the zero level, the fourth switching tube S4 is turned off, and the sixth switching tube S6 is turned on after the fourth switching tube S4 is turned off;
when the positive half-cycle zero-crossing level is switched, the third switching tube S3 is turned on, and the second switching tube S2 is turned off before the third switching tube S3 is turned on; when the negative half-cycle zero-crossing level is switched, the second switching tube S2 is turned on, and the third switching tube S3 is turned off before the second switching tube S2 is turned on.
Further, in an embodiment of the present invention, the driving signal generating module includes a DSP, a CPLD, and a driving board, where the DSP outputs 3 PWM signals to the CPLD; outputting 18 paths of PWM control signals to a driving plate by the CPLD; the drive board outputs 18 drive signals to control the on/off of each switch tube. The CPLD comprises three groups of modules, and each group of modules expands 1-path PWM signals input by the DSP into 6-path PWM temporary signals with dead zones; generating 6 paths of PWM formal signals through time sequence control; and sending the 6 paths of PWM formal signals into a driving board to generate 6 paths of switching tube driving signals.
Certain specific embodiments of the present invention have been described above. Note that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. For example, as used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Although several embodiments of the present invention have been described above with reference to the accompanying drawings, it is to be understood that the invention is not limited to the specific embodiments disclosed. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.

Claims (10)

1. The converter comprises three phases, each phase has 6 switching tubes S1-S6, each switching tube is connected in anti-parallel with a diode, a first switching tube S1 and a fourth switching tube S4 are respectively connected with a positive electrode end P and a negative electrode end N of a direct current network, a connection point of a fifth switching tube S5 and a sixth switching tube S6 is connected with a neutral end O of the direct current network, and a connection point of a second switching tube S2 and a third switching tube S3 is connected with an alternating current network, and the converter is characterized in that the converter comprises:
generating a drive signal;
and controlling the on/off of each switching tube by using the driving signal, wherein,
in the positive half cycle, the second switching tube S2 is kept normally on, the third switching tube S3 and the fourth switching tube S4 are kept normally off, the first switching tube S1 is turned on in the process that the voltage of the neutral end O is converted from zero level to positive level, the fifth switching tube S5 is turned off before the first switching tube S1 is turned on, and the sixth switching tube S6 is turned off before the fifth switching tube S5 is turned off and is turned on after the first switching tube S1 is completely turned on; in the process that the voltage of the neutral end O is changed from the positive level to the zero level, the first switching tube S1 is turned off, and the fifth switching tube S5 is turned on after the first switching tube S1 is turned off;
in the negative half cycle, the third switching tube S3 is kept normally on, the first switching tube S1 and the second switching tube S2 are kept normally off, the fourth switching tube S4 is turned on in the process that the voltage of the neutral end O is converted from zero level to negative level, the sixth switching tube S6 is turned off before the fourth switching tube S4 is turned on, the fifth switching tube S5 is turned off before the sixth switching tube S6 is turned off, and the fourth switching tube S4 is turned on after being completely turned on; in the process of the voltage of the neutral end O changing from the negative level to the zero level, the fourth switching tube S4 is turned off, and the sixth switching tube S6 is turned on after the fourth switching tube S4 is turned off.
2. The method of reducing voltage stress in an ANPC topology based commutation of claim 1, wherein the modulation method further comprises:
when the positive half-cycle zero-crossing level is switched, the third switching tube S3 is turned on, and the second switching tube S2 is turned off before the third switching tube S3 is turned on;
when the negative half-cycle zero-crossing level is switched, the second switching tube S2 is turned on, and the third switching tube S3 is turned off before the second switching tube S2 is turned on.
3. The method of reducing voltage stress based on ANPC topology of claim 1, wherein the step of generating a drive signal comprises:
outputting 3 paths of PWM signals to the CPLD by the DSP;
outputting 18 paths of PWM control signals to a driving plate by the CPLD;
the drive board outputs 18 drive signals to control the turn-off of each switch tube.
4. The method of reducing voltage stress based on ANPC topology of claim 3, wherein the step of outputting 18 PWM control signals to the drive board by the CPLD comprises:
the CPLD comprises three groups of modules, and each group of modules expands 1-path PWM signals input by the DSP into 6-path PWM temporary signals with dead zones;
generating 6 paths of PWM formal signals through time sequence control;
and sending the 6 paths of PWM formal signals into a driving board to generate 6 paths of switching tube driving signals.
5. The method of reducing voltage stress in an ANPC topology based commutation of claim 4, wherein the timing control includes a power-on timing and a power-off timing, wherein,
in the starting time sequence, a fifth switching tube S5 and a second switching tube S6 are firstly started at the same time, then a second switching tube S2 or a third switching tube S3 is started, and finally a first switching tube S1 or a fourth switching tube S4 is started;
in the shutdown sequence, the first switching tube S1 and the fourth switching tube S4 are turned off simultaneously, then the second switching tube S2 and the third switching tube S3 are turned off simultaneously, and finally the fifth switching tube S5 and the second switching tube S6 are turned off simultaneously.
6. An ANPC topology-based converter system for reducing voltage stress, the ANPC converter including three phases, each phase having 6 switching tubes S1 to S6, wherein each switching tube is antiparallel connected to a diode, a first switching tube S1 and a fourth switching tube S4 are respectively connected to a positive terminal P and a negative terminal N of a dc network, a connection point of the fifth switching tube S5 and the sixth switching tube S6 is connected to a neutral terminal O of the dc network, and a connection point of the second switching tube S2 and the third switching tube S3 is connected to an ac network, the modulation system comprising:
the driving signal generation module is used for generating a driving signal;
a modulation module for controlling the on/off of each switching tube by using the driving signal, wherein,
in the positive half cycle, the second switching tube S2 is kept normally on, the third switching tube S3 and the fourth switching tube S4 are kept normally off, the first switching tube S1 is turned on in the process that the voltage of the neutral end O is converted from zero level to positive level, the fifth switching tube S5 is turned off before the first switching tube S1 is turned on, and the sixth switching tube S6 is turned off before the fifth switching tube S5 is turned off and is turned on after the first switching tube S1 is completely turned on; in the process that the voltage of the neutral end O is changed from the positive level to the zero level, the first switching tube S1 is turned off, and the fifth switching tube S5 is turned on after the first switching tube S1 is turned off;
in the negative half cycle, the third switching tube S3 is kept normally on, the first switching tube S1 and the second switching tube S2 are kept normally off, the fourth switching tube S4 is turned on in the process that the voltage of the neutral end O is converted from zero level to negative level, the sixth switching tube S6 is turned off before the fourth switching tube S4 is turned on, the fifth switching tube S5 is turned off before the sixth switching tube S6 is turned off, and the fourth switching tube S4 is turned on after being completely turned on; in the process of the voltage of the neutral end O changing from the negative level to the zero level, the fourth switching tube S4 is turned off, and the sixth switching tube S6 is turned on after the fourth switching tube S4 is turned off.
7. The voltage stress reducing ANPC topology based commutation system of claim 6, wherein the modulation module is further configured to:
when the positive half-cycle zero-crossing level is switched, the third switching tube S3 is turned on, and the second switching tube S2 is turned off before the third switching tube S3 is turned on;
when the negative half-cycle zero-crossing level is switched, the second switching tube S2 is turned on, and the third switching tube S3 is turned off before the second switching tube S2 is turned on.
8. The voltage stress reducing ANPC topology based converter system of claim 6, wherein the drive signal generation module includes a DSP, a CPLD, and a drive board, wherein 3 PWM signals are output by the DSP to the CPLD; outputting 18 paths of PWM control signals to a driving plate by the CPLD; the drive board outputs 18 drive signals to control the turn-off of each switch tube.
9. The voltage stress reducing converter system based on ANPC topology of claim 8, wherein each set of CPLDs expands one PWM signal input from the DSP into 6 PWM temporary signals with dead zones, and generates the 6 PWM temporary signals into PWM control signals sent to the drive board through timing control.
10. The voltage stress reducing ANPC topology based converter system of claim 6, wherein the second switching tube S2 and the third switching tube S3 are power frequency switching tubes.
CN202310247315.5A 2023-03-14 2023-03-14 Converter method and system based on ANPC topology for reducing voltage stress Pending CN116317653A (en)

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