KR20170001858A - Nonvolatile memory module and operation method thereof - Google Patents

Abstract

A nonvolatile memory module according to the present invention includes at least one nonvolatile memory device and a device controller for receiving a storage command from an external device and performing an operation corresponding to the received storage command. The device controller includes a random access memory (RAM), completes the corresponding operation, stores status information in the RAM and transmits a notification signal to the external device. So, the performance of the nonvolatile memory module can be improved.

Description

NONVOLATILE MEMORY MODULE AND OPERATION METHOD THEREOF FIELD OF THE INVENTION [0001]

The present invention relates to a semiconductor memory, and more particularly, to a nonvolatile memory module and an operation method thereof.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP) to be. Semiconductor memory devices are classified into a volatile memory device and a nonvolatile memory device.

Flash memory, which is a type of nonvolatile memory device, is widely used as a storage device in various fields because of its advantages such as large capacity, low noise and low power. In particular, solid state drives (SSDs) based on flash memory are used as mass storage in personal computers, notebooks, workstations, and server systems. Typical SSD devices are connected to a computing system based on a SATA interface or a PCI-express interface. In recent years, however, as the amount of data processed in the computing system increases, the data throughput becomes larger than the data bandwidth or communication speed of the interface connected to the SSD devices, resulting in a data bottleneck. These phenomena act as a factor that hinders the performance of the computing system, and various performance enhancement techniques for solving the above-mentioned problems are being developed.

An object of the present invention is to provide a nonvolatile memory module that transmits a notification signal to an external device (that is, a host) to notify completion of an operation corresponding to a received command, and an operation method thereof .

A non-volatile memory module according to an embodiment of the present invention includes at least one non-volatile memory device; And a device controller for receiving a storage command from an external device and performing an operation corresponding to the received storage command, wherein the device controller includes a RAM, and the device controller, after completing the corresponding operation Stores the state information in the RAM, and transmits a notification signal to the external device.

In an embodiment, the status information includes information about the completion of the corresponding operation.

As an embodiment, the device controller transmits the status information to the external device at the request of the external device after transmitting the notification signal to the external device.

In an embodiment, the device controller communicates with the external device based on a DDR (Double Data Rate) interface.

A non-volatile memory module according to the present invention includes at least one non-volatile memory device and a memory controller for controlling the at least one non-volatile memory device. The method of operating the non-volatile memory module includes receiving a storage command from an external device; Performing an operation corresponding to the received storage command; Storing the state information in the RAM of the memory controller after completing the corresponding operation; And transmitting the notification signal to the external device after storing the status information in the RAM.

A user system according to an embodiment of the present invention includes a processor and a non-volatile memory module electrically connected to the processor. The method of claim 1, further comprising the steps of: the processor transmitting a storage command to the non-volatile memory module; The nonvolatile memory module performing an operation corresponding to the storage command in response to the storage command; After the corresponding operation is completed, the nonvolatile memory module transmits a notification signal to the processor; The processor sending a RAM command and a RAM address to the non-volatile memory system in response to the notification signal; And the nonvolatile memory module transmitting status information to the processor in response to the RAM command and the RAM address.

According to the present invention, the nonvolatile memory system transmits the notification signal to the external device after completing the operation corresponding to the command received from the external device. The external device can recognize completion of the operation of the nonvolatile memory system by reading the status information included in the nonvolatile memory system in response to the notification signal. Thus, a non-volatile memory system with improved performance and a method of operation thereof are provided.

1 is a block diagram illustrating a user system in accordance with an embodiment of the present invention.
Fig. 2 is a diagram for explaining the RAM of Fig.
3 is a flow chart illustrating the operation of the nonvolatile memory system of FIG.
4 is a flowchart for explaining a write operation of the user system of FIG.
5 to 7 are views for explaining the writing operation of FIG. 4 in more detail.
8 is a flowchart showing a read operation of the user system of FIG.
FIGS. 9 to 11 are views for explaining the read operation of FIG. 8 in detail.
12 is a block diagram illustrating a user system according to another embodiment of the present invention.
13 is a flowchart showing the operation of the nonvolatile memory system of FIG.
FIG. 14 is a flowchart showing a write operation of the user system of FIG. 12 in detail.
FIG. 15 is a diagram for explaining steps S2160 and S2170 of FIG. 14 in detail.
16 is a flowchart showing a read operation of the user system of FIG.
17 is a block diagram illustrating a user system according to another embodiment of the present invention.
18 is a flowchart showing the operation of the nonvolatile memory system of FIG.
FIG. 19 is a flowchart showing the write operation of the user system of FIG. 17 in detail.
20 is a diagram for explaining the operations of steps S3160 and S3170 of FIG.
FIG. 21 is a flowchart showing the read operation of the user system of FIG. 17 in detail.
22 is a block diagram illustrating an exemplary first nonvolatile memory device of the plurality of nonvolatile memory devices of FIG.
23 is a circuit diagram showing an example of a first memory block among the memory blocks included in the memory cell array of FIG.
FIG. 24 is a block diagram illustrating a computing system to which a non-volatile memory system according to the present invention is applied.
FIG. 25 is a block diagram illustrating one of the nonvolatile memory modules of FIG. 24 by way of example.
FIG. 26 is a block diagram illustrating one of the nonvolatile memory modules of FIG. 24 by way of example.
FIG. 27 is a block diagram illustrating another example of a computing system to which the nonvolatile memory module according to the present invention is applied.
28 is a block diagram illustrating an exemplary non-volatile memory module of FIG. 27;
29 is a block diagram illustrating an exemplary non-volatile memory module of FIG. 27;
30 is a block diagram illustrating an exemplary non-volatile memory module of FIG. 27;
31 is a diagram illustrating a server system to which a nonvolatile memory system according to an embodiment of the present invention is applied.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to explain the present invention in detail so that those skilled in the art can readily implement the technical idea of the present invention .

The non-volatile memory system according to the present invention transmits the notification signal (Alert_n) to the processor after completing the operation corresponding to the storage command received from the processor (i.e., host). The processor may receive status information from the non-volatile memory system in response to the alert signal (Alert_n). Thus, since the processor does not have to periodically poll the non-volatile memory system to check the status information, system performance is improved and an improved non-volatile memory system is provided.

1 is a block diagram illustrating a user system in accordance with an embodiment of the present invention. Fig. 2 is a diagram for explaining the RAM of Fig. Referring to FIGS. 1 and 2, the user system 10 includes a processor 101 and a non-volatile memory system 100. Illustratively, the user system 100 may be a computer, a portable computer, an Ultra Mobile PC (UMPC), a workstation, a server computer, a net-book, a PDA, a portable computer, a web tablet A wireless phone, a mobile phone, a smart phone, a digital camera, a digital audio recorder, a digital audio player, A digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, And may include one of a variety of electronic devices.

The processor 101 may process data or control components included in the user system 100. For example, the processor 101 may be capable of running various operating systems and running various applications on an operating system. The processor 101 can write data (DATA) to the non-volatile memory system 100 or read the data (DATA) stored in the non-volatile memory system 100. [

Illustratively, the processor 101 may send a RAM command CMD_R, a RAM address ADDR_R, and a clock CK to the non-volatile memory system 100. The processor 101 may exchange the data signal DQ and the data strobe signal DQS with the nonvolatile memory system 100. [ Illustratively, the data signal DQ may be a signal including a storage command CMD_S, a storage address ADDR_S, data DATA, and status information STI.

Illustratively, the RAM command CMD_R and the RAM address ADDR_R may be a command and an address for controlling the RAM 111b included in the physical layer 111 of the nonvolatile memory system 100. The storage command CMD_S and the storage address ADDR_S may be commands for controlling the plurality of nonvolatile memory devices 131 to 13n included in the nonvolatile memory system 100.

Illustratively, the RAM command CMD_R, the RAM address ADDR_R, the clock CK, the data signal DQ, and the data strobe signal DQS, which are transmitted and received between the processor 101 and the nonvolatile memory system 100, May follow a predefined convention by an interface between the processor 101 and the non-volatile memory system 100. Illustratively, the interface between the processor 101 and the non-volatile memory system 100 may be based on a Double Data Rate (DDR) interface. For example, the RAM command CMD_R, the RAM address ADDR_R, and the clock CK may be signals conforming to the protocol defined by the DDR interface.

The interface between the processor 101 and the nonvolatile memory system 100 may be a DDR, DDR2, DDR3, DDR4, LPDDR (Low Power DDR), USB (Universal Serial Bus) , MMC (multimedia card), embedded MMC, peripheral component interconnection (PCI), PCI-express (PCI-express), ATA (Advanced Technology Attachment), Serial- ATA, Parallel- an Enhanced Small Disk Interface (IDE), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), Nonvolatile Memory Express (NVMe), and the like.

The non-volatile memory system 100 may include a device controller 110, a buffer memory 120, a plurality of non-volatile memory devices 131 to 13n, and an auxiliary power supply 140. Illustratively, the non-volatile memory system 100 is responsive to the storage command CMD_S and the storage address ADDR_S received from the processor 101 via the data signal DQ and the data strobe signal DQS, The data DATA received from the processor 101 can be stored in at least one of the plurality of nonvolatile memory devices 131 to 13n through the signal DQ and the data strobe signal DQS. Alternatively, the non-volatile memory system 100 may include a plurality of nonvolatile (non-volatile) memory cells in response to the storage command CMD_S and the storage address ADDR_S received from the processor 101 via the data signal DQ and the data strobe signal DQS. (DATA) stored in at least one of the memory devices 131 to 13n to the processor 101 via the data signal DQ and the data strobe signal DQS.

Illustratively, although not shown in the drawings, the non-volatile memory system 100 may have the form of a dual in-line memory module (DIMM) It can be mounted directly on a DIMM socket.

The device controller 110 may include a physical layer 111 (PHY) and a controller 112. The physical layer 111 may include a RAM controller 111a and a RAM 111b. The physical layer 111 may be electrically connected directly to the processor 101 and may provide an interface between the processor 101 and the controller 112. [

The RAM controller 111a receives information received via the data signal DQ and the data strobe signal DQS in response to the RAM command CMD_R, the RAM address ADDR_R, and the clock CK received from the processor 101 Or data may be stored in the RAM 111b or information or data stored in the RAM 111b may be provided to the processor 101 via the data signal DQ and the data strobe signal DQS. Illustratively, the ram 111b may include multiple port RAM, such as a dual port SRAM, a shared RAM, and the like. That is, the processor 101 or the controller 112 can access the RAM 111b through respective independent ports.

2, the RAM 111b includes a command area (CA), a write area (WA), a read area (RA), and a status area (STA; STATA) Area). Each of the command area CA, the write area WA, the read area RA and the state area STA includes a RAM command CMD_R, a RAM address ADDR_R, and a clock CK received from the processor 101, Respectively.

The command area CA of the RAM 111b can store the storage command CMD_S received from the processor 101 via the data signal DQ and the data strobe signal DQS under the control of the RAM controller 111a . The controller 112 can read the storage command CMD_S stored in the command area CA of the RAM 111b. Illustratively, the storage command CMD_S may include a storage address ADDR_S, and the storage command CMD_S and the storage address ADDR_S may be stored in the command area CA.

The write area WA of the ram 111b may store the write data DATA_W received via the data signal DQ and the data strobe signal DQS under the control of the RAM controller 111a. The controller 111b can read the write data (DATA_W) stored in the write area WA of the RAM 111b.

The read area RD of the RAM 111b may store the read data DATA_R under the control of the controller 112. [ The read area RD of the RAM 111b may be transferred to the processor 101 via the data signal DQ and the data strobe signal DQS.

The state area STA of the RAM 111b stores state information STI received from the processor 101 via the data signal DQ and the data strobe signal DQS or stores the stored state information STI into the processor 101 ). The state area STA of the RAM 111b may transmit the stored state information STI to the controller 112 or store the received state information STI from the controller 112 under the control of the controller 112 .

The controller 112 may communicate with the physical layer 111. The controller 112 can control the buffer memory 120 and the plurality of nonvolatile memory devices 131 to 13n, respectively. When the storage command CMD_S is written in the RAM 111b of the physical layer 111, the controller 112 can perform an operation corresponding to the storage command CMD_S written in the RAM 111b. For example, when the storage command CMD_S written in the RAM 111b is a write command, the controller 112 reads the write data (DATA_W) written in the write area WA of the RAM 111b, The data (DATA_W) can be programmed into at least one of the plurality of nonvolatile memory devices 131 to 13n. When the storage command CMD_S written in the RAM 111b is a read command, the controller 112 reads the data corresponding to the storage address ADDR_S from the plurality of nonvolatile memory devices 131 to 13n, (RA) read data (DATA_S) of the RAM 111b. Illustratively, after the write operation and the read operation are completed, the controller 112 may write state information (STI) indicating the completion of operation in the state area STA.

Illustratively, when the controller 112 completes a write operation or a read operation with respect to the storage command CMD_S and the status information STI is written into the status area STA of the RAM 111b, Lt; RTI ID = 0.0 > Alert_n < / RTI > More specifically, the controller 112 can activate the notification signal (Alert_n) after writing the state information (STI) into the state area (STA). Illustratively, the alert signal (Alert_n) may be provided to the processor 101 via the physical layer 111. Although not shown in the figure, the alert signal Alert_n may be provided to the processor 101 via the RAM controller 111a. Or the alert signal Alert_n may be provided to the processor 101 through a separate driving device. Hereinafter, for ease of explanation and for simplicity of the drawing, it is assumed that the alert signal Alert_n is driven by the controller 112 and provided from the controller 112 to the processor 101. [ It is also assumed that the notification signal Alert_n is activated by the RAM controller 111a to logic low or logic high, but for convenience of explanation, the controller 112 provides or transmits it. That is, when the notification signal Alert_n is provided or transmitted, it means that the alert signal Alert_n is activated for a specific time or repeatedly activated for a specific period. However, the scope of the present invention is not limited thereto.

Although not shown in the figure, the controller 112 can access the RAM 111b through a specific system bus or an internal system bus. Controller 112 may further include hardware or software components such as an Error Correction Code Engine (ECC engine), a scrambler, a data buffer, a flash translation layer, and the like, although not shown in the figure. The controller 112 can descramble the data read from the RAM 111b through the scrambler or scramble the data to be written into the RAM 111b. The controller 112 can detect and correct errors of data read from the RAM 111b through the ECC engine or add ECC codes to the data to be written to the RAM 111b. The controller 112 may temporarily store data read from the RAM 111b through the data buffer or temporarily store data read from the plurality of nonvolatile memory devices 131-131n.

The controller 112 may perform an address translation operation through the flash translation layer. For example, the storage address ADDR_S may be a logical address. The controller 112 may perform the operation of converting the storage address ADDR_S received from the processor 101 through the flash translation layer to the physical address of the plurality of non-volatile memory devices 131 to 13n. Illustratively, the physical location at which the write data (DATA_W) is written by the address translation operation or the physical location at which the read data (DATA_R) is stored can be determined. Illustratively, the physical location refers to the physical location of the plurality of non-volatile memory devices 131-13n.

The buffer memory 120 may be used as a buffer memory, an operation memory, or a cache memory of the device controller 110. The buffer memory 120 may include various information required for the nonvolatile memory system 100 to operate. Illustratively, the buffer memory 120 may include data for managing a plurality of non-volatile memory devices 131 to 13n. For example, the buffer memory 120 is connected to the non-volatile address ADDR_S received from the processor 101 via the data signal DQ and the data strobe signal DQS and the plurality of nonvolatile memory devices 131 through 13n, And a mapping table between the physical addresses of the physical addresses. Illustratively, the buffer memory 120 may include random access memories such as SRAM, DRAM, SDRAM, MRAM, ReRAM, PRAM, FRAM, and the like.

The plurality of nonvolatile memory devices 131 to 13n are connected to the device controller 110 through a plurality of channels CH1 to CHn, respectively. The plurality of nonvolatile memory devices 131 to 131n may program the received data or output the stored data under the control of the device controller 110. [ For example, each of the plurality of nonvolatile memory devices 131 to 13n may include an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase change RAM (PRAM), a ReRAM (Resistive RAM) (Ferroelectric RAM), STT-MRAM (Spin-Torque Magnetic RAM), and the like. For the sake of brevity, it is assumed that each of the plurality of nonvolatile memory devices 131 to 13n includes a NAND flash memory.

As described above, the nonvolatile memory system 100 according to the present invention can activate the notification signal (Alert_n) after writing the state information (STI) into the state area (STA) do. The processor 101 reads the state information STI of the state area STA of the nonvolatile memory system 100 in response to the alert signal Alert_n and responds to the storage command CMD_S based on the state information STI And the information of the nonvolatile memory system 100 can be confirmed. Thus, a nonvolatile memory system with improved performance is provided.

3 is a flow chart illustrating the operation of the nonvolatile memory system of FIG. Referring to FIGS. 1 to 3, in step S1010, the nonvolatile memory system 100 receives a storage command CMD_S from the processor 101. 1 and 2, the non-volatile memory system 100 receives the storage command CMD_S from the processor 101 via the data signal DQ and the data strobe signal DQS, for example, . Illustratively, the non-volatile memory system 100 may further receive the storage address ADDR_S or write data DATA_W.

In step S1020, the nonvolatile memory system 100 may perform an operation corresponding to the received storage command CMD_S. For example, when the received storage command CMD_S indicates a read operation, the nonvolatile memory system 100 reads the data written in the plurality of nonvolatile memory devices 131 to 13n, 111b. Or when the received storage command CMD_S indicates a write operation, the nonvolatile memory system 100 can write the write data written in the write area WA to the plurality of nonvolatile memory devices 131 to 13n have. Illustratively, the storage command CMD_S may be a command corresponding to various other operations (e.g., erase, merge, etc.) other than read and write.

In step S1030, the nonvolatile memory system 100 can write the status information (STI) to the RAM 111b. For example, as described with reference to FIGS. 1 and 2, the non-volatile memory system 100 may store status information (STI) in a RAM (or RAM) after completing operations corresponding to the received storage command CMD_S 111b in the state area STA. Illustratively, the status information (STI) may include whether or not the operation corresponding to the received storage command (CMD_S) has been completed and related information.

In step S1040, the non-volatile memory system 100 may transmit the notification signal Alert_n to the processor 101. [ For example, after the nonvolatile memory system 100 writes the status information STI in the status area STA of the RAM 111b, the processor 101 may read the written status information STI And transmits the alert signal Alert_n to the processor 101. [

Illustratively, the processor 101 can read the state information (STI) written in the state area STA in response to the notification signal Alert_n.

4 is a flowchart for explaining a write operation of the user system of FIG. Illustratively, with reference to FIG. 4, write operations to the non-volatile memory system 10 are described. 1 and 4, in step S1110, the processor 101 transmits a RAM command CMD_R and a RAM address ADDR_R for selecting a command area CA of the RAM 111b to the nonvolatile memory system 100 ). In step S1120, the processor 1120 transfers the data signal DQ and the data strobe signal DQS for writing the storage command CMD_S to the nonvolatile memory system 100.

For example, the RAM command CMD_R in step S1110 of FIG. 4 may be a command for writing the storage command CMD_S into the RAM 111b. The RAM address ADDR_R in step S1110 may be an address corresponding to the command area CA. The storage command CMD_S may be a write command for the plurality of nonvolatile memory devices 131 to 13n of the nonvolatile memory system 100 and may be a write command for the data signal DQ and the data strobe signal DQS in step S1120 . Illustratively, steps S1110 and S1120 may be a storage command process (CMD_S transaction), and the storage command CMD_S may be stored in the command area CA through operations in steps S1110 and S1120.

In step S1130, the processor 101 transmits a RAM command CMD_R and a RAM address ADDR_R for selecting the writing area WA to the nonvolatile memory system 100. In step S1140, the processor 101 transfers the data signal DQ and the data strobe signal DQS for writing the write data (DATA_W) to the nonvolatile memory system 100.

For example, the RAM command CMD_R in step S1130 of FIG. 4 may be a command for writing write data (DATA_W) to the RAM 111b. The RAM address ADDR_R in step S1130 may be an address corresponding to the write area WA. The write data DATA_W may be included in the data signal DQ and the data strobe signal DQS in step S1140. Illustratively, steps S1130 and S1140 may be a write data process (DATA_W transaction), and write data (DATA_W) may be written to the write area WA through operations of steps S1130 and S1140.

In step S1150, the nonvolatile memory system 100 transmits a notification signal Alert_n to the processor 101 to notify completion of writing. For example, as described above, the nonvolatile memory system 100 reads the storage command CMD_S written in the command area CA of the RAM 111b, and in response to the read storage command CMD_S, The write data (DATA_W) written in the area WA can be programmed into the plurality of nonvolatile memory devices 131 to 13n. After completing the program, the nonvolatile memory system 100 can write the status information STI into the status area STA. The non-volatile memory system 100 may then send a notification signal (Alert_n) to the processor 101. Or the non-volatile memory system 100 may activate the alert signal Alert_n.

In step S1160, the processor 101 may transmit the RAM command CMD_R and the RAM address ADDR_R to the nonvolatile memory system 100 for selecting the state area STA. For example, the processor 101 can recognize that the state information (STI) has been written into the state area (STA) of the nonvolatile memory system 100 by the received notification signal (Alert_n). The processor 101 responds to the received notification signal Alert_n to transmit the RAM command CMD_R and the RAM address ADDR_R to the nonvolatile memory system 100 in order to read the status area STA of the nonvolatile memory system 100. [ As shown in FIG. Illustratively, the RAM command CMD_R in step S1160 may be a read command for reading the state area STA, and the RAM address ADDR_R in step S1160 may be an address corresponding to the state area STA.

In step S1170, the nonvolatile memory system 100 may transmit the status information (STI) to the processor 101 via the data signal DQ and the data strobe signal DQS. For example, in response to the RAM command (CMD_R) and the RAM address (ADDR_R) in step S1160, the nonvolatile memory system 100 transmits the state information (STI) of the state area (STA) corresponding to the RAM address (ADDR_R) (101). At this time, the nonvolatile memory system 100 may transmit the status information (STI) to the processor 101 through the data signal DQ and the data strobe signal DQS. Illustratively, the operations of steps S1150 to S1170 may be a CHECK transaction.

5 to 7 are views for explaining the writing operation of FIG. 4 in more detail. For the sake of brevity, the elements unnecessary for explaining the writing operation of the user system 10 are omitted, and the description of the redundant elements is also omitted.

First, referring to FIG. 5, the processor 101 can write the storage command CMD_S to the command CA. (1) For example, as described above, the processor 101 transmits the RAM command CMD_R, the RAM address ADDR_R, and the clock CK to the nonvolatile memory system 100, To the nonvolatile memory system 100, the data signal DQ and the data strobe signal DQS including the CMD_S. The RAM controller 111a of the nonvolatile memory system 100 selects the command area CA in response to the RAM command CMD_S, the RAM address ADDR_R and the clock CK, The storage command CMD_S can be written. Illustratively, the data signal DQ and the data strobe signal DQS may be provided to the RAM 111b via the RAM controller 111a. Illustratively, the operation of the processor 101 described above may be the operations of steps S1110 and S1120 of FIG.

 The controller 112 can read the storage command CMD_S written in the command area CA. (2) For example, the controller 112 may fetch the storage command CMD_S written in the command area CA via the system bus. The controller 112 analyzes the fetched storage command CMD_S to confirm that the storage command CMD_S is a write command. Illustratively, the analysis of the storage command CMD_S may be performed in a separate command analyzer or in a central processing unit (not shown) of the non-volatile memory system 100.

Next, referring to Fig. 6, the processor 101 can write write data (DATA_W) in the write area WA. (3) For example, the processor 101 transmits the command CMD_R, the RAM address ADDR_R, and the clock CK to the nonvolatile memory system 100, and outputs the data signal including the storage command CMD_S (DQ) and data strobe signal (DQS) to the non-volatile memory system (100). The RAM controller 111a of the nonvolatile memory system 100 selects the writing area WA in response to the RAM command CMD_S, the RAM address ADDR_R and the clock CK, Write data (DATA_W) can be written. Illustratively, the operation of the processor 101 described above may be the operations of steps S1130 and S1140 of FIG.

The controller 112 can read the write data (DATA_W) written in the write area WA. (4) The controller 112 can program the write data (DATA_W) in the nonvolatile memory device 131 according to the storage command CMD_S. (5) Illustratively, the controller 112 may package the storage command CMD_S and the write data DATA_W.

Next, referring to FIG. 7, after programming the write data (DATA_W) in the nonvolatile memory device 131, the controller 112 sets the state information (STI) indicating the completion of writing to the write data (DATA_W) It can be written in the state area STA. (6) Illustratively, the controller 112 can write the status information (STI) to the status area (STA) via the system bus.

Thereafter, the controller 112 may transmit the notification signal Alert_n to the processor 101. [ (7) Illustratively, for simplicity and ease of illustration, the controller 112 is shown as providing the alert signal Alert_n to the processor 101, but the scope of the present invention is not limited thereto , The alert signal Alert_n may be transmitted to the processor 101 via other components of the non-volatile memory system 100. [ Illustratively, the transmission operation of the notification signal Alert_n may be the operation in step S1150 of FIG.

The processor 101 can read the state information STI written in the state area STA in response to the notification signal Alert_n. (8) For example, the processor 101 can transmit the RAM command CMD_R, the RAM address ADDR_R, and the clock CK to the nonvolatile memory system 100. The RAM controller 111a of the nonvolatile memory system 100 sends the status information STI of the status area STA to the processor 112 in response to the received RAM command CMD_R, the RAM address ADDR_R, and the clock CK. (101). Illustratively, the status information STI may be transmitted to the processor 101 via the data signal DQ and the data strobe signal DQS.

As described above, the nonvolatile memory system 100 according to the present invention can transmit the notification signal Alert_n to the processor 101 after writing the state information STI into the state area STA. The processor 101 can read the state information STI written in the state area STA in response to the notification signal Alert_n. That is, according to the conventional technique, the processor 101 periodically polls the state area STA to recognize whether the operation of the non-volatile memory system 100 has been completed. However, the nonvolatile memory system 100 according to the present invention writes the state information (STI) into the state area (STA) after completion of operation and then transmits the notification signal (Alert_n) to the processor (101) STI) to the processor 101, the utilization of the processor 101 is increased, and the overhead due to the periodic polling operation is reduced. Thus, a nonvolatile memory system with improved performance is provided.

8 is a flowchart showing a read operation of the user system of FIG. 1, 2, and 8, in step S1210, the processor 101 sends a RAM command CMD_R and a RAM address ADDR_R for selecting the command area CA to the nonvolatile memory system 100, Lt; / RTI > In step S1220, the processor 101 transmits the storage command CMD_S to the nonvolatile memory system 100 via the data signal DQ and the data strobe signal DQS. Illustratively, the RAM command CMD_R in step S1210 may be a command for writing the storage command CMD_S to the RAM 111b. The RAM address ADDR_R in step S1210 may be an address corresponding to the command area CA. The storage command CMD_S in step S1220 may be a write command for the plurality of nonvolatile memory devices 131 to 13n of the nonvolatile memory system 100 and may be a write command for the data signal DQ and the data strobe signal DQS). Illustratively, steps S1210 and S1220 may be a storage command process (CMD_S transaction), and the storage command CMD_S may be stored in the command area CA through operations in steps S1210 and S1220.

In step S1230, the nonvolatile memory system 100 transmits a notification signal Alert_n to the processor 101 to notify completion of reading. For example, the non-volatile memory system 100 may perform a read operation on the plurality of non-volatile memory devices 131 to 13n in response to the storage command CMD_S in step S1220. The nonvolatile memory system 100 can write the read data (DATA_R) read from the plurality of nonvolatile memory devices 131 to 13n into the read area RA. The nonvolatile memory system 100 can write state information STI indicating the completion of the read operation into the state area STA after writing the read data DATA_R in the read area RA. Thereafter, the non-volatile memory system 100 may transmit the notification signal Alert_n to the processor 101. [

In step S1240, the processor 101 may transmit a RAM command CMD_R and a RAM address ADDR_R to the nonvolatile memory system 100 for selecting the state area STA. For example, the processor 101 may receive the notification signal Alert_n and recognize that the status information STI is written or updated in the status area STA by the received notification signal Alert_n. The processor 101 may transmit the RAM command CMD_R and the RAM address ADDR_R to the nonvolatile memory system 100 in order to read the state information STI written in the state area STA. Illustratively, the RAM command CMD_R in step S1240 may be a read command for the RAM 111b, and the RAM address ADDR_R may be an address corresponding to the status area STA.

In step S1250, the nonvolatile memory system 100 may transmit the status information STI to the processor 101 via the data signal DQ and the data strobe signal DQS. For example, the RAM controller 111a of the nonvolatile memory system 100 transmits the state information STI written in the state area STA in response to the RAM command CMD_R and the RAM address ADDR_R in step S1240, (101). Illustratively, the status information STI includes information indicating the completion of the corresponding operation of the storage command CMD_S received in step S1220 and includes information indicating the completion of the corresponding operation of the processor 101 (i. E., The data signal DQ and the data strobe signal DQS) ). ≪ / RTI >

In step S1260, the processor 101 may provide the RAM command CMD_R and the RAM address ADDR_R to the nonvolatile memory system 100 in order to select the read area RA. For example, the state information (STI) in step S1250 may include information on a read area (RA) in which read data is stored. That is, the status information (STI) may include the address of the area where the read data (DATA_R) is stored. The processor 101 may recognize that the nonvolatile memory system 100 has completed the read operation based on the status information STI received in step S1250 and that the read data DATA_R is stored in the read area RA It can be recognized. The processor 101 may transmit the RAM command CMD_R and the RAM address ADDR_R to the nonvolatile memory system 100 in order to read the read data DATA_R stored in the read area RA. Illustratively, the RAM command CMD_R is a read command for the RAM 111b and the RAM address ADDR_R may be an address corresponding to the read area RA (more specifically, the area where the read data is stored) .

In step S1270, the non-volatile memory system 100 may transmit the read data (DATA_R) to the processor 101. [ For example, the RAM controller 111a of the nonvolatile memory system 100 may transmit the read data (DATA_R) to the processor 101 in response to the received RAM command CMD_R and the RAM address ADDR_R. Illustratively, the read data (DATA_R) may be transmitted to the processor 101 via the data signal DQ and the data strobe signal DQS.

FIGS. 9 to 11 are views for explaining the read operation of FIG. 8 in detail. Illustratively, the components unnecessary for explaining the read operation of the user system 10 are omitted, and the description of the redundant components is omitted.

First, referring to Fig. 9, the processor 101 can write the storage command CMD_R into the command area CA. (1) For example, the processor 101 transmits the RAM command CMD_R, the RAM address ADDR_R, and the clock CK to the RAM controller 111a. The RAM controller 111a can write the storage command CMD_S received via the data signal DQ and the data strobe signal DQS to the command area CA in response to the received signals. Illustratively, the storage command CMD_S may be a read command to the non-volatile memory device 131. Illustratively, the above-described operations may be operations of steps S1210 and S1220 of FIG.

The controller 112 can read the storage controller CMD_R stored in the command area CA. Illustratively, the controller 112 may read the storage command CMD_S via the system bus.

The controller 112 can read the read data (DATA_R) from the nonvolatile memory device 131 in accordance with the read storage command CMD_S. (3) Illustratively, the storage command CMD_S is a read command and may include an address (or logical address) corresponding to the read data (DATA_R).

Next, referring to Fig. 10, the controller 112 can write the read data (DATA_R) into the read area (RA). (4), the controller 112 can write the status information STI into the status area STA. (5) Illustratively, the status information (STI) may include information on the completion of the read operation corresponding to the storage command (CMD_S). In addition, the status information STI may include information of the read area RA in which the read data (DATA_R) is stored.

After the state information STI is written into the state area STA, the controller 112 transmits the notification signal Alert_n to the processor 101. [ (6) The processor 101 reads the state information STI written in the state area STA in response to the received alert signal Alert_n. (7) For example, the processor 101 sends a RAM command CMD_R, a RAM address ADDR_R, and a clock CK to the RAM controller 111a to read the state information STI written in the state area STA ). The RAM controller 111a transfers the state information STI written in the state area STA to the processor 101 in response to the received RAM command CMD_R, the RAM address ADDR_R and the clock CK. Illustratively, the status information STI may be transmitted to the processor 101 via the data signal DQ and the data strobe signal DQS.

Next, referring to FIG. 11, the processor 101 can read the read data DARA_R written in the read area RA based on the read state information (STI). (8), for example, the status information STI may include information (i.e., address information) of the read area RA in which the read data (DATA_R) is written. The processor 101 transmits the RAM command CMD_R, the RAM address ADDR_R and the clock CK to the RAM controller 111a in order to read the read data (DATA_R) based on the state information (STI). The RAM controller 111a transmits the read data DATA_R to the processor 101 in response to the received RAM command CMD_R, the RAM address ADDR_R and the clock CK. Illustratively, the read data (DATA_R) may be transmitted to the processor 101 via the data signal DQ and the data strobe signal DQS.

4 to 11, the nonvolatile memory system 100 stores the status information (STI) in the RAM 101 after completing the operation corresponding to the storage command CMD_S received from the processor 101. [ To the state area STA of the memory 111b. Thereafter, the non-volatile memory system 100 transmits the notification signal Alert_n to the processor 101. [ The processor 101 can read the state information STI written in the state area STA in response to the notification signal Alert_n. Thus, a nonvolatile memory system with improved performance is provided.

12 is a block diagram illustrating a user system according to another embodiment of the present invention. Referring to FIG. 12, the user system 20 includes a processor 201 and a non-volatile memory system 200. The non-volatile memory system 200 includes a device controller 210, a buffer memory 220, and a plurality of non-volatile memory devices 231 to 23n. The device controller 210 includes a physical layer 211 and a controller 212. The physical layer 211 includes a RAM controller 211a, a RAM 211b, and a multipurpose register (MPR).

A processor 201, a non-volatile memory system 200, a device controller 210, a buffer memory 220, a plurality of non-volatile memory devices 231 to 23n, a physical layer 211, a controller 212, The controller 211a, and the RAM 211b have been described with reference to FIG. 1, so a detailed description thereof will be omitted.

1, the nonvolatile memory system 200 of FIG. 12 further includes a multipurpose register (MPR). The multipurpose register (MPR) may include a plurality of registers. A multipurpose register (MPR) can store data patterns, error logs, information about mode registers, or information about the update of state information (STI), etc. For example, a multipurpose register (MPR) Purpose register (MPR) may include a log record for cyclic redundancy checking of write data, storage commands, etc. received from the processor 101. A multipurpose register (MPR) The multipurpose register MPR may store information on the update of the status information STI (hereinafter, referred to as "status information log "). Processor (MPR) access mode by changing the operating mode (or mode register) of the physical layer 211 to a multipurpose register (MPR) access mode, The processor 101 can change the operation mode (or mode register) of the physical layer 211 using the RAM command CMD_R and the RAM address ADDR_R.

The nonvolatile memory system 200 according to another embodiment of the present invention writes the state information STI to the multipurpose register MPR after writing the state information STI into the state area STA , And then transmits the notification signal (Alert_n) to the processor 201. The processor 201 may read the status information log from the multipurpose register (MPR) in response to the alert signal Alert_n. The processor 201 can read the status information (STI) written in the status area STA according to the read status information log.

In the following, for the sake of simplicity and ease of explanation, the state information STI is written into the state area STA by the controller 212, and then the state information log is read by the controller 212 in the multipurpose register (MPR ). ≪ / RTI > However, the scope of the present invention is not limited thereto, and the status information log may be stored in a general purpose register (RAM) 211a included in the physical layer 211 or in a separate logic circuit or a separate control circuit located outside the physical layer MPR).

13 is a flowchart showing the operation of the nonvolatile memory system of FIG. 12 and 13, the non-volatile memory system 200 may perform the operations of steps S2010 to S2030. Illustratively, the operations of steps S2010 to S2030 are similar to those of steps S1010 to S1030 of FIG. 3, so a detailed description thereof will be omitted.

In step S2040, the non-volatile memory system 200 may write the status information log (STI log) to the multipurpose register (MPR). For example, the non-volatile memory system 200 may write a status information log (STI log) indicating that the status information (STI) is written in the status area (STA) to the multipurpose register (MPR).

In step S2050, the non-volatile memory system 200 transmits the notification signal Alert_n to the processor 201. [

In step S2060, the non-volatile memory system 200 transmits information written to the multipurpose register (MPR) to the processor 201 at the request of the processor 201. [ For example, the processor 201 may read the multipurpose register (MPR) in response to the alert signal Alert_n in step S2050. At this time, the non-volatile memory system 200 may transmit information written to the multipurpose register (MPR) to the processor 201 in response to a request of the processor 201 (i.e., a multipurpose register (MPR) read request). The information written to the multipurpose register (MPR) may include a status information log (STI log).

Illustratively, the processor 201 may read the status information (STI) written to the RAM 211b in response to the status information log (STI log) in step S2060.

According to the embodiment of the present invention described above, the nonvolatile memory system 200 writes the status information (STI) into the status area (STA) after completing the operation corresponding to the storage command (CMD_S) The log (STI log) is written to the multipurpose register (MPR). Then, the non-volatile memory system 200 provides the notification signal Alert_n to the processor 201. [ The processor 201 may read the status information log (STI log) written to the multipurpose register (MPR) in response to the alert signal Alert_n. The processor 201 can read the status information (STI) written in the status area STA based on the status information log (STI log). Thus, a nonvolatile memory system with improved performance is provided.

Illustratively, the non-volatile memory system 200 may send a notification signal (Alert_n) to the processor 201 in the event of a cyclic redundancy check (CRC) error of the storage command (CMD_S) or write data (DATA_W) have. In this case, the processor 201 reads the error log of the multipurpose register (MPR) and can recognize that a CRC error has occurred. In this case, the processor 201 can retransmit the storage command (CMD_S) or the write data (DATA_W) in which the CRC error has occurred to the nonvolatile memory system (200). That is, the nonvolatile memory system 200 transmits the notification signal Alert_n to the processor 201 when a CRC error occurs or when the status information is updated, and the processor 201 transmits the notification signal Alert_n to the multipurpose register (MPR ), And can operate based on the information read.

FIG. 14 is a flowchart showing a write operation of the user system of FIG. 12 in detail. Referring to Figs. 12 and 14, the processor 201 and the nonvolatile memory system 200 of the user system 20 perform the operations of steps S2110 to S2150. The operations in steps S2110 to S2150 are similar to those in steps S1110 to S1150 in FIG. 5, so that detailed description thereof will be omitted.

In step S2160, the processor 201 transmits a RAM command CMD_R and a RAM address ADDR_R for selecting the multipurpose register (MPR) to the nonvolatile memory system 200. For example, the non-volatile memory system 200 may write a status information log (STI log) to the MRP after writing the status information (STI) into the status area (STA). The processor 201 can transmit the RAM command CMD_R and the RAM address ADDR_R in response to the alert signal Alert_n to read the status information log STI log written in the multipurpose register MPR. Illustratively, the RAM command CMD_R may be a command for setting a mode register (not shown) included in the physical layer 211, and the RAM address ADDR_R may indicate a value of a mode register (not shown) have. Illustratively, the mode register is set by the RAM command CMD_R and the RAM address ADDR_R so that the multipurpose register MPR can be accessed.

In step S2170, the non-volatile memory system 200 may send information of the multipurpose register (MPR) to the processor 201. [ For example, the non-volatile memory system 200 may transmit information written to the multipurpose register (MPR) to the processor 201 in response to the RAM command CMD_R and the RAM address ADDR_R in step S2160. Illustratively, the information written to the multipurpose register (MPR) may include a status information log (STI log) and may be transmitted to the processor 201 via the data signal DQ and the data strobe signal DQS .

The processor 201 may perform the operation of step S2180 based on the read status information log (STI log). The nonvolatile memory system 200 may perform the operation of step S2190. The operations in steps S2180 and S2190 are similar to the operations in steps S1160 and S1170 in FIG. 4, so that descriptions thereof will be omitted.

FIG. 15 is a diagram for explaining steps S2160 and S2170 of FIG. 14 in detail. For the sake of brevity, unnecessary elements for describing the write operation are omitted, and detailed description of the redundant elements is omitted.

15, the processor 201 and the nonvolatile memory system 200 are configured to write a storage command (1), a command area read (2), a write data write (3) described with reference to FIGS. 5 and 6, , Write area read (4), and write data program (5). Thereafter, the controller 212 writes state information (STI) indicating completion of the write operation into the state area STA. (⑥)

Thereafter, the controller 212 may write a status information log (STI log) to the multipurpose register (MPR). (7) For example, the controller 212 may write the status information log (STI log) indicating that the status information (STI) is written in the status area (STA) to the multipurpose register (MPR). Illustratively, although not shown in the figure, the status information log (STI log) may be written to the multipurpose register (MPR) by the RAM controller 211a or by a separate logic circuit.

The controller 212 transmits the notification signal (Alert_n) to the processor 201. (⑧) The processor 201 can read the status information log (STI log) written in the multipurpose register (MPR) in response to the alert signal (Alert_n). (9) For example, the processor 201 transmits the RAM command CMD_R, the RAM address ADDR_R, and the clock CK to the RAM controller 211a. At this time, the RAM command CMD_R is a command for a mode register set (MRS) (not shown), and the RAM address ADDR_R may be a mode register setting value. The RAM controller 211a may set the mode register in response to the received signals and may transmit the information written in the general purpose register (i.e., the status information log (STI log)) to the processor 201 according to the set mode register . Illustratively, the status information log (STI log) may be transmitted to the processor 201 via the data signal DQ and the data strobe signal DQS.

The processor 201 can read the status information (STI) of the status area STA based on the status information log (STI log), as described with reference to FIG.

16 is a flowchart showing a read operation of the user system of FIG. 12 and 16, the processor 201 and the nonvolatile memory system 200 of the user system 20 can perform the operations of steps S2210 to S2290. The operations in steps S2210 to S2230 are similar to those in steps S1210 to S1230 in FIG. 8, so that a detailed description thereof will be omitted.

Operations in steps S2240 and S2250 are similar to those in steps S2160 and S2170 in FIG. 14, and thus detailed description thereof will be omitted. That is, the processor 201 may read the status information log (STI log) from the status multipurpose register (MPR) through operations in steps S2240 and S2250.

Operations in steps S2260 to S2290 are similar to steps 1240 to S1270 in FIG. 8, so that detailed description thereof will be omitted.

According to another embodiment of the present invention described with reference to FIGS. 12 to 16, after the nonvolatile memory system 200 completes the operation corresponding to the received storage command CMD_S, Into the state area STA, and writes the state information log STI log into the multipurpose register MPR. Thereafter, the non-volatile memory system 200 transmits the notification signal Alert_n to the processor 201. [ The processor 201 reads the status information log (STI log) from the multipurpose register (MPR) in response to the alert signal Alert_n and updates the status information (STI log) from the status area (STA) STI). Thus, a non-volatile memory system with improved performance and a method of operation thereof are provided.

Illustratively, according to another embodiment of the present invention described with reference to Figures 12-16, the non-volatile memory system 200 includes a status information log (STI log) or a CRC error log in a multipurpose register (MPR) After the writing, the notification signal Alert_n can be transmitted to the processor 201. The processor 201 can read the log written in the multipurpose register (MPR) in response to the alert signal (Alert_n), determine whether the read log indicates a status information update or a CRC error, can do. That is, since the nonvolatile memory system 200 can notify the processor 201 of information on status information update and CRC error occurrence using one alert signal (Alert_n), the nonvolatile memory system (200) is provided.

17 is a block diagram illustrating a user system according to another embodiment of the present invention. 17, the user system 30 includes a processor 301 and a non-volatile memory system 300. As shown in FIG. The non-volatile memory system 300 includes a device controller 310, a buffer memory 320, and a plurality of non-volatile memory devices 321 to 32n. The device controller 310 includes a physical layer 311 and a controller 312. The physical layer 311 includes a RAM controller 311a and a RAM 311b. The components of the user system 20 of FIG. 17 have been described with reference to FIG. 1, and a detailed description thereof will be omitted.

The processor 301 and the non-volatile memory system 300 can communicate based on a serial bus (SB). By way of example, the serial bus SB may be a two-line serial bus such as I2C, SMBus, PMBus, IPMI, MCTP, and the like.

The nonvolatile memory system 300 according to another embodiment of the present invention writes the status information STI to the RAM 311b after completing the operation corresponding to the storage command CMD_S. Thereafter, the non-volatile memory system 300 transmits the notification signal Alert_n to the processor 301. [

At this time, in contrast to the processor 101 of FIG. 1 and the processor of FIG. 12, the processor 301 may receive status information from the non-volatile memory system 300 via the serial bus SB in response to the alert signal Alert_n STI log). The processor 301 may read the status information (STI) written in the RAM 311b based on the received status information log (STI log).

According to another embodiment of the invention described above, the processor 301 may receive the status information log (STI log) via the serial bus SB in response to the alert signal Alert_n.

18 is a flowchart showing the operation of the nonvolatile memory system of FIG. 17 and 18, the non-volatile memory system 300 may perform the operations of steps S3010 to S3040. Operations in steps S3010 through S3040 are similar to operations in steps S1010 through S1040 of FIG. 3, and thus detailed description thereof will be omitted.

In step S3050, the non-volatile memory system 300 transmits a status information log (STI log) to the processor 301 via the serial bus SB. For example, in response to the alert signal Alert_n in step S3040, the processor 301 may send a request to the non-volatile memory system 300 to read the status information log (STI log) via the serial bus SB have. The non-volatile memory system 300 may send a status information log (STI log) to the processor 301 via the serial bus SB in response to the request.

FIG. 19 is a flowchart showing the write operation of the user system of FIG. 17 in detail. 20 is a diagram for explaining the operations of steps S3160 and S3170 of FIG. 17, 19, and 20, the processor 301 and the nonvolatile memory system 300 can perform the operations of steps S3110 to S3150. The operations of steps S3110 to S3150 are similar to those of steps S1110 to S1150 of FIG. 4, so a detailed description thereof will be omitted.

In step S3160, the processor 301 sends a request to the non-volatile memory system 300 to read the status information log (STI log). Illustratively, a request to read the status information log (STI log) may be sent over the serial bus (SB). The request to read the status information log (STI log) may be a signal defined by the serial bus (SB).

In step S3170, the non-volatile memory system 300 may transmit the status information log (STI log) to the processor 301 in response to the request in step S3160. Illustratively, the status information log (STI log) may be transmitted to the processor 301 via the serial bus SB.

For example, the nonvolatile memory system 300 includes a storage command write (1), a command area read (2), a write data write (3), a write area read (4) , And a write data program (5). Then, as shown in FIG. 20, the controller 312 can write the status information (STI) into the status area (STA). (6), the controller 312 may transmit the notification signal Alert_n to the processor 301. [ (⑦)

The processor 301 may read the status information log (STI log) from the non-volatile memory system 300 in response to the alert signal Alert_n. (8) For example, the processor 301 can read the status information log (STI log) from the nonvolatile memory system 300 via the serial bus SB.

Processor 301 and non-volatile memory system 300 may perform operations S3180 and S3190. Operations in steps S3180 and S3190 are similar to those in steps S1160 and S1170 in FIG. 1, so that detailed description thereof will be omitted.

Illustratively, communication between the processor 301 and the non-volatile memory system 300 based on the serial bus SB is not limited to the reading of the status information log (STI log) described above. By way of example, the processor 301 may request various information from the non-volatile memory system 300 via the serial bus SB, or may receive various information from the non-volatile memory system 300. Or the non-volatile memory system 300 may request various information from the processor 301 via the serial bus SB or may receive various information from the processor 301. [

FIG. 21 is a flowchart showing the read operation of the user system of FIG. 17 in detail. 17 and 21, the processor 301 and the nonvolatile memory system 300 perform steps S3210 to S3290. The operations in steps S3210 to S3230 are similar to the operations in steps S1210 to S1230 in Fig. 8, and operations S3240 to S3250 are similar to operations S3160 and S3170 in Fig. 19, and operations S3260 to S3290 The operations of the steps are similar to those of steps S2260 to S2290 of Fig. 16, so that detailed description of each step is omitted.

According to another embodiment of the present invention described with reference to FIGS. 17 through 21, the non-volatile memory system 300 may be configured to perform the following operations after completing the operation corresponding to the storage command CMD_S received from the processor 301 And writes the information STI in the state area STA. Thereafter, the non-volatile memory system 300 transmits the notification signal Alert_n to the processor 301. [ The processor 301 receives the status information log (STI log) from the nonvolatile memory system 300 via the serial bus SB in response to the alert signal Alert_n. Thus, a nonvolatile memory system with improved performance is provided.

22 is a block diagram illustrating an exemplary first nonvolatile memory device of the plurality of nonvolatile memory devices of FIG. 22, the nonvolatile memory device 131 includes a memory cell array 131a, an address decoder 131b, a control logic and voltage generating circuit 131c, a page buffer 131d, and an input / output circuit 131e .

The memory cell array 131a may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings. Each of the plurality of cell strings includes a plurality of memory cells. The plurality of memory cells may be connected to a plurality of word lines WL. Each of the plurality of memory cells may include a single level cell (SLC) storing one bit or a multi level cell (MLC) storing at least two bits.

The address decoder 131b is connected to the memory cell array 131a through a plurality of word lines WL, string selection lines SSL, and ground selection lines GSL. The address decoder 131b receives the physical address ADDR_P from the external device (for example, the device controller 110) and decodes the received physical address ADDR to drive the plurality of word lines WL can do. For example, the address decoder 131b decodes the physical address ADDR_P received from the external device and generates at least one word line of the plurality of word lines WL based on the decoded physical address ADDR_P And may drive at least one selected word line. Illustratively, the physical address ADDR_P indicates the physical address of the first nonvolatile memory 131 to which the storage address ADDR_S (see FIGS. 1 and 2) has been converted. The address translation operation described above may be performed by a flash translation layer (FTL) driven by the device controller 110 or the device controller 110. [

The control logic and voltage generating circuit 131c receives the storage command CMD_S and the control signal CTRL from the external device and supplies the address decoder 131b, the page buffer 131d, and the input / (131e). For example, the control logic and voltage generation circuit 131c may control other components so that the data (DATA) is stored in the memory cell array 131a in response to the signals CMD_S and CTRL. Or the control logic and voltage generation circuit 131c may control other components so that the data (DATA) stored in the memory cell array 131a is transferred to the external device in response to the signals CMD_S and CTRL. Illustratively, the storage command CMD_S received from the external device may be a modified command of the storage command CMD_S of FIG. The control signal CTRL may be a signal that the device controller 110 provides to control the nonvolatile memory 131. [

The control logic and voltage generation circuit 131c may generate various voltages required for the non-volatile memory 131 to operate. For example, the control logic and voltage generation circuit 131c may include a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, a plurality of unselected read voltages, a plurality of erase voltages, Can generate various voltages such as voltages. The control logic and voltage generation circuit 131c may provide the generated various voltages to the address decoder 131b or to the substrate of the memory cell array 131a.

The page buffer 131d is connected to the memory cell array 131a through a plurality of bit lines BL. The page buffer 131d controls the bit lines BL so that data (DATA) received from the input / output circuit 131e is stored in the memory cell array 131a under the control of the control logic and voltage generation circuit 131c . The page buffer 131d may read the data stored in the memory cell array 110 and transmit the read data to the input / output circuit 131e under the control of the control logic and the voltage generation circuit 131c. Illustratively, the page buffer 131d may receive data on a page-by-page basis from the input / output circuit 131e or may read data on a page-by-page basis from the memory cell array 131a.

The input / output circuit 131a receives the data (DATA) from the external device and can transfer the received data (DATA) to the page buffer 131d. Or the input / output circuit 131e may receive the data (DATA) from the page buffer 131d and transfer the received data (DATA) to an external device (for example, the device controller 110). Illustratively, the input / output circuit 160 can transmit and receive data (DATA) with an external device in synchronization with the control signal CTRL.

Illustratively, as an exemplary embodiment according to the technical concept of the present invention, each of the plurality of non-volatile memory devices 131 to 13n may include a three-dimensional memory array. The three-dimensional memory array may be monolithically formed on one or more physical levels of arrays of memory cells having an active region disposed over a silicon substrate and circuits associated with operation of the memory cells. The circuitry associated with the operation of the memory cells may be located within or on the substrate. The term monolithical means that layers of each level in a three-dimensional array are deposited directly on the lower-level layers of the three-dimensional array.

As an exemplary embodiment according to the technical concept of the present invention, a three-dimensional memory array has vertical directionality and includes vertical NAND strings in which at least one memory cell is located on the other memory cell. The at least one memory cell includes a charge trap layer. Each vertical NAND string may include at least one select transistor located over the memory cells. The at least one select transistor has the same structure as the memory cells and can be formed monolithically with the memory cells.

A three-dimensional memory array comprising a plurality of levels and having word lines or bit lines shared between the levels, a configuration suitable for a three-dimensional memory array is disclosed in U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466 U.S. Patent No. 8,654,587, U.S. Patent No. 8,559,235, and U.S. Patent Application Publication No. 2011/0233648, which are incorporated herein by reference.

23 is a circuit diagram showing an example of a first memory block among the memory blocks included in the memory cell array of FIG. Illustratively, the first memory block BLK1 of a three-dimensional structure will be described with reference to Fig. However, the scope of the present invention is not limited thereto, and other memory blocks included in each of the plurality of nonvolatile memory devices 131 to 13n may have a structure similar to that of the first memory block BLK1.

Referring to FIG. 23, the first memory block BLK1 includes a plurality of cell strings CS11, CS12, CS21, and CS22. A plurality of cell strings CS11, CS12, CS21, and CS22 may be arranged along a row direction and a column direction to form rows and columns.

For example, the cell strings CS11 and CS12 may be connected to the string selection lines SSL1a and SSL1b to form a first row. The cell strings CS21 and CS22 may be connected to the string selection lines SSL2a and SSL2b to form a second row.

For example, the cell strings CS11 and CS21 may be connected to the first bit line BL1 to form a first column. The cell strings CS12 and CS22 may be connected to the second bit line BL2 to form a second column.

Each of the plurality of cell strings CS11, CS12, CS21, and CS22 includes a plurality of cell transistors. For example, each of the plurality of cell strings CS11, CS12, CS21, and CS22 includes the string selected transistors SSTa and SSTb, the plurality of memory cells MC1 to MC8, the ground selected transistors GSTa and GSTb, And dummy memory cells DMC1, DMC2.

Illustratively, each of the plurality of cell transistors included in the plurality of cell strings CS11, CS12, CS21, CS22 may be a charge trap flash (CTF) memory cell.

The plurality of memory cells MC1 to MC8 are connected in series and are stacked in a height direction perpendicular to the plane formed by the row direction and the column direction. The string selected transistors SSTa and SSTb are connected in series and the strings of selected transistors SSTa and SSTb connected in series are provided between the plurality of memory cells MC1 to MC8 and the bit line BL. The ground selected transistors GSTa and GSTb are connected in series and the grounded selected transistors GSTa and GSTb connected in series are provided between the plurality of memory cells MC1 to MC8 and the common source line CSL.

Illustratively, a first dummy memory cell DMC1 may be provided between a plurality of memory cells MC1 to MC8 and ground selected transistors GSTa and GSTb. Illustratively, a second dummy memory cell DMC2 may be provided between the plurality of memory cells MC1 to MC8 and the string selected transistors SSTa and SSTb.

The ground selected transistors GSTa and GSTb of the cell strings CS11, CS12, CS21 and CS22 can be connected in common to the ground selection line GSL.

By way of example, the ground selected transistors in the same row can be connected to the same ground select line, and the ground selected transistors in the other row can be connected to different ground select lines. For example, the first ground selected transistors GSTa of the cell strings CS11, CS12 of the first row may be connected to the first ground selection line and the first ground selected transistors GSTa of the cell strings CS21, CS12 of the second row The first ground selected transistors (GSTa) may be connected to the second ground selection line.

Illustratively, although not shown in the drawings, the ground selected transistors provided at the same height from the substrate (not shown) may be connected to the same ground select line, and the ground selected transistors provided at different heights may be connected to another ground select line Can be connected. For example, the first ground selected transistors (GSTa) of the cell strings (CS11, CS12, CS21, CS22) are connected to the first ground selection line and the second ground selection transistors (GSTb) Line. ≪ / RTI >

Memory cells of the same height from the substrate (or ground selected transistors GSTa, GSTb) are commonly connected to the same word line, and memory cells of different heights are connected to different word lines. For example, cell strings The first to eighth memory cells MC8 of the memory cells CS11, CS12, CS21, and CS22 are commonly connected to the first to eighth word lines WL1 to WL8, respectively.

Strings of the same row among the first string selected transistors (SSTa) of the same height are connected to the same string selection line, and the other strings of string selected transistors are connected to another string selection line. For example, the first string selected transistors SSTa of the cell strings CS11 and CS12 of the first row are connected in common with the string selection line SSL1a and the cell strings CS21 and CS22 of the second row ) Are connected in common with the string selection line SSL1a.

Likewise, string selected transistors of the same row of the second string selected transistors (SSTb) of the same height are connected to the same string select line, and the other strings of string selected transistors are connected to different string select lines. For example, the second string selected transistors SSTb of the cell strings CS11, CS12 of the first row are connected in common with the string selection line SSL1b and the cell strings CS21, CS22 of the second row ) Are connected in common with the string selection line SSL2b.

Although not shown in the figure, string selected transistors of cell strings in the same row may be connected in common to the same string select line. For example, the first and second string selected transistors (SSTa, SSTb) of the cell strings CS11, CS12 of the first row may be connected in common to the same string selection line. The first and second string selected transistors (SSTa, SSTb) of the cell strings CS21, CS22 of the second row may be connected in common to the same string selection line.

Illustratively, dummy memory cells of the same height are connected to the same dummy word line, and dummy memory cells of different heights are connected to another dummy word line. For example, the first dummy memory cells DMC1 are connected to the first dummy word line DWL1, and the second dummy memory cells DMC2 are connected to the second dummy word line DWL2.

In the first memory block BLK1, reading and writing can be performed line by line. For example, one row of the memory block BLKa may be selected by the string selection lines SSL1a, SSL1b, SSL2a, and SSL2b.

For example, when the string selection lines SSL1a and SSL1b are supplied with the turn-on voltage and the turn-off voltage is supplied to the string selection lines SSL2a and SSL2b, the cell strings CS11, CS12 are connected to the bit lines BL1, BL2. When the turn-on voltage is supplied to the string selection lines SSL2a and SSL2b and the turn-off voltage is supplied to the string selection lines SSL1a and SSL1B, the cell strings CS21 and CS22 of the second row are supplied with the bit Connected to the lines BL1 and BL2 and driven. Memory cells of the same height among the memory cells of the cell strings of the row driven by driving the word lines are selected. Read and write operations can be performed on selected memory cells. Selected memory cells may form a physical page unit.

In the first memory block BLK1, erasing may be performed in units of memory blocks or units of subblocks. When erasing is performed in units of memory blocks, all the memory cells MC of the first memory block BLK1 can be erased simultaneously according to one erase request. When performed in units of sub-blocks, some of the memory cells MC of the first memory block BLK1 may be simultaneously erased in response to one erase request, and some of the memory cells MC of the first memory block BLK1 may be erased. A low voltage (e. G., Ground voltage) is applied to the word line connected to the erased memory cells, and the word line connected to the erased memory cells can be floated.

By way of illustration, the first memory block BLK1 shown in FIG. 23 is exemplary and the number of cell strings can be increased or decreased, and the number of rows and columns comprised by cell strings according to the number of cell strings is Increase or decrease. The number of the cell transistors GST, MC, DMC, SST, etc. of the first memory block BLK1 may be increased or decreased, and the height of the first memory block BLK1 Can be increased or decreased. Also, the number of lines (GSL, WL, DWL, SSL, etc.) connected to the cell transistors may be increased or decreased according to the number of cell transistors.

FIG. 24 is a block diagram illustrating a computing system to which a non-volatile memory system according to the present invention is applied. 14, a computing system 1000 includes a processor 1100, non-volatile memory modules 1200 and 1201, RAM modules 1300 and 1301, a chipset 1400, a GPU 1500, an input / 1600, and a storage device 1700.

The processor 1100 may control all operations of the computing system 1000. The processor 1100 may perform various operations performed in the computing system 1000.

The non-volatile memory modules 1200 and 1201 and the RAM modules 1300 and 1301 may be directly connected to the processor 1100. For example, each of the non-volatile memory modules 1200 and 1201 and the RAM modules 1300 and 1301 may have the form of a dual in-line memory module (DIMM) Each of the modules 1200 and 1201 and the RAM modules 1300 and 1301 may be mounted in a DIMM socket directly connected to the processor 1100 to communicate with the processor 1100. Illustratively, the non-volatile memory modules 1200 and 1201 may be the non-volatile memory systems 100, 200, and 300 described with reference to FIGS.

The non-volatile memory modules 1200 and 1201 and the RAM modules 1300 and 1301 may communicate with the processor 1100 through the same interface 1001. For example, the nonvolatile memory modules 1200 and 1201 and the RAM modules 1300 and 1301 can communicate through a double data rate (DDR) interface 1001. Illustratively, processor 1100 may use RAM modules 1300 and 1301 as operational memory, buffer memory, or cache memory of computing system 1000.

The chipset 1400 is electrically connected to the processor 1100 and can control the hardware of the computing system 1000 under the control of the processor 1100. [ For example, the chipset 1400 may be connected to the GPU 1500, the input / output device 1600, and the storage device 1700 via the main buses, respectively, and may serve as a bridge to the main buses.

The GPU 1500 may perform a series of arithmetic operations to output image data of the computing system 1000. Illustratively, GPU 1500 may be implemented within processor 1100 in a system-on-chip form.

The input / output device 1600 includes various devices that input data or instructions to the computing system 1000 or output data to the outside. For example, the input / output device 1600 A user input device such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, Display devices, AMOLED (Active Matrix OLED) displays, LEDs, speakers, motors, and the like.

The storage device 1700 may be used as a storage medium of the computing system 1000. Storage device 1600 may include mass storage media such as hard disk drives, SSDs, memory cards, memory sticks, and the like.

Illustratively, non-volatile memory modules 1200 and 1201 may be used by the processor 1100 as a mass storage medium of the computing system 1000. The interface 1001 between the non-volatile memory modules 1200 and 1201 and the processor 1100 may be a higher speed interface than the interface between the storage device 1700 and the processor 1100. [ That is, the performance of the computing system is improved by the processor 1100 using the nonvolatile memory modules 1200 and 1201 as a storage medium.

FIG. 25 is a block diagram illustrating one of the nonvolatile memory modules of FIG. 24 by way of example. Illustratively, FIG. 25 is a block diagram of a non-volatile memory module 1200 having the form of a Load Reduced DIMM (LRDIMM). Illustratively, the non-volatile memory module 1200 shown in FIG. 15 is in the form of a dual in-line memory module (DIMM) and is mounted in a DIMM socket to communicate with the processor 1100 .

Referring to Figure 25, a non-volatile memory module 1200 includes a device controller 1210, a buffer memory 1220, a non-volatile memory device 1230, and a serial presence detect chip 1240 (SPD) . The device controller 1210 may include a RAM 1211. Illustratively, non-volatile memory device 1230 may include a plurality of non-volatile memories (NVM). Each of the plurality of nonvolatile memories included in the nonvolatile memory device 1230 may be implemented as a separate chip, a separate package, a separate device, or a separate module, respectively. Or non-volatile memory device 1230 may be implemented in one chip or in one package.

By way of example, the device controller 1210, the RAM 1211, the buffer memory 1220, and the non-volatile memory device 1230 may include a device controller, a RAM, a buffer memory, and a plurality Lt; RTI ID = 0.0 > and / or < / RTI > non-volatile memory devices. That is, the non-volatile memory module 1200 may be any one of the non-volatile memory systems 100, 200, and 300 of FIGS.

Illustratively, the device controller 1210 can send and receive a plurality of data signals DQ and a plurality of data strobe signals DQS to and from the processor 1100, and receives a RAM command CMD_R via separate signal lines, The RAM address ADDR_R, and the clock CK. Illustratively, the device controller 1210 may send an alert signal (Alert_n) to the processor 1100 in accordance with the operating method described with reference to Figs. 1-23. Illustratively, the processor 1100 may read the status information (STI) stored in the RAM 1211 in response to the alert signal Alert_n.

SPD 1240 may be a programmable read-only memory (EEPROM). SPD 1240 may include initial information or device information of non-volatile memory module 1200. Illustratively, SPD 1240 may include initial information or device information such as module type, module configuration, storage capacity, module type, execution environment, etc. of non-volatile memory module 1200. When the computing system including the non-volatile memory module 1200 is booted, the processor 1100 of the computing system can read the SPD 1240 and recognize the non-volatile memory module 1200 based on the SPD 1240. The processor 1100 may use the nonvolatile memory module 1200 as a storage medium based on the SPD 1240.

Illustratively, the SPD 1240 may communicate with the processor 1100 via a serial bus SB. The processor 1100 can exchange the signal SBS with the SPD 1240 via the serial bus SB. Illustratively, the SPD 1240 may communicate with the device controller 1210 via the serial bus SB. Illustratively, the serial bus SB may include at least one of two-line serial buses such as I2C, SMBus, PMBus, IPMI, MCTP, and the like.

FIG. 26 is a block diagram illustrating one of the nonvolatile memory modules of FIG. 24 by way of example. Illustratively, FIG. 26 is a block diagram of a non-volatile memory module 2200 in the form of a Registered DIMM (RDIMM). Illustratively, the non-volatile memory module 2200 shown in FIG. 26 has the form of a dual in-line memory module (DIMM) and is mounted in a DIMM socket to communicate with the processor 1100 .

26, the non-volatile memory module 2200 includes a device controller 2210, a buffer memory 2220, a non-volatile memory device 2230, a serial presence detect chip (SPD) 2240, And a data buffer circuit 2250. The device controller 2210 includes a RAM 2211. Since the device controller 2210, the RAM 2211, the nonvolatile memory device 2230, and the SPD 2240 have been described with reference to FIGS. 1 and 15, a detailed description thereof will be omitted.

The data buffer circuit 2250 receives information or data from the processor 1100 (see FIG. 24) via the data signal DQ and the data strobe signal DQS and forwards the received information or data to the device controller 2250 . Or the data buffer circuit 2250 may receive information or data from the device controller 2210 and communicate the received information or data to the processor 1100 via the data signal DQ and the data strobe signal DQS.

Illustratively, data buffer circuit 2250 may include a plurality of data buffers. Each of the plurality of data buffers can exchange data signals DQ and data strobe signals DQS with the processor 1100. Or each of the plurality of data buffers can exchange signals with the device controller 2210. Illustratively, each of the plurality of data buffers may operate under the control of a device controller 2210.

Illustratively, the device controller 2210 may send an alert signal (Alert_n) to the processor 1100 in accordance with the operating method described with reference to Figs. 1-23.

FIG. 27 is a block diagram illustrating another example of a computing system to which the nonvolatile memory module according to the present invention is applied. For the sake of brevity, a detailed description of the components described above is omitted. 27, a computing system 3000 includes a processor 3100, a non-volatile memory module 3200, a chipset 3400, a GPU 3500, an input / output device 3600, and a storage device 3700 . The processor 3100, the chipset 3400, the GPU 3500, the input / output device 3600, and the storage device 3700 have been described with reference to FIG. 24, and a detailed description thereof will be omitted.

The non-volatile memory module 3200 may be directly coupled to the processor 3100. For example, the non-volatile memory module 3200 may take the form of a dual in-line memory module (DIMM) and may be mounted to a DIMM socket to communicate with the processor 3100.

The non-volatile memory module 3200 may include a control circuit 3210, a non-volatile memory device 3220, and a ram device 3230. Unlike the non-volatile memory modules 1200 and 2200 described with reference to FIGS. 24 through 26, the processor 3100 includes a non-volatile memory device 3220 and a non-volatile memory device 3220 of the non- Respectively. As a more detailed example, the control circuit 3210 may store the received data in the non-volatile memory device 3210 or in the RAM device 3220 under the control of the processor 3100. [ Or control circuitry 3210 may send data stored in non-volatile memory device 3210 to processor 3100 or may transfer data stored in ram device 3220 to processor 3100 under the control of processor 3100 have. That is, the processor 3100 can recognize the nonvolatile memory device 3210 and the RAM device 3220 included in the nonvolatile memory module 3200, respectively. The processor 3100 may store data in the non-volatile memory device 3220 of the non-volatile memory module 3200 or may read the stored data. Or processor 3100 may store data to or read data from RAM device 3230. [

The processor 3100 may use the non-volatile memory module 3200 of the non-volatile memory module 3200 as a storage medium of the computing system 3000, The RAM device 3220 of the computing system 3000 can be used as the main memory of the computing system 3000. That is, the processor 3100 can selectively access the nonvolatile memory device or the RAM device included in one memory module mounted on one DIMM socket, respectively.

Illustratively, the processor 3100 may communicate with the non-volatile memory module 3200 via a double data rate (DDR) interface 3001.

28 is a block diagram illustrating an exemplary non-volatile memory module of FIG. 27; 27 and 28, the non-volatile memory module 3200 includes a control circuit 3210, a non-volatile memory device 3220, and a ram device 3220. [ By way of example, non-volatile memory device 3220 may comprise a plurality of non-volatile memories, and RAM device 3230 may comprise a plurality of DRAMs. Illustratively, the plurality of non-volatile memories may be used by the processor 3100 as storage in the computing system 3000. Illustratively, each of the plurality of nonvolatile memories may be implemented as an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase change RAM (PRAM), a Resistive RAM (FRAM) Non-volatile memory devices such as spin-torque magnetic RAM (MRAM) and the like.

The plurality of DRAMs may be used by the processor 3100 as the main memory of the computing system 3000. By way of example, RAM device 3230 may include random access memory devices such as DRAM, SRAM, SDRAM, PRAM, ReRAM, FRAM, MRAM, and the like.

The control circuit 3210 includes a device controller 3211 and an SPD 3212. The device controller 3211 can receive the command CMD, the address ADDR, and the clock CK from the processor 3100. [ The device controller 3211 responds to signals received from the processor 3100 to transfer data received via the data signal DQ and the data strobe signal DQS to the non-volatile memory device 3220 or to the ram device 3230. [ As shown in FIG. Or device controller 3211 responds to signals received from processor 3100 to transfer data stored in non-volatile memory device 3220 or RAM device 3230 to data signal DQ and data strobe signal DQS Lt; RTI ID = 0.0 > 3100 < / RTI >

Illustratively, the processor 3100 may optionally access the non-volatile memory device 3220 or the RAM device 3230 via a command CMD, an address ADDR, or a separate signal or separate information. That is, the processor 3100 can selectively access the non-volatile memory device 3220 or the RAM device 3230 included in the non-volatile memory module 3200. [ Illustratively, the device controller 3211 may send an alert signal (Alert_n) to the processor 3100 in accordance with the operating method described with reference to Figs. 1-23.

29 is a block diagram illustrating an exemplary non-volatile memory module of FIG. 27; Illustratively, the non-volatile memory module 4200 of FIG. 29 has the form of a dual in-line memory module (DIMM) and may be mounted in a DIMM socket to communicate with the processor 3100.

27 and 29, the non-volatile memory module 4200 includes a control circuit 4100, a non-volatile memory device 4220, and a ram device 4230. The control circuit 4210 includes a device controller 4211, an SPD 4212, and a data buffer circuit 4213.

The device controller 4211 receives the command CMD, the address ADDR, and the clock CK from the processor 3100. The device controller 4211 may control the non-volatile memory device 4220 or the RAM device 4230 in response to the received signals. For example, as described with reference to FIG. 28, the processor 3100 may selectively access each of the non-volatile memory device 4220 or the RAM device 4230. The device controller 4231 can control the nonvolatile memory device 4220 or the RAM device 4230 under the control of the processor 3100. [

The data buffer circuit 4213 may receive the data signal DQ and the data strobe signal DQS from the processor 3100 and provide the received signals to the device controller 4211 and the RAM device 4230. Or the data buffer circuit 4213 may provide the data received from the device controller 4211 or the RAM device 4230 to the processor 3100 through the data signal DQ and the data strobe signal DQS.

Illustratively, when the processor 3100 stores data in the nonvolatile memory device 4220, the data received via the data signal DQ and the data strobe signal DQS is provided to the device controller 4211, The device controller 4211 can process the received data and provide it to the nonvolatile memory device 4220. [ Or the processor 3100 reads data stored in the nonvolatile memory device 4220, the data buffer circuit 4213 supplies the data provided from the device controller 4211 to the data signal DQ and the data strobe signal DQS, Lt; / RTI > to the processor 3100 via the network interface. Or the processor 3100 stores data in the RAM device 4230 the data received by the data buffer circuit 4213 is provided to the RAM device 4230 and the device controller 4231 receives the received command CMD, The address ADDR, and the clock CK to the RAM device 4230. Or when the processor 3100 reads data stored in the RAM device 4230, the device controller 4231 transfers the received command CMD, the address ADDR and the clock CK to the RAM device 4230 , The RAM device 4230 provides the data to the data buffer circuit 4213 in response to the transmitted signals and the data buffer circuit 4213 supplies the data signal DQ and the data strobe signal DQS, And may provide data to the processor 3100.

Illustratively, the device controller 4211 may send an alert signal Alert_n to the processor 3100 in accordance with the operating method described with reference to Figs. 1-23.

30 is a block diagram illustrating an exemplary non-volatile memory module of FIG. 27; 27 and 30, the non-volatile memory module 5200 includes a control circuit 5210, a non-volatile memory device 5220, and a RAM device 5230. [ The control circuit 5210 includes a device controller 5211 and an SPD 5212.

The nonvolatile memory module 5200 of FIG. 20 may operate similarly to the nonvolatile memory module 4200 of FIG. The nonvolatile memory module 5200 of FIG. 20 does not include the data buffer circuit 4213 unlike the nonvolatile memory module 4200 of FIG. That is, the nonvolatile memory module 5200 of FIG. 20 provides the data received via the data signal DQ and the data strobe signal DQS from the processor 3100 directly to the device controller 5211 or the RAM device 5230 can do. The data from the device controller 5211 of the nonvolatile memory module 5200 of Figure 20 or the data from the RAM device 5230 is supplied to the processor 3100 through the data signal DQ and the data strobe signal DQS. Can be provided directly.

Illustratively, the non-volatile memory module 4200 of FIG. 19 is a memory module in the form of an LRDIMM (Load Reduced DIMM), and the non-volatile memory module 5200 of FIG. 20 may be a memory module in the form of a Registered DIMM .

Illustratively, the device controller 5211 may send a notification signal Alert_n to the processor 3100 in accordance with the operating method described with reference to Figs. 1-23.

31 is a diagram illustrating a server system to which a nonvolatile memory system according to an embodiment of the present invention is applied. Referring to FIG. 31, the server system 6000 may include a plurality of server racks 6110 to 61n0. Each of the plurality of server racks 6110 to 61n0 may include a plurality of nonvolatile memory modules 6200. [ The plurality of nonvolatile memory modules 6200 may be directly connected to the processors included in each of the plurality of server racks 6110 to 61n0. For example, a plurality of non-volatile memory modules 6200 may take the form of dual in-line memory modules and may be mounted in a DIMM socket electrically connected to the processor to communicate with the processor. Illustratively, a plurality of non-volatile memory modules 6200 may be used as storage for the server system 6000. Illustratively, the plurality of non-volatile memory modules 6200 may operate in accordance with the method described with reference to Figures 1-23.

According to the embodiments of the present invention described above, the non-volatile memory system writes the status information into the status area of the RAM after completing the operation corresponding to the storage command received from the processor (or host). Then, the non-volatile memory system transmits the alert signal Alert_n to the processor, and the processor can read the status information in response to the alert signal Alert_n. Illustratively, the processor can read information from the multipurpose register in response to the alert signal (Alert_n), or receive information from the non-volatile memory system over the serial bus, and read the status information based on the read information or the received information have. That is, since the processor does not periodically poll the non-volatile memory system to check the status information of the non-volatile memory system, the overhead due to the periodic polling is reduced. Thus, not only does the utilization of the processor increase, but also a non-volatile memory system with improved performance and a method of operation thereof are provided.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the following claims.

100: non-volatile memory system 110: device controller
111: physical layer 111a: RAM controller
111b: RAM 111c: storage signal driver
112: controller 120: buffer memory
131 to 13n: a plurality of nonvolatile memory devices
CMD_R: RAM command ADDR_R: RAM address
CK: clock DQ: data signal
DQS: Data strobe signal CMD_S: Storage command
ADDR_S: Storage address DATA: Data
STI: Status information Alert_n: Notification signal

Claims (10)

At least one non-volatile memory device; And
And a device controller for receiving a storage command from an external device and performing an operation corresponding to the received storage command,
Wherein the device controller comprises a RAM,
Wherein the device controller stores status information in the RAM after completing the corresponding operation, and then transmits a notification signal to the external device. The method according to claim 1,
Wherein the status information includes information on the completion of the corresponding operation. The method according to claim 1,
Wherein the device controller transmits the status information to the external device upon request of the external device after transmitting the notification signal to the external device. The method according to claim 1,
Wherein the device controller further comprises a multipurpose register for storing a status information log indicating that the status information is written to the RAM. 5. The method of claim 4,
Wherein the device controller receives a RAM command and a RAM address from the external device and transmits the status information log stored in the multipurpose register to the external device in response to the received RAM command and the RAM address. The method according to claim 1,
Wherein the device controller transmits a status information log indicating that the status information is written in the RAM to the external device via a serial bus in response to a request from the external device after transmitting the notification signal to the external device, Memory modules. The method according to claim 6,
Wherein the serial bus is an I2C bus. The method according to claim 1,
Wherein the device controller receives a RAM command, a RAM address, a clock, a data signal, and a data strobe signal from the external device, and receives the RAM command, the RAM address, And stores the data command and the storage command included in the data strobe signal in a part of the RAM. The method according to claim 1,
Wherein the storage command is a command indicating a write, read, or erase operation to the at least one non-volatile memory device. The method according to claim 1,
Wherein the device controller communicates with the external device based on a DDR (Double Data Rate) interface.

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