KR20160150183A - Display device for high-speed driving and driving method of the same - Google Patents

Abstract

According to an embodiment of the present invention, a display device for high-speed driving comprises: a display panel; a source driver to supply a data voltage to data lines of the display panel; a gate driver to supply a gate pulse to gate lines of the display panel; a memory to sequentially store input image data applied from the outside; and a timing controller to divide input image data of one frame stored in the memory into a first data group to a k^th data group (k is an integer larger than or equal to two), and control operations of the source driver and the gate driver to sequentially write from the first data group to the k^th data group in from a first block to a k^th block according to an output frame frequency higher than an input frame frequency. The first data group to the k^th data group are completely written in corresponding blocks during a scan period shorter than n/k time (n indicates one frame period according to the input frame frequency). Drive power applied to buffer units of the source driver is blocked during a skip period excluding the scan period in the n/k time.

Description

[0001] The present invention relates to a display device for high-speed driving and a method of driving the same,

The present invention relates to a display device for high-speed driving and a driving method thereof.

The display device is used for various display devices such as portable information devices, office equipment, computers, and televisions. The display device includes a display panel for displaying an image and a driver for driving the display panel. In the display panel, a plurality of data lines and a plurality of gate lines are formed, and a pixel is formed for each of the intersection areas. The driver includes a source driver for driving the data lines and a gate driver for driving the gate lines.

Various methods for reducing the power consumption in the display device are known, and one of them is a 60 Hz HRR (High Refresh Rate) driving method as shown in FIG. The 60 Hz HRR method refreshes the entire screen of the display with a frame frequency higher than the input frame frequency. The 60Hz HRR method receives 60Hz input, stores it in the frame memory, and outputs the stored data to 120Hz quickly for the next frame. Refreshing to 120 Hz for the first 1 / 120s, and turning off the source driver IC for the remaining 1 / 120s to reduce power consumption. As described above, the method for driving the 60 Hz HRR requires a frame memory which is a storage medium (storage means), as shown in Fig. 2, in order to convert data of 60 Hz to data of 120 Hz. That is, since the data is inputted at 60 Hz in the 60 Hz HRR driving method, one frame of data must be stored in advance in order to output it at 120 Hz. Accordingly, since the timing controller must be mounted on the frame memory, the cost increases greatly.

Another method for reducing power consumption is a 120 Hz frame skip driving method. Since the 120Hz frame skip driving method is driven at 120Hz instead of 60Hz, the number of LVDS ports is doubled compared to 60Hz. Accordingly, the 120 Hz frame skip driving method requires twice the number of physical lines, doubling the number of connectors, and doubling the number of user cables.

As described above, in the 120 Hz frame skip driving method, a 4-port input must be input on the basis of the LVDS input as shown in FIG. 3, so that the data of the user cable, The transmission line is doubled in comparison with 60 Hz. Therefore, it is a driving method which is not possible with a 60Hz interface, and a 120Hz frame can be driven by a 120Hz frame skip so that the cost increases.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an image processing apparatus and a method thereof, in which a plurality of groups of data obtained by dividing input image data are scanned during a scanning period shorter than n / k time (k is a positive integer of 2 or more, A display device for a high-speed driving device capable of significantly reducing power consumption by controlling the driving power applied to the buffer portions of the source driver to be cut off during a skip period excluding the scanning period among n / k times, And a driving method thereof.

A source driver for supplying a data voltage to the data lines of the display panel, a gate driver for supplying gate pulses to the gate lines of the display panel, and a gate driver for sequentially supplying input image data, (K is a positive integer equal to or larger than 2) of the input image data of one frame stored in the memory and the memory is divided into a first data group to a k-th data group Wherein the first data group to the k-th data group are sequentially written in the first block to the k-th block of the display panel, wherein each of the first to k- k < / RTI > time (n indicates one frame period in accordance with the input frame frequency) Include those per block write is complete and, n / driving power applied to the buffer portions of the source driver during the period other than the k skip scanning period in time in a block.

A source driver for supplying a data voltage to the data lines of the display panel, a gate driver for supplying gate pulses to the gate lines of the display panel, The method comprising: dividing input image data of one frame stored in a memory into a first data group to a k-th data group (k is a positive integer of 2 or more) Controlling the operation of the source driver and the gate driver so that the first to k-th data groups are sequentially written to the first to k-th blocks of the display panel according to the dividing step and the output frame frequency higher than the input frame frequency , And the control step includes a step of setting each of the first to k-th data groups to n / k time A first frame period shorter than the first frame period and indicating one frame period according to the input frame frequency) and a step of switching the driving power applied to the buffer units of the source driver during the skip period excluding the scan period among n / k times Lt; / RTI >

The present invention is characterized in that a plurality of data groups obtained by dividing input image data are divided into a plurality of blocks during a scan period shorter than n / k time (k is a positive integer of 2 or more, n is one frame period according to the input frame frequency) The writing operation is sequentially completed and the driving power applied to the buffer portions of the source driver during the skip period excluding the scanning period among the n / k times can be controlled to be shut off. As a result, the power consumption can be reduced.

In addition, the present invention is characterized in that a plurality of data groups are sequentially written to a plurality of blocks of a display panel, so that pixel data of all the lines of the pixel array can be stored, can do. As described above, there is an effect that the production cost can be reduced by utilizing the memory mounted on the timing controller without applying the frame memory.

FIG. 1 is a diagram showing the power consumption reduction through a conventional 60 Hz HRR. FIG.
Figure 2 is a simplified block diagram for driving a conventional 60 Hz HRR;
3 is a simplified block diagram for driving a conventional 120 Hz frame skip.
4 is a block diagram showing a display device for high-speed driving according to an embodiment of the present invention.
5 is a block diagram showing a timing controller according to an embodiment of the present invention;
FIGS. 6 to 8 are schematic views illustrating the principle of scan and skip driving sequentially to a first data group and a second data group according to the present invention;
9 is a schematic diagram showing a driving signal controlled by a timing controller according to an embodiment of the present invention.
10 is a view showing a specific configuration of a source driver according to an embodiment of the present invention.
Fig. 11 is a schematic diagram showing that consumption current is zeroed by operating with Fig. 10; Fig.
12 to 14 are schematic diagrams illustrating the principle of scan & skip driving sequentially to a plurality of data groups according to various embodiments of the present invention.
15 is a view showing an effect of power consumption reduction when the present invention is driven.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 4 to 11. FIG.

4 is a block diagram showing a display device for high-speed driving according to an embodiment of the present invention. 5 is a block diagram illustrating a timing controller according to an embodiment of the present invention. 6 to 8 are schematic diagrams illustrating the principle of scan and skip driving sequentially to the first data group and the second data group according to the present invention. 9 is a schematic diagram showing a driving signal controlled by a timing controller according to an embodiment of the present invention.

4, the display device for high-speed driving according to the present invention includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) An organic light emitting diode (OLED) display, and an electrophoresis (EPD) display device. In the following embodiments, the display device will be described mainly with respect to the liquid crystal display device, but it should be noted that the display device of the present invention is not limited to the liquid crystal display device.

In the liquid crystal display panel 10, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 10 includes liquid crystal cells Clc arranged in a matrix form by an intersection structure of the data lines 15 and the gate lines 16. [

On the lower glass substrate of the liquid crystal display panel 10, a pixel array is formed. The pixel array includes a liquid crystal cell (Clc, pixel) formed at the intersection of the data lines 15 and the gate lines 16, TFTs connected to the pixel electrode 1 of the pixels, A common electrode 2 and a storage capacitor Cst. Each of the liquid crystal cells Clc is connected to a TFT (Thin Film Transistor) and driven by an electric field between the pixel electrode 1 and the common electrode 2.

A black matrix, red (R), green (G), and blue (B) color filters are formed on the upper glass substrate of the liquid crystal display panel 10. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, a polarizing plate is attached and an alignment film for setting a pre-tilt angle of the liquid crystal is formed.

The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving method such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode. And is formed on the lower glass substrate together with the pixel electrode 1 in the horizontal electric field driving system.

The liquid crystal display panel 10 applicable to the present invention may be implemented in any liquid crystal mode as well as a TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In Plane Switching) mode, FFS . The liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, and a reflective liquid crystal display device. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The timing controller 11 receives input image data RGB from the host system 14 through a low voltage differential signaling (LVDS) interface method and supplies the input image data RGB to the source driver 12 through an LVDS interface method. . Here, the present invention is not limited to the LVDS interface method, and a Mini-LVDS interface method or an EPI (Embedded Clock Point-to-Point Interface) method is also available.

The timing controller 11 arranges the input image data (RGB) input from the host system 14 in accordance with the layout configuration of the pixel array, and supplies the sorted image data to the source driver 12. [

The timing controller 11 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock CLK from the host system 14, And generates control signals for controlling the operation timings of the driver 12 and the gate driver 13. [ The control signals include a gate timing control signal for controlling the operation timing of the gate driver 13 and a source timing control signal for controlling the operation timing of the source driver 12. [

The timing controller 11 controls operations of the source driver 12 and the gate driver 13 to implement high-speed driving through interface driving. The timing controller 11 controls the timing controller 11 so that the digital video data RGB input at the first frequency is refreshed in the pixel array of the liquid crystal display panel 10 in conformity with the second frequency which is twice or more of the first frequency, And appropriately generates a control signal and a source timing control signal. Here, the first frequency may have an input frame frequency and a frequency range of 50 to 60 Hz. The second frequency may have a frequency range of 120 Hz which is an output frame frequency and is at least twice the first frequency.

5, the timing controller 11 receives a timing signal and input image data (RGB) from the host system 14 through a first LVDS port or a second LVDS port and outputs the timing signal and the input image data RGB to a reception unit (LVDS Rx 111) . The receiving unit 111 converts the received input image data RGB into a TTL signal and supplies the TTL signal to a memory 112. The memory 112 sequentially stores input image data applied from the outside and supplies the stored input image data RGB to an EPI block. The memory 112 receives the dot clock CLK corresponding to twice the first frequency from the memory oscillator 114 and outputs the input image data RGB in accordance with the speed of the dot clock CLK, (EPI block 113). Wherein the memory has a memory capacity in which pixel data of a plurality of lines of the pixel array can be stored. The line memory also has a memory capacity in which one line of pixel data of the pixel array can be stored. The EPI block 113 receives the dot clock CLK corresponding to twice or more the first frequency from the Oscillator_EPI block 115 of the EPI block and outputs the dot clock CLK corresponding to the speed of the dot clock CLK And the input image data (RGB) is output. Although the above description has been made on the EPI block, various interface methods such as the Mini-LVDS interface method are also possible.

The gate timing control signal includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), and the like. The gate start pulse GSP is applied to a gate driver IC (integrated circuit) generating a first gate pulse to control the gate driver IC so that a first gate pulse is generated. The gate shift clock GSC is a clock signal commonly input to the gate driver ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate driver ICs.

The source timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), a source output enable signal (SOE) . The source start pulse SSP controls the data sampling start timing of the source driver 12. [ The source sampling clock SSC is a clock signal for controlling the sampling timing of data in the source driver 12 on the basis of the rising or falling edge. The polarity control signal POL controls the polarity of the data voltages sequentially output from each of the source driver ICs. The source output enable signal SOE controls the output timing of the source driver 12.

6 and 7, the timing controller 11 virtually divides the liquid crystal display panel 10 into at least one block, and stores the input image data stored in the memory in the divided blocks in accordance with the driving order And can be driven sequentially.

The timing controller 11 divides the input image data of one frame stored in the memory into a first data group and a second data group and outputs the first data group to the liquid crystal display panel 10 according to an output frame frequency higher than the input frame frequency. And controls the operations of the source driver and the gate driver so as to be sequentially written to the first block and the second block. In the timing controller 11, the first data group is written in the corresponding block for a scan period shorter than n / 2 time (n indicates one frame period according to the input frame frequency) So that the driving power applied to the buffer units of the source driver is interrupted during the skip period.

8, when one frame is formed of 1080 lines, each of the first block and the second block of the display panel may be divided into 540 lines.

The timing controller 11 may sequentially write the first data group to the first block and the second block of the display panel 10 according to the output frame frequency higher than the input frame frequency.

The timing controller 11 controls the input data of one frame stored in the memory to sequentially write the first data group to the first block and the second block of the display panel in accordance with a frame frequency higher than the input frame frequency, The input image data to be supplied to the data group is stored in the memory.

The timing controller 11 completes writing in the corresponding block during a scan period in which the first data group is shorter than n / 2 time. In this case, n may indicate one frame period according to the input frame frequency. Accordingly, writing can be completed to the corresponding block 540 line for a short period in which the first data group is written up to 270 lines.

Herein, the timing controller 11 has described that the first data group is written in the corresponding block for a scan period shorter than n / k time (k is a positive integer of 2 or more), but the present invention is not limited thereto, and the n / k time Or may write the first data group in the corresponding block for a scan period longer than n / k time.

Accordingly, each of the scan period and the skip period may be equal to n / 2k time. In addition, if the scan period is shortened, the skip period may be relatively long. On the contrary, if the scan period is long, the scan period may be relatively short.

9 (b), the timing controller 11 controls the gate shift clock (GSC) of the conventional gate shift clock (GSC) shown in FIG. 9 (a) The amplitude of the gate shift clock can be reduced in order to control the first data group to be written in the corresponding block for a shorter time. In addition, a source output enable (SOE) signal of the source driver 12 is controlled to supply a data voltage synchronized with the scan of the first data group to the data lines. Then, the timing controller 11 can suspend the operation of the source driver 12 during the first skip period in which writing to the corresponding block is completed.

The timing controller 11 controls the operation of the source driver and the gate driver so that the second data group is sequentially written to the first block and the second block of the liquid crystal display panel 10 in accordance with the output frame frequency higher than the input frame frequency do. The timing controller 11 completes writing in the corresponding block during a scan period in which the second data group is shorter than n / 2 time (n indicates one frame period according to the input frame frequency) So that the driving power applied to the buffer units of the source driver is interrupted during the skip period. The method of driving the scan and the skip by the second data group is substantially the same as the method of driving the scan and the skip by the first data group, and a detailed description thereof will be omitted.

As described above, the timing controller 11 writes in the corresponding block during a scan period shorter than n / k time (n indicates one frame period according to the input frame frequency) for each of the first data group and the second data group And controls the driving power applied to the buffer units of the source driver to be cut off during the skip period excluding the scan period among the n / k times.

That is, the timing controller 11 generates a buffer operation control signal after completion of writing to the corresponding block during a short scan period by high-speed driving, and turns off the operation of the source driver during a skip period excluding the scan time.

9 (b), the timing controller 11 generates the buffer operation control signal LITEST at the on level (LV1) when the writing to the corresponding block is completed, and outputs the buffer operation control signal LITEST at the off level LV2 to control the switching of the first and second power switches SW1 and SW2 of the source driver 12 shown in Fig. Although the first level LV1 is shown as an ON level and the second level LV2 is shown as an OFF level in FIG. 9B, the first and second power switches SW1 and SW2 of FIG. Depending on the type (P type, N type, etc.), the on level and off level may vary. The driving power source (high potential driving voltage, base low voltage) applied to the buffer portions of the source driver 12 is not blocked when the buffer operation control signal LITEST is generated at the first level LV1, And is cut off when the control signal LITEST is generated at the second level LV2. The timing controller 11 controls the source driver 12 to stop the driving of the source driver 12 during the remaining period after the writing of the first data group or the second data group in the scan period, that is, during the skip period, And the static current flowing in the buffer units of the source driver 12 can be removed. As a result, the power consumption of the source driver 12 can be drastically reduced.

The source driver 12 includes a shift register, a latch array, a digital-analog converter, an output circuit, and the like. The source driver 12 latches the digital video data RGB according to the source timing control signal and then converts the latched data into an analog positive / negative gamma compensation voltage to convert the data voltages whose polarities are reversed in a predetermined cycle to a plurality of To the data lines 15 through the output channels. The output circuit includes a plurality of buffer portions. The buffer portions are connected to the output channels, and each of the output channels is connected to the data lines 15 on a one-to-one basis. The source driver 12 controls the polarity of the data voltages output to the output channels in a column inversion manner in order to reduce power consumption. Based on the column-inversion method, the polarity of the data voltage output on the same output channel can be inverted on a frame-by-frame basis. And the polarities of the data voltages output from the neighboring output channels are opposite to each other.

The gate driver 13 supplies gate pulses to the gate lines 16 in accordance with the gate timing control signals using the shift register and level shifter in the above-described interlace driving method. The shift register of the gate driver 13 may be formed directly on the lower glass substrate according to a gate-driver in panel (GIP) scheme.

10 shows a specific configuration of the source driver 12 in detail. FIG. 11 shows that the consumption current is zeroed by operating according to FIG.

10 and 11, the source driver 12 includes a first digital-analog converter (P-DAC) for converting input digital video data to a positive gamma compensation voltage, and a second digital-to-analog converter A second digital-analog converter (N-DAC) for converting the input digital video data to a negative gamma compensation voltage, a second digital-to-analog converter (N-DAC) And a buffer unit BUF2.

The first buffer unit BUF1 and the second buffer unit BUF2 are supplied with the high potential driving voltage VDD and the ground potential GND and the intermediate potential driving voltage HVDD between these potentials VDD and GND. The voltage level of the intermediate potential driving voltage HVDD corresponds to half of the high potential driving voltage VDD and can be selected to be substantially equal to the common voltage Vcom applied to the liquid crystal display panel 10. [

The first buffer unit BUF1 includes a first input part PI operated by a high potential driving voltage VDD and a ground potential GND and a second input part PI by a high potential driving voltage VDD and an intermediate potential driving voltage HVDD And a first output (PO) to be operated.

The second buffer unit BUF2 includes a second input unit NI operated by a high potential driving voltage VDD and a ground voltage GND and a second input unit NI operated by an intermediate potential driving voltage HVDD and a ground voltage GND And a second output unit NO.

A first dynamic current DIDD1 is output from the first output unit PO or a second dynamic current DIDD2 is output from the first output unit PO by the switching operation of the first output unit PO, Respectively. A third dynamic current DIDD3 is output from the second output unit NO by the switching action of the second output unit NO or a fourth dynamic current DIDD4 is output from the second output unit NO . The first and third dynamic currents DIDD1 and DIDD3 flow to the data lines through the output channels CH1 and CH2 to realize the high and low gradation images and the second and fourth dynamic currents DIDD2 and DIDD4, Flows through the data lines (CH1, CH2) from the data line when implementing a low-gradation image.

In order for the polarities of the data voltages output from the neighboring output channels CH1 and CH2 to be opposite to each other and the polarity of the data voltage output from the same output channel to be inverted in units of frames in the source driver 12, Fourth polarity inversion switches OS1, OS2, OS3, OS4 may be further provided. The ON times of the first and fourth polarity inversion switches OS1 and OS4 are alternated with the ON time of the second and third polarity inversion switches OS2 and OS3 in units of frames. 10, the first and fourth polarity inversion switches OS1 and OS4 are turned on in the first frame and off in the second frame, while the second and third polarity inversion switches (OS1 and OS4) OS2, OS3 may be off in the first frame and turned on in the second frame. The present invention is characterized in that the number of the first digital-analog converter (P-DAC) and the number of the second digital-analog converter (N-DAC) are different from each other through the alternating operation of the polarity reversing switches OS1, OS2, OS3, The number can be reduced to half each.

A first power switch SW1 connected between an input terminal of the high potential driving voltage VDD and the first output unit PO and a second power switch SW2 connected between the input terminal of the high potential driving voltage VDD and the first output unit PO to completely block the static current SIDD in the skip period of each frame, And a second power switch SW2 connected between the input terminal of the ground voltage GND and the second output unit NO.

The first and second power switches SW1 and SW2 are turned on or turned off in response to the buffer operation control signal LITEST input from the timing controller 11. [ The first and second power switches SW1 and SW2 are turned on according to the buffer operation control signal LITEST of the on level LV1 during the first scan period and the second scan period of one frame, And is turned off according to the buffer operation control signal LITEST of the off level LV2 during the skip period of one frame. When the first and second power switches SW1 and SW2 are turned off in a skip period of one frame, a closed loop through which a static current can flow is canceled.

The static current flowing between the input terminal of the high potential driving voltage VDD and the first buffer unit BUF1 and the static current flowing between the input terminal of the ground voltage GND and the second buffer unit BUF2, Time period.

The present invention described so far is characterized in that the first data group and the second data group are sequentially written in the first block to the second block of the display panel so that pixel data of all the lines of the pixel array can be stored It can have less memory capacity than the frame memory. Thus, the present invention can operate with a memory capacity that is 1/2 smaller than the memory capacity of the frame memory.

12 to 14 show the principle of scan & skip driving sequentially to a plurality of data groups according to various embodiments of the present invention.

12 and 13, when one frame is formed by 1080 lines, each of the first through fourth blocks may be divided into 270 lines.

The timing controller 11 can sequentially write the first data group to the first block to the fourth block of the display panel 10 according to the output frame frequency higher than the input frame frequency.

The timing controller 11 completes writing in the first block during a scan period in which the first data group is shorter than n / 4 time. In this case, n may indicate one frame period according to the input frame frequency. Thus, writing can be completed to the 270th line, which is the first block, for a short period in which the first data group is written up to 135 lines. When the first data group completes writing in the first block for a scan period shorter than n / 4 time, the timing controller 11 can complete the write in the second block to the fourth block sequentially after the skip period.

In addition, the timing controller 11 performs operations of the source driver and the gate driver such that the second data group is sequentially written to the first block to the fourth block of the liquid crystal display panel 10 in accordance with the output frame frequency higher than the input frame frequency . The timing controller 11 completes writing of the second data group in the corresponding block for a scan period shorter than n / 4 time (n indicates one frame period according to the input frame frequency) So that the driving power applied to the buffer units of the source driver is interrupted during the skip period.

The present invention is also applicable to the case where the first and second power switches SW1 and SW2 added to the source driver 12 are turned off during the skip period of the first block to the fourth block, The static current flowing between the input terminal and the first buffer unit BUF1 and the static current flowing between the input terminal of the ground voltage GND and the second buffer unit BUF2 are cut off. A detailed description thereof has already been described above, and therefore, it will be omitted.

As described above, the timing controller 11 determines whether the first data group and the second data group are in the first block or the second block during a scan period shorter than n / 4 time (n indicates one frame period according to the input frame frequency) The writing operation is sequentially completed in the fourth block and the driving power applied to the buffer portions of the source driver is cut off during the skip period excluding the scanning period among n / 4 times.

That is, according to the present invention, the first data group and the second data group are sequentially written in the first block to the fourth block of the display panel, whereby a frame having a memory capacity capable of storing pixel data of all the line amounts of the pixel array It can have less memory capacity than memory. Accordingly, the present invention can operate at a memory capacity of 1/4 smaller than the memory capacity of the frame memory.

As shown in FIG. 14, when one frame is formed by 1080 lines, each of the first to eighth blocks may be divided into 135 lines.

The timing controller 11 can sequentially write the first data group to the first to eighth blocks of the display panel 10 according to the output frame frequency higher than the input frame frequency.

The timing controller 11 completes writing in the first block during a scan period in which the first data group is shorter than n / 8 hours. In this case, n may indicate one frame period according to the input frame frequency. Accordingly, writing can be completed to the 135th line, which is the first block, for a short time period in which the first data group is written up to the 67th to 68th lines. When the first data group completes writing in the first block for a scan period shorter than n / 8 time, the timing controller 11 can complete the write in the second to eighth blocks sequentially after the skip period.

In addition, the timing controller 11 controls the operation of the source driver and the gate driver so that the second data group is sequentially written to the first to eighth blocks of the liquid crystal display panel 10 in accordance with the output frame frequency higher than the input frame frequency . The timing controller 11 completes writing in the corresponding block during a scan period in which the second data group is shorter than n / 8 time (n indicates one frame period according to the input frame frequency) So that the driving power applied to the buffer units of the source driver is interrupted during the skip period.

The present invention is also applicable to a case where the first and second power switches SW1 and SW2 added to the source driver 12 are turned off during the skip period of the first to eighth blocks to turn off the high- The static current flowing between the input terminal and the first buffer unit BUF1 and the static current flowing between the input terminal of the ground voltage GND and the second buffer unit BUF2 are cut off. A detailed description thereof has already been described above, and therefore, it will be omitted.

As described above, the timing controller 11 determines whether the first data group and the second data group are in the first block or the second block during a scan period shorter than n / 8 hours (n indicates one frame period according to the input frame frequency) The writing operation is sequentially completed in the eighth block, and the driving power applied to the buffer portions of the source driver during the skip period excluding the scanning period among the n / 4 times is shut off.

That is, according to the present invention, the first data group and the second data group are sequentially written in the first to eighth blocks of the display panel, whereby a frame having a memory capacity capable of storing pixel data of all the lines of the pixel array It can have less memory capacity than memory. Accordingly, the present invention can operate with a memory capacity of 1/8 smaller than the memory capacity of the frame memory.

15 shows the power consumption reduction effect according to the time during which the source driver is turned off during the skip period according to the present invention.

Referring to FIG. 15, it can be seen that as the time during which the source driver is turned off during the skip period of the present invention, the power consumption is greatly reduced compared to the power consumption at 60 Hz normal driving.

As described above, according to the present invention, the input image data divided into the first data group and the second data group are sequentially written into the first to K-th blocks at an output frame frequency higher than the input frame frequency, The generation of the static current is blocked in the remaining skip period, and the power consumption of the source driver can be greatly reduced.

Further, the present invention can have a memory capacity smaller than a frame memory having a memory capacity in which pixel data of all the lines of the pixel array can be stored, by sequentially writing the block of the display panel into a plurality of blocks. As a result, the production cost can be reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: liquid crystal display panel 11: timing controller
12: Source driver 13: Gate driver
15: Data lines 16: Gate lines

Claims (9)

Display panel;
A source driver for supplying a data voltage to the data lines of the display panel;
A gate driver for supplying a gate pulse to gate lines of the display panel;
A memory for sequentially storing input image data applied from outside; And
(K is a positive integer equal to or larger than 2) of the input image data of one frame stored in the memory to the first data group to the k-th data group and a timing controller for controlling operations of the source driver and the gate driver so that the k data groups are sequentially written in the first block to the k-th block of the display panel,
Each of the first data group to the k-th data group is written into the corresponding block for a scan period shorter than n / k time (n indicates one frame period according to the input frame frequency), and the n / k time The driving power applied to the buffer units of the source driver is cut off during a skip period excluding the scan period. The method according to claim 1,
Wherein the scan period and the skip period are each n / 2k hours. The method according to claim 1,
Wherein the timing controller generates a buffer operation control signal when writing to the corresponding block is completed,
Maintains the buffer operation control signal at the on level during the scan period and maintains the buffer operation control signal at the off level during the skip period. The method according to claim 1,
Wherein the operation of supplying the data voltage of the source driver during the skip period is stopped. The method according to claim 1,
The buffer units of the source driver,
A first input part operated by a high potential driving voltage and a low voltage and a first output part operated by the high potential driving voltage and the intermediate potential driving voltage to buffer and output the positive potential gamma compensation voltage, ;
A second input part operated by the high potential driving voltage and the base low voltage and a second output part operated by the base low voltage and the intermediate potential driving voltage to buffer and output the negative gamma compensation voltage, ;
A first power switch connected between the input of the high potential driving voltage and the first output unit; And
And a second power switch connected between the input terminal of the base voltage and the second output unit;
Wherein the first power switch and the second power switch are turned on during the scan period and turned off during the skip period in response to the buffer operation control signal. A gate driver for supplying a gate pulse to the gate lines of the display panel; and a gate driver for sequentially storing input image data applied from the outside, wherein the gate driver supplies data voltages to data lines of the display panel, A method of driving a display device for high-speed driving including a memory,
A dividing step of dividing the input image data of one frame stored in the memory into a first data group to a k-th data group (k is a positive integer of 2 or more)
A control step of controlling operations of the source driver and the gate driver such that the first data group to the k-th data group are sequentially written in the first block to the k-th block of the display panel according to an output frame frequency higher than the input frame frequency ; And,
The control step
Each of the first data group to the k-th data group is written in a corresponding block during a scan period shorter than n / k time (n indicates one frame period according to the input frame frequency)
And turning off the driving power applied to the buffer units of the source driver during the skip period excluding the scan period among the n / k times. The method according to claim 6,
Wherein the scan period and the scan period are set to n / 2k hours. The method according to claim 6,
And generating a buffer operation control signal when the write operation is completed in the corresponding block, maintaining the buffer operation control signal at the ON level during the scan period, and maintaining the buffer operation control signal at the off level during the skip period And a driving method of the high-speed driving display device. The method according to claim 6,
Wherein the operation of supplying the data voltage of the source driver during the skip period is stopped.

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