KR20160149445A - Active load with current correction circuit for high impedance - Google Patents
Active load with current correction circuit for high impedance Download PDFInfo
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- KR20160149445A KR20160149445A KR1020150086410A KR20150086410A KR20160149445A KR 20160149445 A KR20160149445 A KR 20160149445A KR 1020150086410 A KR1020150086410 A KR 1020150086410A KR 20150086410 A KR20150086410 A KR 20150086410A KR 20160149445 A KR20160149445 A KR 20160149445A
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- high impedance
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
- G01R35/005—Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31704—Design for test; Design verification
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- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Tests Of Electronic Circuits (AREA)
- Logic Circuits (AREA)
Abstract
Description
The present invention relates to an active load design method and circuit for a test board having a high impedance current correction circuit.
On the test board for evaluation, the output stage of the driver must maintain a constant common mode level. An active load must have the ability to maintain a constant common-mode level at the output stage when connected to the output stage when setting a specific mode. This is possible by comparing the reference level with the output level and supplying or removing the current to the output end load. The supply current should have a fixed value even with changes in the output load and 14-bit DAC control must be possible.
An object of the present invention is to provide a design method and circuit for stabilizing an output level and preventing an overcurrent at an output end of an evaluation board ASIC. Sourcing or sinking current to the output stage through comparison of the common mode level and the reference value of the output signal and adjusting the current value ± 25mA through the 14-bit DAC according to user setting A design method and circuit are provided.
According to one aspect of the present invention, there is provided a method of designing an active-rod active-rod for a test board having a high-impedance current correction circuit, the method comprising: comparing a signal of an output terminal of an evaluation board with a reference signal; Correcting the high impedance current by sourcing a current from the power supply voltage to the output terminal when the output terminal is greater than the mode level, and when the signal of the output terminal is less than the output common mode level, Adjusting a high impedance current, and setting a point in an output swing of a signal of an output terminal subjected to the step of correcting the high impedance current to an output common mode level.
The sourced current and the sinked current may be set according to a sourcing set current and a sink set current, which are DAC signals of a predetermined bit.
It is possible to increase the impedance to the current source circuit through the feedback process to correct the high impedance current and to maintain the constant common mode level by supplying the fixed current regardless of the sourcing and sinking operation, Do.
In another aspect, an active load circuit for a test board having a high impedance current correction circuit proposed in the present invention compares a signal of an output terminal of an evaluation board with a reference signal, A bridge circuit for setting the output common mode level to the output common mode level when the signal of the output terminal is higher than the output common mode level, And a high impedance correcting circuit for correcting the current by sinking the signal of the output terminal to the ground when the output signal is smaller than the mode level.
The sourcing current and sink current of the high impedance correction circuit can be set according to the sourcing setting current and the sink setting current which are DAC signals of a predetermined bit.
The high impedance correction circuit can maintain a constant common mode level by increasing the impedance to the current source circuit through the feedback process, changing the set current, and supplying a fixed current regardless of the sourcing and sinking operations.
According to embodiments of the present invention, by using the proposed active load, a constant common mode level can be maintained at the output stage. By sensing the level change of the output based on the set common mode level, the current can be supplied or pulled out, which keeps the load value at the output stage. The amount of current flowing is adjustable via a 14-bit DAC. The high-impedance correction circuit for supplying a fixed current source can improve the stability and reliability of the current source circuit. It can also be used in a variety of driver load circuits.
1 is a block diagram and logic diagram of an active load circuit for a test board having a high impedance current correction circuit according to an embodiment of the present invention.
FIG. 2 is a flowchart illustrating a method of designing an active load for a test board having a high impedance current correction circuit according to an embodiment of the present invention. Referring to FIG.
3 is a graph of VIT / DUT node current change according to a DUT signal in an active load according to an exemplary embodiment of the present invention.
4 is a graph of change in DUT current according to VIOH change and VIOL change according to an embodiment of the present invention.
5 is a layout photograph of an active load circuit according to an embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
1 is a block diagram and logic diagram of an active load circuit for a test board having a high impedance current correction circuit according to an embodiment of the present invention.
1 (a) is a block diagram of an active load circuit for a test board having a high impedance current correction circuit.
The active load circuit for a test board having a high impedance current correction circuit may include a
The
The high
The high
Further, the high
Referring to FIG. 1 (a), VIT, VIOH, and VIOL are signals to be connected to the DAC, respectively, which means an output common mode level, a sourcing set current, and a sink set current. The DUT is an output terminal of the evaluation board ASIC and, according to an embodiment of the present invention, is matched to 50 ohms through a driver circuit.
Referring to FIG. 1 (b), LOAD_PWR_DOWN and LOAD_CONNECT are signals entering the switch gate for determining the active load mode of operation. LOAD_PWR_DOWN and LOAD_CONNECT can be expressed as follows.
The operation mode determination signal is generated in the ASIC SPI block according to the user's setting. The bridge circuit is implemented by connecting the gate and drain of the transistor. Between the p-type transistor and the n-type transistor diode, the VIT signal serving as the reference signal is connected to the signal of the output terminal DUT. The current source circuit is composed of simple transistors and is configured to control the gate voltage through a 14-bit DAC. The proposed high-impedance current compensation circuit consists of one transistor and a high-gain differential amplifier (differential op-amp).
The operation of the circuit is as follows. The ASIC output terminal DUT signal is compared with the reference VIT signal. The reference VIT is set to the common mode level which is the middle point of the output swing of the output terminal DUT. For example, since the power supply voltage used in the circuit is 5V, generally VIT is set to 2.5V.
When the output terminal DUT is larger than the reference VIT, current is sourced from the power supply voltage VDD5 to the output terminal DUT. When the output terminal DUT is less than the reference VIT, the current sinks from the output terminal DUT to the VSS (i.e., ground voltage).
According to the embodiment of the present invention, the sourcing and sinking currents are set according to the sourcing set current VIOH, which is a 14-bit DAC signal for each angle, and the sink set current VIOL, and its value is designed to a maximum of ± 25 mA. The high impedance current correction circuit increases the impedance of the current source circuit through the feedback process and enables a fixed current source regardless of the set current change and the sourcing / sinking operation.
FIG. 2 is a flowchart illustrating a method of designing an active load for a test board having a high impedance current correction circuit according to an embodiment of the present invention. Referring to FIG.
A method for designing an active load for a test board having a high impedance current correction circuit, comprising the steps of: comparing (210) a signal at an output terminal of an evaluation board to a reference signal; if the signal at the output terminal is greater than the output common mode level, A
In step 210, the signal at the output terminal of the evaluation board and the reference signal can be compared. The signal of the output terminal DUT of the evaluation board ASIC is compared with the reference signal VIT signal. The VIT as the reference signal is set to the common mode level which is the middle point of the output terminal DUT output swing. For example, since the power supply voltage used in the circuit is generally 5V, the reference signal VIT is set to 2.5V.
In
In
The sourcing and sinking currents may be set according to a sourcing set current and a sink set current, which are DAC signals of a predetermined bit.
For example, the sourcing and sinking currents are set according to VIOH and VIOL, which are 14-bit DAC signals, and their values are designed to ± 25mA maximum. The high impedance current correction circuit increases the impedance of the current source circuit through the feedback process and enables a fixed current source regardless of the set current change and the sourcing / sinking operation.
In the proposed method, it is possible to increase the impedance to the current source circuit through the feedback process to correct the high impedance current. In addition, the set current can be changed, and a constant common mode level can be maintained by supplying a fixed current irrespective of sourcing and sinking operations.
3 is a graph of VIT / DUT node current change according to a DUT signal in an active load according to an exemplary embodiment of the present invention.
Referring to FIG. 3, when the DUT is applied from 5 V to 0 V after fixing the VIT as the reference signal at the common mode level of 2.5 V, it is a current graph obtained from the VIT and the DUT node. The sourcing / sinking current was set to ± 25 mA. Based on the common mode level 2.5V, it can be confirmed that the DUT node is sourced by +25 mA when the VIT is low and -25 mA is sinked when the DUT is larger than the VIT.
4 is a graph of change in DUT current according to VIOH change and VIOL change according to an embodiment of the present invention.
4 (a) is a graph of sourcing current change according to the sourcing set current VIOH signal change.
4 (b) is a graph of a change in the sink current according to the change in the sink set current VIOL. Sourcing setting current VIOH signal and Sink setting current VIOL It can be confirmed that the current changes from 0mA to ± 25mA at the output terminal DUT according to the signal change.
5 is a layout photograph of an active load circuit according to an embodiment of the present invention.
The total layout area of the proposed active load circuit is 0.245 mm2 . If you set the sourcing / sinking current to ± 25mA at a supply voltage of 5V, it will generate 125mA of power consumption.
By using the proposed active load, a constant common mode level can be maintained at the output stage. By sensing the level change of the output based on the set common mode level, the current can be supplied or pulled out, which keeps the load value at the output stage. The amount of current flowing is adjustable via a 14-bit DAC. In addition, a high impedance correction circuit for supplying a fixed current source not only improves the stability and reliability of the current source circuit, but also can be used for various driver load circuits.
The apparatus described above may be implemented as a hardware component, a software component, and / or a combination of hardware components and software components. For example, the apparatus and components described in the embodiments may be implemented within a computer system, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA) A programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For ease of understanding, the processing apparatus may be described as being used singly, but those skilled in the art will recognize that the processing apparatus may have a plurality of processing elements and / As shown in FIG. For example, the processing unit may comprise a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as a parallel processor.
The software may include a computer program, code, instructions, or a combination of one or more of the foregoing, and may be configured to configure the processing device to operate as desired or to process it collectively or collectively Device can be commanded. The software and / or data may be in the form of any type of machine, component, physical device, virtual equipment, computer storage media, or device , Or may be permanently or temporarily embodied in a transmitted signal wave. The software may be distributed over a networked computer system and stored or executed in a distributed manner. The software and data may be stored on one or more computer readable recording media.
The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.
Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.
Claims (6)
Comparing a signal of an output terminal of the evaluation board with a reference signal;
Correcting the high impedance current by sourcing the current from the power supply voltage to the output terminal when the signal of the output terminal is greater than the output common mode level; And
Correcting the high impedance current by sinking the signal of the output terminal to ground when the signal of the output terminal is smaller than the output common mode level
Wherein the method comprises the steps of:
The sourced current and the sink current are set according to a sourcing set current and a sink set current, which are DAC signals of predetermined bits
Wherein the method comprises the steps of:
It is possible to increase the impedance to the current source circuit through the feedback process to correct the high impedance current, to change the set current, to maintain a constant common mode level by supplying the fixed current regardless of the sourcing and sinking operations that
Wherein the method comprises the steps of:
A bridge circuit for comparing a signal of an output terminal of the evaluation board with a reference signal and setting a point in an output swing of a signal of the output terminal to an output common mode level; And
And corrects the current by sourcing a current from the power supply voltage to the output terminal when the signal of the output terminal is larger than the output common mode level and when the signal of the output terminal is smaller than the output common mode level, A high-impedance correction circuit for correcting the current by sinking the signal to ground
And an active load circuit for a test board.
The sourcing current and the sink current of the high impedance correction circuit are set according to a sourcing setting current and a sink setting current which are DAC signals of a predetermined bit
The active load circuit for a test board.
Wherein the high impedance correction circuit comprises:
It is possible to maintain a constant common mode level by increasing the impedance to the current source circuit, changing the set current, supplying a fixed current regardless of sourcing and sinking operation through feedback process
The active load circuit for a test board.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020150086410A KR101742875B1 (en) | 2015-06-18 | 2015-06-18 | Active load with current correction circuit for high impedance |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020150086410A KR101742875B1 (en) | 2015-06-18 | 2015-06-18 | Active load with current correction circuit for high impedance |
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| Publication Number | Publication Date |
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| KR20160149445A true KR20160149445A (en) | 2016-12-28 |
| KR101742875B1 KR101742875B1 (en) | 2017-06-01 |
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| KR1020150086410A KR101742875B1 (en) | 2015-06-18 | 2015-06-18 | Active load with current correction circuit for high impedance |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100097192A1 (en) | 2006-12-04 | 2010-04-22 | David Alan Weston | Back-door data synchronization for a multiple remote measurement system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5952821A (en) * | 1997-08-29 | 1999-09-14 | Credence Systems Corporation | Load circuit for integrated circuit tester |
| US7256600B2 (en) | 2004-12-21 | 2007-08-14 | Teradyne, Inc. | Method and system for testing semiconductor devices |
| JP4636461B2 (en) | 2009-01-13 | 2011-02-23 | セイコーインスツル株式会社 | Power supply voltage monitoring circuit and electronic circuit including the power supply voltage monitoring circuit |
| JP2013181831A (en) | 2012-03-01 | 2013-09-12 | Advantest Corp | Test device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20100097192A1 (en) | 2006-12-04 | 2010-04-22 | David Alan Weston | Back-door data synchronization for a multiple remote measurement system |
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