KR20160144547A - Storage device and operating method of storage device - Google Patents
Storage device and operating method of storage device Download PDFInfo
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- KR20160144547A KR20160144547A KR1020150080641A KR20150080641A KR20160144547A KR 20160144547 A KR20160144547 A KR 20160144547A KR 1020150080641 A KR1020150080641 A KR 1020150080641A KR 20150080641 A KR20150080641 A KR 20150080641A KR 20160144547 A KR20160144547 A KR 20160144547A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/544—Buffers; Shared memory; Pipes
Abstract
The present invention relates to a storage device. The storage apparatus of the present invention comprises nonvolatile memories and a device controller for receiving write data having a first stream identifier from an external device and storing the received write data in a stream buffer together with a first stream identifier. The device controller programs the first data group into the nonvolatile memories when the capacity of the first data group having the first stream identifier stored in the stream buffer reaches the threshold capacity. If the free capacity of the stream buffer is smaller than the size of the write data when the write data having the first stream identifier is received, the device controller determines that the capacity of the second data group having the second stream identifier stored in the stream buffer is smaller than the threshold capacity Program the second data group into the nonvolatile memories.
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly, to a storage apparatus including a nonvolatile memory.
A computing device includes a processor, main memory, and storage device. As semiconductor technology advances, the performance of processors, main memory, and storage devices is improving. As the performance of processors, main memories and storage devices is improved, the performance of computing devices is also improving.
Typically, the factor that hinders the operating speed of a computing device was the performance of the storage device. However, as nonvolatile memories such as flash memory, PRAM (Phase-change Random Access Memory), RRAM (Resistive RAM), MRAM (Magnetic RAM) and FeRAM (Ferroelectric RAM) are applied to storage devices, . Accordingly, the factor that hinders the operation speed of the computing device is shifting from the performance of the storage device to the communication speed between the processor and the storage device.
Accordingly, there is a need for a new apparatus and method for improving the communication speed between the processor and the storage device. There is also a need for new devices and methods for solving the problems found in the process of improving the communication speed between the processor and the storage device.
It is an object of the present invention to provide a method of operating a storage device and a storage device having reduced manufacturing costs while maintaining reliability and operational performance.
A storage apparatus according to an embodiment of the present invention includes nonvolatile memories and an external apparatus for receiving write data having a first stream identifier and storing the received write data in the stream buffer together with the first stream identifier Lt; / RTI > The device controller is configured to program the first data group into the nonvolatile memories when the capacity of the first data group having the first stream identifier stored in the stream buffer reaches a threshold capacity. The apparatus controller of claim 1, wherein, when the write data having the first stream identifier is received, if the free capacity of the stream buffer is smaller than the size of the write data, a second data group having a second stream identifier And to program the second data group in the nonvolatile memories even if the capacity is less than the critical capacity.
A storage apparatus according to another exemplary embodiment of the present invention includes nonvolatile memories and a stream buffer. The storage apparatus receives write data having a first stream identifier from an external apparatus and writes the received write data to the first stream identifier To the stream buffer. ≪ RTI ID = 0.0 > The device controller is configured to program the first data group into the nonvolatile memories when the capacity of the first data group having the first stream identifier stored in the stream buffer reaches a threshold capacity. Wherein the device controller, when the write data having the first stream identifier is received, if the free capacity of the stream buffer is smaller than the size of the write data, Or a combination of more than one data group, into the non-volatile memories.
A method of operating a storage apparatus according to an embodiment of the present invention, including a nonvolatile memories and a device controller configured to control the nonvolatile memories, is characterized in that the device controller receives write data having a first stream identifier from an external device Storing the write data in the stream buffer when the free capacity of the stream buffer of the device controller is equal to or greater than the capacity of the write data; Combining the data groups corresponding to two or more stream identifiers stored in the stream buffer into the nonvolatile memories and storing the write data in the stream buffer if the stream data is small, And having the first stream identifier If the capacity of the data group has reached a threshold capacity, and a step of programming the data group in the non-volatile memory.
According to the embodiments of the present invention, when the storage capacity of the stream buffer storing the write data is insufficient, the data group corresponding to the specific stream identifier stored in the stream buffer is flushed to the nonvolatile memories. There is provided a method of operating a storage apparatus and a storage apparatus having a reduced manufacturing cost while maintaining reliability and operation performance because the capacity of the stream buffer is reduced while maintaining the operational performance and reliability of the storage apparatus.
1 is a block diagram illustrating a computing device in accordance with an embodiment of the present invention.
2 is a block diagram illustrating a storage apparatus according to an embodiment of the present invention.
3 is a block diagram illustrating a device controller in accordance with an embodiment of the present invention.
4 is a flowchart illustrating a method for a storage apparatus to manage write data using a stream buffer according to an embodiment of the present invention.
5 to 10 show how write data is managed in the stream buffer.
11 is a flowchart showing a first example in which a group of data stored in a stream buffer is flushed.
FIG. 12 shows a process of flushing a data group according to the example of FIG.
13 is a flowchart showing a second example in which a group of data stored in the stream buffer is flushed.
FIG. 14 shows a process of flushing a data group according to the example of FIG.
15 is a flowchart showing a third example in which a group of data stored in the stream buffer is flushed.
16 is a flowchart showing a fourth example in which the data group stored in the stream buffer is flushed.
FIG. 17 shows a process of flushing a data group according to the example of FIG.
18 is a flowchart showing a fifth example in which a group of data stored in the stream buffer is flushed.
FIG. 19 shows a process of flushing a data group according to the example of FIG.
20 is a flowchart showing a sixth example in which a group of data stored in the stream buffer is flushed.
21 is a flowchart showing a seventh example in which the data group stored in the stream buffer is flushed.
Figure 22 is a flow chart illustrating how a processor writes data to a storage device in accordance with an embodiment of the invention.
23 is a flowchart illustrating a method for a processor to read data from a storage device in accordance with an embodiment of the present invention.
24 shows an example of a server apparatus in which a storage apparatus according to an embodiment of the present invention is mounted.
25 is a block diagram illustrating a storage apparatus according to a second embodiment of the present invention.
26 is a block diagram illustrating a hybrid storage apparatus according to a third embodiment of the present invention.
27 is a block diagram illustrating a hybrid storage apparatus according to a fourth embodiment of the present invention.
28 is a block diagram illustrating one of the non-volatile memories according to an embodiment of the present invention.
29 is a circuit diagram showing a memory block according to an embodiment of the present invention.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention. .
1 is a block diagram illustrating a
The
The
The
The
The
The
The input /
The
The communication speed (e.g., the communication speed with the processor 1100) of the
2 is a block diagram illustrating a
Data buffers 110 may receive data signals DQ and data strobe signals DQS from
The
The RAM command CMD_R may be a command requesting access to the
The
The
The
3 is a block diagram illustrating a
The
The
The
Illustratively, the storage space of the
The storage command CMD_S and the storage address ADDR_S stored in the
The
The
The
Illustratively, the
For example, the
The
The
The same stream identifier (SID) is allocated to write data (DATA_W) having similar characteristics, and a different stream identifier (SID) is assigned to write data (DATA_W) having different characteristics. Therefore, write data (DATA_W) having similar characteristics is programmed in the same memory block, and write data (DATA_W) having different characteristics are programmed in different memory blocks. Therefore, the management performance of the write data (DATA_W) programmed in the
4 is a flowchart showing a method of the
In step S120, the
In step S140, the write data (DATA_W) is stored in the
In step S150, the
As described above, the
The
A data group smaller than the critical capacity (CCR) among the data groups stored in the
5 to 10 show how the write data (DATA_W) is managed in the
Referring to FIG. 5, the capacity of the
The write data DATA_W may be received together with one of the first to fifth stream identifiers SID1 to SID5. Illustratively, the threshold capacity (CCR) of the data group of each stream identifier (SID) may be four slots. For example, if four slots are registered in the data group of each stream identifier (SID), the corresponding data group may be output through the
In FIG. 5, slots are not registered in the first to fifth stream identifiers SID1 to SID5, and it is assumed that ten free slots FS exist.
Referring to FIG. 6, first to third data D1 to D3 are received from the
Referring to FIG. 7, the fourth to eighth data D4 to D8 are received from the
Referring to FIG. 8, the ninth data D9 is received from the
Referring to FIG. 10, the 10th to 14th data D10 to D14 are received as write data (DATA_W) from the
When the tenth through fourteenth data D10 through D14 are stored in the
11 is a flowchart showing a first example in which a group of data stored in the
An example in which the data group is flushed according to Fig. 11 is shown in Fig. 11 and 12, the fifteenth data D15 having the first stream identifier SID1 may be received from the
Illustratively, the data group corresponding to the third stream identifier SID3 has three data slots. Therefore, the sixth to eighth data D6 to D8 of the data group corresponding to the third stream identifier SID3 can be programmed into the
Illustratively, there may be a plurality of groups of data having the largest capacity. When there are a plurality of data groups having the largest capacity, the target data group to be flushed may be determined according to a separate rule. For example, a data group including the oldest data among the candidate data groups, a data group including the latest data, a data group having the highest access frequency, or a data group having the lowest access frequency can be selected have.
As another example, the
Illustratively, when the fifteenth data D15 is received and the capacity of the data group reaches the threshold capacity CCR, the data corresponding to the fifteenth data D15 and the fifteenth data D15 The group can be normally programmed into the
13 is a flowchart showing a second example in which a group of data stored in the
An example in which the data group is flushed according to Fig. 13 is shown in Fig. 13 and 14, the fifteenth data D15 having the first stream identifier SID1 may be received from the
Illustratively, among the data stored in the
As another example, the
15 is a flowchart showing a third example in which the data group stored in the
As another example, the
16 is a flowchart showing a third example in which the data group stored in the
An example in which the data group is flushed according to Fig. 16 is shown in Fig. 16 and 17, the fifteenth data D15 having the first stream identifier SID1 may be received from the
Illustratively, the total capacity of the data group corresponding to the third stream identifier SID3 and the data group corresponding to the fifth stream identifier SID5 corresponds to the threshold capacity CCR. Thus, the
For example, the
D6 to D8 and the fourteenth data D14 corresponding to the third and fifth stream identifiers SID3 and SID5 are formed and a data group in which the seventeenth data D14 is combined are formed in the nonvolatile memories 130 ).
Illustratively, a plurality of combinations of data groups corresponding to a critical capacity (CCR) may exist. If there are a plurality of combinations of data groups corresponding to the critical capacity (CCR), the data groups to be combined may be determined according to a separate rule. For example, a combination of data groups including the oldest data among the candidate combinations, a combination of data groups including the latest data, a combination of data groups having the highest access frequency, or data with the lowest access frequency A combination of groups may be selected.
18 is a flowchart showing a fourth example in which the data group stored in the
In step S620, the detected stream identifiers (SID) are combined. For example, the
The data groups corresponding to the detected stream identifiers (SID) may also be combined to form a combined data group corresponding to the threshold capacity (CCR). For example, when the total capacity of the data groups corresponding to the detected stream identifiers (SID) is greater than the threshold capacity (CCR), at least one data group among the data groups of the detected stream identifiers (SID) And the other data group may have residual data. For example, a data group having a larger capacity, a data group having a smaller capacity, a data group including older data, a data group including more recent data, a higher access frequency Or a data group having a lower access frequency can all be included in a combined data group. Some of the data of another data group that does not meet the above-mentioned condition may be included in the combined data group, and the remaining part of the data may be maintained as the remaining data group. Illustratively, in another data group, older data or more recent data may be included in the combined data group. Data that does not meet the above conditions can be retained as residual data.
In step S630, the combined data group corresponding to the combined stream identifier (SID) is flushed. That is, the data of the combined data group is programmed into the
As another example, the
An example in which the data group is flushed according to Fig. 18 is shown in Fig. 18 and 19, the fifteenth data D15 having the first stream identifier SID1 may be received from the
Illustratively, third and fourth stream identifiers SID3 and SID4 may be detected. The sixth to eighth data D6 to D8 of the third stream identifier SID3 and the twelfth data D12 of the fourth stream identifier SID4 are combined to form a data group in the nonvolatile memories 130). The thirteenth data D13 of the fourth stream identifier SID4 may be residual data.
20 is a flowchart showing a fifth example in which the data group stored in the
In step S720, the detected stream identifiers (SID) are combined. The data groups corresponding to the detected stream identifiers (SID) may also be combined to form a combined data group corresponding to the threshold capacity (CCR). Stream identifiers (SID) and data groups may be combined as described with reference to FIG.
In step S730, the combined data group corresponding to the combined stream identifier (SID) is flushed. That is, the data of the combined data group is programmed into the
As another example, the
21 is a flowchart showing a sixth example in which the data group stored in the
In step S820, the detected stream identifiers (SID) are combined. The data groups corresponding to the detected stream identifiers (SID) may also be combined to form a combined data group corresponding to the threshold capacity (CCR). Stream identifiers (SID) and data groups may be combined as described with reference to FIG.
In step S830, the combined data group corresponding to the combined stream identifier (SID) is flushed. That is, the data of the combined data group is programmed into the
As another example, the
FIG. 22 is a flowchart showing how the
Referring to FIGS. 1, 2, 3 and 22, in step S910, the
Steps S910 and S920 may form a command transaction that conveys a write command to the
In step S930, the
Steps S930 and S940 may form a data transaction for transferring write data (DATA_W) to the
As the storage command CMD_S, the storage address ADDR_S and the write data DATA_W are stored in the
The storage command CMD_S, the storage address ADDR_S and the write data DATA_W may be written to the command area CA of the
In step S950, the
When the writing to the
23 is a flowchart showing how the
Referring to FIGS. 1, 2, 3 and 23, in step S1010, the
Steps S1010 and S1020 may form a command transaction that conveys a read command to
The storage command CMD_S and the storage address ADDR_S may be written to the command area CA of the
As the storage command CMD_S is descrambled, the
In step S1030, the
When the reading from the
When the state information STI is read from the
The
The
Communication between the
FIG. 24 shows an example of a
Illustratively, each of the
25 is a block diagram showing a
Compared with the
Except for operating in accordance with the RDIMM specification, the
26 is a block diagram showing a hybrid storage apparatus 300 according to a third embodiment of the present invention. 1 and 26, the hybrid storage device 300 includes data buffers 310, a device controller 320, non-volatile memories 330, a buffer memory 340, an SPD 350, Access memories (360). Hybrid storage device 300 may be coupled to
The non-volatile memories 330 and random access memories 360 of the hybrid storage device 300 may be identified at the physical layer of the
When the
Data buffers 310 operate in response to a buffer command CMD_B. Data buffers 310 may communicate data signals DQ and data strobe signals DQS with
The data buffers 310 may select an object with which to communicate the data signal DQ and the data strobe signal DQS under the control of the device controller 320. [ For example, data buffers 310 may communicate data signals DQ and data strobe signals DQS with device controller 320 under the control of device controller 320. [ As another example, the data buffers 310 may communicate data signals DQ and data strobe signals DQS with the random access memories 360 under the control of the device controller 320.
The device controller 320 can receive the command CMD, the address ADDR and the clock CK from the
In response to a command CMD, an address ADDR or a control signal received via the
The device controller 320 can control the data buffers 310 to communicate the data signals DQ and the data strobe signals DQS to the device controller 320 when the object of access is non-volatile memories 330 have. The device controller 320 can output the command CMD and the address ADDR received via the
Hybrid storage device 300 may operate as described with reference to FIGS. The device controller 320 may flush to the non-volatile memories 330 a group of data having a capacity less than the threshold capacity or a combined data group when there is no free slot FS in the stream buffer.
The device controller 320 controls the data buffers 310 to communicate the data signal DQ and the data strobe signal DQS with the random access memories 360 when the access target is the random access memories 360. [ can do. The device controller 320 may output the received command CMD, address ADDR and clock CK to the random access memories 360 via the
The nonvolatile memories 330 can write data transferred as the data signal DQ in response to the command CMD and the address ADDR. The nonvolatile memories 330 can read data in response to the command CMD and the address ADDR and output the read data as the data signal DQ.
The buffer memory 340 may correspond to the
The SPD 350 corresponds to the
The random access memories 360 can write data transferred as the data signal DQ in response to the command CMD, the address ADDR and the clock CK. The random access memories 360 can read the data in response to the command CMD, the address ADDR and the clock CK and output the read data as the data signal DQ.
Illustratively, the device controller 320 may communicate the command CMD, the address ADDR, and the data signal DQ to the non-volatile memories 330 as input and output signals. For example, the command CMD, the address ADDR, and the data signal DQ may be communicated through common input / output lines. The device controller 320 may further communicate control signals used to control the non-volatile memories 330 with the non-volatile memories 330. The control signals can be communicated via the control lines separate from the input / output lines.
For example, the device controller 320 includes a chip enable signal / CE for selecting at least one nonvolatile memory chip among the nonvolatile memories 330, a signal transmitted to the input / output signals is a storage command CMD_S, An address latch enable signal ALE that indicates a signal transmitted to the input / output signals is a storage address ADDR_S, and a latch enable signal ALE that is periodically toggled at the time of reading to be used for timing A write enable signal / WE that is activated when a command or an address is transmitted, a write enable signal / WP that is activated to prevent unintended write or erase when power is changed, ), And may transmit the data strobe signal DQS, which is periodically toggled at the time of writing, to be used for synchronizing the data to the non-volatile memories 330. [ The device controller 320 also includes Ready and busy signals (R / nB) indicating whether the non-volatile memories 330 are performing a program, erase or read operation, a read enable signal From the non-volatile memories 330, a data strobe signal DQS that is generated from the refresh / RE and is periodically toggled and used to synchronize the data.
Illustratively, the hybrid device 300 may operate in accordance with the specifications of the LRDIMM.
FIG. 27 is a block diagram illustrating a
The
The
The
Compared with the hybrid storage device 300 of FIG. 26, the data buffers 310 are not provided to the
Except for operating in accordance with the RDIMM specification, the
28 is a block diagram illustrating one of the
The
The
For example, at the time of programming, the
The
At the time of programming, the
The data input /
The
Illustratively, upon reading, the
29 is a circuit diagram showing a memory block BLKa according to an embodiment of the present invention. Referring to FIG. 29, the memory block BLKa includes a plurality of cell strings CS11 to CS21, CS12 to CS22. The plurality of cell strings CS11 to CS21 and CS12 to CS22 may be arranged along a row direction and a column direction to form rows and columns.
For example, the cell strings CS11 and CS12 arranged along the row direction form the first row and the cell strings CS21 and CS22 arranged along the row direction form the first row, Two rows can be formed. The cell strings CS11 and CS21 arranged along the column direction form the first column and the cell strings CS12 and CS22 arranged along the column direction form the second column can do.
Each cell string may include a plurality of cell transistors. The plurality of cell transistors include ground selection transistors GST, memory cells MC1 to MC6, and string selection transistors SSTa and SSTb. The ground selection transistors GST, memory cells MC1 to MC6 and string selection transistors SSTa and SSTb of each cell string are arranged such that cell strings CS11 to CS21 and CS12 to CS22 are arranged along rows and columns (For example, a plane on the substrate of the memory block BLKa) perpendicular to the substrate surface.
The plurality of cell transistors may be charge trap type transistors having threshold voltages varying depending on the amount of charge trapped in the insulating film.
The sources of the lowermost ground selection transistors (GST) may be connected in common to the common source line (CSL).
The control gates of the ground selection transistors GST of the plurality of cell strings CS11 to CS21, CS12 to CS22 may be connected to the ground selection lines GSL1 and GSL2, respectively. Illustratively, the ground select transistors of the same row may be connected to the same ground select line, and the different row of ground select transistors may be connected to different ground select lines. For example, the ground selection transistors GST of the cell strings CS11 and CS12 of the first row are connected to the first ground selection line GSL1 and the ground selection transistors GST of the cell strings CS21 and CS12 of the second row The ground selection transistors GST may be connected to the second ground selection line GSL2.
The control gates of the memory cells located at the same height (or in sequence) from the substrate (or the ground selection transistors GST) are commonly connected to one word line, and the control gates of the memory cells located at different heights May be connected to different word lines WL1 to WL6, respectively. For example, the memory cells MC1 are commonly connected to the word line WL1. The memory cells MC2 are connected in common to the word line WL2. The memory cells MC3 are commonly connected to the word line WL3. The memory cells MC4 are connected in common to the word line WL4. The memory cells MC5 are commonly connected to the word line WL5. The memory cells MC6 are connected in common to the word line WL6.
In the first string selection transistors SSTa of the same height (or order) of the plurality of cell strings CS11 to CS21, CS12 to CS22, the control gates of the first string selection transistors SSTa in different rows And are connected to different string selection lines (SSL1a to SSL2a), respectively. For example, the first string selection transistors SSTa of the cell strings CS11 and CS12 are connected in common to the string selection line SSL1a. The first string selection transistors SSTa of the cell strings CS21 and CS22 are connected in common to the string selection line SSL2a.
In the second string selection transistors SSTb of the same height (or order) of the plurality of cell strings CS11 to CS21, CS12 to CS22, the control gates of the second string selection transistors SSTb in different rows And are connected to different string selection lines SSL1b to SSL2b, respectively. For example, the second string selection transistors SSTb of the cell strings CS11 and CS12 are connected in common to the string selection line SSL1b. The second string selection transistors SSTb of the cell strings CS21 and CS22 are connected in common to the string selection line SSL2b.
That is, cell strings in different rows are connected to different string selection lines. The string select transistors of the same height (or sequence) of cell strings in the same row are connected to the same string select line. String selection transistors of different heights (or sequences) of cell strings in the same row are connected to different string selection lines.
By way of example, the string select transistors of the cell strings of the same row may be connected in common to one string select line. For example, the string selection transistors SSTa and SSTb of the cell strings CS11 and CS12 of the first row may be connected in common to one string selection line. The string selection transistors SSTa and SSTb of the sal strings CS21 and CS22 of the second row may be connected in common to one string selection line.
The columns of the plurality of cell strings CS11 to CS21 and CS12 to CS22 are connected to different bit lines BL1 and BL2, respectively. For example, the string selection transistors SSTb of the cell strings CS11 to CS21 in the first column are connected in common to the bit line BL1. The string selection transistors SST of the cell strings CS12 to CS22 in the second column are connected in common to the bit line BL2.
Cell strings CS11 and CS12 may form a first plane. The cell strings CS21 and CS22 may form a second plane.
In the memory block BLKa, memory cells of each height of each plane can form a physical page. The physical page may be a unit of writing and reading of the memory cells MC1 to MC6. For example, one plane of the memory block BLKa may be selected by the string selection lines SSL1a, SSL1b, SSL2a, and SSL2b. When the string selection lines SSL1a and SSL1b are supplied with the turn-on voltage and the turn-off voltage is supplied to the string selection lines SSL2a and SSL2b, the cell strings CS11 and CS12 of the first plane are bit- And connected to lines BL1 and BL2. That is, the first plane is selected. When the turn-on voltage is supplied to the string select lines SSL2a and SSL2b and the turn-off voltage is supplied to the string select lines SSL1a and SSL1B, the cell strings CS21 and CS22 of the second plane are bit- And connected to lines BL1 and BL2. That is, the second plane is selected. In the selected plane, one row of memory cells MC can be selected by the word lines WL1 to WL6. In the selected row, a selection voltage may be applied to the second word line WL2 and a non-selection voltage may be applied to the remaining word lines WL1, WL3 to WL6. That is, by adjusting the voltages of the string selection lines SSL1a, SSL1b, SSL2a, SSL2b and the word lines WL1 to WL6, a physical page corresponding to the second word line WL2 of the second plane can be selected have. In the memory cells MC2 of the selected physical page, writing or reading can be performed.
In the memory block BLKa, erasing of the memory cells MC1 to MC6 may be performed in units of memory blocks or units of subblocks. When an erase is performed on a memory block basis, all the memory cells MC of the memory block BLKa can be erased simultaneously according to one erase request (for example, an erase request from an external memory controller). Some of the memory cells MC1 to MC6 of the memory block BLKa are simultaneously erased in response to one erase request (for example, an erase request from an external memory controller), and the remaining Some may be prohibited from being erased. A word line connected to the erased memory cells MC is supplied with a low voltage (e.g., a ground voltage or a low voltage having a level similar to the ground voltage), and the word line connected to the erased memory cells MC can be floated have.
The memory block BLKa shown in Fig. 29 is an exemplary one. The technical concept of the present invention is not limited to the memory block BLKa shown in Fig. For example, the number of rows of cell strings may be increased or decreased. As the number of rows of cell strings is changed, the number of string select lines or ground select lines connected to the rows of cell strings, and the number of cell strings connected to one bit line can also be changed.
The number of columns of cell strings can be increased or decreased. As the number of columns of cell strings changes, the number of bit lines connected to columns of cell strings and the number of cell strings connected to one string selection line can also be changed.
The height of the cell strings can be increased or decreased. For example, the number of ground select transistors, memory cells, or string select transistors stacked on each of the cell strings may be increased or decreased.
Illustratively, memory cells MC belonging to one physical page may correspond to at least three logical pages. For example, k (k is a positive integer greater than 2) bits can be programmed into one memory cell MC. In the memory cells MC belonging to one physical page, the k bits programmed into each memory cell MC can form k logical pages, respectively.
As an example according to the technical idea of the present invention, a three-dimensional memory array is provided. The three-dimensional memory array may be monolithically formed on one or more physical levels of arrays of memory cells having an active region disposed over a silicon substrate and circuits associated with operation of the memory cells. The circuitry associated with the operation of the memory cells may be located within or on the substrate. What is uniformly formed means that the layers of each level of the three-dimensional array are directly deposited on the lower-level layers of the three-dimensional array.
As an example according to the technical idea of the present invention, a three-dimensional memory array has vertical directionality and includes vertical NAND strings in which at least one memory cell is located on another memory cell. The at least one memory cell includes a charge trapping layer. Each vertical NAND string further includes at least one select transistor located above the memory cells. At least one selection transistor has the same structure as the memory cells and is formed uniformly with the memory cells.
A configuration in which the three-dimensional memory array is composed of a plurality of levels and the word lines or bit lines are shared between levels is disclosed in U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466, U.S. Patent No. 8,654,587 U.S. Patent No. 8,559,235, and U.S. Published Patent Application No. 2011/0233648, which are incorporated herein by reference.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.
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Claims (10)
And a device controller configured to receive write data having a first stream identifier from an external device and store the received write data in a stream buffer together with the first stream identifier,
Wherein the device controller is configured to program the first data group into the nonvolatile memories when a capacity of a first data group having the first stream identifier stored in the stream buffer reaches a threshold capacity,
The apparatus controller of claim 1, wherein, when the write data having the first stream identifier is received, if the free capacity of the stream buffer is smaller than the size of the write data, a second data group having a second stream identifier And to program the second data group in the nonvolatile memories even if the capacity is smaller than the critical capacity.
The device controller generates a data group in which a third data group having a third stream identifier stored in the stream buffer and a second data group are combined to form a combined data group and the combined data group is programmed into the nonvolatile memories Lt; / RTI >
Wherein the device controller is configured to select the second stream identifier and the third stream identifier such that the combined capacity of the second data group and the third data group is the critical capacity.
Wherein the device controller is configured to select, as the second data group and the third data group, data groups having the largest capacity among the data groups stored in the stream buffer.
Wherein the device controller is configured to select, as the second data group and the third data group, data groups having the smallest capacity among the data groups stored in the stream buffer.
Wherein the device controller is configured to select the oldest data groups among the data groups stored in the stream buffer as the second data group and the third data group.
Wherein the device controller is configured to select the most recent data groups among the data groups stored in the stream buffer as the second data group and the third data group.
And if the capacity of the combined data group is less than the threshold capacity, the device controller is further configured to combine a fourth data group having a fourth stream identifier stored in the stream buffer with the combined data group.
And a device controller configured to receive write data having a first stream identifier from an external device and to store the received write data in the stream buffer together with the first stream identifier,
Wherein the device controller is configured to program the first data group into the nonvolatile memories when a capacity of a first data group having the first stream identifier stored in the stream buffer reaches a threshold capacity,
Wherein the device controller, when the write data having the first stream identifier is received, if the free capacity of the stream buffer is smaller than the size of the write data, Or more of the data groups are combined and programmed into the non-volatile memories.
The device controller receiving write data having a first stream identifier from an external device;
Storing the write data in the stream buffer if the free capacity of the stream buffer of the device controller is equal to or greater than the capacity of the write data;
If the free capacity of the stream buffer of the device controller is smaller than the capacity of the write data, the data groups corresponding to two or more stream identifiers stored in the stream buffer are combined and programmed into the nonvolatile memories, Storing the write data in the stream buffer; And
And programming the data group into the nonvolatile memories when the capacity of the data group having the first stream identifier reaches the threshold capacity in the stream buffer.
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KR1020150080641A KR20160144547A (en) | 2015-06-08 | 2015-06-08 | Storage device and operating method of storage device |
US15/083,834 US9799402B2 (en) | 2015-06-08 | 2016-03-29 | Nonvolatile memory device and program method thereof |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20170133247A (en) * | 2016-05-25 | 2017-12-05 | 삼성전자주식회사 | Address based multi-stream storage device access |
KR20190127309A (en) * | 2018-05-04 | 2019-11-13 | 에스케이하이닉스 주식회사 | Memory system and operating method thereof |
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2015
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20170133247A (en) * | 2016-05-25 | 2017-12-05 | 삼성전자주식회사 | Address based multi-stream storage device access |
KR20190127309A (en) * | 2018-05-04 | 2019-11-13 | 에스케이하이닉스 주식회사 | Memory system and operating method thereof |
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