KR102606468B1 - Nonvolatile memory device, storage device including nonvolatile memory device and programming method for programming data into nonvolatile memory device - Google Patents

Abstract

A storage device according to embodiments of the present invention includes a non-volatile memory device, transmits first data, an address, and a first command to the non-volatile memory device, and after transmitting the first command, the non-volatile memory device It includes a controller configured to further transmit at least one data. The nonvolatile memory device starts a program operation based on the first data in response to the first command, and as the at least one data is further transmitted, the nonvolatile memory device starts the program operation based on the first data and the at least one data. It is configured to continue operation.

Description

A non-volatile memory device, a storage device including a non-volatile memory device, and a program method for programming data in a non-volatile memory device

The present invention relates to semiconductor circuits, and more specifically, to a non-volatile memory device, a storage device including a non-volatile memory device, and a programming method for programming data in a non-volatile memory device.

A storage device is a device that stores data under the control of a host device such as a computer, smart phone, smart pad, etc. Storage devices are devices that store data on magnetic disks, such as hard disk drives (HDDs), and semiconductor memories, especially non-volatile memories, such as solid state drives (SSDs) and memory cards. Includes devices that

Non-volatile memory includes ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), flash memory, PRAM (Phase-change RAM), MRAM (Magnetic RAM), Includes RRAM (Resistive RAM), FRAM (Ferroelectric RAM), etc.

As semiconductor manufacturing technology develops, the operating speed of host devices such as computers, smartphones, and smart pads that communicate with storage devices is improving. Additionally, the capacity of content used in storage devices and their host devices is increasing. Accordingly, demands for storage devices with improved operating speeds are continuously being raised.

The purpose of the present invention is to provide a non-volatile memory device with improved operating speed, a storage device including a non-volatile memory device, and a programming method for programming data in the non-volatile memory device.

A storage device according to embodiments of the present invention includes a non-volatile memory device, transmits first data, an address, and a first command to the non-volatile memory device, and after transmitting the first command, the non-volatile memory device It includes a controller configured to further transmit at least one data. The nonvolatile memory device starts a program operation based on the first data in response to the first command, and as the at least one data is further transmitted, the nonvolatile memory device starts the program operation based on the first data and the at least one data. It is configured to continue operation.

A nonvolatile memory device according to embodiments of the present invention includes a memory cell array including a plurality of memory cells, a page buffer connected to the plurality of memory cells through bit lines, and configured to load data received from an external device. circuit, and a row decoder circuit connected to the plurality of memory cells through word lines and configured to perform a program operation on selected memory cells among the plurality of memory cells according to data loaded into the page buffer circuit. . As first data is loaded into the page buffer circuit, the row decoder circuit and the page buffer circuit are configured to start a program operation. As second data and third data are further sequentially loaded into the page buffer circuit, the program operation is sequentially updated and continued.

A programming method for programming data in a non-volatile memory device according to embodiments of the present invention includes starting a program operation by transmitting first data to the non-volatile memory device, and transmitting second data to the non-volatile memory device. updating the program operation and continuing the program operation, and transmitting third data to the non-volatile memory device to further update the program operation and continue the program operation.

According to embodiments of the present invention, second data is loaded while a program loop based on first data is performed. Since the time at which the second data is loaded is shadowed, a non-volatile memory device with improved operation speed, a storage device including the non-volatile memory device, and a programming method for programming data in the non-volatile memory device are provided.

1 is a block diagram showing a storage device according to an embodiment of the present invention.
Figure 2 is a flowchart showing an example of a program operation performed by a program control unit of a nonvolatile memory device and a program control unit of a controller.
Figure 3 is a block diagram showing a non-volatile memory device according to an embodiment of the present invention.
Figure 4 is a block diagram showing a page buffer circuit according to an embodiment of the present invention.
Figures 5 and 6 are timing diagrams showing program operations according to an embodiment of the present invention from the perspective of input/output lines and ready-busy signals.
Figure 7 shows an example in which threshold voltages of memory cells are formed according to data programmed into the memory cells.
Figure 8 is a flowchart showing the process in which program operations are performed according to embodiments of the present invention.
9 is a flowchart showing how verification read is performed during verification.
Figure 10 shows threshold voltage distributions of memory cells in an erased state.
FIG. 11 shows a process in which the first program loop is performed in the memory cells of FIG. 10.
FIG. 12 shows an example where the threshold voltages of memory cells are changed from FIG. 10.
Figure 13 shows the process in which the second program loop is performed following Figure 11.
FIG. 14 shows an example in which the threshold voltages of memory cells are changed from FIG. 12.
Figure 15 shows the threshold voltages of memory cells when second data is transmitted first and programming of the first program loop is performed.
Figure 16 shows an example in which the program voltage is maintained in the second program loop.
Figure 17 shows a process in which a program operation according to an embodiment of the present invention is performed when one physical page includes three logical pages.
Figure 18 shows an example of the threshold voltages of memory cells when 3-bits are programmed in each memory cell.
Figure 19 shows the process in which the first program loop is performed when 3-bits are programmed in each memory cell.
Figure 20 shows an example in which memory cells are programmed through two or more program operations.
Figure 21 shows another example in which memory cells are programmed through two or more program operations.
Figure 22 shows an example of the threshold voltages of memory cells when 4-bits are programmed in each memory cell.
Figure 23 is a flowchart showing an application example in which a program operation is performed by the program control unit of the non-volatile memory device and the controller.
Figures 24 and 25 are timing diagrams showing program operations according to an embodiment of the present invention from the perspective of input/output lines and ready-busy signals.
FIG. 26 shows the process in which a program loop progresses in memory cells according to the method of FIG. 23.
Figures 27 and 28 show examples where the threshold voltages of memory cells change due to the program loops of Figure 26.
Figure 29 shows another example of a program loop in memory cells according to the method of Figure 23.
Figure 30 shows an example of the threshold voltages of memory cells changing due to the program loops of Figure 29.
Figure 31 shows another example of a program loop in memory cells according to the method of Figure 23.
FIG. 32 shows another example of a program loop in memory cells according to the method of FIG. 23.
Figure 33 is a circuit diagram showing a memory block according to an embodiment of the present invention.
Figure 34 is a block diagram showing a controller according to an embodiment of the present invention.
Figure 35 is a block diagram showing a computing device according to an embodiment of the present invention.

Hereinafter, in order to explain in detail enough to enable a person skilled in the art of the present invention to easily implement the technical idea of the present invention, embodiments of the present invention will be described with reference to the attached drawings. .

Figure 1 is a block diagram showing a storage device 100 according to an embodiment of the present invention. Referring to FIG. 1 , the storage device 100 includes a non-volatile memory device 110, a controller 120, and RAM 130.

The non-volatile memory device 110 includes a plurality of non-volatile memory cells and is configured to perform a program operation, a read operation, and an erase operation on the plurality of non-volatile memory cells under the control of the controller 120. The nonvolatile memory device 110 may receive a command or address from the controller 120 through the input/output lines (DQ) and exchange data with the controller 120. The non-volatile memory device 110 may transmit a ready-busy signal (RnB) to the controller 120, indicating whether it is in a state in which it can process the request for the command 120. For example, when the non-volatile memory device 110 is in a ready state capable of processing a request from the controller 120, the non-volatile memory device 110 may set the ready-busy signal (RnB) to a high level. . When the non-volatile memory device 110 is in a busy state in which it is performing an internal operation and cannot process a request from the controller 120, the non-volatile memory device 110 may set the ready-busy signal (RnB) to a low level. there is.

The nonvolatile memory device 110 includes a program control unit (PCU1) configured to control program operations according to requests from the controller 120. The program control unit (PCU1) can control program operations according to requests from the controller 120. The program operation controlled by the program control unit (PCU1) is explained in more detail with reference to FIG. 2.

The controller 120 may control the nonvolatile memory device 110 according to a request from an external host device. For example, the controller 120 may control program operations, read operations, and erase operations of the nonvolatile memory device 110. The controller 120 may transmit commands and addresses to the non-volatile memory device 110 through input/output lines (DQ) and exchange data with the non-volatile memory device 110. The controller 120 may control the non-volatile memory device 110 based on the ready-busy signal received from the non-volatile memory device 110.

The controller 120 includes a program control unit (PCU2). The program control unit (PCU2) may request a program operation of the non-volatile memory device 110 and control the program operation. The program operation controlled by the program control unit (PCU2) is explained in more detail with reference to FIG. 2.

The controller 120 may use the RAM 130 as a buffer memory, cache memory, or operation memory. For example, the controller 120 stores data received from an external host device in the RAM 130, transfers the data stored in the RAM 130 to the non-volatile memory device 110, and transfers the data stored in the RAM 130 to the non-volatile memory device 110. 110), a program operation can be requested. The controller 120 requests a read operation from the non-volatile memory device 110, stores the data received from the non-volatile memory device 110 in the RAM 130, and transfers the data stored in the RAM 130 to an external host. It can be output to a device.

FIG. 2 is a flowchart showing an example of a program operation performed by the program control unit (PCU1) of the nonvolatile memory device 110 and the program control unit (PCU2) of the controller 120. Referring to FIGS. 1 and 2 , in step S110, the program control unit (PCU2) of the controller 120 may transmit first data to the non-volatile memory device 110. For example, the first data may be some of the data to be programmed into memory cells through a single program operation. For example, the first data may include data corresponding to at least one logical page among logical pages belonging to one physical page.

After transmitting the first data, the program control unit (PCU2) of the controller 120 may confirm program execution. That is, the program control unit (PCU) may request the nonvolatile memory device 110 to start a program operation before all of the data to be programmed is transmitted through the program operation.

Upon confirmation of program execution, in step S130, the program control unit (PCU1) of the non-volatile memory device 110 may start a program operation based on the first data. After starting the program operation, the program control unit (PCU1) of the non-volatile memory device 110 may convert the ready-busy signal to a ready state and notify the controller 120 that additional data can be received.

In step S140, the program control unit (PCU1) of the controller 120 may transmit second data to the non-volatile memory device 110 while a program operation is performed in the non-volatile memory device 110. For example, the second data may be remaining data to be programmed into memory cells through one program operation. For example, the second data may include data corresponding to at least one logical page among logical pages belonging to one physical page.

As the second data is received, in step S150, the nonvolatile memory device 110 may continue the program operation based on the first data and the second data. For example, the nonvolatile memory device 110 may continue the program operation started in step S130 based on the first data and the second data.

According to embodiments of the present invention, the program operation begins after first data, which is part of data to be programmed through the program operation, is transmitted to the non-volatile memory device 110. While the program operation is performed, the remaining data, the second data, is transmitted to the non-volatile memory device 110. Accordingly, the time at which the second data is transmitted to the non-volatile memory device 110 can be shadowed, and the time for the program operation of the storage device 100 is reduced.

Exemplarily, steps S110 to S150 may be performed sequentially. After transmitting the first data (step S110) and starting the program operation (steps S120 and S130), the controller 120 may immediately transmit the second data (step S140). Even if the nonvolatile memory device 110 sets the ready-busy signal to the ready state after transmitting the first data and starting the program operation, the controller 120 will not allow any other access operation other than transmitting the second data. You can. For example, access operations in which the controller 120 requests another program operation, a read operation, or an erase operation to the non-volatile memory device 110 may be prohibited. For example, the controller 120 resets the non-volatile memory device 110, requests to stop operation of the non-volatile memory device 110, or determines the state of the non-volatile memory device 110. Control operations such as requesting to read status may be permitted.

Figure 3 is a block diagram showing a non-volatile memory device 110 according to an embodiment of the present invention. 1 and 3, the nonvolatile memory device 110 includes a memory cell array 111, a row decoder circuit 113, a page buffer circuit 115, a pass-fail check circuit (PFC), and a data input/output circuit. (117), and includes a control logic circuit (119).

The memory cell array 111 includes a plurality of memory blocks BLK1 to BLKz. Each memory block includes a plurality of memory cells. Each memory block may be connected to the row decoder circuit 113 through at least one ground select line (GSL), a plurality of word lines (WL), and at least one string select line (SSL). Each memory block may be connected to the page buffer circuit 115 through a plurality of bit lines BL. A plurality of memory blocks (BLK1 to BLKz) may be commonly connected to a plurality of bit lines (BL). Memory cells of the plurality of memory blocks BLK1 to BLKz may have the same structures.

By way of example, each of the plurality of memory blocks BLK1 to BLKz may be a unit of an erase operation. Memory cells of the memory cell array 111 may be erased in units of one memory block. Memory cells belonging to one memory block can be erased simultaneously. As another example, each memory block may be divided into a plurality of sub-blocks. Each of the plurality of sub-blocks may be a unit of an erase operation.

Exemplarily, each of the plurality of memory blocks BLK1 to BLKz may include a physical storage space identified by a block address. Each of the plurality of word lines WL may correspond to a physical storage space identified by a row address. Each of the plurality of bit lines BL may correspond to a physical storage space identified by a column address.

By way of example, each memory block may include a plurality of physical pages, and each physical page may include a plurality of memory cells. Each physical page may be a unit of program operation. Memory cells in each physical page can be programmed simultaneously. Each physical page may include multiple logical pages. Bits programmed into each memory cell of each physical page may form logical pages. The first bits programmed into the memory cells of each physical page may form the first logical page. The K-th bits (K is a positive integer) programmed into the memory cells of each physical page may form the K-th logical page.

The row decoder circuit 113 is connected to the memory cell array 111 through a plurality of ground select lines (GSL), a plurality of word lines (WL), and a plurality of string select lines (SSL). The row decoder circuit 113 operates under the control of the control logic circuit 119. The row decoder circuit 113 decodes the address received through the input/output channel from the controller 120 and selects string select lines (SSL), word lines (WL), and ground select lines (GSL) according to the decoded address. ) can be controlled.

For example, during a program operation, the row decoder circuit 113 applies a program voltage (VGPM) to the selected word line of the memory block selected by the address and applies a pass voltage (VGPM) to the unselected word lines of the selected memory block. VPASS) can be authorized. During a read operation, the row decoder circuit 113 applies the select read voltage (VRD) to the selected word line of the memory block selected by the address and applies the unselected read voltage (VREAD) to the unselected word lines of the selected memory block. can be approved. During an erase operation, the row decoder circuit 113 may apply erase voltages (eg, ground voltage or low voltages having levels similar to the ground voltage) to word lines of the memory block selected by the address.

The page buffer circuit 115 is connected to the memory cell array 111 through a plurality of bit lines BL. The page buffer circuit 115 is connected to the data input/output circuit 117 through a plurality of data lines DL. The page buffer circuit 115 operates under the control of the control logic circuit 119.

During a program operation, the page buffer circuit 115 may store data to be programmed in memory cells. Based on the stored data, the page buffer circuit 115 may apply voltages to the plurality of bit lines BL. For example, the page buffer circuit 115 may function as a write driver. During a read operation or verification read, the page buffer circuit 115 may sense voltages of the bit lines BL and store the sensing result. For example, the page buffer circuit 115 may function as a sense amplifier.

The pass-fail check circuit (PFC) may receive the sensing result from the page buffer circuit 115 during verification. Based on the received sensing results, the pass-fail check circuit (PFC) can determine pass or fail. For example, during program verification, the page buffer circuit 115 may count the number of on-cells that are turned on. If the number of on-cells is greater than the threshold, the pass-fail check circuit (PFC) can determine a fail. If the number of on-cells is less than the threshold, the pass-fail check circuit (PFC) can determine the pass. For example, during erase verification, the page buffer circuit 115 may count the number of off-cells that are turned off. If the number of off cells is greater than the threshold, the pass-fail check circuit (PFC) can determine a fail. If the number of on-cells is less than the threshold, the pass-fail check circuit (PFC) can determine the pass. The pass or fail determination result is transmitted to the control logic circuit 119.

The data input/output circuit 117 is connected to the page buffer circuit 115 through a plurality of data lines DL. The data input/output circuit 117 outputs data read by the page buffer circuit 115 to the controller 120 through an input/output channel, and outputs data received from the controller 120 through an input/output channel to the page buffer circuit 115. It can be delivered.

The control logic circuit 119 may receive a command from the controller 120 through an input/output channel and a control signal through a control channel. The input/output channel may include input/output lines (DQ), and the control channel may include a line through which a ready-busy signal (RnB) is transmitted. The control logic circuit 119 receives commands received through the input/output channel in response to the control signal, routes the address received through the input/output channel to the row decoder circuit 113, and stores data received through the input/output channel. It can be routed to the data input/output circuit 117. The control logic circuit 119 may decode the received command and control the non-volatile memory device 110 according to the decoded command.

For example, during a read operation, the control logic circuit 119 may generate a data strobe signal (DQS) from the read enable signal (/RE) received from the controller 120 through a control channel. The generated data strobe signal (DQS) may be output to the controller 120 through a control channel. During a program operation, the control logic circuit 119 may receive a data strobe signal (DQS) from the controller 120 through a control channel.

Under the control of the control logic circuit 119, program operations, erase operations, and read operations may be performed on memory cells of each memory block. A program operation may include multiple program loops. The program loop can be repeated until a path is determined.

Each program loop can include program and verification. During programming, the page buffer circuit 115 may apply voltages to the bit lines 115 according to data to be programmed. For example, a low voltage having a ground voltage or similar level is applied to the bit line corresponding to a memory cell whose threshold voltage is to be increased, and a memory cell whose threshold voltage will not be increased (e.g., a memory cell to be program inhibited). A positive voltage having a power supply voltage or a similar level may be applied. The row decoder circuit 113 may apply a program voltage to word lines connected to selected memory cells and a pass voltage to the remaining word lines. In verification, the results of the program can be verified. Verification may include verification read and pass-fail determination. During verification read, the page buffer circuit 115 may apply a power voltage or a positive voltage having a level similar thereto to the bit lines BL or bit lines corresponding to memory cells that are targets of verification read. The row decoder circuit 113 may apply a verification voltage to word lines connected to selected memory cells that are subject to verification and a read pass voltage to the remaining word lines. The result of the verification read may be sensed by the page buffer circuit 115 and transmitted to a pass-fail check (PFC). When determining pass-fail, the pass-fail check circuit (PFC) can determine pass or fail according to the result of verification read.

For example, during a program operation of the non-volatile memory device 110, the non-volatile memory device 110 continuously receives all bits to be programmed into each memory cell of the selected physical page of the memory cell array 111, and , the program of the selected physical page can be completed through one program operation based on sequentially received bits. Completion of the program means that all bits to be programmed in the corresponding physical page have been programmed in a readable state, and additional programming for the corresponding physical page is prohibited.

The read operation is performed similarly to verification read. During a read operation, the page buffer circuit 115 may apply a power supply voltage or a positive voltage having a level similar thereto to the bit lines BL or bit lines corresponding to memory cells that are targets of verification read. The row decoder circuit 113 may apply a read voltage to word lines connected to selected memory cells that are the target of a read operation and apply a read pass voltage to the remaining word lines. The result of the read operation may be sensed by the page buffer circuit 115 and output through the data input/output circuit 117.

An erase operation may include multiple erase loops. The erase loop can be repeated until a pass is determined. Each erase loop may include erase and verify. When erasing, the row decoder circuit 113 may apply ground voltage or low voltages having a similar level to word lines connected to selected memory cells. An erase voltage may be applied to channels of selected memory cells through the substrate. Upon verification, the results of erasure can be verified. Verification may include verification read and pass-fail determination. During verification read, the page buffer circuit 115 may apply a power voltage or a positive voltage having a level similar thereto to the bit lines BL or bit lines corresponding to memory cells that are targets of verification read. The row decoder circuit 113 may apply an erase verification voltage to word lines connected to selected memory cells that are subject to verification. The result of the verification read may be sensed by the page buffer circuit 115 and transmitted to a pass-fail check (PFC). When determining pass-fail, the pass-fail check circuit (PFC) can determine pass or fail according to the result of verification read.

The program control unit (PCU2) may control the row decoder circuit 113, the page buffer circuit 115, and the data input/output circuit 117 to perform a program operation according to the method described with reference to FIG. 2.

Figure 4 is a block diagram showing the page buffer circuit 115 according to an embodiment of the present invention. By way of example, configurations corresponding to one bit line BL are shown in FIG. 4 . Referring to FIGS. 3 and 4 , the page buffer circuit 115 includes a control circuit (CC), a cache latch (CL), data latches (DL1 and DL2), and a sense latch (SL).

The control circuit (CC) is connected to the data line (DL) and the bit line (BL). The control circuit (CC) may load data transmitted through the data line (DL) into the cache latch (CL). The control circuit (CC) may dump the data loaded in the cache latch (CL) into one of the data latches (DL1 and DL2) under the control of the control logic circuit (119). The control circuit (CC) may set the sense latch (SL) according to the data loaded into the data latches (DL1, DL2) or the data latches (DL1, DL2) and the cache latch (CL). According to the value set in the sense latch (SL), the bit line (BL) may be set up.

The sense latch (SL) may be set according to the voltage of the bit line (BL). The control circuit (CC) can set the data latches (DL1, DL2) or the data latches (DL1, DL2) and the cache latch (CL) according to the value set in the sense latch (SL). The control circuit (CC) outputs the data set in the data latches (DL1, DL2) or the cache latch (CL) to the data line (DL) or the pass-fail check circuit (PFC). You can.

Illustratively, the number of data latches (DL1, DL2) or data latches (DL1, DL2) and cache latches (CL) is the number of bits programmed in each memory cell of each memory block, that is, in one physical page. It can be determined according to the number of logical pages it belongs to.

Figures 5 and 6 are timing diagrams showing program operations according to an embodiment of the present invention from the perspective of input/output lines (DQ) and ready-busy signals (RnB). Referring to FIGS. 1, 3, 4, and 5, at a first time T1, the controller 120 may transmit the first input sequence S_P1in through the input/output lines DQ. For example, the controller 120 transmits a data input command (C_Din), an address (ADDR_P), first data (D_P1), a dump command (C_DM), and an end command (C_E1) through the input/output lines (DQ). You can. The data input command (C_Din) indicates that data to be programmed is input, and may be '80h'. The address (ADDR_P) indicates the address of memory cells in which data will be programmed, for example, a physical page. The first data D_P1 may be data of one logical page among logical pages belonging to the physical page corresponding to the address ADDR_P. The dump command (C_DM) is a command that requests dumping of data, and may be 'C0h'. The end command (C_E1) indicates that transmission of the first logical page has ended, and may be '11h'.

While the first input sequence (S_P1in) is in progress, the non-volatile memory device 110 may maintain the ready-busy signal in a high level ready state. The internal ready-busy signal (iRnB) indicates whether an operation is performed inside the non-volatile memory device 110, separately from the ready-busy signal (RnB) that the non-volatile memory device 110 outputs to the controller 120. You can. While the first input sequence (S_P1in) progresses, the internal ready-busy signal (iRnB) may be maintained in a high level ready state.

In the first input sequence S_P1in, the first data D_P1 transmitted from the controller 120 to the non-volatile memory device 110 through the input/output lines DQ may be stored in the cache latches CL. . As the dump command (C_DM) and the end command (C_E1) are received through the input/output lines (DQ), the non-volatile memory device 110 converts the first data (D_P1) loaded into the cache latch (CL) into the first data It can be dumped into the latches DL1 or the second data latches DL2. As the non-volatile memory device 110 dumps the first data (D_P1), the internal ready-busy signal (iRnB) of the non-volatile memory device 110 switches to a low-level busy state at the second time (T2). do. The ready-busy signal (RnB) also transitions to a low-level busy state. When dumping of the first data (D_P1) is completed, at the third time (T3), the internal ready-busy signal (iRnB) and the ready-busy signal (RnB) are each converted to a high level ready state.

As the ready-busy signal (RnB) transitions to the high level ready state at the third time (T3), the controller 120 proceeds with the confirm sequence (S_CFM). For example, the controller 120 may sequentially transmit a first confirm command (C_PC1), an address (ADDR_P), and a second confirm command (C_PC2) through the input/output lines (DQ). The first confirm command (C_PC1) indicates the start of the confirm sequence (S_CFM) and may be '88h'. The address (ADDR_P) indicates the address of memory cells on which a program operation is to be performed, for example, a physical page. The second confirm command (C_PC2) indicates the end of the confirmation sequence and may be '15h'.

As the confirmation sequence S_CFM is received through the input/output lines DQ, at the fourth time T4, the nonvolatile memory device 110 starts programming the first program loop. The internal ready-busy signal (iRnB) of the non-volatile memory device 110 transitions to a low-level busy state. When the program of the first program loop starts, the non-volatile memory device 110 transitions the ready-busy signal (RnB) to a low-level busy state. When the control circuit (CC) and the cache latch (CL) are in a state capable of receiving data while the program of the first program loop is being performed, at the fifth time (T5), the non-volatile memory device 110 is ready- The busy signal (RnB) transitions to the high level ready state.

As the ready-busy signal RnB transitions to the high level ready state at the fifth time T5, the controller 120 proceeds with the second data input sequence S_P2in. For example, the controller 120 may sequentially transmit a data input command (C_Din), an address (ADDR_P), second data (D_P2), and an end command (C_E2). Compared to the first data input sequence (S_P1in), the controller 120 transmits the second data (D_P2) in the second data input sequence (S_P2in). The second data D_P2 may be data of the second logical page to be programmed into memory cells corresponding to the address ADDR_P. Additionally, the controller 120 may transmit the end command C_E2 to the nonvolatile memory device 110 without transmitting the dump command C_DM to the nonvolatile memory device 110 . The end command (C_E2) indicates that the transfer of data of the second logical page has been completed, and may be '12h'.

1 and 3 to 6, as the end command C_E2 is received through the input/output lines DQ, the memory cells corresponding to the address ADDR_P are programmed at the sixth time T6. All of the data is loaded into the page buffer circuit 115. Accordingly, the nonvolatile memory device 110 may transition the ready-busy signal RnB to a low-level busy state and continue the program operation. For example, the nonvolatile memory device 110 may perform verification of the first program loop. For example, the nonvolatile memory device 110 may perform verification read and pass-fail check after all data to be programmed is received.

As the program operation continues, between the seventh time T7 and the eighth time T8, the nonvolatile memory device 110 executes the second program based on the first data D_P1 and the second data D_P2. Loops can be performed. At the kth time (Tk), as the nonvolatile memory device 110 performs the n-th program loop, the program operation may be terminated. When the program operation is terminated, the internal ready-busy signal (iRnB) and the ready-busy signal (RnB) of the nonvolatile memory device 110 may each transition to a high level ready state.

Exemplarily, the second data (D_P2) may be required when verifying the first program loop. Therefore, according to embodiments of the present invention, the program of the first program loop is performed in parallel with the transmission of the second data (D_P2), and the verification of the first program loop is performed after the second data (D_P2) is transmitted. It can be. This is explained in more detail with reference to FIGS. 8 and 9 .

Figure 7 shows an example in which threshold voltages of memory cells are formed according to data programmed into the memory cells. In Figure 7, the horizontal axis indicates the threshold voltage (Vth) of memory cells, and the vertical axis indicates the number of memory cells. That is, Figure 7 shows threshold voltage distributions of memory cells on which a program operation has been performed.

Referring to FIG. 7, when the bit of the first data (D_P1) is '1' and the bit of the second data (D_P2) is '1', the memory cells maintain the erase state (E) even when the program operation is performed. . When the bit of the first data (D_P1) is '0' and the bit of the second data (D_P2) is '1', the memory cells have the first program state (P1) after the program operation is performed. The first program state (P1) is verified through the first verification voltage (VFY1). When the bit of the first data (D_P1) is '0' and the bit of the second data (D_P2) is '0', the memory cells have the second program state (P2) after the program operation is performed. The second program state (P2) can be verified using the second verification voltage (VFY2). When the bit of the first data (D_P1) is '1' and the bit of the second data (D_P2) is '0', the memory cells have a third program state (P3) after the program operation is performed. The third program state (P3) can be verified using the third verification voltage (VFY3).

According to an embodiment of the present invention, when hiding the transmission time of the second data (D_P2), the program of the first program loop is performed in parallel with the transmission of the second data (D_P2), and verification of the first program loop is performed in 2 Can be performed after data (D_P2) is transmitted. That verification of the first program loop is performed after transmission of the second data (D_P2) is explained in more detail with reference to FIGS. 8 and 9.

In order to hide the transmission time of the second data (D_P2) according to an embodiment of the present invention, the controller 120 selects the state corresponding to the lowest threshold voltage range (for example, the erase state (E)) and the next lowest threshold voltage range. It is configured to select data having the discrimination point DP1 between the states corresponding to the threshold voltage range (for example, the first program state P1) as the first data D_P1 to be transmitted first. The discrimination point DP1 indicates a point where the values of the nearest bits are different from each other. For example, in the first data (D_P1), the erase state (E) corresponds to '1', and the first program state (P1) corresponds to '0'. Accordingly, the first data (D_P1) is selected as data to be transmitted first. The discrimination point DP1 is described in more detail with reference to FIGS. 10 to 16.

Figure 8 is a flowchart showing the process in which program operations are performed according to embodiments of the present invention. Referring to FIGS. 1, 3, and 8, in step S210, the nonvolatile memory device 110 may receive first data (D_P1) and confirm command (C_PC).

In step S220, the nonvolatile memory device 110 may perform programming during programming and verification of program operations by applying a program voltage to the word line connected to the selected memory cells. Thereafter, in step S230, the nonvolatile memory device 110 may stop the program operation and wait until the second data D_P2 is received.

When the second data D_P2 is received, the nonvolatile memory device 1100 performs verification in step S240. If the verification result is pass, the program operation is terminated. If the verification result is fail, the program operation is completed in step S260. The voltage is increased, and the program is performed by applying the program voltage in step S270. Afterwards, verification can be performed again in step S240.

9 is a flowchart showing how verification read is performed during verification. Referring to FIGS. 1, 3, 4, and 9, in steps S310 to S330, verification read for the first program state (P1) is performed. In step S310, the nonvolatile memory device 110 performs verification read by applying the first verification voltage VFY1 to the word line connected to the selected memory cells. The result of the verification read may be stored in sense latches (SL). In step S320, a selection dump for the first program state (P1) is performed. For example, the control circuit (CC) controls the data latches (DL1, DL2) connected to a specific bit line or the data stored in the data latches (DL1, DL2) and the cache latch (CL) to the second program state (P2) or When corresponding to the third program state (P3), the result of the verification read stored in the sense latch (SL) connected to the corresponding bit line can be initialized. For example, the control circuit (CC) may initialize the result of the verification read stored in the sense latch (SL) to indicate a fail. Afterwards, in step S330, an inhibit dump is performed. For example, the control circuit (CC) includes data latches (DL1, DL2) or data latches (DL1, DL2) and a cache latch associated with the sense latches that store the value corresponding to the pass among the sense latches (SL). Information indicating the path can be stored in (CL).

In steps S340 to S360, verification read for the second program state (P2) is performed. In step S340, the nonvolatile memory device 110 performs verification read by applying the second verification voltage VFY2 to the word line connected to the selected memory cells. The result of the verification read may be stored in sense latches (SL). In step S350, a selection dump for the second program state (P2) is performed. For example, the control circuit (CC) when the data latches (DL1, DL2) connected to a specific bit line or the data stored in the data latches (DL1, DL2) and the cache latch (CL) correspond to the third program state, The result of the verification read stored in the sense latch (SL) connected to the corresponding bit line can be initialized. For example, the control circuit (CC) may initialize the result of the verification read stored in the sense latch (SL) to indicate a fail. Afterwards, in step S360, an inhibit dump is performed. For example, the control circuit (CC) includes data latches (DL1, DL2) or data latches (DL1, DL2) and a cache latch associated with the sense latches that store the value corresponding to the pass among the sense latches (SL). Information indicating the path can be stored in (CL).

In steps S370 and S380, verification read for the third program state (P3) is performed. In step S370, the nonvolatile memory device 110 performs verification read by applying the third verification voltage VFY3 to the word line connected to the selected memory cells. The result of the verification read may be stored in sense latches (SL). In step S380, an inhibit dump is performed. For example, the control circuit (CC) includes data latches (DL1, DL2) or data latches (DL1, DL2) and a cache latch associated with the sense latches that store the value corresponding to the pass among the sense latches (SL). Information indicating the path can be stored in (CL).

As described above, when performing a selective dump, information indicating the second program state (P2) and the third program state (P3) is required, and the corresponding information includes the first data (D_P1) and the second data (D_P2). They all exist and can be acquired. Therefore, the nonvolatile memory device 110 according to an embodiment of the present invention performs the program of the first program loop and holds verification of the first program loop until the second data (D_P2) is received. You can.

Exemplarily, in FIG. 9 , verification reads for the first to third program states (P1 to P3) are described as being sequentially performed. However, when the verification of at least one program state among the first to third program states P1 to P3 is passed first, the verification read associated with the at least one program state passed first may be omitted.

As shown in FIG. 9, the selection dump (step S320) of the first program state (P1) may be performed after the verification read (step S310) using the first verification voltage (VFY1) is performed. Therefore, in addition to the program of the first program loop being performed in parallel with the transmission of the second data (D_P2), the verification read using the first verification voltage (VFY1) of the verification of the first program loop is performed in parallel with the transmission of the second data (D_P2). ) The technical idea of the present invention can be applied by being performed in parallel with the transmission of ).

Figure 10 shows threshold voltage distributions of memory cells in an erased state. In Figure 10, the horizontal axis indicates threshold voltages (Vth) of memory cells, and the vertical axis indicates the number of memory cells.

Referring to FIGS. 7 and 10 , reference symbol 'E_E' indicates memory cells that maintain an erased state (E) during a program operation. Reference symbol 'E_P1' indicates memory cells that are programmed from the erase state (E) to the first program state (P1). Reference symbol 'E_P2' indicates memory cells that are programmed from the erase state (E) to the second program state (P2). Reference symbol 'E_P3' indicates memory cells that are programmed from the erase state (E) to the third program state (P3).

The reference symbol 'W_E' indicates the range of the threshold voltage (Vth) corresponding to memory cells in the erased state (E). Reference symbol 'W_P1' indicates the range of the threshold voltage (Vth) corresponding to memory cells in the first program state (P1). Reference symbol 'W_P2' indicates the range of the threshold voltage (Vth) corresponding to memory cells in the second program state (P2). Reference symbol 'W_P3' indicates the range of the threshold voltage (Vth) corresponding to memory cells in the third program state (P3).

Before the program operation is performed, the memory cells (E_E, E_P1, E_P2, E_P3) may belong to the threshold voltage range (W_E) of the erase state (E).

FIG. 11 shows a process in which the first program loop is performed in the memory cells of FIG. 10. In FIG. 11, the horizontal axis indicates time (T), and the vertical axis indicates voltage (V) applied to data transmitted through input/output lines (DQ) and word lines connected to selected memory cells.

Referring to FIGS. 3, 7, 10, and 11, first data D_P1 may be input to the page buffer circuit 115 through the input/output line DQ at a first time T1. When input of the first data D_P1 is completed, the page buffer circuit 115 may set up the bit lines BL according to the first data D_P1. For example, bit lines corresponding to memory cells (E_E, E_P3) to be programmed to the erase state (E) and the third program state (P3) may be set to prohibit programming. Bit lines corresponding to the memory cells E_P1 and E_P2 to be programmed in the first program state (P1) and the second program state (P2) may be set to be programmed. Thereafter, at a second time T2, the row decoder circuit 113 may apply the program voltage VPGM to the selected word line. During a program that applies the program voltage VPGM, second data D_P2 may be input to the page buffer circuit 115 through the input/output lines DQ.

When input of the second data D_P2 is completed, the page buffer circuit 115 may precharge the bit lines BL at the third time T3. For example, before performing a verification read using the first verification voltage (VFY1), the page buffer circuit 115 supplies power to the bit lines corresponding to the memory cells (E_P1) programmed to the first program state (P1). Positive voltages having a voltage or similar level can be charged. The page buffer circuit 115 may charge the remaining bit lines with low voltages having a ground voltage or similar level, or may float the remaining bit lines. Afterwards, the row decoder circuit 113 may apply the first verification voltage (VFY1) to the selected word line.

After the page buffer circuit 115 charges the bit lines corresponding to the memory cells E_P2 to be programmed to the second program state P2, the row decoder circuit 113 applies the second verification voltage VFY2 to the selected word line. can be approved. Additionally, after the page buffer circuit 115 charges the bit lines corresponding to the memory cells E_P3 to be programmed to the third program state P3, the row decoder circuit 113 applies a third verification voltage ( VFY3) can be approved.

As another example, the page buffer circuit 115 applies voltage to all bit lines BL before one of the verification voltages VFY1 to VFY3 is applied to the selected word line, regardless of the program states P1 to P3. It may be configured to charge the power supply voltage or a positive voltage having a level similar thereto.

When the first program loop shown in FIG. 11 progresses, the threshold voltages of memory cells may change from FIG. 10 to FIG. 12. Referring to FIG. 12 , the threshold voltages of memory cells E_P1 and E_P2 that are programmed into the first and second program states P1 and P2 may increase. Since the memory cells E_P3 programmed in the third program state P3 are program-inhibited in the first program loop according to the first data D_P1, the threshold voltages of the memory cells E_P3 are maintained without rising.

Figure 13 shows the process in which the second program loop is performed following Figure 11. Referring to FIGS. 12 and 13 , the threshold voltages of some (MC_P) of the memory cells (E_P1) to be programmed to the first program state (P1) are higher than the first verification voltage (VFY1), and the threshold voltages of the remaining portions are higher than the first verification voltage (VFY1). It is below the verification voltage (VFY1). Accordingly, some (MC_P) of the memory cells (E_P1) are set to program prohibited, and some of the remaining memory cells (E_P1) are set to program. The memory cells E_P2 and E_P3 that are programmed in the second and third program states P2 and P3 are all in a fail state. Accordingly, the memory cells E_P2 and E_P3 are set to the program. Afterwards, at the fourth time T4, the increased program voltage VPGM is applied.

When the increased program voltage VPGM is applied, the threshold voltages of the memory cells change from FIG. 12 to FIG. 14. Referring to FIG. 14 , the threshold voltages of memory cells E_P2 and E_P3 that are programmed to the second and third program states P2 and P3 increase. Since the threshold voltages of some (MC_P) of the memory cells (E_P1) programmed to the first program state (P1) do not increase, the threshold voltages of the memory cells (E_P1) may increase but the distribution width may decrease.

Figure 15 shows the threshold voltages of memory cells when the second data (D_P2) is transmitted first and the program of the first program loop is performed. As shown in FIG. 7, the erase state (E) and the first program state (P1) correspond to '1' in the second data (D_P2), and the second and third program states (P2 and P3) are Corresponds to '0'. Therefore, when the first program loop is performed based on the second data (D_P2), the memory cells (E_P2, E_P3) are programmed to the second and third program states (P2, P3), and the first program state is programmed. Memory cells (E_P1) that are programmed with (P1) are program inhibited. Accordingly, as shown in FIG. 15, the threshold voltages of the memory cells E_P3 and E_P2 increase, and the threshold voltages of the memory cells E_P1 do not increase but remain.

When an increased program voltage is applied in the second program loop, some memory cells (MC_P) shown in FIG. 12 are programmed with the increased program voltage and thus may be overprogrammed. In order to prevent some memory cells (MC_P) from being overprogrammed, as shown in FIG. 16, the program voltage (VPGM) of the second program loop must be maintained without increasing. That is, when the second data (D_P2) is input to the nonvolatile memory device 110 before the first data (D_P1) and the program operation begins, the program loop must be performed twice using the same program voltage (VPGM). . Accordingly, the time of program operation may not decrease but rather increase.

The controller 120 according to an embodiment of the present invention operates in a state corresponding to the lowest threshold voltage range, for example, a bit value in the erase state (E) and a state corresponding to the next lowest threshold voltage range, for example, 1 It is configured to first transmit data of a logical page with a different bit value of the program state (P1) to the non-volatile memory device 110. Accordingly, the memory cells E_P1 programmed to the lowest program state P1 are programmed and verified in the first program loop, and the execution time of the program loop is shadowed with the transmission time of the second data D_P2.

As another example, to improve the reliability of memory cells, the second data D_P2 may be loaded first, as shown in FIG. 15, and the program operation may begin. While the program of the first loop of the program operation is performed based on the second data D_P2, the first data D_P1 may be loaded into the page buffer circuit 115. In this case, after the threshold voltages of the memory cells E_P2 programmed to the second program state P2 and the memory cells E_P3 programmed to the third program state P3 are increased as shown in FIG. 15, the same The program loop is performed again using the program voltage (VPGM). For example, after pre-programming to increase the threshold voltages of the memory cells E_P2 and E_P3 as shown in FIG. 15, a program operation may be started.

In this case, as the threshold voltages of the memory cells E_P2 and E_P3 rise as shown in FIG. 15, the coupling transmitted to the memory cells E_P1 causes the memory cells E_P1 to be in the first program state P1. Can be offset while being programmed. That is, if the first data (D_P1) is loaded first and the second data (D_P2) is loaded after the program operation starts, disturbances such as coupling that occur during the program operation are reduced. Accordingly, the reliability of data programmed into memory cells is improved.

Figure 17 shows a process in which a program operation according to an embodiment of the present invention is performed when one physical page includes three logical pages. In Figure 17, the horizontal axis indicates time. Referring to FIGS. 1, 3, and 17, at a first time T1, the controller 120 transmits the first data input sequence S_P1in to the non-volatile memory device 110 through the input/output lines DQ. do. The first data input sequence (S_P1in) may include data of the first logical page. The first logical page may have a discrimination point (DP1) between the erase state (E) and the lowest program state (P1).

At the second time T2, the nonvolatile memory device 110 performs dumping according to the first data input sequence S_P1in. While the nonvolatile memory device 110 performs dumping, the internal ready-busy signal (iRnB) and the ready-busy signal (RnB) may transition to a low-level busy state. When dumping is completed, at the third time T3, the nonvolatile memory device 110 transitions the ready-busy signal RnB to the high level ready state. The internal ready-busy signal (iRnB) can also transition to a high level ready state.

As the ready-busy signal RnB transitions to the high level ready state, the controller 120 may transmit the confirm sequence S_CFM to the non-volatile memory device 110 through the input/output lines DQ. At the fourth time T4, the nonvolatile memory device 110 starts a program operation, and the internal ready-busy signal (iRnB) and the ready-busy signal (RnB) transition to a low level busy state. While the internal ready-busy signal (iRnB) remains at a low level until the program operation is completed, the ready-busy signal (RnB) remains at a high level when the non-volatile memory device 110 is in a state capable of receiving data. Transition to the ready state of the level.

As the ready-busy signal (RnB) transitions to the high level, at the fifth time (T5), the controller 120 sends the second data input sequence (S_P2in) to the non-volatile memory device (S_P2in) through the input/output lines (DQ). 110). The second data input sequence (S_P2in) may include data of the second logical page. While the second data input sequence S_P2in is in progress, the nonvolatile memory device 110 may perform a program of the first program loop.

When the second data input sequence S_P2in is completed, the nonvolatile memory device 110 may dump the second data at the sixth time T6. While the nonvolatile memory device 110 dumps the second data, the ready-busy signal RnB may transition to a low level. When dumping is completed, the nonvolatile memory device 110 may transition the ready-busy signal (RnB) to a high level.

As the ready-busy signal RnB transitions to a high level, at the seventh time T7, the controller 120 transmits the third data input sequence S_P3in to the non-volatile memory device through the input/output lines DQ. send. The third data input sequence (S_P3in) may include data of the third logical page.

Illustratively, after performing the program of the first program loop, the nonvolatile memory device 110 may have a hold period in which the program operation is held until data of all logical pages are received.

When the third data input sequence S_P3in is completed, at the eighth time T8, the nonvolatile memory device 110 may perform verification of the first program loop. Afterwards, the nonvolatile memory device 110 may perform a second program loop between the ninth time T9 and the tenth time T10. At the kth time (Tk), the nonvolatile memory device 110 may perform the n-th program loop and end the program operation.

For example, when 2-bits are programmed into each memory cell, and even when loading of the second data is not completed even after the programming of the first program loop is completed, a hold period may occur. For example, after the program of the first program loop is completed and until the loading of the second data is completed, the non-volatile memory device 110 has a hold period in which it waits for the loading of the second data and does not perform any other operations. You can.

The technical idea of the present invention is not limited to including two or three logical pages in one physical page. For example, the technical idea of the present invention can be extended to include m-number of logical pages in one physical page. That is, the technical idea of the present invention can be extended to m-bits being programmed in one physical page. After data of at least one logical page is transferred to the non-volatile memory device 110, a program operation may begin. For example, a program of the first program loop may be performed in the nonvolatile memory device 110. After the data of the remaining logical pages are transferred to the non-volatile memory device 110, the program operation may continue. For example, verification of the first program loop and second and subsequent program loops may be performed.

In the above-described embodiments, the technical idea of the present invention has been explained assuming an example in which 2-bits are programmed in each memory cell. However, the technical idea of the present invention is not limited to 2-bits being programmed in each memory cell.

Figure 18 shows an example of the threshold voltages of memory cells when 3-bits are programmed in each memory cell. Figure 19 shows the process in which the first program loop is performed when 3-bits are programmed in each memory cell. In Figure 18, the horizontal axis indicates the threshold voltage (Vth) of memory cells, and the vertical axis indicates the number of memory cells. In FIG. 19, the horizontal axis indicates time (T), and the vertical axis indicates voltage (V) applied to data transmitted through input/output lines (DQ) and word lines connected to selected memory cells.

Referring to FIGS. 3, 18, and 19, memory cells may have an erase state (E) and first to seventh program states (P1 to P7). To program memory cells, data (D_P1, D_P2, D_P3) corresponding to three pages may be loaded into the page buffer circuit 115. Three data latches (DL, see FIG. 4) may be connected to one bit line (BL). 3-bits corresponding to each of the three pages may be loaded into the three data latches (DL).

Exemplarily, as shown with reference to FIGS. 7, 12, 13, and 14, the bits corresponding to the erase state (E) and the bits corresponding to the first program state (P1) are data of different pages. may first be loaded into the page buffer circuit 115 as first data (D_P1). While the program of the first program loop of the program operation is performed, data (D_P2, D_P3) of the remaining two pages may be loaded into the page buffer circuit 115.

Exemplarily, as described with reference to FIGS. 7, 15, and 16, data on a page with the same bits corresponding to the erase state (E) and the first program state (P1) are used as first data (D_P1). It may first be loaded into the page buffer circuit 115. For example, a page where the bits of the program state with large coupling occurring during program operation, i.e., the highest seventh program state (P7) or the second highest sixth program state (P6), point to a program that is not program inhibited. The data may first be loaded into the page buffer circuit 115 as first data D_P1. While the program of the first program loop of the program operation is performed, data (D_P2, D_P3) of the remaining two pages may be loaded into the page buffer circuit 115.

By way of example, memory cells may be programmed from an erase state through a single program operation. Program completion means that all program procedures performed by the controller 120 by transmitting one or more commands to the non-volatile memory device 110 are completed, and the controller 120 performs a read operation on the non-volatile memory device 110, This may mean that an erase operation or another program operation can be requested.

Figure 20 shows an example in which memory cells are programmed through two or more program operations. In Figure 20, the horizontal axis indicates the threshold voltage (Vth) of memory cells, and the vertical axis indicates the number of memory cells.

Referring to FIGS. 3 and 20 , memory cells can be programmed through three program operations (PO1 to PO3). In Figure 20, it is assumed that 3-bits are programmed in each memory cell.

During the first program operation PO1, memory cells are programmed from the erase state E to the erase state E and the first to fourth intermediate program states I1 to I4. During the first program operation, at least two pages of data are required. As described with reference to FIGS. 1 to 19 , a program operation may begin after one page data among at least two pages of data is loaded into the page buffer 115 . While the program of the first program loop of the program operation is performed, data of the remaining pages may be loaded into the page buffer 115.

Illustratively, after the program operation starts, data of the second page may be loaded. Afterwards, verification of the first program loop can be performed. Exemplarily, while verification of the first program loop is performed and program operation continues, data of the third page may be loaded. Since the data of the third page is not used in the first program operation PO1, it can be loaded into the page buffer circuit 115 in parallel with the program operation.

The first program operation PO1 may be performed roughly. For example, memory cells on which the first program operation PO1 has been performed are not the target of the read operation, and therefore, the read operation may be performed roughly without considering read errors.

Data of at least two pages loaded into the page buffer circuit 115 may be separately programmed in the backup area. For example, one bit can be programmed into each memory cell in the backup area.

During the second program operation (PO2), memory cells are programmed to the erase state (E) and the first to seventh program states (P1 to P7). For example, if the data of the third page is not loaded during the first program operation (PO1), the data of the third page may be loaded when the second program operation (PO2) starts. The second program operation (PO2) is performed based on the data programmed in the backup area or the data programmed in the backup area and the data of the third page loaded into the page buffer circuit 115 from the controller 120 (see FIG. 1). You can.

The second program operation PO1 may be performed roughly. For example, memory cells on which the second program operation PO2 has been performed are not the target of the read operation, and therefore, the read operation may be performed roughly without considering read errors.

During the third program operation PO3, the threshold voltage distribution of memory cells can be finely programmed. The third program operation PO3 may be performed based on data programmed in the backup area. When the third program operation PO3 is performed, the programming of the memory cells is completed.

Figure 21 shows another example in which memory cells are programmed through two or more program operations. In Figure 21, the horizontal axis indicates the threshold voltage (Vth) of memory cells, and the vertical axis indicates the number of memory cells.

Referring to FIGS. 3 and 21 , memory cells can be programmed through two program operations PO1 and PO2. In Figure 21, it is assumed that 3-bits are programmed in each memory cell.

During the first program operation PO1, memory cells are programmed from the erase state E to the erase state E and the first to seventh program states P1 to P7. Exemplarily, the first program operation PO1 may correspond to the second program operation PO2 of FIG. 20.

A program operation may begin after the data of the first page is loaded into the page buffer circuit 115. While the program of the first program loop is being performed, data of the remaining pages may be loaded into the page buffer circuit 115.

After the first program operation PO1 is performed, the second program operation PO2 may be performed. The second program operation PO2 may correspond to the third program operation PO3 in FIG. 20. When the second program operation PO2 is performed, the memory cells are programmed.

Figure 22 shows an example of the threshold voltages of memory cells when 4-bits are programmed in each memory cell. In Figure 22, the horizontal axis indicates the threshold voltage (Vth) of memory cells, and the vertical axis indicates the number of memory cells.

Referring to FIGS. 3 and 22 , memory cells may have an erase state (E) and first to fifteenth program states (P1 to P15). To program memory cells, data corresponding to four pages may be loaded into the page buffer circuit 115. Four data latches (DL, see FIG. 4) may be connected to one bit line (BL). 4-bits corresponding to each of the four pages may be loaded into the four data latches (DL).

After the data of the first page is loaded into the page buffer circuit 115, program operation can begin. While the program of the first program loop is being performed, data of the remaining pages or data of some pages among the remaining pages may be loaded into the page buffer circuit 115.

FIG. 23 is a flowchart showing an application example in which a program operation is performed by the program control unit (PCU1) of the nonvolatile memory device 110 and the program control unit (PCU2) of the controller 120. Referring to FIGS. 1 and 23 , in step S410, the program control unit (PCU2) of the controller 120 may transmit first data to the non-volatile memory device 110. For example, the first data may include data corresponding to at least one logical page among logical pages belonging to one physical page.

After the first data is transmitted, in step S420, the nonvolatile memory device 110 may start a program operation based on the first data. After starting the program operation, the program control unit (PCU1) of the non-volatile memory device 110 may convert the ready-busy signal to a ready state and notify the controller 120 that additional data can be received.

In step S430, the program control unit (PCU1) of the controller 120 may transmit second data to the non-volatile memory device 110 while a program operation is performed in the non-volatile memory device 110. For example, the second data may include data corresponding to at least one logical page among logical pages belonging to one physical page.

As the second data is received, in step S440, the nonvolatile memory device 110 may continue the program operation based on the first data or the second data. For example, the nonvolatile memory device 110 may continue the program operation started in step S420 based on the first data and the second data. As another example, the nonvolatile memory device may continue the program operation started in step S420 based on the second data. The program control unit (PCU1) of the non-volatile memory device 110 may convert the ready-busy signal to a ready state and notify the controller 120 that additional data can be received.

In step S450, the program control unit (PCU1) of the controller 120 may transmit third data to the non-volatile memory device 110 while a program operation is performed in the non-volatile memory device 110. For example, the third data may include data corresponding to at least one logical page among logical pages belonging to one physical page.

As the third data is received, in step S460, the nonvolatile memory device 110 may continue the program operation based on the first data, second data, and third data. For example, the nonvolatile memory device 110 may continue the program operation started in step S420 based on the first data, second data, and third data.

According to embodiments of the present invention, the program operation begins after first data, which is part of data to be programmed through the program operation, is transmitted to the non-volatile memory device 110. While the program operation is performed, the remaining data, second data and third data, are transmitted to the nonvolatile memory device 110. As the second data or third data is transmitted, the nonvolatile memory device 110 may continue a program operation based on the received second data or third data. Accordingly, the time at which data is transmitted to the non-volatile memory device 110 may be shadowed by the time at which the program operation is performed, and the time for the program operation of the storage device 100 is reduced.

Illustratively, steps S410 to S460 may be performed sequentially. For example, while the program operation in steps S410 to S460 is performed, the controller 120 may be prohibited from requesting a read operation, an erase operation, or another program operation from the nonvolatile memory device 110.

Illustratively, steps S410 to S460 may be all or part of a program operation. For example, memory cells of the nonvolatile memory device 110 may be programmed according to a High Speed Program (HSP) scheme. In a high-speed programming scheme, memory cells can be programmed through one program operation. For memory cells that have completed programming, further programming operations may be prohibited. As another example, memory cells of the nonvolatile memory device 100 may be programmed by a reprogram (repgroam) scheme. In a reprogramming scheme, memory cells can be programmed through two or more program operations. For example, a read operation on memory cells before the program is completed may be prohibited. For memory cells that have been programmed through two or more program operations, additional program operations may be inhibited.

Figures 24 and 25 are timing diagrams showing program operations according to an embodiment of the present invention from the perspective of input/output lines (DQ) and ready-busy signals (RnB). Referring to FIGS. 1, 3, 24, and 25, at a first time T1, the controller 120 may transmit the first input sequence S_P1in through the input/output lines DQ. For example, the controller 120 transmits a data input command (C_Din), an address (ADDR_P), first data (D_P1), a dump command (C_DM), and an end command (C_E1) through the input/output lines (DQ). You can. The data input command (C_Din) indicates that data to be programmed is input, and may be '80h'. The address (ADDR_P) indicates the address of memory cells in which data will be programmed, for example, a physical page. The first data D_P1 may be data of one logical page among logical pages belonging to the physical page corresponding to the address ADDR_P. The dump command (C_DM) is a command that requests dumping of data, and may be 'C0h'. The end command (C_E1) may indicate that transmission of the first logical page has ended.

While the first input sequence (S_P1in) is in progress, the non-volatile memory device 110 may maintain the ready-busy signal in a high level ready state. The internal ready-busy signal (iRnB) indicates whether an operation is performed inside the non-volatile memory device 110, separately from the ready-busy signal (RnB) that the non-volatile memory device 110 outputs to the controller 120. You can. While the first input sequence (S_P1in) progresses, the internal ready-busy signal (iRnB) may be maintained in a high level ready state.

In the first input sequence S_P1in, the first data D_P1 transmitted from the controller 120 to the non-volatile memory device 110 through the input/output lines DQ may be stored in the cache latches CL. . As the dump command (C_DM) and the end command (C_E1) are received through the input/output lines (DQ), the non-volatile memory device 110 converts the first data (D_P1) loaded into the cache latch (CL) into the first data It can be dumped into the latches DL1 or the second data latches DL2. While the non-volatile memory device 110 dumps the first data (D_P1), the internal ready-busy signal (iRnB) of the non-volatile memory device 110 switches to a low-level busy state at the second time (T2). do. The ready-busy signal (RnB) also transitions to a low-level busy state. When dumping of the first data D_P1 is completed, the ready-busy signal RnB switches to the high level ready state at the third time T3.

At the third time T3, the nonvolatile memory device 110 starts programming the first program loop PL1. When the control circuit (CC) and cache latch (CL) are in a state in which data can be received while the program of the first program loop (PL1) is performed, the non-volatile memory device 110 sends a ready-busy signal (RnB) Transitions to the high level ready state. Exemplarily, before the second data input sequence (S_P2in) starts, program or program and verify read may be performed.

As the ready-busy signal (RnB) transitions to the high level ready state, the controller 120 proceeds with the second data input sequence (S_P2in). For example, the controller 120 may sequentially transmit a data input command (Din), an address (ADDR_P), second data (D_P2), a dump command (C_DM), and an end command (C_E2). Compared to the first data input sequence (S_P1in), the controller 120 transmits the second data (D_P2) in the second data input sequence (S_P2in). The second data D_P2 may be data of the second logical page to be programmed into memory cells corresponding to the address ADDR_P. The end command (C_E2) may indicate that transmission of data of the second logical page has been completed.

As the dump command (C_DM) and end command (C_E2) are received through the input/output lines (DQ), the non-volatile memory device 110 converts the second data (D_P2) loaded into the cache latch (CL) into the second data It can be dumped into the latches DL2 or the first data latches DL1. While the nonvolatile memory device 110 dumps the second data D_P2, the ready-busy signal RnB switches to the low level busy state at the fourth time T4. When dumping of the second data D_P2 is completed, at the fifth time T5, the ready-busy signal RnB switches to the high level ready state.

At the fifth time T5, the nonvolatile memory device 110 performs the remaining processes of the first program loop PL1. For example, a select dump, inhibit dump, and pass-fail check of the first program loop (PL1), or a verify read, select dump, inhibit dump, and pass-fail check of the first program loop (PL1) may be performed. .

Additionally, as the ready-busy signal (RnB) transitions to the high level ready state, the controller 120 proceeds with the third data input sequence (S_P3in). For example, the controller 120 may sequentially transmit a data input command (Din), an address (ADDR_P), third data (D_P3), and an end command (C_E2). The third data D_P3 may be data of the third logical page to be programmed into memory cells corresponding to the address ADDR_P. The end command (C_E3) may indicate that transmission of data of the third logical page has been completed.

While the third data input sequence S_P3in is performed, when the first program loop PL1 is completed at the sixth time T6, the nonvolatile memory device 110 performs the program of the second program loop PL2. You can. For example, the nonvolatile memory device 110 may perform the second program loop PL2 based on the first data D_P1 or the first data D_P1 and the second data D_P2. For example, the nonvolatile memory device 110 may perform a program or program and verify read of the second program loop PL2.

When the third data input sequence S_P3in is completed at the seventh time T7, the nonvolatile memory device 110 operates based on the first data D_P1, second data D_P2, and third data D_P3. Program operation can continue.

Illustratively, after the program operation is completed or when the next command can be received, the ready busy signal (RnB) may return to the high level ready state.

As explained with reference to FIGS. 23 to 25 , to perform a program operation in the non-volatile memory device 110 in which 3-bit data is written to each memory cell, three data transfers are required. However, if a program loop proceeds while a second data transfer is performed after one data transfer is performed, the time of data transfer may be hidden by the program time. Additionally, if one more program loop proceeds while the third data transfer is performed, the time of data transfer may be further hidden by the program time. Accordingly, the operating speed of the storage device 100 is improved.

FIG. 26 shows the process in which a program loop progresses in memory cells according to the method of FIG. 23. In FIG. 26, the horizontal axis indicates time (T), and the vertical axis indicates voltage (V) applied to data transmitted through input/output lines (DQ) and word lines connected to selected memory cells.

Referring to FIGS. 3 and 24 to 26 , first data D_P1 may be input to the page buffer circuit 115 through the input/output line DQ at a first time T1. When the program of the first program loop PL1 starts at the third time T3, the page buffer circuit 115 may set up the bit lines BL according to the first data D_P1. For example, the page buffer circuit 115 may set bit lines to be program prohibited or program target. The row decoder circuit 113 may apply a program voltage (VPGM) to the selected word line. While applying the program voltage VPGM, second data D_P2 may be input to the page buffer circuit 115 through the input/output lines DQ.

Exemplarily, the verification read of the first program loop (PL1) may be performed for the erase state (E) and the program state (P1) corresponding to the lowest threshold voltage (or lowest threshold voltage distribution range). For example, verification read of the first program loop PL1 may be performed using the first verification voltage VFY1. The verification read of the first program loop (PL1) is performed using the first data (D_P1) while the second data (D_P2) is input, or by using the first data (D_P1) or the first data (D_P2) after the second data (D_P2) is input. It may be performed using data (D_P1) and second data (D_P2). Select dump, inhibit dump, and pass-fail check of the first program loop (PL1) may be performed using the first data (D_P1) and the second data (D_P2) after the second data (D_P2) is received.

When the program of the second program loop PL2 starts at the sixth time T6, the page buffer circuit 115 stores the first data D_P1, the second data D_P2, or the first data D_P1 and the second data. The bit lines (BL) can be set up according to the data (D_P2). For example, the page buffer circuit 115 may set bit lines to be program prohibited or program target. The row decoder circuit 113 may apply a program voltage (VPGM) to the selected word line. While applying the program voltage VPGM, third data D_P3 may be input to the page buffer circuit 115 through the input/output lines DQ.

Exemplarily, the verification read of the second program loop (PL2) is the program state (P1) corresponding to the lowest threshold voltage (or lowest threshold voltage distribution range) and the second lowest threshold voltage (or second lowest threshold voltage distribution range). It may be performed for the program state (P2) corresponding to the voltage distribution range), and for the program state (P1) corresponding to the erase state (E) and the lowest threshold voltage. For example, the verification read of the second program loop PL2 may be performed using the first verification voltage VFY1 and the second verification voltage VFY2. The verification read of the second program loop (PL2) is performed using the first data (D_P1) and the second data (D_P2) while the third data (D_P3) is input, or the first data (D_P3) is input after the third data (D_P3) is input. It may be performed using data (D_P1), second data (D_P2), and third data (D_P3). The select dump, inhibit dump, and pass-fail check of the first program loop (PL1) select the first data (D_P1), second data (D_P2), and third data (D_P3) after the third data (D_P3) is received. It can be performed using

Exemplarily, in the second program loop PL2, verification read using the first verification voltage VFY1 may be performed while the third data D_P3 is input. In the second program loop (PL2), selection dump using the first verification voltage (VFY1), inhibit dump, and verification using the second verification voltage (VFY2) are performed on the first data after the input of the third data (D_P3) is completed. It may be performed based on (D_P1), second data (D_P2), and third data (D_P3).

When the input of the third data (D_P3) is completed, the nonvolatile memory device 110 performs a normal program operation using the first data (D_P1), the second data (D_P2), and the third data (D_P3). You can. For example, the nonvolatile memory device 110 may select bit lines as program inhibited or program targets using the first data (D_P1), the second data (D_P2), and the third data (D_P3). After the program voltage VPGM is applied, the nonvolatile memory device 110 may perform verification reads using the first to seventh verification voltages VFY1 to VFY7 corresponding to each program state. For each verification read using each verification voltage, the nonvolatile memory device 110 uses first data (D_P1), second data (D_P2), and third data (D_P3) to perform select dump, inhibit dump, and pass. -Fail check can be performed.

Figures 27 and 28 show examples where the threshold voltages of memory cells change due to the program loops of Figure 26. In Figure 27, the horizontal axis indicates threshold voltages (Vth) of memory cells, and the vertical axis indicates the number of memory cells.

23 to 27, reference symbol 'E_E' indicates memory cells that maintain an erased state (E) during a program operation. Inhibited memory cells (E_E) refer to memory cells that are program inhibited during a program operation and remain in an erased state. The program memory cells (E_P1 to E_P7) indicate memory cells that are programmed to the first to seventh program states (P1 to P7), respectively.

Exemplarily, the first data D_P1 may indicate whether the memory cells belong to the first to fourth program memory cells E_P1 to E_P4. The second data D_P2 may indicate whether the memory cells belong to the second, third, sixth, and seventh program memory cells E_P2, E_P3, E_P6, and E_P7.

The program of the first program loop (PL1) is performed using the first data (D_P1). Accordingly, the threshold voltages of the first to fourth program memory cells E_P1 to E_P4 increase together. When performing a verification read of the first program loop PL1, it may be determined whether the threshold voltages of the first to fourth program memory cells E_P1 to E_P4 are higher than the first verification voltage VFY1. Memory cells determined to have a threshold voltage higher than the first verification voltage VFY1 during verification read may be program-inhibited. When the second data (D_P2) is received, select dump and inhibit dump may be performed. Based on the first data (D_P1) and the second data (D_P2), memory cells that are programmed to a program state higher than the first program state (P1) corresponding to the first verification voltage (VFY1) may be released from program inhibition. there is. For example, the program inhibition of the second, third, sixth, and seventh program memory cells (E_P2, E_P3, E_P6, and E_P7) may be released.

23 to 28, the second program loop PL2 is performed using first data D_P1 and second data D_P2. Accordingly, among memory cells that are not program inhibited, the threshold voltages of the first to fourth program memory cells E_P1 to E_P4 and the sixth and seventh program memory cells E_P6 and E_P7 may increase.

Figure 29 shows another example of a program loop in memory cells according to the method of Figure 23. In FIG. 29, the horizontal axis indicates time (T), and the vertical axis indicates voltage (V) applied to data transmitted through input/output lines (DQ) and word lines connected to selected memory cells.

Compared to FIG. 26, the second verification voltage (VFY2) is applied in the second program loop (PL2) and the first verification voltage (VFY1) is not applied. For example, program and verification read of the second program loop PL2 may be performed using the second data D_P2.

Figure 30 shows an example of the threshold voltages of memory cells changing due to the program loops of Figure 29. In Figure 27, the horizontal axis indicates threshold voltages (Vth) of memory cells, and the vertical axis indicates the number of memory cells. As an example, an example in which the threshold voltages of the memory cells shown in FIG. 27 are programmed by the second program loop PL2 of FIG. 29 is shown in FIG. 30 .

Compared to FIG. 27, in the second program loop, programming is performed on the second, third, sixth, and seventh program memory cells (E_P2, E_P3, E_P6, and E_P7) distinguished by the second data (D_P2). . During verification read of the second program loop (PL1), determine whether the threshold voltages of the second, third, sixth, and seventh program memory cells (E_P2, E_P3, E_P6, E_P7) are higher than the second verification voltage (VFY2). It can be. Memory cells determined to have a threshold voltage higher than the second verification voltage VFY2 during verification read may be program-inhibited.

Figure 31 shows another example of a program loop in memory cells according to the method of Figure 23. In FIG. 31, the horizontal axis indicates time (T), and the vertical axis indicates voltage (V) applied to data transmitted through input/output lines (DQ) and word lines connected to selected memory cells.

Compared to FIG. 26, the verification voltage is not applied in the first program loop (PL1) and the second program loop (PL2). That is, no verification is performed. Exemplarily, the first data D_P1 may identify relatively high program states, for example, the fourth, fifth, sixth, or seventh program states P4, P5, P6, or P7. In the first program loop PL1 and the second program loop PL2, threshold voltages of memory cells corresponding to relatively high program states are increased in advance. Accordingly, since the amount of change in the threshold voltages of memory cells decreases in subsequent program loops, the stress applied to the memory cells is reduced and the reliability of the memory cells is improved. Since memory cells corresponding to relatively high program states are programmed in the first program loop PL1 and the second program loop PL2, overprogramming of memory cells at a level higher than the verification voltage does not occur.

FIG. 32 shows another example of a program loop progressing in memory cells according to the method of FIG. 23. In FIG. 32, the horizontal axis indicates time (T), and the vertical axis indicates voltage (V) applied to data transmitted through input/output lines (DQ) and word lines connected to selected memory cells.

Compared to FIG. 26, verification is not performed in the first program loop (PL1). The first data (D_P1) may identify relatively high program states, for example, the fourth, fifth, sixth, or seventh program state (P4, P5, P6, or P7). In the first program loop PL1, preprogramming may be performed on memory cells corresponding to relatively high program states. In the second program loop (PL2), the first verification voltage (VFY1) is applied. Exemplarily, the second data (D_P2) can distinguish between the erase state (E) and the lowest first program state (P1). Accordingly, the second data (D_P2) can support verification using the first verification voltage (VFY1).

Figure 33 is a circuit diagram showing a memory block (BLKa) according to an embodiment of the present invention. Referring to FIG. 33, the memory block BLKa includes a plurality of cell strings CS11 to CS21 and CS12 to CS22. A plurality of cell strings CS11 to CS21 and CS12 to CS22 may be arranged along a row direction and a column direction to form rows and columns.

For example, the cell strings CS11 and CS12 arranged along the row direction form the first row, and the cell strings CS21 and CS22 arranged along the row direction form the first row. Can form 2 rows. Cell strings CS11 and CS21 arranged along the column direction form a first column, and cell strings CS12 and CS22 arranged along the column direction form a second row. can do.

Each cell string may include a plurality of cell transistors. The plurality of cell transistors include ground selection transistors (GST), memory cells (MC1 to MC6), and string selection transistors (SSTa and SSTb). The ground selection transistor (GST) of each cell string, the memory cells (MC1 to MC6), and the string selection transistors (SSTa and SSTb) are arranged along the rows and columns of the cell strings (CS11 to CS21, CS12 to CS22). They may be stacked in a height direction perpendicular to a plane (eg, a plane on the substrate of the memory block BLKa).

The plurality of cell transistors may be charge trap type transistors having threshold voltages that vary depending on the amount of charge trapped in the insulating film.

Sources of the bottom ground select transistors (GST) may be commonly connected to the common source line (CSL).

Control gates of the ground selection transistors GST of the cell strings CS11 and CS12 in the first row are commonly connected to the ground selection line GSL1, and are connected to the ground of the cell strings CS21 and CS22 in the second row. Control gates of the selection transistors (GST) are commonly connected to the ground selection line (GSL2). That is, cell strings in different rows are connected to different ground selection lines.

As an example, the memory block BLKa may be changed so that ground selection transistors of different heights in the same row are connected to different ground selection lines. As an example, the memory block BLKa may be changed so that ground selection transistors connected to ground selection transistors of the same height in different rows are connected to each other and are controlled in common. As an example, the memory block BLKa may be changed so that ground selection lines connected to ground selection transistors are connected to each other and are commonly controlled.

Control gates of memory cells located at the same height (or order) from the substrate (or ground select transistors (GST)) are commonly connected to one word line, and control gates of memory cells located at different heights (or order) may be respectively connected to different word lines (WL1 to WL6). For example, the memory cells MC1 are commonly connected to the word line WL1. The memory cells MC2 are commonly connected to the word line WL2. The memory cells MC3 are commonly connected to the word line WL3. The memory cells MC4 are commonly connected to the word line WL4. The memory cells MC5 are commonly connected to the word line WL5. The memory cells MC6 are commonly connected to the word line WL6.

In the first string selection transistors SSTa of the same height (or order) of the plurality of cell strings CS11 to CS21 and CS12 to CS22, the control gates of the first string selection transistors SSTa in different rows are They are each connected to different string selection lines (SSL1a to SSL2a). For example, the first string selection transistors SSTa of the cell strings CS11 and CS12 are commonly connected to the string selection line SSL1a. The first string selection transistors SSTa of the cell strings CS21 and CS22 are commonly connected to the string selection line SSL2a.

In the second string selection transistors SSTb of the same height (or order) of the plurality of cell strings CS11 to CS21 and CS12 to CS22, the control gates of the second string selection transistors SSTb in different rows are They are each connected to different string selection lines (SSL1b to SSL2b). For example, the second string selection transistors SSTb of the cell strings CS11 and CS12 are commonly connected to the string selection line SSL1b. The second string selection transistors SSTb of the cell strings CS21 and CS22 are commonly connected to the string selection line SSL2b.

That is, cell strings in different rows are connected to different string selection lines. String selection transistors of the same height (or order) of cell strings in the same row are connected to the same string selection line. String selection transistors of different heights (or orders) of cell strings in the same row are connected to different string selection lines.

Exemplarily, string selection transistors of cell strings in the same row may be commonly connected to one string selection line. For example, the string selection transistors SSTa and SSTb of the cell strings CS11 and CS12 in the first row may be commonly connected to one string selection line. The string selection transistors SSTa and SSTb of the sal strings CS21 and CS22 in the second row may be commonly connected to one string selection line.

The columns of the plurality of cell strings (CS11 to CS21 and CS12 to CS22) are respectively connected to different bit lines (BL1 and BL2). For example, the string select transistors SSTb of the cell strings CS11 to CS21 in the first row are commonly connected to the bit line BL1. The string select transistors SST of the cell strings CS12 to CS22 in the second row are commonly connected to the bit line BL2.

The memory block BLKa may be characterized in that memory cells located at the same height from the substrate share a word line. In different memory blocks, word lines may be characterized as unshared. For example, a memory cell at a first height in a first memory block may share a word line with another memory cell at a first height in the first memory block. The memory cells at the first height of the first memory block may not share a word line with the memory cells at the first height of the second memory block. A subblock may be characterized as part of memory blocks (BLKa).

The cell strings CS11 and CS12 may form a first plane. The cell strings CS21 and CS22 may form a second plane.

In the memory block BLKa, memory cells at each height of each plane may form a physical page. A physical page may be a unit of writing and reading of memory cells (MC1 to MC6). For example, one plane of the memory block BLKa may be selected by the string selection lines SSL1a, SSL1b, SSL2a, and SSL2b. When the turn-on voltage is supplied to the string selection lines (SSL1a, SSL1b) and the turn-off voltage is supplied to the string selection lines (SSL2a, SSL2b), the cell strings (CS11, CS12) of the first plane are bit It is connected to lines BL1 and BL2. That is, the first plane is selected. When the turn-on voltage is supplied to the string selection lines (SSL2a, SSL2b) and the turn-off voltage is supplied to the string selection lines (SSL1a, SSL1B), the cell strings (CS21, CS22) of the second plane are bit It is connected to lines BL1 and BL2. That is, the second plane is selected. In the selected plane, one row of memory cells MC can be selected by word lines WL1 to WL6. In the selected row, a selection voltage may be applied to the second word line (WL2), and a non-selection voltage may be applied to the remaining word lines (WL1, WL3 to WL6). That is, by adjusting the voltages of the string selection lines (SSL1a, SSL1b, SSL2a, SSL2b) and word lines (WL1 to WL6), the physical page corresponding to the second word line (WL2) of the second plane can be selected. there is. Writing or reading may be performed in the memory cells MC2 of the selected physical page.

Two or more bits may be written into each of the memory cells MC. Bits written to each memory cell (MC) belonging to one physical page form logical pages. The first bit written into each of the memory cells (MC) belonging to one physical page forms the first logical page. The N-th bit written in each of the memory cells (MC) belonging to one physical page forms the N-th logical page. A logical page may be a unit of data access. When reading is performed on one physical page, data can be accessed in units of logical pages.

In the memory block BLKa, erasing of the memory cells MC1 to MC6 may be performed on a memory block basis or a sub-block basis. When erasing is performed on a memory block basis, all memory cells MC of the memory block BLKa may be simultaneously erased according to one erase request (eg, an erase request from an external controller). When performed in units of subblocks, some of the memory cells MC1 to MC6 of the memory block BLKa are simultaneously erased according to one erase request (for example, an erase request from an external controller), and some of the remaining memory cells MC1 to MC6 of the memory block BLKa are erased simultaneously. Erasure may be prohibited. A low voltage (e.g., ground voltage or a low voltage having a level similar to the ground voltage) is supplied to the word line connected to the memory cells MC to be erased, and the word line connected to the erase-inhibited memory cells MC may be floated. there is.

The memory block BLKa shown in FIG. 33 is exemplary. The technical idea of the present invention is not limited to the memory block BLKa shown in FIG. 33. For example, the number of rows of cell strings can be increased or decreased. As the number of rows of cell strings changes, the number of string selection lines or ground selection lines connected to the rows of cell strings, and the number of cell strings connected to one bit line may also change.

The number of rows of cell strings can be increased or decreased. As the number of columns of cell strings changes, the number of bit lines connected to the columns of cell strings and the number of cell strings connected to one string selection line may also change.

The height of cell strings can be increased or decreased. For example, the number of ground selection transistors, memory cells, or string selection transistors stacked on each of the cell strings may be increased or decreased.

By way of example, memory cells MC belonging to one physical page may correspond to at least three logical pages. For example, k bits (k is a positive integer greater than 2) can be programmed into one memory cell MC. In memory cells MC belonging to one physical page, k bits programmed in each memory cell MC may form k logical pages.

As described above, the memory block BLKa is provided as a three-dimensional memory array. A three-dimensional memory array may be formed monolithically on one or more physical levels of arrays of memory cells (MC) having an active area disposed over a silicon substrate and circuitry associated with the operation of the memory cells (MC). You can. Circuitry associated with the operation of the memory cells MC may be located within or on the substrate. Uniformly formed means that the layers of each level of the three-dimensional array are deposited directly on top of the layers of the lower level of the three-dimensional array.

As an example according to the technical spirit of the present invention, a three-dimensional memory array has a vertical orientation and includes vertical NAND strings (or cell strings) where at least one memory cell is located above another memory cell. At least one memory cell (MC) includes a charge capture layer. Each vertical NAND string further includes at least one select transistor located above the memory cells MC. At least one selection transistor has the same structure as the memory cells MC and is uniformly formed together with the memory cells MC.

A three-dimensional memory array is composed of a plurality of levels, and word lines or bit lines are shared between the levels in U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466, and U.S. Patent No. 8,654,587. It is disclosed in U.S. Patent Publication No. 8,559,235, and U.S. Patent Publication No. 2011/0233648, and is incorporated by reference in the present invention.

Referring again to FIG. 1 , the nonvolatile memory device 110 may perform a program operation, a read operation, and an erase operation under the control of the controller 120. The nonvolatile memory device 110 may receive commands and addresses from the controller 120 through an input/output channel. The nonvolatile memory device 110 may exchange data with the controller 120 through an input/output channel.

The nonvolatile memory device 110 may exchange control signals with the controller 120 through a control channel. For example, the non-volatile memory device 110 may include a chip enable signal (/CE) that selects at least one non-volatile memory chip among the plurality of non-volatile memory chips of the non-volatile memory device 110, and a controller 120. A command latch enable signal (CLE) indicating that the signal received through the input/output channel from the controller 120 is a command, an address latch enable signal (ALE) indicating that the signal received through the input/output channel from the controller 120 is an address, and the controller 120 when reading. A read enable signal (/RE) generated by 120 and toggled periodically and used for timing, and a write enable signal (/WE) activated by controller 120 when a command or address is transmitted. , the write protection signal (/WP), which is activated by the controller 120 to prevent unintentional writing or erasing when the power changes, is generated by the controller 120 during writing and is periodically toggled to close the input/output channel. A data strobe signal (DQS) used to synchronize data transmitted through the controller may be received from the controller 120. For example, the non-volatile memory device 110 is generated from the read enable signal (/RE) by the non-volatile memory device 110 in addition to the ready-busy signal (RnB) and is periodically toggled to sync the output of data. The data strobe signal (DQS) used to adjust can be output to the controller 120.

The non-volatile memory device 110 may include flash memory. However, the non-volatile memory device 110 is not limited to including flash memory. The non-volatile memory device 110 may include at least one of various non-volatile memory devices, such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FeRAM).

The controller 120 is configured to control the non-volatile memory device 110. For example, the controller 120 may control the non-volatile memory device 110 through an input/output channel and a control channel so that the non-volatile memory device 110 performs a program operation, a read operation, or an erase operation.

The controller 120 may control the nonvolatile memory device 110 according to the control of an external host device (not shown). For example, the controller 120 may communicate with an external host device according to a format different from the format used for communication with the non-volatile memory device 110. The unit of data communicated by the controller 120 with the non-volatile memory device 110 may be different from the unit of data communicated with an external host device.

The controller 120 may use RAM 130 as buffer memory, cache memory, or operation memory. The controller 120 may store data or code necessary to manage the non-volatile memory device 110 in the RAM 130. For example, the controller 120 may read data or code necessary to manage the non-volatile memory device 110 from the non-volatile memory device 110, load it into the RAM 130, and drive it.

RAM 130 includes dynamic RAM (DRAM), static RAM (SRAM), synchronous DRAM (SDRAM), phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FeRAM). It may include at least one of various random access memory devices.

The non-volatile memory device 110 may include a plurality of non-volatile memory chips. By way of example, the controller 120 and non-volatile memory chips may be connected to each other based on channels and ways. One channel may include one data channel and one control channel. One data channel may include eight input/output lines (DQ). One control channel includes the above-described chip enable signal (/CE), command latch enable signal (CLE), address latch enable signal (ALE), read enable signal (/RE), and write enable signal (/WE). ), a write protection signal (/WP), and a ready-busy signal (RnB).

Nonvolatile memory chips connected to one channel can form a way. When n nonvolatile memory chips are connected to one channel, an n-way can be formed. Nonvolatile memory chips belonging to one way have input/output lines (DQ), command latch enable signal (CLE), address latch enable signal (ALE), read enable signal (/RE), and write enable signal ( /WE), and control lines that transmit the write protection signal (/WP) can be shared. Each of the non-volatile memory chips belonging to one way can communicate with the controller 120 through dedicated control lines that transmit a chip enable signal (/CE) and a ready-busy signal (RnB).

The controller 120 can alternately access n-way nonvolatile memory chips connected to one channel. The controller 120 can independently access non-volatile memory chips connected to different channels. The controller 120 may alternately or simultaneously access non-volatile memory chips connected to different channels.

As an example, non-volatile memory chips may be connected to the controller 120 in a wide IO format. For example, nonvolatile memory chips connected to different channels may share the control line of one chip enable signal (/CE). Non-volatile memory chips that share the control line of one chip enable signal (/CE) can be accessed simultaneously. Because data lines of different channels are used simultaneously, a wide input/output bandwidth can be achieved.

The storage device 100 may include a solid state drive (SSD) or a hard disk drive (HDD). The storage device 100 includes a PC card (PCMCIA, personal computer memory card international association), compact flash card (CF), smart media card (SM, SMC), memory stick, multimedia card (MMC, RS-MMC, MMCmicro), It may include memory cards such as SD cards (SD, miniSD, microSD, SDHC), USB (Universal Serial Bus) memory cards, and Universal Flash Storage (UFS). The storage device 100 may include embedded memory such as embedded MultiMedia Card (eMMC), UFS, Perfect Page NAND (PPN), etc.

In FIG. 1 , the storage device 100 is shown as including RAM 130 disposed external to the controller 120 . However, the storage device 100 may not have RAM 130 disposed outside of the controller 120. The controller 120 may be configured to use the internal RAM (see FIG. 34) as a buffer memory, operation memory, or cache memory.

Figure 34 is a block diagram showing the controller 120 according to an embodiment of the present invention. 1 and 34, the controller 120 includes a bus 121, a processor 122, a RAM 123, an error correction block 124, a host interface 125, a buffer control circuit 126, and Includes a memory interface 127.

Bus 121 is configured to provide a channel between components of controller 120.

The processor 122 can control overall operations of the controller 120 and perform logical operations. The processor 122 communicates with an external host device through the host interface 125, with the non-volatile memory device 110 through the memory interface 127, and with the RAM (130) through the buffer control circuit 126. ) can communicate with. The processor 122 may control the storage device 100 using the RAM 123 as an operating memory, cache memory, or buffer memory.

RAM 123 may be used as an operating memory, cache memory, or buffer memory of the processor 122. RAM 123 may store codes and instructions that processor 122 executes. RAM 123 may store data processed by processor 122. RAM 123 may include SRAM (Static RAM).

The error correction block 124 may perform error correction. The error correction block 124 may perform error correction encoding based on data to be written to the non-volatile memory device 110 through the memory interface 127. Error correction encoded data may be transmitted to the non-volatile memory device 110 through the memory interface 127. The error correction block 124 may perform error correction decoding on data received from the nonvolatile memory device 110 through the memory interface 127. By way of example, the error correction block 124 may be included in the memory interface 127 as a component of the memory interface 127 .

The host interface 125 is configured to communicate with an external host device under the control of the processor 122. The host interface 125 includes USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), and PCIe. (PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered) DIMM), LRDIMM (Load Reduced DIMM), etc. may be configured to communicate using at least one of various communication methods.

The buffer control circuit 126 is configured to control the RAM 130 under the control of the processor 122.

The memory interface 127 is configured to communicate with the non-volatile memory device 110 under the control of the processor 122. As described with reference to FIG. 1 , the memory interface 127 may communicate commands, addresses, and data with the non-volatile memory device 110 through an input/output channel. The memory interface 127 may communicate control signals with the non-volatile memory device 110 through a control channel.

The memory interface 127 may include a program control unit (PCU2) according to an embodiment of the present invention. The program control unit (PCU) may control the timing of transmitting commands, addresses, or data to the non-volatile memory device 110 during program operations. For example, the program control unit (PCU) may be configured to transmit sequences to the non-volatile memory device 110 as shown in FIGS. 5, 6, or 17.

For example, if the RAM 130 is not provided to the storage device 100, the buffer control circuit 126 may not be provided to the controller 120.

By way of example, the processor 122 may control the controller 120 using codes. The processor 122 may load codes from a non-volatile memory device (eg, Read Only Memory) provided inside the controller 120. As another example, the processor 122 may load codes from the non-volatile memory device 110 through the memory interface 127.

By way of example, the bus 121 of the controller 120 may be divided into a control bus and a data bus. The data bus may be configured to transmit data within the controller 120, and the control bus may be configured to transmit control information such as commands and addresses within the controller 120. The data bus and control bus are separated from each other and may not interfere with or affect each other. The data bus may be connected to the host interface 125, buffer control circuit 126, error correction block 124, and memory interface 127. The control bus may be connected to the host interface 125, processor 122, buffer control circuit 126, RAM 123, and memory interface 127.

Figure 35 is a block diagram showing a computing device 1000 according to an embodiment of the present invention. Referring to FIG. 35, the computing device 1000 includes a processor 1100, a memory 1200, a storage device 1300, a modem 1400, and a user interface 1500.

The processor 1100 can control overall operations of the computing device 1000 and perform logical operations. The processor 1100 may be a hardware-based data processing device that includes a circuit physically configured to execute operations expressed as instructions included in code or a program. For example, the processor 1100 may be configured as a system-on-chip (SoC). Processor 1100 may be a general-purpose processor, special-purpose processor, or application processor.

RAM 1200 may communicate with processor 1100. RAM 1200 may be the processor 1100 or the main memory of the computing device 1000. The processor 1100 may temporarily store code or data in the RAM 1200. The processor 1100 can execute code and process data using the RAM 1200. The processor 1100 can execute various software such as an operating system and applications using RAM 1200. The processor 1100 may control overall operations of the computing device 1000 using the RAM 1200. RAM 1200 is volatile memory such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), or Phase-change RAM (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), FeRAM ( It may include non-volatile memory devices such as ferroelectric RAM).

The storage device 1300 may communicate with the processor 1100. The storage device 1300 may store data that must be preserved for a long period of time. That is, the processor 1100 may store data that must be preserved for a long period of time in the storage device 1300. The storage device 1300 may store a boot image for driving the computing device 1000. The storage device 1300 can store source codes of various software such as operating systems and applications. The storage device 1300 can store data processed by various software such as an operating system and applications.

By way of example, the processor 1100 loads source codes stored in the storage device 1300 into the RAM 1200 and executes the codes loaded into the RAM 1200, thereby driving various software such as an operating system and applications. there is. The processor 1100 may load data stored in the storage device 1300 into the RAM 1200 and process the data loaded into the RAM 1200. The processor 1100 may store data to be preserved for a long period of time among the data stored in the RAM 1200 in the storage device 1300.

The storage device 1300 may include a non-volatile memory device such as flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

The modem 1400 can communicate with an external device under the control of the processor 1100. For example, the modem 1400 may perform wired or wireless communication with an external device. The modem 140 supports LTE (Long Term Evolution), WiMax, GSM (Global System for Mobile communication), CDMA (Code Division Multiple Access), Bluetooth, NFC (Near Field Communication), and WiFi. , various wireless communication methods such as RFID (Radio Frequency IDentification), USB (Universal Serial Bus), SATA (Serial AT Attachment), HSIC (High Speed Interchip), SCSI (Small Computer System Interface), and Firewire. , PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), SDIO, UART (Universal Asynchronous Receiver Transmitter), SPI (Serial Peripheral Interface) , HS-SPI (High Speed SPI), RS232, I2C (Inter-integrated Circuit), HS-I2C, I2S, (Integrated-interchip Sound), S/PDIF (Sony/Philips Digital Interface), MMC (MultiMedia Card), Communication may be performed based on at least one of various wired communication methods, such as eMMC (embedded MMC).

The user interface 1500 may communicate with the user under the control of the processor 1100. For example, the user interface 1500 may include user input interfaces such as a keyboard, keypad, button, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, etc. The user interface 150 may include user output interfaces such as a Liquid Crystal Display (LCD), Organic Light Emitting Diode (OLED) display, Active Matrix OLED (AMOLED) display, LED, speaker, motor, etc.

The storage device 1300 may include at least one of the storage devices 100, 200, and 300 according to an embodiment of the present invention. Processor 1100, RAM 1200, modem 1400, and user interface 1500 may form a host device that communicates with storage device 1300.

In the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope and technical spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims and equivalents of this invention as well as the claims described later.

100; storage device 110; non-volatile memory device
111; memory cell array 113; row decoder circuit
115; page buffer circuit 117; data input/output circuit
119; Control logic circuit PCU1; program control unit
120; controller 121; bus
122; processor 123; random access memory
124; error correction block 125; host interface
126; buffer control circuit 127; memory interface
PCU2; Program control unit 130; Random access memory (RAM)
1000; computing device 1100; processor
1200; random access memory 1300; storage device
1400; modem 1500; user interface

Claims (20)

A non-volatile memory device including a plurality of physical pages; and
During a program operation on a selected physical page among the plurality of physical pages, first data, an address, and a first command are transmitted to the non-volatile memory device, and after transmitting the first command, the non-volatile memory device A controller configured to further transmit at least one data to,
The nonvolatile memory device starts a program operation of the selected physical page based on the first data in response to the first command, and as the at least one data is further transmitted, the first data and the at least one data configured to continue the program operation for the selected physical page based on
The controller is configured to transmit second data including the at least one data, the address, and a second command to the non-volatile memory device after transmitting the first data, the address, and the first command, and
The nonvolatile memory device is configured to continue the program operation for the selected physical page based on the first data and the second data in response to the second command,
the controller is configured to transmit third data, the address, and a third command to the non-volatile memory device after transmitting the second data, the address, and the second command, and
The nonvolatile memory device is configured to continue the program operation for the selected physical page using the first data, the second data, and the third data in response to the third command,
While the second data, the address, and the second command are received, the nonvolatile memory device is configured to apply a program voltage of a first program loop to memory cells of the selected physical page corresponding to the address. Device. According to claim 1,
The first data is programmed as first bits in the memory cells of the selected physical page of the nonvolatile memory device corresponding to the address, and the second data is programmed as second bits in the memory cells of the selected physical page. and the third data is programmed as third bits in the memory cells of the selected physical page. According to claim 1,
When the program voltage of the first program loop is applied, the non-volatile memory device is configured to distinguish a program target and a program inhibit target among memory cells of the selected physical page using the first data. According to claim 1,
While receiving the second data, the address, and the second command, the non-volatile memory device is configured to perform a verify read of the first program loop on memory cells of the selected physical page. According to clause 4,
The storage device wherein the verification read of the first program loop is performed using the verification voltage associated with the program state having the lowest threshold voltage distribution range. According to clause 4,
After the second data, the address, and the second command are received, the nonvolatile memory device determines whether an additional program is prohibited based on at least one of the first data and the second data with respect to the result of the verify read. Select the storage device that is configured to perform the dump. According to claim 1,
After receiving the second data, the address, and the second command, the nonvolatile memory device is configured to perform a pass-fail check of the first program loop on memory cells of the selected physical page. According to claim 1,
While the third data, the address, and the third command are received, the nonvolatile memory device is configured to apply a program voltage of a second program loop to memory cells of the selected physical page corresponding to the address. Device. According to clause 8,
When the program voltage of the second program loop is applied, the nonvolatile memory device selects a program target and a program inhibit target among memory cells of the selected physical page using at least one of the first data and the second data. A storage device configured to differentiate. According to clause 8,
While the third data, the address, and the third command are received, the nonvolatile memory device is configured to perform a verify read of the second program loop on memory cells of the selected physical page. According to claim 10,
The verify read of the second program loop uses at least one of a first verify voltage associated with the program state having the lowest threshold voltage distribution range and a second verify voltage associated with the program state having the second lowest threshold voltage distribution range. Storage device performed by. According to claim 10,
After the third data, the address, and the third command are received, the nonvolatile memory device determines an additional program based on the first data, the second data, and the third data for the result of the verify read. A storage device configured to perform a dump that selects prohibited targets. According to clause 8,
After the third data, the address, and the third command are received, the nonvolatile memory device is configured to perform a pass-fail check of the second program loop on memory cells of the selected physical page. According to clause 8,
A storage device in which the first program loop and the second program loop are performed without verification. According to clause 8,
The storage device wherein the first program loop is performed without verification, and the second program loop includes verification using a verification voltage associated with the lowest threshold voltage distribution range. A non-volatile memory device including a plurality of physical pages; and
During a program operation on a selected physical page among the plurality of physical pages, first data, an address, and a first command are transmitted to the non-volatile memory device, and after transmitting the first command, the non-volatile memory device A controller configured to further transmit at least one data to,
The nonvolatile memory device starts a program operation of the selected physical page based on the first data in response to the first command, and as the at least one data is further transmitted, the first data and the at least one data configured to continue the program operation for the selected physical page based on
The controller is configured to transmit second data including the at least one data, the address, and a second command to the non-volatile memory device after transmitting the first data, the address, and the first command,
The nonvolatile memory device is configured to continue the program operation for the selected physical page based on the first data and the second data in response to the second command,
After the program operation starts, the nonvolatile memory device sets up bit lines connected to the plurality of physical pages based on the first data, and
The non-volatile memory device is configured to set up the bit lines based on the first data and the second data after the second data is received. a memory cell array including a plurality of physical pages each including a plurality of memory cells;
a page buffer circuit connected to the plurality of physical pages through bit lines and configured to load data received from an external device; and
A row decoder circuit connected to the plurality of physical pages through word lines and configured to perform a program operation on memory cells of a physical page selected from among the plurality of physical pages according to data loaded into the page buffer circuit. Contains,
As the first data is loaded into the page buffer circuit in response to receiving the first command, address, and first data from an external device, the row decoder circuit and the page buffer circuit perform a program operation of the selected physical page. is configured to start, and
The second command, the address, and the second data are received from the external device, and the second data and the third data are stored in the page buffer circuit in response to receiving the third command, the address, and the third data. As additional loading is sequentially performed, the row decoder circuit and the page buffer circuit sequentially update the program operation of the selected physical page based on the first data, the second data, and the third data and continue. It is configured to
After the program operation starts, the page buffer circuit sets up the bit lines based on the first data,
After the second data is received, the page buffer circuit sets up the bit lines based on the first data and the second data, and
After the third data is received, the page buffer circuit is configured to set up the bit lines based on the first data, the second data, and the third data. In a programming method for programming data in a non-volatile memory device including a plurality of physical pages:
Transmitting a first command, an address, and first data to the nonvolatile memory device, setting up bit lines connected to the plurality of physical pages based on the first data, and selecting a physical page selected from the plurality of physical pages starting the program operation of the page;
transmitting a second command, the address, and second data to the nonvolatile memory device to set up the bit lines based on the first data and the second data, and update the program operation of the selected physical page; , and continuing the program operation of the selected physical page; and
Transmitting a third command, the address, and third data to the nonvolatile memory device to set up the bit lines based on the first data, the second data, and the third data, and set up the bit lines of the selected physical page. Further updating a program operation, and continuing the program operation of the selected physical page. delete delete

Images