Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention. .
1 is a block diagram illustrating a computing device 1000 in accordance with an embodiment of the present invention. 1, a computing device 1000 includes a processor 1100, a fast storage device 1200, a chipset 1300, a graphics processor 1400, a display device 1500, an input / output device 1600, (1700).
The processor 1100 may control all operations of the computing device 1000 and may perform logical operations. The processor 1100 may operate an operating system (OS) and applications. The processor 1100 may be a central processing unit (CPU) or an application processor (AP).
The fast storage device 1200 is configured to communicate with the processor 1100 via a high speed interface 1230. The high-speed interface 1200 may include the main memory 1210 and the storage device 100. [ The main memory 1210 can be used as an operation memory of the processor 1100. The main memory 1210 may include a DRAM, more specifically, a double data rate (DDR) SDRAM (Synchronous Dynamic Random Access Memory). The main memory 1210 may be configured to operate based on a specification of a Dual In-line Memory Module (DIMM), more specifically a Registered DIMM (RDIMM) or a Load Reduced DIMM (LRDIMM). The high speed interface 1230 may include a DIMM interface defined by a DIMM specification.
The storage device 100 may be coupled to the processor 1100 via a high speed interface 1230, for example, a DIMM interface, similar to the main memory 1210. The storage device 100 may include non-volatile memories such as Flash memory, Phase-change Random Access Memory (PRAM), Resistive RAM (RRAM), Magnetic RAM (MRAM), Ferroelectric RAM (FeRAM) The storage device 100 may be configured to operate based on a specification of a DIMM, more specifically an RDIMM or an LRDIMM.
The chipset 1300 is configured to arbitrate the connection between the processor 1100 and other devices under the control of the processor 1100. For example, the chipset 1300 may include a south bridge. In addition, the chipset 1300 may include various devices such as a sound processor, an Ethernet adapter, and the like.
The graphics processor 1400 is configured to perform image processing and to display an image through the display device 1500. Graphics processor 1400 may be a graphics processing unit (GPU). Illustratively, the graphics processor 1400 may be included within the chipset 1300.
The display device 1500 is configured to output an image under the control of the graphics processor 1400. For example, the display device 1500 may include a liquid crystal display (LCD) device, a light emitting diode (LED) display device, a beam projector, and the like.
The input / output device 1600 may include an input device that receives a signal from a user of the computing device 1000 and an output device that outputs a signal to the user. For example, the input / output device 1600 may include an input device such as a keyboard, a mouse, a microphone, a touch pad, a touch panel, etc., and an output device such as a speaker, lamp, printer,
The storage device 1700 is configured to operate in accordance with control of the chipset 1300. The storage device 1700 may be any of various types of storage devices such as Serial AT Attachment (SATA), Universal Serial Bus (USB), Universal Flash Storage (UFS), Peripheral Component Interconnect (PCI), PCI Express, NVMexpress, Small Computer System Interface SCSI), and the like.
The communication speed (e.g., the communication speed with the processor 1100) of the storage device 100 directly connected to the processor 1100 through the high-speed interface 1230 is determined by the communication speed of the storage device 1700 connected to the chipset 1300 (E.g., the communication speed with the chipset 1300). Accordingly, when the storage device 100 connected to the processor 1100 through the high-speed interface 1230 is provided, the operational performance of the computing device 1000 is improved.
2 is a block diagram illustrating a storage device 100 according to an embodiment of the present invention. 1 and 2, a storage device 100 includes data buffers 110, a device controller 120, nonvolatile memories 130 or NVM, a buffer memory 140, and SPDs 150, Presence Detect).
Data buffers 110 may receive data signals DQ and data strobe signals DQS from processor 1100 via high speed interface 1230. [ The data buffers 110 may be configured in a manner determined by the DDR4 LRDIMM specification. For example, the storage device 100 may be provided with nine data buffers 110. Each of the data buffers 110 may communicate eight data signals DQ and two data strobe signals DQS to an external device, e.g., the processor 1100. Data buffers 110 may communicate data signals DQ and data strobe signals DQS to device controller 120. [
The device controller 120 receives the data signals DQ and data strobe signals DQS from the data buffers 110. [ The device controller 120 can receive the RAM command CMD_R, the RAM address ADDR_R and the clock CK from the processor 1100 via the high speed interface 1230. [
The RAM command CMD_R may be a command requesting access to the RAM 123 inside the device controller 120. [ The RAM address ADDR_R may be an address belonging to the address range of the RAM 123. [ The device controller 120 transfers data received in the data signals DQ of the high-speed interface 1230 to the RAM 123 (RAM) in response to the RAM command CMD_R and the RAM address ADDR_R received via the high- ). The device controller 120 transmits the data stored in the RAM 123 to the data signals DQ of the high speed interface 1230 in response to the RAM command CMD_R and the RAM address ADDR_R received via the high- . That is, the physical layer of the processor 1100 can identify that the RAM 123 of the storage device 100 is connected to the high-speed interface 1230. The physical layer of the processor 1100 can access the RAM 123 using the RAM command CMD_R and the RAM address ADDR_R.
The device controller 120 can detect the storage command CMD_S and the storage address ADDR_S for the nonvolatile memory 130 from the data stored in the RAM 123. [ In response to the storage command CMD_S and the storage address ADDR_S, the device controller 120 can write write data (DATA_W) among the data stored in the RAM 123 into the nonvolatile memories 130. In response to the storage command CMD_S and the storage address ADDR_S, the device controller 120 can read data from the non-volatile memories 130 and store the read data (DATA_R) in the RAM 123. That is, the device driver of the upper layer of the physical layer of the processor 1100, for example, the processor 1100, can identify the non-volatile memories 130 connected to the high-speed interface 1230 via the RAM 123 . The device driver of the processor 1100 may store the storage command CMD_S for the non-volatile memories 130, the storage address ADDR_S and the data to the storage device 100 via the data signals DQ of the high- Lt; / RTI >
The device controller 120 may send the buffer command CMD_B to the data buffers 110. [ For example, the device controller 120 can output the buffer command CMD_B itself in response to the RAM command CMD_R or the RAM address ADDR_R, or without the RAM command CMD_R and the RAM address ADDR_R . The buffer command CMD_B may be communicated to the data buffers 110 in common.
The device controller 120 is configured to control the buffer memory 140 and to communicate with the buffer memory 140. The buffer memory 140 may include a random access memory such as DRAM, SRAM, PRAM, MRAM, RRAM, FeRAM, and the like. The device controller 140 may load the metadata for managing the non-volatile memories 130 into the buffer memory 140. For example, the device controller 120 may include a mapping table including mapping information between logical addresses assigned to the non-volatile memories 130 by the processor 1100 and physical addresses of the non-volatile memories 130, Can be loaded into the buffer memory 140. The device controller 120 may read the mapping table from the non-volatile memories 130 and load the read mapping table into the buffer memory 140. [ Illustratively, the buffer memory 140 may be provided within the device controller 123.
SPD 150 is configured to communicate with processor 1100 via supplemental signals (SS) of high speed interface 1230. In addition, the SPD 150 is configured to communicate with the device controller 120 via the auxiliary signals SBS. The auxiliary signals SBS may include Serial Peripheral Interface (SPI) signals, Inter-Integrated Circuit (I2C) signals, Universal Asynchronous Receiver / Transmitter (UART) signals, and the like. For example, the SPD 150 may store information about physical characteristics, logical characteristics, driving characteristics, and the like of the storage device 100. The information stored in the SPD 150 may be read by the processor 1100 via the auxiliary signals SBS of the high speed interface 1230 when the computing device 1000 is powered on.
3 is a block diagram illustrating a device controller 120 in accordance with an embodiment of the present invention. Referring to Figures 1, 2 and 3, the device controller 120 includes a physical layer circuit 121 or PHY and a controller 124. [
The physical layer circuit 121 is configured to support the communication method specified by the specification of the high speed interface 1230. [ For example, the physical layer circuit 121 is configured to support a communication method defined by a specification of a DIMM, more specifically an RDIMM or an LRDIMM. The physical layer circuit 121 includes a RAM controller 122 and a RAM 123. [
The RAM controller 122 is configured to receive the RAM command CMD_R, the RAM address ADDR_R and the clock CK via the high speed interface 1230. [ Based on the RAM command (CMD_R), the RAM address (ADDR_R) and the clock (CK), the RAM controller (122) can control the RAM (123). For example, the RAM controller 122 may interpret the request of the processor 1100 based on the RAM command CMD_R and the RAM address ADDR_R. The RAM controller 122 may control the RAM 123 to communicate the data signals DQ and the data strobe signals DQS to the processor 1100. [
The RAM 123 can communicate data signals DQ and data strobe signals DQS with the processor 1100 via the high speed interface 1230 under the control of the RAM controller 122. [ Illustratively, high speed interface 1230 may have a signaling scheme based on a first type of memory, e.g., SDRAM. RAM 123 may have a signaling scheme based on a second type of memory, e.g., SRAM. Therefore, the RAM 123 does not directly receive the RAM command CMD_R, the RAM address ADDR_R, and the clock CK from the processor 1100 through the high-speed interface 1230 but under the control of the RAM controller 122 And may communicate the data signals DQ and data strobe signals DQS with the processor 1100.
Illustratively, the storage space of the RAM 123 may be divided into a command area CA, a writing area WA, a reading area RA, and a state area SA.
The storage command CMD_S and the storage address ADDR_S stored in the RAM 123 as the data signals DQ from the processor 1100 can be written in the command area CA. The write data DATA_W stored in the RAM 123 as the data signals DQ from the processor 1100 can be written to the write area WA. The read data (DATA_R) read from the RAM 123 as the data signals DQ by the processor 1100 can be read from the read area RA. The status information STI communicated by the processor 1100 to the RAM 123 as the data signals DQ may be communicated in the status area SA. The status information (STI) may indicate information about the operating state of the processor 1100 or the storage device 100. [
The controller 124 may communicate with the non-volatile memories 130 via the first interface 125 and the buffer memory 140 via the second interface 126. For example, the first interface 125 may include a communication interface of a NAND flash memory, PRAM, MRAM, RRAM, or FeRAM. The second interface 126 may include a communication interface of the SDRAM.
The controller 124 descrambles or error-corrects and decodes the storage command CMD_S and the storage address ADDR_S stored in the command area CA of the RAM 123 and supplies the descrambled or error correction decoded data to the nonvolatile memories 130). The controller 124 may transmit the write data DATA_W stored in the write area WA of the RAM 123 to the nonvolatile memories 130 through the first interface 125. [ The controller 124 can write the data (DATA_R) read from the nonvolatile memories 130 to the read area RA of the RAM 123. [ The controller 124 stores various information such as processing information of a write or read operation on the nonvolatile memories 130 and information on the operation state of the storage device 100 in the status area SA of the RAM 123 Information (STI). In addition, the controller 124 can read various status information (STI) written in the status area SA of the RAM 123 via the high-speed interface 1230.
The physical layer circuit 121 may be configured to output the buffer command CMD_B to the data buffers 110. For example, the physical layer circuit 121 may be configured to output the buffer command CMD_B in accordance with the RAM command CMD_R or the RAM address ADDR_R.
Illustratively, the controller 124 may provide the storage command CMD_S, the storage address ADDR_S, the write data DATA_W, and the read data DATA_R to the non-volatile memories 130 ). ≪ / RTI > The storage command CMD_S, the storage address ADDR_S, the write data DATA_W, and the read data DATA_R can be communicated via common input / output lines. The controller 124 may further communicate control signals used to control the non-volatile memories 130 via the first interface 125 with the non-volatile memories 130. The control signals can be communicated via the control lines separate from the input / output lines.
For example, the controller 124 controls the chip enable signal / CE to select at least one nonvolatile memory chip among the nonvolatile memories 130, the signal transmitted to the input / output signals is the storage command CMD_S An address latch enable signal (ALE) indicating a signal transmitted to the input / output signals as a storage address (ADDR_S), a read latch signal (ALE) periodically being toggled at the time of reading and used for timing A write enable signal / WE that is activated when a command or an address is transmitted, a write protect signal / WP that is activated to prevent unintended write or erase when power is changed, To the non-volatile memories 130, a data strobe signal DQS that is periodically toggled at the time of writing and used to align the write data (DATA_W). The controller 124 also includes a Ready and Busy signal R / nB indicating whether the non-volatile memories 130 are performing a program, erase or read operation, a read enable signal / RE and periodically toggled to receive the data strobe signal DQS used to match the sync of the read data DATA_R from the non-volatile memories 130.
The controller 124 includes a stream buffer 127. The processor 1100 can assign a stream identifier (SID) to the write data in accordance with the characteristics of the write data (DATA_W) in the nonvolatile memories 130. [ The processor 1100 can write the write data DATA_W and the stream identifier SID to the write area WA of the RAM 123 via the high speed interface 1230. [ The controller 124 can read the write data (DATA_W) and the stream identifier (SID) from the write area WA of the RAM 123. [ The controller 124 can store the write data (DATA_W) in the stream buffer 127 and manage it according to the stream identifier (SID).
The controller 124 may write the write data (DATA_W) having the same stream identifier (SID) to the same memory block of the non-volatile memories 130. [ The controller 124 may program the write data (DATA_W) with different stream identifiers (SID) into different memory blocks of the non-volatile memories 130. For example, the non-volatile memories 130 may include NAND flash memories, and the memory blocks may be erase units of NAND flash memories.
The same stream identifier (SID) is allocated to write data (DATA_W) having similar characteristics, and a different stream identifier (SID) is assigned to write data (DATA_W) having different characteristics. Therefore, write data (DATA_W) having similar characteristics is programmed in the same memory block, and write data (DATA_W) having different characteristics are programmed in different memory blocks. Therefore, the management performance of the write data (DATA_W) programmed in the nonvolatile memories 130 is improved.
The controller 124 may manage the data groups according to the stream identifiers. The write data (DATA_W) received together with the first stream identifier may be managed as a data group corresponding to the first stream identifier. The write data (DATA_W) received together with the Kth stream identifier may be managed as a data group corresponding to the Kth stream identifier. The controller 124 can accumulate the write data (DATA_W) in the stream buffer 127 until the capacity of the data group corresponding to at least one stream identifier reaches the threshold capacity. When the capacity of the data group corresponding to at least one stream identifier reaches the critical capacity, the controller 124 can write the data of the corresponding data group to the nonvolatile memories 130. For example, the critical capacity may be determined according to the operating characteristics of the non-volatile memories 130 and the characteristics of the inter-operation between the non-volatile memories 130 and the device controller 120. For example, the threshold capacity may be 64 KB.
4 is a flowchart showing how the storage apparatus 100 according to the embodiment of the present invention accesses the non-volatile memories 130 by using the stream buffer 127. FIG. Referring to FIGS. 1 to 4, in step S110, the storage device 100 may trigger a read operation to the non-volatile memory 130. FIG. For example, the device controller 120 may trigger a read operation in response to a request from the processor 1100 or according to a schedule occurring internally. For example, the controller 124 may control the garbage collection, read reclaim, bad block management, or wear leveling of the non-volatile memories 130 As a part, the read operation can be triggered.
For example, garbage collection may occur when valid data and invalid data are scattered in the memory blocks of each of the non-volatile memories 130. [ When garbage collection is performed, the valid data of the source memory block may be migrated or copied to the target memory block, and the source memory block may be erased or invalidated. That is, the garbage collection may include a read operation from the source memory block and a write operation to the target memory block. The target memory block does not store data and may be a free block with an erase state.
The read reclaim may occur when a read error is detected in the memory blocks of each of the non-volatile memories 130. [ When the number of error bits is more than the threshold value in the read operation, the memory block in which the read operation is performed is selected as the source memory block. When read reclaim is performed, data or valid data in the source memory block may be migrated or copied to the target memory block, and the source memory block may be erased or invalidated. That is, the read reclaim may include a read operation from the source memory block and a write operation to the target memory block. The target memory block does not store data and may be a free block with an erase state.
Bad block management may occur when a bad block is detected in the memory blocks of each of the non-volatile memories 130. [ If an error occurs during the write operation, the memory block in which the error occurred is selected as the source memory block. The data or valid data of the source memory block is migrated or copied to the target memory block, and the source memory block is set as the bad block. That is, the bad block management may include a read operation from the source memory block. The target memory block does not store data and may be a free block with an erase state.
Wear leveling may occur when there is a difference between the erase counts of bad blocks in the memory blocks of each of the non-volatile memories 130. [ If the difference between the erase counts between the first and second memory blocks is greater than or equal to the threshold value, the data or valid data in the first memory block and the data or valid data in the second memory block are swapped or swapped . That is, wear leveling may include read operations from the first and second memory blocks and write operations to the first and second memory blocks.
In step S220, the controller 124 determines whether the stream buffer 127 has free capacity. If there is a free capacity in the stream buffer 127 or if the free capacity of the stream buffer 127 is greater than or equal to the size of the data to be read by the read operation, step S160 is performed. If the free capacity of the stream buffer 127 does not exist, or if the free capacity of the stream buffer 127 is smaller than the size of the data to be read by the read operation, step S130 is performed.
In step S130, the device controller 124 triggers a flush operation. For example, the flush operation may include writing data stored in the stream buffer 127 to the non-volatile memories 130. For example, when the flush operation is performed, data of a data group that does not reach the critical capacity among the data groups stored in the stream buffer 127 can be programmed into the nonvolatile memories 130. [
In step S140, the controller 124 determines whether the object of the flush operation matches the object of the read operation. For example, it can be determined whether the first non-volatile memory to be executed in the flush operation among the non-volatile memories 130 matches the second non-volatile memory to be read. If the subject of the flush operation does not match the subject of the read operation, step S150 is performed. In step S150, the controller 124 performs a flush operation. Thereafter, in step S160, a read operation is performed.
If the object of the flush operation coincides with the object of the read operation, the read operation is canceled in step S170. In step S180, a flush operation is performed. Thereafter, step S110 is performed again.
That is, the controller 124 may trigger a read operation to the first of the non-volatile memories 130 (step S110). The read operation may be triggered on demand by the processor 1100 or according to an internal schedule such as garbage collection, read reclaim, bad block management, and wear leveling.
If the free capacity of the stream buffer 127 is sufficient, a read operation is performed (steps S120 and S160). If the free capacity of the stream buffer 127 is not sufficient, a flush operation is triggered (steps S120 and S130).
If the object of the flush operation does not match the object of the read operation, the controller 124 performs a flush operation to secure the free capacity of the stream buffer 127, and then performs a read operation (steps S140 to S160).
If the object of the flush operation matches the object of the read operation, a deadlock may occur. For example, in order for the controller 124 to perform a read operation from the nonvolatile memory, the controller 124 must perform a flush operation on the nonvolatile memory. However, since the read operation for the nonvolatile memory is triggered, the flush operation can not be performed. The storage device 100 according to the embodiment of the present invention cancels the read operation and performs the flush operation when the object of the flush operation and the object of the read operation match (S140, S170, and S180). Thereafter, the read operation is triggered again (step S110). Therefore, deadlock is prevented from occurring in the storage apparatus 100. [ The occurrence of a deadlock in the storage apparatus 100 is prevented even when a free capacity of the stream buffer 127 does not exist so that the operation of the stream buffer 127 can be performed while maintaining the operation performance and reliability of the storage apparatus 100. [ Can be reduced in size. Thus, the manufacturing cost of the storage device 100 is reduced.
5 to 8 are diagrams for explaining a process of the storage device 100 performing a read operation and a flush operation. In Figures 5-8, some configurations of the controller 124 are shown. Illustratively, portions of controller 124 associated with non-volatile memories 130 are shown in Figures 5-8.
5, the controller 124 includes an interconnect INT, a stream buffer 127, non-volatile memory managers 128_1 through 128_N, and a processor core 129. [
The interconnect INT may provide a channel between the components of the controller 124.
The stream buffer 127 can manage write data (DATA_W) received from the processor 1100 (see FIG. 1) according to stream identifiers (SID). Illustratively, it is assumed that the stream buffer 127 manages write data (DATA_W) according to the first to fifth stream identifiers SID1 to SID5.
The non-volatile memory managers 128_1 to 128_N may correspond to the non-volatile memories 130, respectively. A single non-volatile memory manager 128 may control one non-volatile memory 130 via the first interface 125. [ One non-volatile memory 130 may include non-volatile memory chips. One nonvolatile memory manager 128 is connected to the nonvolatile memory chips of one nonvolatile memory 130 via the first interface 125 with a command latch enable signal CLE, an address latch enable signal ALE, The read enable signal / RE, the write enable signal / WE, and the write protection signal / WP can be transmitted in common. One nonvolatile memory manager 128 commonly communicates data strobe signals DQS and data signals DQ with the nonvolatile memory chips of one nonvolatile memory 130 via the first interface 125 . One nonvolatile memory manager 128 may transmit chip enable signals / CE to the nonvolatile memory chips of one nonvolatile memory 130 via the first interface 125, respectively. One nonvolatile memory manager 128 can receive ready and busy signals R / nB from the nonvolatile memory chips of one nonvolatile memory 130 via the first interface 125, respectively.
The processor core 129 may control the stream buffer 127 and the non-volatile memory managers 128_1 through 128_N via the interconnect INT. The processor core 129 may control the non-volatile memory managers 128_1 to 128_N using the control table CT.
Illustratively, the first to third data D1 to D3 corresponding to the first stream identifier SID1 and the fourth and fifth data D4 and D5 corresponding to the second stream identifier SID2, The fifth to eighth data D5 to D8 corresponding to the third stream identifier SID3 and the ninth and tenth data D9 and D10 corresponding to the fourth stream identifier SID4 are written And is stored as data (DATA_W). It is assumed that there is no free capacity in the stream buffer 127.
Referring to FIG. 6, the processor core 129 may trigger a read operation to the first non-volatile memory manager 128_1. For example, the read operation R may be marked in the control table CT corresponding to the first nonvolatile memory manager 128_1.
Since there is no free capacity of the stream buffer 127, the processor core 129 may trigger a flush operation. At this time, the sixth and eighth data D6 to D8 corresponding to the third stream identifier SID3 may be selected as objects of the flush operation. Illustratively, the sixth and eighth data D6 to D8 corresponding to the third stream identifier SID3 may correspond to the first nonvolatile memory manager 128_1. For example, the sixth and eighth data D6 to D8 may be written to the nonvolatile memory 130 via the first nonvolatile memory manager 128_1. That is, the object of the read operation and the object of the flush operation may coincide with each other.
Referring to FIG. 7, the processor core 129 may cancel the read operation and perform the flush operation. For example, the write operation (W) may be marked in the control table (CT) corresponding to the first nonvolatile memory manager (128_1). The sixth to eighth data D6 to D8 corresponding to the third stream identifier SID3 are stored in the selected one of the nonvolatile memories 130 under the control of the first nonvolatile memory manager 128_1 . As the sixth to eighth data D6 to D8 are flushed, the free capacity of the stream buffer 127 can be secured.
Referring to FIG. 8, as the free capacity of the stream buffer 127 is secured, the processor core 129 can trigger the read operation again. For example, the read operation R may be marked in the control table CT corresponding to the first nonvolatile memory manager 128_1. The first nonvolatile memory manager 128_1 can read the eleventh data D11 from the selected nonvolatile memory 130 of the nonvolatile memories 130. [ Illustratively, the eleventh data D11 is shown as being included in the data group corresponding to the fifth stream identifier SID5. However, the eleventh data D11 is not limited to being included in the data group corresponding to the stream identifiers SID1 to SID5.
For example, the eleventh data D11 may be included in a read data group (not shown) of the stream buffer 127 as read data (DATA_R) to be output to the processor 1100 (see FIG. 1). In this case, the embodiment can be implemented by replacing the fifth stream identifier SID5 in Fig. 8 with a pointer, an address or an identifier indicating a read data group.
For example, the eleventh data D11 is data to be written to another memory block of the selected nonvolatile memory, and performs a background operation such as garbage collection, read reclaim, bad block management, and wear leveling May be included in the temporary data group used. In this case, the embodiment can be implemented by replacing the fifth stream identifier SID5 of FIG. 8 with a pointer, an address or an identifier indicating a temporary data group.
FIG. 9 is a flow chart illustrating how a processor 1100 writes data to a storage device 100 in accordance with an embodiment of the invention. Illustratively, a method by which processor 1100 writes data to non-volatile memories 130 is shown in FIG.
Referring to FIGS. 1, 2, 3 and 9, in step S210, the processor 1100 reads a RAM command (CMD_R) for requesting a write and a RAM address ADDR_R) to the storage device (100). In step S220, the processor 1100 writes the storage command CMD_S for requesting a write and the storage address ADDR_S for selecting a write target among the storage spaces of the nonvolatile memories 130 to the data signals DQ and data To the storage device 100 via the strobe signals DQS.
Steps S210 and S220 may form a command transaction that conveys a write command to non-volatile memories 130 to storage device 100. [ The storage command CMD_S and the storage address ADDR_S are written in the command area CA of the RAM 123. In step S210,
In step S230, the processor 1100 transmits a RAM command (CMD_R) for requesting a write and a RAM address (ADDR_W) for selecting a write area WA of the RAM 123 to the storage device 100. In step S240, the processor 1100 transmits the write data (DATA_W) to the storage device 100 via the data signals (DQ) and the data strobe signals (DQS).
Steps S230 and S240 may form a data transaction for transferring write data (DATA_W) to the non-volatile memories 130 to the storage device 100. When step S230 and step S240 are performed, write data (DATA_W) is written into the write area WA of the RAM 123. [
As the storage command CMD_S, the storage address ADDR_S and the write data DATA_W are stored in the RAM 123, the controller 124 writes the write data DATA_W in response to the storage command CMD_S and the storage address ADDR_S The non-volatile memories 130 of the memory controller 130 may begin writing.
The storage command CMD_S, the storage address ADDR_S and the write data DATA_W may be written to the command area CA of the RAM 123 as one or more phase groups PG. The controller 124 checks the phase bits PB of the phase groups PG written in the command area CA and descrambles the phase groups PG when the phase bits PB are valid .
In step S250, the processor 1100 transmits a RAM command (CMDR_R) for requesting reading and a RAM address (ADDR_R) for selecting the state area (SA) to the storage device (100). In step S460, the processor 1100 can read the status information STI from the storage device 100 as data signals DQ and data strobe signals DQS. Steps S450 and S460 may form a check transaction to check if the write has been processed.
When the writing to the nonvolatile memories 130 is terminated or the writing is scheduled (or enqueued) in the storage apparatus 100, the storage apparatus 100 sends status information (STI) indicating that the writing has been processed to the status area SA (Step S270). The processor 1100 can periodically repeat steps S250 and S260 until the status information STI indicating that the writing has been processed is read from the status area SA. When the state information STI is read from the storage device 100 (step S280), the processor 1100 identifies that the storage device 100 has been subjected to the write operation and performs the next access to the storage device 100 can do.
10 is a flow chart illustrating how the processor 1100 reads data from the storage device 100 in accordance with an embodiment of the invention. Illustratively, the manner in which processor 1100 reads data from non-volatile memories 130 is illustrated in FIG.
Referring to FIGS. 1, 2, 3 and 10, in step S310, the processor 1100 reads a RAM command (CMD_R) for requesting a write and a RAM address ADDR_R) to the storage device (100). In step S320, the processor 1100 reads the storage command CMD_S requesting a read operation and the storage address ADDR_S for selecting an object to be read out from the storage space of the nonvolatile memories 130 as data signals DQ and data To the storage device 100 via the strobe signals DQS.
Steps S310 and S320 may form a command transaction that conveys a read command to non-volatile memories 130 to the storage device 100. [ The storage command CMD_S and the storage address ADDR_S are written in the command area CA of the RAM 123. In step S310,
The storage command CMD_S and the storage address ADDR_S may be written to the command area CA of the RAM 123 as one or more phase groups PG. The controller 124 checks the phase bits PB of the phase groups PG written in the command area CA and descrambles the phase groups PG when the phase bits PB are valid .
As the storage command CMD_S is descrambled, the controller 124 may begin reading the read data (DATA_R) from the non-volatile memories 130 in response to the storage command CMD_S and the storage address ADDR_S. For example, the controller 124 may store the read data (DATA_R) in the read area (RA) of the RAM 123. [
In step S330, the processor 1100 transmits a RAM command (CMDR_R) for requesting reading and a RAM address (ADDR_R) for selecting the state area (SA) to the storage device (100). In step S340, the processor 1100 can read the status information STI from the storage device 100 as data signals DQ and data strobe signals DQS. Steps S330 and S340 may form a check transaction to check if the reading has been completed.
When reading from the non-volatile memories 130 is completed in the storage apparatus 100, the storage apparatus 100 can write state information (STI) indicating that the reading is completed in the state area SA (step S350 ). The processor 1100 may repeat steps S330 and S340 periodically until the status information STI indicating that the reading is completed is read from the status area SA.
When the state information STI is read from the storage device 100, the processor 1100 can identify that the reading operation of the storage device 100 is completed (step S360). In step S370, the processor 1100 transmits a RAM command (CMD_R) for requesting a read and a RAM address (ADDR_W) for selecting a read area WA of the RAM 123 to the storage device 100. In step S380, the processor 1100 may receive the read data (DATA_R) from the storage device 100 as data signals (DQ) and data strobe signals (DQS). Steps S370 and S380 may form a data transaction to transfer the read data (DATA_R) from the non-volatile memories 130. [
The processor 1100 can identify the RAM 123 as being a memory coupled to the high speed interface 1230 and write and read to the RAM 123 according to the specification of the high speed interface 1230 have. Data written to or read from the RAM 123 is communicated to the storage command CMD_S, the storage address CMD_S and the nonvolatile memories 130 requesting access of the nonvolatile memories 130 Write data (DATA_W) and read data (DATA_R).
The storage device 100 may support communication between the RAM 123 and the processor 1100 in accordance with specifications of the high speed interface 1230. The storage device 100 can extract the storage command CMD_S and the storage address ADDR_S from the data stored in the RAM 123. [ The storage device 100 also writes the write data DATA_W stored in the RAM 123 into the nonvolatile memories 130 and the data DATA_R read from the nonvolatile memories 130 into the RAM 123 Can be stored.
Communication between the processor 1100 and the storage device 100 is performed according to specifications of the high speed interface 1230 and data communicated in accordance with the specification of the high speed interface 1230 is used to access the non-volatile memories 130 Protocol. ≪ / RTI >
11 shows an example of a server apparatus 2000 on which a storage apparatus 100 according to an embodiment of the present invention is mounted. Referring to FIG. 11, the server apparatus 2000 may include two or more racks 2010, racks. Two or more storage devices 100 may be mounted on each of the racks 2010. [
Illustratively, each of the racks 2010 includes storage devices 100 according to an embodiment of the present invention, main memory devices 1210 (see FIG. 1), at least one processor 1100, at least one chipset 1300 ), And at least one storage device 1700 can be mounted. The input / output device 1600, the graphics processor 1400, and the display device 1500 may be provided in the server device 2000.
12 is a block diagram showing a storage device 200 according to a second embodiment of the present invention. 12, the storage device 200 includes a device controller 220, non-volatile memories 230, a buffer memory 240, and an SPD 250. The device controller 220 includes a RAM 223. The storage device 200 communicates the data signal DQ, the data strobe signal DQS and the auxiliary signal SS to the processor 1100 (see FIG. 1) via the high-speed interface 1230, The command CMD_R, the RAM address ADDR_R, and the clock CK. The device controller 220 can extract the storage command CMD_S and the storage address CMD_R from the data signal DQ received via the high speed interface 1230. [ The device controller 220 can write the write data (DATA_W) received in the data signal DQ to the nonvolatile memories 230. [ The device controller 220 can output the data (DATA_R) read from the non-volatile memories 230 through the high-speed interface 1230 as the data signal DQ.
Compared with the storage device 100 of FIG. 2, the data buffers 110 are not provided to the storage device 200. FIG. The data signal DQ and the data strobe signal DQ may be transmitted directly to the device controller 220 via the high speed interface 1230. [ By way of example, the high speed interface 1230 may operate in accordance with a specification of an RDIMM. The device controller 220 may communicate with the processor 1100 via the high-speed interface 1230 in accordance with the specifications of the RDIMM.
Except for operating in accordance with the RDIMM specification, the storage device 200 may operate as described with reference to Figures 3-10. The device controller 220 may flush to the non-volatile memories 230 a data group or a combined data group having less capacity than the threshold capacity when free slots FS do not exist in the stream buffer.
13 is a block diagram showing a hybrid storage apparatus 300 according to a third embodiment of the present invention. 1 and 13, the hybrid storage device 300 includes data buffers 310, a device controller 320, non-volatile memories 330, a buffer memory 340, an SPD 350, Access memories (360). Hybrid storage device 300 may be coupled to processor 1100 via a high speed interface 1230, e.g., a DIMM, RDIMM, or LRDIMM interface.
The non-volatile memories 330 and random access memories 360 of the hybrid storage device 300 may be identified at the physical layer of the processor 1100. When the processor 1100 accesses the non-volatile memories 330, the processor 1100 reads the command CMD for the non-volatile memories 330 and the address CMD for the storage space of the non-volatile memories 330 (ADDR) to the device controller 320 via the high speed interface 1230. The processor 1100 may communicate data to be written to or read from the non-volatile memories 330 with the data buffers 310 as data signals DQ.
When the processor 1100 accesses the random access memories 360, the processor 1100 reads the command CMD for the random access memories 360 and the address CMD for the random access memories 360 (ADDR) to the device controller 320 via the high speed interface 1230. Processor 1100 may communicate data to be written to random access memories 360 or data read from random access memories 360 with data buffers 310 as data signals DQ.
Data buffers 310 operate in response to a buffer command CMD_B. Data buffers 310 may communicate data signals DQ and data strobe signals DQS with processor 1100 via high speed interface 1230. [ The data buffers 310 may output the data signals DQ and the data strobe signals DQS received from the processor 1100 to the device controller 320 or the random access memories 360. [ The data buffers 310 may transfer the data signals DQ and data strobe signals DQS received from the device controller 320 or the random access memories 360 to the processor 1100 via the high speed interface 1230 have.
The data buffers 310 may select an object with which to communicate the data signal DQ and the data strobe signal DQS under the control of the device controller 320. [ For example, data buffers 310 may communicate data signals DQ and data strobe signals DQS with device controller 320 under the control of device controller 320. [ As another example, the data buffers 310 may communicate data signals DQ and data strobe signals DQS with the random access memories 360 under the control of the device controller 320.
The device controller 320 can receive the command CMD, the address ADDR and the clock CK from the processor 1100 via the high speed interface 1230. [ The device controller 320 is configured to control the data buffers 310 via the buffer command CMD_B.
In response to a command CMD, an address ADDR or a control signal received via the high speed interface 1230, the device controller 320 determines whether the object to which the processor 1100 accesses is non-volatile memories 330 or random The access memories 360 can be discriminated.
The device controller 320 can control the data buffers 310 to communicate the data signals DQ and the data strobe signals DQS to the device controller 320 when the object of access is non-volatile memories 330 have. The device controller 320 can output the command CMD and the address ADDR received via the high speed interface 1230 to the nonvolatile memories 330. [ The device controller 320 may communicate the data signals DQ received from the data buffers 310 to the non-volatile memories 330. Illustratively, the device controller 320 includes an internal memory 320 for buffering data of data signals DQ to be transferred to the non-volatile memories 330 or data of data signals DQ read from the non-volatile memories 330 Buffer. As another example, the device controller 320 may store data of data signals DQ to be transferred to the non-volatile memories 330 or data signals DQ of data signals DQ to be read from the non-volatile memories 330, 340).
The hybrid storage device 300 may operate as described with reference to FIGS. The device controller 320 may flush to the non-volatile memories 330 a group of data having a capacity less than the threshold capacity or a combined data group when there is no free slot FS in the stream buffer.
The device controller 320 controls the data buffers 310 to communicate the data signal DQ and the data strobe signal DQS with the random access memories 360 when the access target is the random access memories 360. [ can do. The device controller 320 may output the received command CMD, address ADDR and clock CK to the random access memories 360 via the high speed interface 1230. [
The nonvolatile memories 330 can write data transferred as the data signal DQ in response to the command CMD and the address ADDR. The nonvolatile memories 330 can read data in response to the command CMD and the address ADDR and output the read data as the data signal DQ.
The buffer memory 340 may correspond to the buffer memory 140 of FIG. The buffer memory 340 may load metadata for managing the non-volatile memories 330.
The SPD 350 corresponds to the SPD 150 of FIG. The SPD 350 may communicate the ancillary signal SS via the high speed interface 1230.
The random access memories 360 can write data transferred as the data signal DQ in response to the command CMD, the address ADDR and the clock CK. The random access memories 360 can read the data in response to the command CMD, the address ADDR and the clock CK and output the read data as the data signal DQ.
Illustratively, the device controller 320 may communicate the command CMD, the address ADDR, and the data signal DQ to the non-volatile memories 330 as input and output signals. For example, the command CMD, the address ADDR, and the data signal DQ may be communicated through common input / output lines. The device controller 320 may further communicate control signals used to control the non-volatile memories 330 with the non-volatile memories 330. The control signals can be communicated via the control lines separate from the input / output lines.
For example, the device controller 320 includes a chip enable signal / CE for selecting at least one nonvolatile memory chip among the nonvolatile memories 330, a signal transmitted to the input / output signals is a storage command CMD_S, An address latch enable signal ALE that indicates a signal transmitted to the input / output signals is a storage address ADDR_S, and a latch enable signal ALE that is periodically toggled at the time of reading to be used for timing A write enable signal / WE that is activated when a command or an address is transmitted, a write enable signal / WP that is activated to prevent unintended write or erase when power is changed, ), And may transmit the data strobe signal DQS, which is periodically toggled at the time of writing, to be used for synchronizing the data to the non-volatile memories 330. [ The device controller 320 also includes Ready and busy signals (R / nB) indicating whether the non-volatile memories 330 are performing a program, erase or read operation, a read enable signal From the non-volatile memories 330, a data strobe signal DQS that is generated from the refresh / RE and is periodically toggled and used to synchronize the data.
Illustratively, the hybrid device 300 may operate in accordance with the specifications of the LRDIMM.
FIG. 14 is a block diagram illustrating a hybrid storage apparatus 400 according to a fourth embodiment of the present invention. 1 and 14, the hybrid storage device 400 includes a device controller 420, non-volatile memories 430, a buffer memory 440, an SPD 450, and random access memories 460 . Hybrid storage apparatus 400 communicates data signal DQ, data strobe signal DQS and ancillary signal SS with processor 1100 (see FIG. 1) via high speed interface 1230, The command CMD, the address ADDR, and the clock CK.
The device controller 420 identifies an access target among the nonvolatile memories 430 and the random access memories 460 according to a command CMD, an address ADDR or other signal received via the high speed interface 1230 can do. When the access target is the non-volatile memories 430, the device controller 420 performs control such that the data signal DQS and the data strobe signal DQ received via the high-speed interface 1230 are received by the device controller 420 can do. The device controller 420 transfers the data signal DQS and the data strobe signal DQ received via the high speed interface 1230 to the random access memories 460 when the access target is the random access memories 460. [ . For example, the hybrid storage device 400 may further include a switch for controlling the path of the data signal DQS and the data strobe signal DQS.
The device controller 420 may transfer the command CMD and the address ADDR received via the high speed interface 1230 to the nonvolatile memories 430 when the access target is the nonvolatile memories 430. [ The device controller 420 transfers the data signal DQ received through the high speed interface 1230 to the nonvolatile memories 430 and transmits the data signal DQ transmitted from the nonvolatile memories 430 to the high- (1230).
The device controller 420 outputs the command CMD, the address ADDR and the clock CK received via the high-speed interface 1230 to the random access memories 460 when the access target is the random access memories 460. [ .
Compared with the hybrid storage device 300 of FIG. 13, the data buffers 310 are not provided to the hybrid storage device 400. The data signal DQ and the data strobe signal DQ may be transferred directly to the device controller 420 or the random access memories 460 via the high speed interface 1230. [ By way of example, the high speed interface 1230 may operate in accordance with a specification of an RDIMM. Device controller 420 may communicate with processor 1100 via high speed interface 1230 in accordance with the specifications of the RDIMM.
Except for operating in accordance with the RDIMM specification, the hybrid storage device 400 may operate as described with reference to Figures 3-10. The device controller 420 may flush to the non-volatile memories 430 a data group or a combined data group that has less capacity than the threshold capacity when there is no free slot FS in the stream buffer.
15 is a block diagram illustrating one of the non-volatile memories 130 according to an embodiment of the present invention. 2 and 15, the nonvolatile memory 130 includes a memory cell array 131, a row decoder circuit 133, a page buffer circuit 135, a data input / output circuit 137, and a control logic circuit 139 ).
The memory cell array 131 includes a plurality of memory blocks BLK1 to BLKz. Each memory block includes a plurality of memory cells. Each memory block may be connected to the row decoder circuit 133 via at least one ground select line GSL, a plurality of word lines WL, and at least one string select line SSL. Each memory block may be connected to the page buffer circuit 135 via a plurality of bit lines (BL). The plurality of memory blocks BLK1 to BLKz may be commonly connected to the plurality of bit lines BL. The memory cells of the plurality of memory blocks BLK1 to BLKz may have the same structures. Illustratively, each of the plurality of memory blocks BLK1 to BLKz may be a unit of an erase operation. The memory cells of the memory cell array 131 can be erased in units of one memory block. The memory cells belonging to one memory block can be erased simultaneously. As another example, each memory block may be divided into a plurality of sub-blocks. Each of the plurality of subblocks may be a unit of an erase operation.
The row decoder circuit 133 is connected to the memory cell array 131 via a plurality of ground selection lines GSL, a plurality of word lines WL and a plurality of string selection lines SSL. The row decoder circuit 133 operates under the control of the control logic circuit 139. The row decoder circuit 133 decodes the address received from the controller 120 via the input and output channels and outputs the string selection lines SSL, word lines WL and ground selection lines GSL And the like.
For example, at the time of programming, the row decoder circuit 133 applies the program voltage VGPM to the selected word line of the memory block selected by the address and applies the pass voltage VPASS to the unselected word lines of the selected memory block ) Can be applied. At the time of reading, the row decoder circuit 133 applies the selected read voltage VRD to the selected word line of the memory block selected by the address and applies the unselected read voltage VREAD to the unselected word lines of the selected memory block . Upon erase, the row decoder circuit 133 may apply erase voltages (e. G., Low voltages with levels similar to ground voltage or ground voltage) to the word lines of the memory block selected by the address.
The page buffer circuit 135 is connected to the memory cell array 131 through a plurality of bit lines BL. The page buffer circuit 135 is connected to the data input / output circuit 137 via a plurality of data lines DL. The page buffer circuit 135 operates under the control of the control logic circuit 139.
At the time of programming, the page buffer circuit 135 may store data to be programmed into the memory cells. Based on the stored data, the page buffer circuit 135 can apply voltages to the plurality of bit lines BL. For example, the page buffer circuit 135 may function as a write driver. At the time of reading, the page buffer circuit 135 can sense the voltages of the bit lines BL and store the sensing result. For example, the page buffer circuit 135 may function as a sense amplifier.
The data input / output circuit 137 is connected to the page buffer circuit 135 through a plurality of data lines DL. The data input / output circuit 137 outputs the data read by the page buffer circuit 135 to the controller 120 through the input / output channel and the data received through the input / output channel from the controller 120 to the page buffer circuit 135 .
The control logic circuit 139 may receive the command from the controller 120 via the input / output channel and receive the control signal via the control channel. The control logic circuit 139 receives the command received via the input / output channel in response to the control signal, routes the address received through the input / output channel to the row decoder circuit 133, and outputs the data received via the input / And can be routed to the data input / output circuit 137. The control logic circuit 139 may decode the received command and control the non-volatile memory 130 in accordance with the decoded command.
Illustratively, upon reading, the control logic circuit 139 may generate a data strobe signal DQS from the read enable signal / RE received via the control channel from the controller 120. The generated data strobe signal DQS may be output to the controller 120 via the control channel. At the time of writing, the control logic circuit 139 may receive the data strobe signal DQS from the controller 120 via the control channel.
16 is a circuit diagram showing a memory block BLKa according to an embodiment of the present invention. Referring to FIG. 16, the memory block BLKa includes a plurality of cell strings CS11 to CS21, CS12 to CS22. The plurality of cell strings CS11 to CS21 and CS12 to CS22 may be arranged along a row direction and a column direction to form rows and columns.
For example, the cell strings CS11 and CS12 arranged along the row direction form the first row and the cell strings CS21 and CS22 arranged along the row direction form the first row, Two rows can be formed. The cell strings CS11 and CS21 arranged along the column direction form the first column and the cell strings CS12 and CS22 arranged along the column direction form the second column can do.
Each cell string may include a plurality of cell transistors. The plurality of cell transistors include ground selection transistors GST, memory cells MC1 to MC6, and string selection transistors SSTa and SSTb. The ground selection transistors GST, memory cells MC1 to MC6 and string selection transistors SSTa and SSTb of each cell string are arranged such that cell strings CS11 to CS21 and CS12 to CS22 are arranged along rows and columns (For example, a plane on the substrate of the memory block BLKa) perpendicular to the substrate surface.
The plurality of cell transistors may be charge trap type transistors having threshold voltages varying depending on the amount of charge trapped in the insulating film.
The sources of the lowermost ground selection transistors (GST) may be connected in common to the common source line (CSL).
The control gates of the ground selection transistors GST of the plurality of cell strings CS11 to CS21, CS12 to CS22 may be connected to the ground selection lines GSL1 and GSL2, respectively. Illustratively, the ground select transistors of the same row may be connected to the same ground select line, and the different row of ground select transistors may be connected to different ground select lines. For example, the ground selection transistors GST of the cell strings CS11 and CS12 of the first row are connected to the first ground selection line GSL1 and the ground selection transistors GST of the cell strings CS21 and CS12 of the second row The ground selection transistors GST may be connected to the second ground selection line GSL2.
The control gates of the memory cells located at the same height (or in sequence) from the substrate (or the ground selection transistors GST) are commonly connected to one word line, and the control gates of the memory cells located at different heights May be connected to different word lines WL1 to WL6, respectively. For example, the memory cells MC1 are commonly connected to the word line WL1. The memory cells MC2 are connected in common to the word line WL2. The memory cells MC3 are commonly connected to the word line WL3. The memory cells MC4 are connected in common to the word line WL4. The memory cells MC5 are commonly connected to the word line WL5. The memory cells MC6 are connected in common to the word line WL6.
In the first string selection transistors SSTa of the same height (or order) of the plurality of cell strings CS11 to CS21, CS12 to CS22, the control gates of the first string selection transistors SSTa in different rows And are connected to different string selection lines (SSL1a to SSL2a), respectively. For example, the first string selection transistors SSTa of the cell strings CS11 and CS12 are connected in common to the string selection line SSL1a. The first string selection transistors SSTa of the cell strings CS21 and CS22 are connected in common to the string selection line SSL2a.
In the second string selection transistors SSTb of the same height (or order) of the plurality of cell strings CS11 to CS21, CS12 to CS22, the control gates of the second string selection transistors SSTb in different rows And are connected to different string selection lines SSL1b to SSL2b, respectively. For example, the second string selection transistors SSTb of the cell strings CS11 and CS12 are connected in common to the string selection line SSL1b. The second string selection transistors SSTb of the cell strings CS21 and CS22 are connected in common to the string selection line SSL2b.
That is, cell strings in different rows are connected to different string selection lines. The string select transistors of the same height (or sequence) of cell strings in the same row are connected to the same string select line. String selection transistors of different heights (or sequences) of cell strings in the same row are connected to different string selection lines.
By way of example, the string select transistors of the cell strings of the same row may be connected in common to one string select line. For example, the string selection transistors SSTa and SSTb of the cell strings CS11 and CS12 of the first row may be connected in common to one string selection line. The string selection transistors SSTa and SSTb of the sal strings CS21 and CS22 of the second row may be connected in common to one string selection line.
The columns of the plurality of cell strings CS11 to CS21 and CS12 to CS22 are connected to different bit lines BL1 and BL2, respectively. For example, the string selection transistors SSTb of the cell strings CS11 to CS21 in the first column are connected in common to the bit line BL1. The string selection transistors SST of the cell strings CS12 to CS22 in the second column are connected in common to the bit line BL2.
Cell strings CS11 and CS12 may form a first plane. The cell strings CS21 and CS22 may form a second plane.
In the memory block BLKa, memory cells of each height of each plane can form a physical page. The physical page may be a unit of writing and reading of the memory cells MC1 to MC6. For example, one plane of the memory block BLKa may be selected by the string selection lines SSL1a, SSL1b, SSL2a, and SSL2b. When the string selection lines SSL1a and SSL1b are supplied with the turn-on voltage and the turn-off voltage is supplied to the string selection lines SSL2a and SSL2b, the cell strings CS11 and CS12 of the first plane are bit- And connected to lines BL1 and BL2. That is, the first plane is selected. When the turn-on voltage is supplied to the string select lines SSL2a and SSL2b and the turn-off voltage is supplied to the string select lines SSL1a and SSL1B, the cell strings CS21 and CS22 of the second plane are bit- And connected to lines BL1 and BL2. That is, the second plane is selected. In the selected plane, one row of memory cells MC can be selected by the word lines WL1 to WL6. In the selected row, a selection voltage may be applied to the second word line WL2 and a non-selection voltage may be applied to the remaining word lines WL1, WL3 to WL6. That is, by adjusting the voltages of the string selection lines SSL1a, SSL1b, SSL2a, SSL2b and the word lines WL1 to WL6, a physical page corresponding to the second word line WL2 of the second plane can be selected have. In the memory cells MC2 of the selected physical page, writing or reading can be performed.
In the memory block BLKa, erasing of the memory cells MC1 to MC6 may be performed in units of memory blocks or units of subblocks. When an erase is performed on a memory block basis, all the memory cells MC of the memory block BLKa can be erased simultaneously according to one erase request (for example, an erase request from an external memory controller). Some of the memory cells MC1 to MC6 of the memory block BLKa are simultaneously erased in response to one erase request (for example, an erase request from an external memory controller), and the remaining Some may be prohibited from being erased. A word line connected to the erased memory cells MC is supplied with a low voltage (e.g., a ground voltage or a low voltage having a level similar to the ground voltage), and the word line connected to the erased memory cells MC can be floated have.
The memory block BLKa shown in Fig. 16 is an exemplary one. The technical idea of the present invention is not limited to the memory block BLKa shown in Fig. For example, the number of rows of cell strings may be increased or decreased. As the number of rows of cell strings is changed, the number of string select lines or ground select lines connected to the rows of cell strings, and the number of cell strings connected to one bit line can also be changed.
The number of columns of cell strings can be increased or decreased. As the number of columns of cell strings changes, the number of bit lines connected to columns of cell strings and the number of cell strings connected to one string selection line can also be changed.
The height of the cell strings can be increased or decreased. For example, the number of ground select transistors, memory cells, or string select transistors stacked on each of the cell strings may be increased or decreased.
Illustratively, memory cells MC belonging to one physical page may correspond to at least three logical pages. For example, k (k is a positive integer greater than 2) bits can be programmed into one memory cell MC. In the memory cells MC belonging to one physical page, the k bits programmed into each memory cell MC can form k logical pages, respectively.
As an example according to the technical idea of the present invention, a three-dimensional memory array is provided. The three-dimensional memory array may be monolithically formed on one or more physical levels of arrays of memory cells having an active region disposed over a silicon substrate and circuits associated with operation of the memory cells. The circuitry associated with the operation of the memory cells may be located within or on the substrate. What is uniformly formed means that the layers of each level of the three-dimensional array are directly deposited on the lower-level layers of the three-dimensional array.
As an example according to the technical idea of the present invention, a three-dimensional memory array has vertical directionality and includes vertical NAND strings in which at least one memory cell is located on another memory cell. The at least one memory cell includes a charge trapping layer. Each vertical NAND string further includes at least one select transistor located above the memory cells. At least one selection transistor has the same structure as the memory cells and is formed uniformly with the memory cells.
A configuration in which the three-dimensional memory array is composed of a plurality of levels and the word lines or bit lines are shared between levels is disclosed in U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466, U.S. Patent No. 8,654,587 U.S. Patent No. 8,559,235, and U.S. Published Patent Application No. 2011/0233648, which are incorporated herein by reference.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.
