KR20160142236A - Large dynamic range rf voltage sensor and method for voltage mode rf bias application of plasma processing systems - Google Patents

Abstract

A voltage sensor of a substrate processing system, which detects RF voltages in an electrostatic chuck of a plasma processing system, comprises a multi-divider circuit, a clamping circuit, a first output unit, and a second output unit. The multi-divider circuit receives an RF signal indicating an RF voltage in a substrate. The multi-divider circuit includes dividers of respective channels and outputs a first reduced voltage and a second reduced voltage based on the received RF signal. The reduced voltages are lower than the RF voltage. The clamping circuit clamps the first reduced voltage to a first predetermined voltage when the RF voltage exceeds a second predetermined voltage or the first reduced voltage exceeds a third predetermined voltage. While the received RF signal is in first and second voltage ranges, the first output unit and the second output unit output output signals based respectively on the first reduced voltage and the second reduced voltage. The first predetermined voltage is based on the maximum value of the first voltage range.

Description

TECHNICAL FIELD [0001] The present invention relates to a large dynamic range RF voltage sensor, and a method for voltage mode RF bias application of plasma processing systems. BACKGROUND OF THE INVENTION < RTI ID = 0.0 > [0001] <

This disclosure relates to plasma processing systems, and more particularly, to detecting RF voltages within an electrostatic chuck of a plasma processing system.

The background description provided herein is generally intended to provide a context for this disclosure. As a result of the inventors' accomplishments, the performance to the degree described in this Background section, as well as aspects of the technology which may not be recognized as prior art at the time of filing, are not explicitly or implicitly recognized as prior art to this disclosure.

Ionized gases, or plasma, are often used during the processing and fabrication of semiconductor devices. For example, the plasma may be used to etch or remove material from a substrate such as a semiconductor wafer and to deposit material on the substrate by PVD or CVD. Generating a plasma for use in a fabrication process or manufacturing process typically begins by introducing process gases into the processing chamber. The substrate is placed on a substrate support structure, such as an electrostatic chuck or pedestal, in a processing chamber.

The processing chamber may include a transformer coupled plasma (TCP) source coil that receives RF power supplied by a radio frequency (RF) power generator. A dielectric window made of a material such as ceramic is included in the upper surface of the processing chamber. The dielectric window causes RF power from the TCP source coil to be transferred into the interior of the processing chamber. The RF power excites the gas molecules in the processing chamber to produce a plasma.

The plasma includes electrons and charged particles. Electrons lighter than charged particles tend to move more easily and form a sheath on the surfaces of the processing chamber. The self-biasing effect causes a net negative charge on the inner surfaces of the processing chamber. This net negative charge is provided for ground (referred to as DC (direct current) bias) and for the potential of the plasma (referred to as DC cis potential). The DC bias is the potential difference between the surface in the processing chamber and ground. The DC crosstalk potential is the difference between the potential of the surface in the processing chamber and the potential of the plasma. The DC cis potential causes more strongly positively charged particles to be deposited toward the inner surfaces of the processing chamber. The intensity of this DC sheath potential on the substrate generally determines the energy that positively charged particles strike the substrate. This energy affects process characteristics such as etch rate or deposition rate.

The bias RF power source supplies biasing RF power to the substrate support structure. The biasing RF power can be used to increase the DC bias and / or the crosstalk potential so that the charged particles strike the substrate. Variations in the biasing RF power produce corresponding variations in DC bias and / or crossover potential at the substrate that affect process characteristics.

A voltage control interface (VCI) including a pickup device and signal processing circuitry may be used to detect the RF peak voltage at the substrate support structure. The pick-up device may be attached to the substrate support structure and receives an RF peak voltage (i.e., an RF bias voltage). The signal processing circuit is coupled to the pickup device and converts the RF peak voltage to an analog signal having a magnitude proportional to the peak value of the RF voltage upon detection. When the bias RF system operates in voltage mode, the biasing RF power is adjusted based on the detected RF peak voltage such that the bias RF voltage is adjusted to a set value of the bias RF voltage given in the process recipe.

The pick-up device or voltage sensor of the VCI may include a capacitive voltage divider for RF voltage detection for the corresponding channel. The VCI may include circuitry for processing and signal conditioning the received voltage signal on the channel. The voltage sensor has a dynamic range that is typically limited to less than 40 db with reduced accuracy at low voltages. For example, the voltage sensor may have a dynamic range of 25.6 V (volts) peak to 1200.6 V peak with an accuracy of ± (1 V + 1.5% of the National Institute of Standards and Technology (NIST) reference) .

A voltage sensor of the substrate processing system is provided. The voltage sensor includes a multi-divider circuit, a clamping circuit, a first output, and a second output. The multi-divider circuit is configured to receive an RF signal. The received RF signal represents the RF voltage provided to the substrate within the plasma chamber of the substrate processing system. The multi-divider circuit includes a first divider and a second divider. The first divider corresponds to the first channel and outputs a first reduced voltage based on the received RF signal. The second divider corresponds to the second channel and outputs a second reduced voltage based on the received RF signal. The first reduced voltage and the second reduced voltage are less than the RF voltage. The clamping circuit is configured to clamp the first reduced voltage to a first predetermined voltage when (i) the RF voltage is above a second predetermined voltage, or (ii) when the first reduced voltage is above a third predetermined voltage, do. The first output of the first channel is configured to output a first output signal based on a first reduced voltage while the received RF signal is within a first voltage range and a second voltage range. The second voltage range is higher than the first voltage range. The first predetermined voltage is based on a maximum value of the first voltage range. And the second output of the second channel is configured to output a second output signal based on the second reduced voltage while the received RF signal is within the first voltage range and the second voltage range.

In other features, a method of operating a voltage sensor of a plasma processing system is provided. The method includes receiving an RF signal at a first divider and at a second divider. The voltage sensor includes a first divider and a second divider. The first divider corresponds to the first channel. And the second divider corresponds to the second channel. The received RF signal represents the RF voltage applied to the substrate in the plasma chamber of the plasma processing system. The method includes: generating a first reduced voltage through a first divider based on a received RF signal; Generating a second reduced voltage via a second divider based on the received RF signal, wherein the first reduced voltage and the second reduced voltage are less than the RF voltage; And clamping the first reduced voltage to a first predetermined voltage when (i) the RF voltage is above a second predetermined voltage, or (ii) the first reduced voltage is above a third predetermined voltage . The method includes the steps of: providing a first output signal on a first channel based on a first reduced voltage while the received RF signal is within a first voltage range and a second voltage range, Providing a first output signal that is higher than the voltage range and the first predetermined voltage is based on a maximum value of the first voltage range; And providing a second output signal on a second channel based on a second reduced voltage while the received RF signal is within a first voltage range and a second voltage range.

Further areas of applicability of the present disclosure will become apparent from the detailed description, claims and drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the disclosure.

The present disclosure will be more fully understood from the detailed description and the accompanying drawings.
1 is a functional block diagram of a substrate processing system including a multi-range voltage sensor according to the present disclosure;
2 is a functional block diagram of a voltage control interface according to the present disclosure;
3 illustrates a method of operating a substrate processing system and a voltage control interface, in accordance with the present disclosure.
4 is a schematic diagram of a voltage divider circuit according to the present disclosure;
5 is a schematic diagram of a voltage clamping circuit according to the present disclosure;
6 is a schematic diagram of a buffer circuit according to the present disclosure;
7 is a schematic diagram of a voltage compensation circuit according to the present disclosure;
In the drawings, reference numerals may be reused to identify similar and / or identical elements.

Cross reference of related applications

This disclosure relates to United States Patent Application Serial No. 14 / 336,355, filed July 21, The entire disclosure of the above-mentioned applications is incorporated herein by reference.

Increasingly higher bias RF voltages are required for certain substrate processes. For example, high voltage bias pulsing (HVBP) may require that the voltage sensor of the VCI be able to detect peak voltages up to 2500 volts. A voltage sensor comprising a single voltage divider per channel has limited accuracy at low voltages. It will become clearer that the peak voltage becomes larger. In order to overcome this limitation, the voltage sensor is used to measure the voltages within the first (or lower) range of the first channel and the second voltage measurement channel is used to measure voltages within the second (or higher) And may include a plurality of measurement channels. The output of a single voltage divider may be provided to each of the measurement channels, and each of the measurement channels has its own signal processing circuit. While channels may be used to detect respective voltage ranges, channels designed to detect low range voltages may be overloaded and / or damaged when high range voltages are detected.

To overcome the overloading problem, a switching circuit may be added to the first channel used to detect low range voltages. The switching circuit may turn the first channel on or turn it off. The switching circuit may include a diode (e.g., a pin diode) that receives the output of the voltage divider and may be activated via a DC bias voltage. The DC bias voltage may be provided through a controller that activates the diodes based on whether the RF voltages are in the low voltage range or the high voltage range. The diodes are deactivated to protect the remainder of the channel designed to detect low range voltages while high voltages are detected.

A problem with using a switching circuit design is that the controller needs to generate a DC bias voltage to turn the switching circuit on or off (power OFF). The switching circuit may also include DC blocking capacitors. The DC blocking capacitors prevent the DC voltage supplied to turn on and turn off the switching circuit from being received in the voltage divider and / or signal processing circuitry. DC blocking capacitors can negatively affect measurement accuracy due to (i) associated signal disturbances and (ii) increase the complexity of the calibration.

The following examples provide VCIs and corresponding voltage sensors that passively operate without requiring a DC bias voltage while providing a plurality of channels to detect RF voltages within respective voltage ranges. The VCIs and / or voltage sensors have a high accuracy and a large dynamic range and / or a monitored voltage range for each channel. This includes high accuracy at low RF voltages.

1 illustrates a substrate processing system 10 in accordance with the present disclosure. The substrate processing system 10 may be a conductive etch processing system. The substrate processing system 10 includes a coil drive circuit 11. In some examples, the coil drive circuit 11 includes an RF source 12 and a tuning circuit 13. The tuning circuit 13 may be directly connected to one or more coils 16 or may be connected to one or more coils 16 by a coil inversion circuit 15. [ The tuning circuit 13 is used to tune the output of the RF source 12 to a predetermined frequency and / or a predetermined phase. The coil inversion circuit 15 is used to selectively switch the polarity of the current through one or more coils 16.

In some instances, the gas plenum 20 may be disposed between the coils 16 and the window 24. A window 24 is disposed along one side of the processing chamber 28. The processing chamber 28 further includes a substrate support structure 32 (sometimes referred to as a pedestal). The substrate support structure 32 may comprise an electrostatic chuck, a mechanical chuck or other type of chuck. A process gas is supplied to the processing chamber 28 and a plasma 40 is generated inside the processing chamber 28. Plasma 40 etches the exposed surface of substrate 34. RF source 50 and bias matching circuit 52 may be used to bias substrate support structure 32 during operation.

A gas delivery system 56 may be used to supply the process gas mixture to the processing chamber 28. The gas delivery system 56 may include process and inert gas sources 57, a gas metering system 58 such as valves and mass flow controllers, and a manifold 59. The gas delivery system 60 may be used to deliver the gas 62 through the valve 61 to the gas plenum 20. The gas may include cooling gases used to cool the coils 16 and the window 24. The heater / cooler assembly 64 may be used to heat the substrate support structure 32 to a predetermined temperature. The exhaust system 65 includes a valve 66 and a pump 67 to remove reactants from the processing chamber 28 by purging or evacuating.

The controller 54 may be used to control the etching process. The controller 54 monitors the system parameters and controls delivery, plasma striking, maintenance and extinguishing of the gas mixture, removal of reactants, supply of cooling gas, and the like.

The substrate processing system 10 may further include a VCI 70. VCI 70 includes all of the circuitry between the pick-up device 72, the multi-range voltage sensor 74 (hereinafter referred to as a "voltage sensor"), the controller 54 and the voltage sensor 74 and the controller 54 . ≪ / RTI > The pick-up device 72 may extend into the substrate support structure 32 and be located within the cathode assembly 76 of the substrate support structure 32. The pickup device 72 is connected to the voltage sensor 74 via a wire 78 and is used to generate an RF voltage signal. The voltage sensor 74 is configured to detect peak voltages in the RF voltage signal for a plurality of voltage ranges. The voltage sensor 74 has a plurality of channels. The channels are assigned to corresponding ranges of input voltages received from the pick-up device 72. Each of the channels may provide a linear output response to at least a portion of a corresponding input voltage range.

The voltage sensor 74 generates output signals that may be monitored and / or used to adjust the biasing RF signal generated by the bias compensation end point (BiCEP) circuit 79. The BiCEP circuit 79 includes a bipolar high voltage DC supply that provides clamping DC voltages to the electrodes 80 in the cathode assembly 76 of the substrate support structure 32 and / . The BiCEP circuit 79 may be controlled by the controller 54 based on the RF voltages detected by the voltage sensor 74. The bias matching circuit 52 may supply a bias voltage to the metal base 92 based on the RF voltages detected by the voltage sensor 74. [

The substrate support structure 32 may further include a thermal energy control assembly (TECA) 90 and a metal base 92. The heater / cooler assembly 64 may circulate the coolant between the TECA 90 and the reservoir 94 and may be used to control the temperature of the substrate support structure 32.

The operation of the voltage sensor 74 may be monitored via the controller 54. The controller 54 may display the output voltages of the channels of the voltage sensor 74 on the display 98. [ The display 98 may be included in the controller 54, although it is shown as being separated from the controller 54. The controller 54 may receive input signals from the voltage sensor 74 and may control the operation of the bias matching circuit 52 and the BiCEP circuit 79 based on the input signals. The voltage sensor 74 is further described below with respect to Figures 2-7.

The controller 54 may adjust the bias RF signal generated by the bias matching circuit 52 and / or the BiCEP circuit 79 to vary the amount of DC sheath potential and / or DC bias at the substrate 34 . The controller 54 may compare the representative values derived based on the outputs of the channels and / or the outputs of the channels of the voltage sensor 74 to one or more setpoints. The settings may be stored in the memory 100 that is accessible to the controller 46 and / or included in the controller 46 and may be predetermined. The bias RF signal may be adjusted based on (i) differences between the outputs of the voltage sensor 74 and / or representative values and (ii) one or more set values. The bias RF signal may pass through the bias matching circuit 52. The output (referred to as the matched signal) provided by the bias matching circuit 52 then passes through the substrate support structure 32.

Figure 2 shows a VCI 150 that includes a multi-range voltage sensor 152 (hereinafter referred to as a "voltage sensor") and a controller 54 operating in a bias RF voltage control mode. The bias RF voltage control mode includes adjusting the bias RF voltage supplied to the cathode assembly 76 of FIG. 1 based on the peak RF voltages and / or RF voltages detected by the voltage sensor 152. The voltage sensor 152 may be used within the substrate processing system 10 of FIG. 1 and / or may replace the voltage sensor 74. Voltage sensor 152 includes a plurality of channels 154, 156. Although two channels are shown, the voltage sensor 152 may include any number of channels. The controller 54 may monitor one or more of the channels for each of the voltage ranges. Adjacent ranges of voltage ranges corresponding to the channels may overlap to provide a wide continuous full range (e.g., 0 to 2500 V) where the voltages are monitored by the controller 54.

The voltage sensor 152 includes a multi-divider circuit 160 and channels 154 and 156. The multi-divider circuit 160 receives the RF voltage from the pickup device 72 of FIG. An example of the multi-divider circuit 160 is shown in FIG. The multi-divider circuit 160 includes a plurality of voltage dividers and provides reduced voltages to the channels 154 and 156 based on the RF voltage from the pickup device 72.

The first channel 154 includes a first filter circuit 170, a clamping circuit 172, a first rectifier 174, a first buffer circuit 176, and a first signal processing circuit 178. The first channel 154 may include a voltage compensation and / or isolation circuit (hereinafter "voltage compensation circuit") 177. The second channel 156 includes a second filter circuit 180, a second rectifier 182, a second buffer circuit 184, and a second signal processing circuit 188. The second channel 156 may include a voltage compensation and / or isolation circuit (hereinafter "voltage compensation circuit") 186. Although two voltage compensation circuits 177 and 186 are shown, the voltage compensation circuits 177 and 186 may be combined into a single voltage compensation circuit. The voltage compensation circuits 177 and 186 may be connected in parallel with the signal processing circuits 178 and 188, respectively. The operation of the corresponding channels 154 and 156 and the voltage sensor 152 is further described in the method of FIG. The channels 154,156 and / or any other contained channels can be used to determine the need for an external control signal and / or the determination of the actual measured RF voltage magnitudes and / or the setpoint values contained within the substrate processing recipes .

The VCIs disclosed herein may be operated using a number of methods, and an exemplary method is illustrated in FIG. In Figure 3, a method of operating a substrate processing system including a VCI is shown. Although the following tasks are primarily described with respect to the implementations of Figs. 1 and 2 and Figs. 4-7, the tasks may be easily modified to apply different implementations of the present disclosure. Tasks may be executed repeatedly.

The method may start at 200. At 201, the controller 54 may select an operation or voltage mode, a low voltage mode, a high voltage mode, a multi-range voltage mode, or other RF voltage mode, which may include operating in a bias RF voltage control mode . The low voltage mode may refer to providing and / or detecting voltages within a low (or first predetermined) range. The high voltage mode may refer to providing and / or detecting voltages within a high (or second predetermined) range. The multi-range voltage mode may refer to providing and / or detecting voltages within a plurality of ranges that may include a low range and a high range. Adjacent ranges of the plurality of ranges may overlap each other as described above.

At 202, the controller 54 controls the bias matching circuit 52 and BiCEP circuit 79 to control the voltages provided to the metal base 92 and electrodes 80 of the substrate support structure 32 based on the mode of operation. . The controller 54 may set the target bias RF voltage for the BiCEP circuit 79. The multi-divider circuit 160 receives the RF voltage from the pickup device 72 and outputs each of the voltage signals to two or more channels (e.g., channels 154, 156). An example of the multi-divider circuit 160 is shown in FIG.

At 203, task 204 is performed if the target bias RF voltage is in the low range, otherwise the target bias RF voltage is in the high range and task 214 is performed. At 204, the first filter circuit 170 receives and filters the first voltage signal received from the multi-divider circuit 160. Clamping circuit 172 clamps voltages from first filter circuit 170 and / or multi-divider circuit 160. For example, if the overall voltage range of the VCI is 2500 V and the channels 154 and 156 are configured to detect voltages within the respective ranges of 0 to 1500 V and 1000 to 2500 V, then the clamping circuit 172 is at 1500 V Or may clamp the output of the first filter circuit 170 and / or the multi-divider circuit 160 to a corresponding predetermined reduced voltage or other predetermined maximum voltage in the low voltage range. Clamping may occur when (i) the received RF voltage is above a second predetermined voltage or (ii) the reduced voltage is above a third predetermined voltage. The predetermined maximum voltage may be the same as the third predetermined voltage. The second predetermined voltage is a predetermined maximum voltage and a third predetermined voltage. The components of the clamping circuit 172 are preselected to clamp the output of the first filter circuit 170 and / or the multi-divider circuit 160 to a predetermined maximum voltage. An example of the clamping circuit 172 is shown in Fig.

At 208, the first rectifier 174 rectifies the output of the first filter circuit 170 from a first AC (alternating current) signal to a first DC signal. At 210, the first buffer circuit 176 buffers the first DC signal (or the first rectified signal). The first buffer circuit 176 may include an unity gain buffer and / or may be implemented as a unit gain buffer.

At 212, the first signal processing circuit 178 signals and / or processes the output of the first buffer circuit 176. This may include filtering, amplifying and / or adjusting the levels of the output of the first buffer circuit 176. As an example, the output of the first signal processing circuit 178 may be a voltage within a predetermined range (e.g., 0-10 V) based on the RF voltage received at the pickup device 72. The output voltage of the first signal processing circuit 178 may be proportional to the received RF voltage and / or may be directly related to the received RF voltage.

Although not shown in FIG. 3, the voltage compensation circuit 177 may receive the output of the first buffer circuit 176 and may also adjust the output of the first signal processing circuit 178 to adjust the DC bias to ground have. This balances the clamping voltages on the electrodes (80). An example of a voltage compensation circuit is shown in Fig. In one embodiment, the voltage compensation may not be performed on the output of the first signal processing circuit 178. [

At 214, the second filter circuit 180 receives and filters the second voltage signal received from the multi-divider circuit 160. As shown, the output of the second filter circuit 180 is not clamped as an output of the first filter circuit 170. This is because the second channel 156 may be used to monitor a voltage range above and / or beyond the monitored voltage range using the first channel 154.

At 216, the second rectifier 182 rectifies the output of the second filter circuit 180 from the second AC signal to the second DC signal. At 218, the second buffer circuit 184 buffers the second DC signal. An example of the second buffer circuit 184 is shown in Fig.

At 222, the second signal processing circuit 188 signals conditioning and / or processes the output of the voltage compensation circuit 186. This may include filtering, amplifying and / or adjusting the levels of the output of the voltage compensation circuit 186. As an example, the output of the second signal processing circuit 188 may be a voltage within a predetermined range (e.g., 0 to 10 V) based on the RF voltage received at the pickup device 72. The predetermined range of the second signal processing circuit 188 may be the same as or different from the predetermined range of the first signal processing circuit 178. The output voltage of the second signal processing circuit 188 may be proportional to the received RF voltage and / or may be directly related to the received RF voltage.

Although not shown in FIG. 3, the voltage compensation circuit 186 may receive the output of the second buffer circuit 184 and may also adjust the output of the second signal processing circuit 188 to adjust the DC bias to ground have. This balances the clamping voltages on the electrodes (80). An example of a voltage compensation circuit is shown in Fig. In one embodiment, the voltage compensation may not be performed on the output of the second signal processing circuit 188.

At 224, the controller 54 may adjust the voltages provided by the BiCEP circuit 79 and the bias matching circuit 52 to the substrate support structure 32. The voltages may be adjusted based on the outputs of the signal processing circuits 178, 188. This may include adjusting the RF bias power to adjust the RF bias voltage to a predetermined set value. The controller 54 may adjust the settings described above based on the outputs of the signal processing circuits 178, 188 and / or the voltage compensation circuits 177, 186. The outputs of the signal processing circuits 178 and 188 and / or the voltage compensation circuits 177 and 186 may be provided directly to the BiCEP circuit 79. The outputs of the signal processing circuits 178 and 188 may be used to offset one or more voltages of the BiCEP circuit 79 to equalize the clamping voltages of the substrate support structure 32. This may be referred to as adjusting BiCEP bias compensation to provide the same clamping voltages. Each of these adjustments and offsets may be based on a first output and / or a second output of the signal processing circuits 178, 188 when the received RF voltage is within a low voltage range. Each of these adjustments and offsets may be based on a first output and / or a second output of the signal processing circuits 178, 188 when the received RF voltage is within a high voltage range. (I) the first output of the first processing circuit 178 rather than the second output of the second processing circuit 188 when the received RF voltage is within the low voltage range, and (ii) the second output of the second processing circuit 188 rather than the first output of the first processing circuit 178 when the received RF voltage is within the high voltage range. After task 224, the method may end at 226, as shown, or task 202 may be performed.

The tasks described above are intended to be illustrative examples; Tasks may be performed sequentially, synchronously, concurrently, sequentially, or in a different order depending on applications for overlapping time periods. Also, any tasks may not be performed or skipped depending on the implementation and / or sequence of events.

4 shows an example of a multi-divider circuit 160 that includes a first voltage divider 300 and a second voltage divider 302. The multi- The first voltage divider 300 may include a first capacitance C ₁ , a second capacitance C ₂ , a third capacitance C _3, and a first resistance R ₁ . The first capacitance C ₁ is connected in series between (i) the input terminal 304 and (ii) the capacitances C ₂ , C ₃ and the first resistance R ₁ . The capacitances C ₂ , C ₃ and the first resistance R ₁ are connected in parallel between the first capacitance C ₁ and the ground reference. An output terminal 306 is coupled to the output of the first capacitance C _{1 and to} the inputs of the capacitances C ₂ , C ₃ and the first resistance R ₁ .

The second voltage divider 302 may include a fourth capacitance C ₄ , a fifth capacitance C ₅ , a sixth capacitance C _6, and a second resistance R ₂ . The fourth capacitance C ₄ is connected in series between (i) the input terminal 304 and (ii) the capacitances C ₅ , C ₆ and the second resistance R ₂ . The capacitances C ₅ , C ₆ and the second resistance R ₂ are connected in parallel between the fourth capacitance C ₄ and the ground reference. An output terminal 308 is coupled to the output of the fourth capacitance C _{4 and to} the inputs of the capacitances C ₅ , C ₆ and the second resistance R ₂ .

The first voltage divider 300 may have a first impedance ratio. The second voltage divider circuit 302 may have a second impedance ratio. The second impedance ratio may be equal to or different from the first impedance ratio.

Figure 5 illustrates an example of a voltage clamping circuit 172 that may include a first zener diode 310 and a second zener diode 312. [ Zener diodes 310 and 312 are connected in series between (i) the output of the first filter circuit 170 and (ii) the ground reference. Zener diodes 310 and 312 are also connected in series between (i) the input of the first rectifier 174 and (ii) the ground reference. The cathode ends of the Zener diodes 310 and 312 may be directly connected to each other. Zener diodes 310 and 312 provide protection against high voltages or voltages above a predetermined voltage. Zener diodes 310 and 312 are shunted to the input of the corresponding first channel 154. As a result, the zener diodes 310, 312 automatically clip the RF voltage at the input to the first channel 154 to a safety level to protect the components of the first channel 154 during high-bias RF voltage operation (clip).

Figure 6 illustrates an example of a second buffer circuit 184, which may include an operational amplifier 320, a capacitance C ₇ , a resistance R _3, and a voltage divider 322. The capacitance C ₇ and resistance R ₃ are connected in parallel between (i) the non-inverting input of the second rectifier circuit 182 and the operational amplifier 320 and (ii) the ground reference. Voltage divider 322 may include resistances R ₄ , R ₅ connected in series between a voltage source and a ground reference. The output of the voltage divider 322 is provided to the inverting input of the operational amplifier 320. The voltage divider 322 may be used to offset the voltage provided to the non-inverting input of the operational amplifier 320.

The operational amplifier 320 compares the voltage at the non-inverting input with the voltage at the inverting input. If the voltage at the non-inverting input is greater than the voltage at the inverting input, then the output of the operational amplifier is greater than 0V. If the voltage at the non-inverting input is less than the voltage at the inverting input, the output of the operational amplifier is less than 0V. The output of the operational amplifier 320 is provided to a voltage compensation circuit 186.

FIG. 7 is a circuit diagram of the diodes D ₁ , D ₂ ; A voltage divider 330 including resistances R ₆ and R ₇ ; Capacitance C ₈ ; And a resistance compensation circuit 186, which may include resistance R ₈ . The diodes D ₁ , D ₂ and the resistances R ₆ , R ₇ are connected in series between (i) the capacitance C ₈ and the resistance R ₈ and (ii) the ground reference. The anodes of the diodes D ₁ , D ₂ are connected to each other and to the output of the second buffer circuit 184. The voltage divider is connected between diode D ₂ and the ground reference. The capacitance C ₈ is connected between (i) the diode D ₁ and the ground reference and (ii) between the resistance R ₈ and the negative voltage source-V. A signal tap off of the resistance R ₆ is provided and connected to the second signal processing circuit 188. The resistance R ₆ may be a variable resistance having a signal tap at a predetermined position.

The voltage sensors described above provide a large dynamic range and high accuracy per end on a full scale for VCI applications. VCI applications may include conductor etch processing systems and / or other suitable processing systems, where the VCI is used to facilitate the bias RF voltage control mode. Examples include high measurement at both the lowest and highest values of the entire RF voltage range without a reduction in measurement accuracy due to poor signal-to-noise at low RF voltages and / or without overloading at high RF voltages Accuracy is enabled. Examples include dual or multiple channels with clamping circuitry for self-protection of one or more channels that are configured for low voltage ranges and receive high voltages, and dual or multiple voltage dividers to provide high dynamic range and high accuracy Providing more rigid and less complex VCIs. This protection is provided without the need for external control of the switching circuit.

The foregoing description is merely exemplary in nature and is not intended to limit the present disclosure, its application, or uses in any way. The broad teachings of the present disclosure may be implemented in a variety of forms. Thus, while this disclosure includes specific examples, the true scope of the disclosure should not be so limited since other modifications will become apparent by studying the drawings, specification, and the following claims. It should be understood that one or more steps within a method may be performed in a different order (or concurrently) without changing the principles of the present disclosure. Furthermore, although each of the embodiments is described above as having specific features, any one or more of these features described for any embodiment of the present disclosure may be implemented in any other embodiment And / or in combination with features of any other embodiment. That is, the described embodiments are not mutually exclusive, and substitutions with other embodiments of one or more embodiments remain within the scope of the present disclosure.

The spatial and functional relationships between elements (e.g., modules, circuit elements, semiconductor layers, etc.) are referred to as "connected," "engaged," "coupled Quot ;, "adjacent ", " adjacent to, " " next to," " on top of, "" above, ""quot;, " disposed ", and the like. Unless expressly stated to be "direct ", when a relationship between a first element and a second element is described in the above disclosure, this relationship is to be understood as meaning that other intervening elements between the first element and the second element May be a direct relationship that does not exist, but may also be an indirect relationship in which there is one or more intermediary elements (spatially or functionally) between the first element and the second element. As used herein, at least one of the terms A, B, and C should be interpreted logically (A or B or C), using a non-exclusive logical OR, and "at least one A Quot ;, at least one B, and at least one C ".

In some implementations, the controller is part of a system that may be part of the above-described instances. Such systems may include semiconductor processing equipment, including processing tools or tools, chambers or chambers, processing platforms or platforms, and / or specific processing components (wafer pedestal, gas flow system, etc.) . These systems may be integrated into an electronic device for controlling their operation prior to, during, and after the processing of a semiconductor wafer or substrate. An electronic device may also be referred to as a "controller" that may control various components or sub-components of the system or systems. The controller may control the delivery of the processing gases, the temperature settings (e.g., heating and / or cooling), the pressure settings, the vacuum settings, the power settings, and the like, depending on the processing requirements and / RF configuration parameters, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, location and operation settings, tools and other delivery tools And / or any of the processes disclosed herein, including wafer transfers into and out of load locks that are interfaced or interfaced with a particular system.

Generally speaking, the controller may be implemented with various integrated circuits, logic, memory, and / or software that receive instructions and issue instructions, control operations, enable cleaning operations, enable endpoint measurements, May be defined as an electronic device. The integrated circuits may be implemented as chips that are in the form of firmware that stores program instructions, digital signal processors (DSPs), chips that are defined as application specific integrated circuits (ASICs), and / or one that executes program instructions (e.g., Microprocessors, or microcontrollers. The program instructions may be instructions that are passed to the controller or to the system in the form of various individual settings (or program files) that define operating parameters for executing a particular process on a semiconductor wafer or semiconductor wafer. In some embodiments, the operating parameters may be varied to achieve one or more processing steps during fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / It may be part of the recipe specified by the engineer.

The controller, in some implementations, may be coupled to or be part of a computer that is integrated into the system, coupled to the system, or otherwise networked to the system, or a combination thereof. For example, the controller may be all or part of a factory host computer system capable of remote access to wafer processing, or may be in a "cloud ". The computer monitors the current progress of manufacturing operations, examines the history of past manufacturing operations, examines trends or performance metrics from a plurality of manufacturing operations, changes parameters of current processing, and performs processing steps following current processing Or may enable remote access to the system to start a new process. In some instances, a remote computer (e.g., a server) may provide process recipes to the system via a network that may include a local network or the Internet. The remote computer may include a user interface that enables input or programming of parameters and / or settings to be communicated from the remote computer to the system at a later time. In some instances, the controller receives instructions in the form of data, specifying parameters for each of the process steps to be performed during one or more operations. It should be appreciated that these parameters may be specific to the type of tool that is configured to control or interfere with the controller and the type of process to be performed. Thus, as described above, the controllers may be distributed, for example, by including one or more individual controllers networked together and cooperating together for common purposes, for example, for the processes and controls described herein. An example of a distributed controller for this purpose is one or more integrated on a chamber communicating with one or more integrated circuits remotely located (e.g., at the platform level or as part of a remote computer) Circuits.

Exemplary systems include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, A chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD (atomic layer deposition) chamber or module, an ALE (atomic layer etch) chamber or module, an ion implantation chamber or module, a track chamber or module, Or any other semiconductor processing systems that may be used or associated with fabrication and / or fabrication of wafers.

As described above, depending on the process steps or steps to be performed by the tool, the controller may be used to transfer the material to move the containers of wafers from / to the tool positions and / May communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located all over the plant, main computer, other controller or tools.

Claims (20)

A voltage sensor in a substrate processing system,
The voltage sensor includes:
1. A multi-divider circuit configured to receive a radio frequency (RF) signal, the received RF signal representing an RF voltage applied to a substrate in a plasma chamber of the substrate processing system, wherein the multi-divider circuit includes a first divider and a second Wherein the first divider corresponds to a first channel and outputs a first reduced voltage based on the received RF signal, wherein the second divider corresponds to a second channel and the received RF Signal, wherein the first reduced voltage and the second reduced voltage are less than the RF voltage;
(i) the RF voltage is greater than a second predetermined voltage, or (ii) when the first reduced voltage is greater than a third predetermined voltage, to clamp the first reduced voltage to a first predetermined voltage , A clamping circuit;
A first output of the first channel configured to output a first output signal based on the first reduced voltage while the received RF signal is within a first voltage range and a second voltage range, The range being higher than the first voltage range and the first predetermined voltage being based on a maximum value of the first voltage range; And
And a second output of the second channel configured to output a second output signal based on the second reduced voltage while the received RF signal is within the first voltage range and the second voltage range, Voltage sensors in processing systems. The method according to claim 1,
The first divider comprising a first capacitance connected in series with a second capacitance; And
Wherein the second divider comprises a third capacitance connected in series with a fourth capacitance. 3. The method of claim 2,
Wherein the first divider comprises a first resistance and a fifth capacitance connected in parallel with the second capacitance; And
Wherein the second divider comprises a second and a sixth capacitance connected in parallel with the fourth capacitance. The method according to claim 1,
Wherein the clamping circuit comprises a pair of Zener diodes. The method according to claim 1,
The first predetermined voltage being equal to the third predetermined voltage; And
Wherein the second predetermined voltage is greater than the first predetermined voltage and the third predetermined voltage. The method according to claim 1,
The second channel comprising a buffer circuit;
The buffer circuit comprising an amplifier and a voltage divider;
The amplifier receiving a first input and a second input;
The first input being generated based on the second reduced voltage;
The second input being generated based on an output of the voltage divider; And
Wherein the second output signal is generated based on an output of the amplifier. The method according to claim 6,
Wherein the second channel is less than a fourth predetermined voltage, and wherein the voltage circuit is configured to block voltages from the amplifier. 8. The method of claim 7,
The voltage circuit comprising a pair of diodes; And
Wherein the predetermined voltage is 0V. The method according to claim 1,
The first channel includes a first rectifier;
The second channel includes a second rectifier;
The first rectifier generating a first rectified signal based on the first reduced voltage; And
And the second rectifier generates a second rectified signal based on the second reduced voltage. 10. The method of claim 9,
The first channel comprising a first buffer circuit;
The second channel includes a second buffer circuit;
The first buffer circuit buffering the first rectified signal; And
And the second buffer circuit buffers the second rectified signal. The voltage sensor according to claim 1, And
(i) the first output signal while the received RF voltage is within the first voltage range, and (ii) the second output signal while the received RF voltage is within the second voltage range. And a controller configured to control a bias voltage supplied to the substrate support structure in the plasma chamber. The voltage-controlled interface of claim 11;
The plasma chamber;
A pickup device configured to receive the RF voltage and generate the RF signal;
A chuck disposed in the plasma chamber and connected to the pick-up device; And
And a power source configured to supply the bias voltage to the chuck. A method of operating a voltage sensor of a plasma processing system,
The method comprises:
Receiving an RF signal at a first divider and at a second divider, wherein the voltage sensor includes the first divider and the second divider, the first divider corresponding to a first channel, and the second The divider corresponding to a second channel, the received RF signal representing an RF voltage provided on a substrate in a plasma chamber of the plasma processing system;
Generating a first reduced voltage through the first divider based on the received RF signal;
Generating a second reduced voltage via the second divider based on the received RF signal, wherein the first reduced voltage and the second reduced voltage are less than the RF voltage, the second reduced voltage ;
(i) clamping a first reduced voltage to a first predetermined voltage when the RF voltage is above a second predetermined voltage, or (ii) when the first reduced voltage is above a third predetermined voltage;
Providing a first output signal on the first channel based on the first reduced voltage while the received RF signal is within a first voltage range and a second voltage range, Wherein the first output voltage is higher than the first voltage range and the first predetermined voltage is based on a maximum value of the first voltage range; And
And providing a second output signal on the second channel based on the second reduced voltage while the received RF signal is within the first voltage range and the second voltage range. Of the voltage sensor. 14. The method of claim 13,
Filtering the first reduced voltage signal to produce a first filtered output;
Rectifying the first filtered output, the first output signal being generated based on the first filtered output; rectifying the first filtered output;
Filtering a second reduced voltage signal to produce a second filtered output; And
Further comprising rectifying the second filtered output, wherein the second output signal is generated based on the second filtered output. ≪ RTI ID = 0.0 >< / RTI & A method of operating a sensor. 14. The method of claim 13,
Further comprising receiving a first input and a second input at an amplifier,
The second channel comprising the amplifier and a voltage divider;
The first input being generated based on the second reduced voltage;
The second input being generated based on an output of the voltage divider; And
Wherein the second output signal is generated based on an output of the amplifier. 16. The method of claim 15,
And wherein the second channel is less than a fourth predetermined voltage, the voltage circuit being configured to block voltages from the amplifier. 14. The method of claim 13,
Generating a first rectified signal through a first rectifier based on the first reduced voltage; And
Further comprising generating a second rectified signal via a second rectifier based on the second reduced voltage,
The first output signal being generated based on the first rectified signal; And
Wherein the second output signal is generated based on the second rectified signal. 14. The method of claim 13,
Wherein the second voltage range overlaps the first voltage range. ≪ Desc / Clms Page number 17 > 14. The method of claim 13,
Further comprising controlling a bias voltage supplied to the substrate support structure in the plasma chamber based on the first output signal and the second output signal. 14. The method of claim 13,
Controlling the clamping voltage supplied to the substrate support structure in the plasma chamber based on the first output signal and the second output signal.

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