CN100530529C

CN100530529C - Double offset frequency plasma body reactor with electrostatic chuck voltage feedback control

Info

Publication number: CN100530529C
Application number: CNB2006100993378A
Authority: CN
Inventors: 蒋国杨; 丹尼尔·J·霍夫曼; 史蒂文·C·香农; 道格拉斯·H·伯恩斯; 翁瑟科·李; 柯康苏
Original assignee: Applied Materials Inc
Current assignee: Applied Materials Inc
Priority date: 2006-07-17
Filing date: 2006-07-17
Publication date: 2009-08-19
Anticipated expiration: 2026-07-17
Also published as: CN101110347A

Abstract

A plasma reactor is provided, which comprises a RF bias power source of a dual-frequency plasma with a first frequency component and a second frequency component for RF bias power, an input end coupled to the RF bias power source of the plasma, a RF power path coupled to an output end of a wafer support base, a first frequency component and a second frequency component that respectively provide the measurement voltage next to the input end of the RF power path, a sensor circuit for the measurement signal of the first frequency component and the second frequency component in current measuring, a first frequency component and second frequency component processor that provides voltage signal for the wafer. The first frequency component and second frequency component for the voltage signal of the wafer respectively equals a first sum for multiplying the first frequency component with a first coefficient and a second coefficient or, a second sum for multiplying the second frequency component with a third coefficient and a fourth coefficient. The processor generates a DC wafer voltage by modulating a DC component for the first frequency component and the second frequency component of a correction factor composite wafer voltage. The correction factor equals is elevated to a designated power and multiplies with the DC component of the first frequency component and the second frequency component for the wafer voltage with designated coefficient.

Description

Double offset frequency plasma body reactor with the control of electrostatic chuck Voltage Feedback

Technical field

The double offset frequency plasma body reactor of the FEEDBACK CONTROL of (ESC) voltage that the present invention relates to have electrostatic chuck, particularly, the present invention relates to have the double offset frequency plasma body reactor of the FEEDBACK CONTROL of the ESC voltage that the wafer voltage measurement that utilizes biasing supply output place carries out.

Background technology

The plasma reactor general using electrostatic chuck (ESC) that is used for process semiconductor wafers is with the chamber interior of wafer holder at reactor.The plasma ion energy at wafer surface place is controlled by applying bias voltage via ESC to wafer.ESC is made of insulating barrier basically, and insulating barrier has the top surface that is used to support wafer.The electrode or the conductive grid of the insulating barrier inside of wafer below receive dc voltage, produce voltage drop on the insulating barrier between electrode and the wafer, and this has produced the electrostatic force of wafer being clamped down on ESC.The power of clamping down on is determined by the time average of wafer voltage and the difference that is applied between the dc voltage of ESC electrode.Clamp down on voltage and must be accurately controlled (by accurate control DC supply voltage) to avoid voltage or the excessive voltage of clamping down on clamped down in shortage.The voltage of clamping down in shortage can make wafer break away from ESC.The excessive voltage of clamping down on can make electric current by wafer increase to may to destroy the level that is formed on the circuit feature on the wafer surface.(electric current arrives wafer from the ESC electrode stream through dielectric layer, and returns through the plasma in the chamber.The power of clamping down on is strong more, and the conductivity between wafer and the ESC is just big more, thereby just big more by the electric current of wafer.) clamp down on voltage in order accurately to control, must accurately measure the wafer dc voltage.Error during wafer voltage is measured may cause wafer to break away from or excessive ESC-wafer current.

Use the ESC-wafer to contact the control wafer temperature also the accurate control of clamping down on voltage to be proposed strict more requirement.As on August 26th, 2004 by Douglas Buchberger, Jr. the unsettled U.S. Patent application No.10/929 that is entitled as " Gasless High Voltage High Contact Force Wafer Contact-CoolingElectrostatic Chuck " that waits the people to submit to, disclosed in 104 (being transferred to assignee of the present invention), ESC can be heated or cooled, thereby wafer is heated or cools off with the speed that the power of being clamped down on by ESC is determined.Therefore, chip temperature can accurately be provided with and control on demand.In fact, to increase rate of heat transfer also very big along with clamping down on voltage so that with compared in the past, chip temperature can maintain the temperature that many higher than heat load.Thereby for example, wafer bias power may increase to and surpass the previous level that allows.Yet the chip temperature scope is limited, because can't accurately determine under the situation of wafer voltage, clamping down on voltage can not be very near from the upper limit (it is excessive to surpass upper limit wafer current) or lower limit (being lower than the lower limit wafer may break away from from ESC).(clamping down on voltage is to determine from the time average of wafer voltage and the difference between the DC supply voltage.) currently be used to estimate that the method for wafer voltage is not very accurate, thereby clamp down on voltage range must be limited to guarantee that the wafer voltage measure error can not cause clamping down on voltage and cross upper and lower bound.

The exact method that is used for determining wafer voltage has disclosed at the unsettled U.S. Patent application No.10/440 that Daniel Hoffman submitted on May 16th, 2003 in 364 (being transferred to assignee of the present invention).This method can be used for such plasma reactor, wherein has only the bias power of single offset frequency to be coupled to wafer from ESC.This method is coarse when existing more than an offset frequency.For example, reactor may apply the bias power with low frequency (LF) component and high frequency (HF) component, to obtain to help the ion energy distribution of the plasma treatment such as plasma intensified response ion(ic) etching.When adopting this double frequency to setover, big wafer voltage measure error can take place.We find that wafer voltage measure error in this case may produce the voltage error of clamping down on above the deliverability of the dc voltage of ESC.

Needed is a kind of exact method of measuring the wafer voltage under the double frequency biasing.This can allow to clamp down on voltage and be set as and more approach maximum or the minimum value that allows to clamp down on voltage, and does not worry because the wafer voltage measure error is violated these limits.This has correspondingly allowed the expansion of chip temperature scope again, so this is a tangible advantage.

Summary of the invention

Plasma reactor have be used for supply comprise respectively first frequency component f (1) and second frequency component f (2) the RF bias power dual frequency plasma RF bias power supply and have the input that is coupled to the supply of plasma RF bias power and be coupled to the RF power path of the output of wafer support pedestal, and the sensor circuit that the measuring-signal of the first frequency component of the first frequency component of measuring voltage of the input vicinity of representing the RF power path and second frequency component and measurement electric current and second frequency component is provided.Reactor also comprises and is used to provide the first frequency component of wafer voltage signal and the processor of second frequency component, the first frequency component of described wafer voltage signal and second frequency component be respectively measuring voltage and the first frequency component of measuring electric current be multiplied by respectively that first of first coefficient and second coefficient adds and and measuring voltage and the second frequency component of measuring electric current are multiplied by respectively that second of tertiary system number and Quaternary system number adds and.Processor by utilizing correction factor resultant wafer voltage the first frequency component and the DC component of second frequency component generate the DC wafer voltage, correction factor is to be lifted to selected power and to be multiplied by first component of wafer voltage of selected voltage and the product of the DC component of second component.Correction factor has compensated the intermodulation effect between two frequency components of bias power.The DC wafer voltage that is obtained is highly accurate, and can be used for clamping down in the electrostatic chuck precision control of voltage.Clamp down on voltage and can be used to the control wafer temperature.

Description of drawings

Figure 1A illustrates the plasma reactor that has measuring instrument in the electrostatic chuck feedback control loop, and this reactor has the bias voltage source that has low frequency (LF) component and high frequency (HF) component.

Figure 1B is the block diagram that is used for determining based on the electric current of the HF of biasing supply voltage and LF component and feedback control loop the device of wafer voltage in the measuring instrument.

Fig. 2 illustrates the electric model of the plasma reactor of measuring instrument employing.

Fig. 3 A illustrates the LF structure partly of the measuring instrument of Fig. 1.

Fig. 3 B illustrates the HF structure partly of the measuring instrument of Fig. 1.

Fig. 4 A illustrates the input phase processor of the LF measuring instrument part of Fig. 3 A.

Fig. 4 B illustrates the input phase processor of the HF measuring instrument part of Fig. 3 B.

Fig. 5 A illustrates the transmission line transform processor in the measuring instrument LF part of Fig. 3 A.

Fig. 5 B illustrates the transmission line transform processor in the measuring instrument HF part of Fig. 3 B.

Fig. 6 A illustrates grid in the measuring instrument LF part of Fig. 3 A to the ground transform processor.

Fig. 6 B illustrates grid in the measuring instrument HF part of Fig. 3 B to the ground transform processor.

Fig. 7 A illustrates grid in the measuring instrument LF part of Fig. 3 A to the wafer transform processor.

Fig. 7 B illustrates grid in the measuring instrument HF part of Fig. 3 B to the wafer transform processor.

Fig. 8 A illustrates the combined transformation processor in the measuring instrument LF part of Fig. 3 A.

Fig. 8 B illustrates the combined transformation processor in the measuring instrument HF part of Fig. 3 B.

Fig. 9 illustrates the used constant of the measuring instrument that is used to provide Figure 1A or the device of the factor.

Embodiment

ESC with the cooling of high contact force wafer:

Figure 1A illustrate have cylindrical side wall 10, roof roof 12 contacts cooling electrostatic chuck (ESC) 14 plasma reactor with wafer.Pumping endless belt 16 is limited between chuck 14 and the sidewall 10.Although wafer contact cooling electrostatic chuck 14 can be used in the plasma reactor or other reactors (as the heat treatment reactor) of any kind, the reactor in the example of Figure 1A is such one type reactor: wherein handling gas can introduce by constituting roof 12 gas distribution plate 18 (or " spray head ") greatly.Perhaps, reactor can have gas distribution inlet 20 (dotted lines) that are separated with roof 12.Wafer contact cooling electrostatic chuck 14 can not be used in combination with any plasma source (illustrating in the drawings), as induction coupled RF plasma source, capacitive coupling RF plasma source or microwave plasma source or annular (torroidal) plasma source.Handle gas supply 34 and be coupled to gas distribution plate 18 (or gas ejector 20).Semiconductor wafer or work package 40 are placed in the top of chuck 14.Processing region 42 is limited between wafer 40 and the roof 12 (comprising gas distribution plate 18).

Plasma RF bias power from low frequency RF bias power generator 125 and high-frequency RF bias power generator 125 ' is applied on the wafer support pedestal 14 by impedance matching circuit 130.DC chuck voltage is applied on the chuck 14 from chuck voltage source 48, and chuck voltage source 48 is isolated by isolating capacitor 50 and RF bias power generator 125.Depend on the level and the duration of the RF plasma bias power that is applied, the RF power that is delivered to wafer 40 from RF bias power generator 125,125 ' can be heated to wafer 40 and surpass 400 degrees centigrade temperature.Can be sure of about 80% or more RF power in wafer 40, be dissipated as heat.

The electrostatic chuck 14 of Fig. 2 is wafer contact cooling electrostatic chucks, and wherein that part of the chuck of contact wafer is cooled.Wafer contact cooling electrostatic chuck 14 neither needs the gas cooled source also not need the internal gas coolant channel to keep the wafer cooling and removes heat (although also can comprise such feature) from wafer.On the contrary, by cooling chuck 14 self, keep the direct powerful contact between wafer 40 and the chuck 14 simultaneously, heat is removed from wafer with the speed of the time speed of the rising that limited maximum chip temperature during the plasma treatment or chip temperature, and this will be described below.Perhaps, chuck voltage can change during processing of wafers, changing selected thermal transmission coefficient, thereby chip temperature is controlled at desired value.This back one feature can be by monitoring chip temperature and changing chuck voltage so that the poor minimum between chip temperature that records and the target temperature is carried out.Surpass the maximum target temperature along with the chip temperature that records rises, chuck voltage increases, and along with being reduced to the target minimum temperature under the chip temperature that records, chuck voltage can reduce.And, even the contact cooling of the brute force of wafer also can the control wafer temperature when high RF bias power level.

Chuck 14 has the top layer 60 that is called as disk (puck), and it is made of insulation or semi insulating material, and as aluminium nitride or aluminium oxide, these materials can be doped with other materials to control its electrical properties and hot attribute.The metal of disk 60 inside (for example molybdenum) silk screen or metal level 62 have constituted negative electrode (or electrode), wherein apply chuck voltage and RF bias power via coaxial cable 210 to negative electrode.Disk 60 can be made by pottery.Perhaps, it can be handled or chemical vapor deposition process or plasma or flame-spraying or additive method are made by plasma or physical deposition.It is supported on the metal level 64, and metal level 64 preferably is made of the metal with high heat conductance such as aluminium.Metal level 64 is positioned on the high-insulation layer 66, select thickness, dielectric constant and the dielectric dissipation factor (tangent) of high-insulation layer 66, to provide to chuck 14 and reactor design and the compatible mutually selected RF characteristic (for example electric capacity, loss resistance) of processing demands.Metallic substrate layer 68 is connected to ground.Wafer 40 remains on the chuck 14 by applying dc voltage from chuck voltage source 48 to electrode 62.The insulator 60 that applied the voltage polarizing that strides across insulating barrier 60, and in the bottom surface of wafer 40, induce and produced opposite (attracting each other) image charge.In the situation of semi-insulating layer 60, produced the image charge except in the bottom surface of wafer, inducing, the charge migration that comes self-electrode 62 is through semi-insulating layer 60, being accumulated in very position, thereby make the gap minimum (term " semi-insulator " is discussed below) between electric charge and the upper chip 40 near the end face of semi-insulating layer 60.This induces in the bottom surface of wafer 40 and has produced opposite (attracting each other) image charge.Because the charge migration that makes progress in the insulating barrier 60, the effective clearance between two relative charge layers is very little, so that for the less relatively chuck voltage that applies, the attraction between chuck and the wafer 40 is very big.For example, only produced the clamping force that is equal to about 100Torr pressure on the wafer 40 on the electrode 62 for the chuck voltage of 300V DC.Therefore, disk semi-insulating layer 60 is made of the material with expectation charge mobility, is not insulator (thereby term is called " semi-insulator ") completely thereby make material.Although this semi-insulator material is not an insulator completely, can not be typical semiconductor in some cases yet.Under any circumstance, induce the electric charge of generation in the semi-insulator material of discs layers 60, all to move by the chuck voltage on the electrode 62, therefore can think that disk semi-insulator layer 60 is made of " charge migration " material.An example that is suitable for the material of disk semi-insulator or electric charge migrating layer 60 is an aluminium nitride.Another example is an aluminium oxide, and it can be doped alternatively to improve charge mobility.For example, dopant material can be a titanium dioxide.

Can be applied to electrode 62 by impedance matching circuit 130 from RF bias power generator 125,125 ' RF bias power, perhaps can be applied to the metal level 64 that is used for the RF coupling by semi-insulating discs layers 60.

Very high thermal transmission coefficient between wafer 40 and the disk 60 is to realize by keeping very high clamping force.The OK range of this power depends on the expection heat load of wafer, and this will be in the hereinafter discussion of specification.(unit is W/m to wafer to the thermal transmission coefficient of the contact-making surface of disk ²° K or to the heat flux density under the fixed difference difference) be suitable for removing heat with the speed that heat is deposited on the wafer.Particularly, thermal transmission coefficient is suitable, because during plasma treatment, itself or chip temperature is limited in the scope of the maximum temperature that is lower than appointment, perhaps the time speed with the rising of chip temperature is limited in the scope of the maximum rate that is lower than rising.Depend on heat load, can select any temperature of maximum chip temperature in from 100 degrees centigrade of magnitudes to higher actual range.The maximum rate that heat during the processing rises can be any value in from 3 to the 20 degree/second scopes.Specific example can be 20 degree/seconds or 10 degree/seconds or 3 degree/seconds.By relatively, if wafer is not cooled, then in the situation of typical 300mm silicon wafer (heat load 7500W), the speed that heat rises can be 86.7 degree/seconds, and wherein 80% heat is absorbed by wafer.Thereby in one embodiment of the invention, the speed that temperature rises is reduced to 1/4 of heat climbing speed when uncolled.

This performance realizes in the following manner: at first, disk (is for example maintained enough low temperature, be lower than about 80 ℃ of aimed wafer temperature), secondly, end face to disk 60 (for example provides enough even curface fineness, in the magnitude of tens of microinch RMS deviations, perhaps preferably in the magnitude of microinch RMS deviation).For this reason, the end face 60a of disk 60 can be by high polish to for example surface smoothness of the magnitude of about 2 microinch RMS deviations.In addition, by cool metal layer 64 heat is removed from disk 60.For this reason, in metal level 64, provide the internal coolant path 70 that is coupled to cooling medium pump 72 and heat sink or cooling source 74.In alternative embodiment, except extend past metal level 64 or different with extend past metal level 64 be, inner cooling channel 70 can also extend in the disk 60 or be adjacent with its back side.Under any circumstance, coolant channel 70 all directly or by metal level 64 is thermally coupled to disk 60, and is used to cool off disk 60.Circulation can for example be water, ethylene glycol or mixture through the coolant liquid of internal path 70.Perhaps, cooling agent can be the perfluorochemical heat transfer liquids, as " fluorinert " (being made by 3M company).Different with the internal gas coolant channel of traditional chuck is, this feature shows electric arc seldom or does not show electric arc under the situation that has high RF bias power, wherein this high RF bias power is applied on the chuck 14 by RF bias power generator 125.

The contact cooling of this wafer is than an advantage of the conventional method that adopts refrigerating gas, according to gas and two surfaces (promptly, chuck surface and wafer bottom surface) the thermal accommodation coefficient of material, the heat transfer efficiency in refrigerating gas and two surfaces between each is very limited.Rate of heat transfer is decayed to the product of chuck thermal accommodation coefficient to wafer thermal accommodation coefficient and gas by gas.If these two coefficients all are about 0.5 (this is a height "ball-park" estimate), then the decay factor of the thermal conductance of wafer-gas-chuck is about 0.25.On the contrary, the contact cooling thermal conductance among the present invention does not in fact have such decay, and thermal accommodation coefficient is consistent for the chuck 14 of Figure 1A-4 effectively.Therefore, contact cooling electrostatic chuck 14 can surpass the factor of traditional electrostatic chuck (that is, adopting gas-cooled electrostatic chuck) about four times (or bigger), and sufficiently high attraction electrostatic force is arranged between wafer and chuck.We have observed the improvement of about three times of factors in preliminary test.

Thermal transmission coefficient in the wafer contact cooling electrostatic chuck 14 between wafer 40 and the disk 60 is subjected to the influence of disk end face surface smoothness and clamping force.These parameters can be conditioned to obtain necessary thermal transmission coefficient under the specific environment.An important environmental factor determining needed thermal transmission coefficient is the RF bias power level that is applied.Can be sure of, in wafer 40, be dissipated as heat from least 80% RF bias power of bias generator 125.Therefore, for example,, in wafer 40, be dissipated as heat from 80% RF bias power of bias generator 125, and chip area is 706cm if RF bias power level is 7500W ²(300mm diameter wafer) allows 80 degrees centigrade the temperature difference between wafer 40 and disk 60, then needed thermal transmission coefficient is h=7500 * 80%W/ (706cm ²* 80 ° of K), it is 1071W/m ²° K.For bigger RF bias power level, can come enhancing heat transfer by increasing any one or both in the aforementioned factor (temperature of promptly striding disk descends the clamping force of disc surfaces or evenness).This high heat transfer coefficient (seldom obtaining in the conventional electrostatic chuck) is easy to obtain in the electrostatic chuck 14 of Fig. 2, for example by applying the sufficiently high chuck voltage of 1kV magnitude.

In addition, by providing the bigger disc surfaces area that can be used for directly contacting to improve heat conduction with chip back surface.In traditional chuck, can be used for the disc surfaces of wafer contact and greatly reduce owing to there is open cooled gas path (by machining, grinding or otherwise be formed in the disc surfaces).These passages have occupied a big chunk of disc surfaces.

The double offset power-frequency of the etching performance that is used to strengthen:

The reactor of Figure 1A has adopted two different bias power frequencies (being f1 and f2) to optimize etching performance.The first offset frequency f1 is low frequency (LF) the RF signal such as 2MHz, and enough low to follow the vibration of its electric field for the ion at plasma sheath place.Because some will quicken along shell with the ion of LF electric field homophase, and will slow down along plasma sheath, so the LF bias source provides relatively broad ion energy to compose with other ions of LF electric field out-phase.For example, for the nominal RF bias level of 1000V under the 2MHz, the scope of ion energy will be from about 300eV to 1800eV.The second offset frequency f2 is high frequency (HF) RF signal, and it is too high and can not be followed by the ion at plasma sheath place, thus the ion energy distribution relative narrower that produces by the HF bias source, and be centered close to mean value corresponding to half of P-to-P voltage.The combination results of the wide ion energy distribution of the LF bias source of the narrow ion energy distribution of the HF bias source of (frequency f 2) and (frequency f 1) extend horizontally to the ion energy distribution that generates by the LF bias source from the mean ion energy that generates by the HF bias source than the high ion energy level.Can be sure of, thisly strengthen etching performance than the high ion energy level.Problem is that the intermodulation products between two offset frequencies (f1 and f2) make and seem to be difficult to measure exactly clean wafer voltage.

Wafer contact force FEEDBACK CONTROL:

Traditional sensing circuit 132 in the impedance matching circuit 130 has output 133, and output 133 provides and indicates low-frequency voltage V (f1), electric current I (f1) and (optionally) power P respectively _Bias(f1) and high frequency voltage V (f2), electric current I (f2) and (optionally) power P _Bias(f2) signal, these signals are provided to wafer support pedestal 14 from the output of impedance matching circuit 130.Measuring instrument 140 uses from the signal of output 133 and measures voltage on the wafer 40.Measuring instrument 140 adopts based on below with the processing of the electric model of the reactor 100 described.Processor 80 periodically calculates the dc voltage of wafer 40.Subtracter 82 calculates the DC wafer voltage and is applied to poor between the dc voltage on the pedestal 14 by chuck voltage source 48, as clean chuck voltage.Feedback controller 84 will be compared with the clean chuck voltage of expectation determining error by the clean chuck voltage that subtracter 82 provides, thereby and apply correction signal and reduce this error with the DC output that changes dc voltage supply 48.The clean chuck voltage of expectation can be provided by the chip temperature processor controls, and this processor converts the chip temperature of user command to the clean chuck voltage of expectation.

Have measurement to the wafer voltage of the correction of the intermodulation products of f1 and f2:

With reference to Figure 1B, the voltage V of processor 90 by recording in input to cable 210 _InAnd electric current I _InBe multiplied by each constant and to these two products add and, determine the voltage V at electrode or grid 62 places _JunctionAs the unsettled U. S. application No.10/440 that is submitted to by Daniel Hoffman on May 16th, 2003, disclosed in 364 (being transferred to assignee of the present invention), this sum of products adds and adopts following form:

V _in{cosh[(V _ch)(-length)]}+I _in{Z _chsinh[(V _ch)(-length)]}。

Therefore, a constant is cosh[(V _Ch) (length)], another constant is Z _ChSinh[(V _Ch) (length)].These two constants are called as K1 and K2 respectively.Z _ChBe the characteristic impedance of coaxial cable 210, V _ChBe the complex phase bit rate of cable 210, " length " is cable length.The voltage V at wafer 40 places _WaferBe operation, by with factor Z according to the processor 830 of the processor 520 of Fig. 5 A of cited application and Fig. 8 A _Wafer/ Z _GridBe incorporated into and obtain in each constant.Z _WaferBe the impedance between grid 62 and the wafer 120, and Z _GridIt is the impedance between grid 62 and the ground.Utilize this to be incorporated into correction factor in the constant, it becomes following form:

K1＝(Z _wafer/Z _grid)cosh[(V _ch)(-length)]

K2＝(Z _wafer/Z _grid)Z _chsinh[(V _ch)(-length)]。

According to cited application, aforementioned content is effective for single offset frequency.Parameter Z _Wafer, Z _GridAnd V _ChIn each estimate at certain bias frequency place, thereby K1 and K2 depend on frequency.

In the reactor of Figure 1A, two bias sources 125,125 ' are arranged, it provides the bias power at LF frequency f 1 place and HF frequency f 2 places respectively.Therefore, two processors 90 of Figure 1B adopt constant K 1, the K2 (specific as follows: K1 (f1), K2 (f1), K1 (f2), K2 (f2)) that estimates at different offset frequencies place with 91, the independent wafer voltage of calculating at each offset frequency f1, f2 place.Measuring instrument 132 provides LF input voltage V to processor 90 _In(f1) and input current I _In(f1), provide HF input voltage V to processor 91 _In(f2) and input current I _In(f2).LF processor 90 adopts LF constant K 1 (f1), K2 (f1), and HF processor 91 adopts HF constant K 1 (f2), K2 (f2), to produce LF wafer voltage V respectively _Wafer(f1) and HF wafer voltage V _Wafer(f2).Then, these two RF wafer voltage V _Wafer(f1) and V _Wafer(f2) be used to the DC wafer voltage that location survey really as follows gets.Utilize

processor

92,93 to determine the wafer dc voltage V at two frequency places at first, respectively _DC(f1), V _DC(f2), as LF and HF wafer voltage V _Wafer(f1), V _Wafer(f2) RMS value.

For the total dc voltage on the wafer of determining to be attributable to these two frequency components, we find, at the simple addition that adopts these two frequency components, V _DC(f1)+V _DC(f2) time, tangible error can take place.This is because this simple addition is not considered two intermodulation effects between the offset frequency.As in this specification before as described in, error may surpass the ability of chuck dc voltage supply 48.Therefore, deduct correction factor from the result, this correction factor comprises two dc voltage component V _DC(f1), V _DC(f2) product.Simply add and and the combination of correction factor utilize processor 94 to carry out, to determine the total dc voltage on the wafer:

V _DC(total)＝V _DC(f1)+V _DC(f2)+E{[V _DC(f1)][V _DC(f2)]} ^F

Wherein E and F are constants.In theory, F=1/2 and E=1, but in actual applications, we find, the result preferably of acquisition is F=0.43 and E=1.This provides the measurement result V of dc voltage on the highly accurate wafer _DC(wafer), V _DC(wafer) be imported into the ESC that management is applied to wafer and clamp down on the

feedback control loop

82,84,48 of power.Subtracter 82 definite clean wafers are clamped down on voltage δ V _DC, as the DC wafer voltage V that records of from processor 80 _DC(total) poor with by between the dc voltages of DC chuck voltage supply 48 outputs.Feedback controller 84 will be worth with the voltage of clamping down on of expectation compares with definite error, and changes the output of ESC dc voltage supply 48 so that reduce this error.

The measurement of the wafer voltage of carrying out based on the electrical characteristics of chamber:

Fig. 2 shows the electric model of the plasma reactor of Figure 1A, and it defines and be used for determining from the RF voltage and current of the output of impedance matching 130 electrical quantity of some reactor assemblies of the voltage on the wafer 40 in measuring instrument 140.In the model of Fig. 2, electrostatic chuck (ESC) 14 comprises the dielectric disk 60 that comprises electrode or conductive grid 62, and disk 60 is divided into very thin upper strata dielectric layer 115-2 and the dielectric layer 115-3 of lower floor by electrode 62.Layer 115-3 can be to layer 60 (than lower part), 64 and 66 compositional modeling, and it is separated electrode 62 metallic substrates 68 with ground connection.Fig. 2 also shows the coaxial cable 210 that the output of impedance matching circuit 130 is connected to grid 62.Coaxial cable 210 has inner wire 212 and outer conductor 214.

Electric model shown in Fig. 2 has been portrayed the electrical properties of plasma reactor, and these attributes utilize conventional art to be easy to determine.Particularly, coaxial transmission line or cable 210 are characterised in that three amounts: (1) its length, (2) Z _Ch, its characteristic impedance and (3) V _Ch, the complex phase bit rate in its equation for transmission line.Because complex phase bit rate V _ChDepend on along the frequency of the signal of coaxial cable propagation, so it is called as V here _Ch(f) to indicate its dependence to frequency.ESC 14 is characterised in that the dielectric layer 115-2 of the upper and lower and the electrical properties of 115-3.Particularly, lower floor's dielectric layer 115-3 has capacitor C _D, it is the function of following parameter: the DIELECTRIC CONSTANT of (1) dielectric layer 115-3 _D, the conduction loss component tan of (2) dielectric layer 115-3 _D, the radius of the thickness gap of (3) dielectric layer 115-3 and (4) wafer 40.Conduction loss component tan _DDepend on the signal frequency of coupling, therefore, be called as tan here through dielectric layer _D(f) to indicate its dependence to frequency.Upper strata dielectric layer 115-2 has capacitor C _P, it is the function of following parameter: the thickness gap of (1) dielectric layer 115-2 _P, the DIELECTRIC CONSTANT of (2) dielectric layer 115-2 _PAnd the conduction loss component tan of (3) dielectric layer 115-2 _PConduction loss component tan _PDepend on the signal frequency of coupling, therefore, be called as tan here through dielectric layer _P(f) to indicate its dependence to frequency.

In one implementation, the measuring instrument 140 of Figure 1A can be divided into two parts 140a, 140b, and these two parts are exclusively used in the measurement of respective component of the wafer voltage at frequency f 1, f2 place respectively.For this reason, from transducer 132 with LF component output signal related (promptly, V (f1), I (f1), P (f1)) be provided to measuring instrument part 140a, and be provided to measuring instrument part 140b with HF component output signal related (that is, V (f2), I (f2), P (f2)) from transducer 132.Therefore, these two parts 140a, 140b adopt the different above-mentioned model parameter values that depends on frequency.Thereby measuring instrument part 140a uses V _Ch(f1), tan _D(f1), tan _P(f1), these values are parameter values that depend on frequency of estimating at LF frequency f 1 place.Similarly, measuring instrument part 140b uses V _Ch(f2), tan _D(f2), tan _P(f2), these values are parameter values that depend on frequency of estimating at HF frequency f 2 places.Fig. 3 A and 3B illustrate each measuring instrument part 140a of Figure 1A, the structure of 140b.

LF measuring instrument part 140a:

With reference to figure 3A, in measuring instrument part 140a, low frequency (LF) P that input phase processor 310 receives from the impedance matching sensing circuit 132 of Figure 1A _Bias(f1), V (f1) and I (f1) signal, and produce the LF input current I that locates near terminal (that is, from the nearest end of impedance matching circuit 130) of indication coaxial cable 210 _In(f1) and LF input voltage V _In(f1) corresponding signal.[in one embodiment, do not adopt input phase processor 310, thus LF input current and voltage I _In(f1), V _In(f1) identical with LF voltage and current V (f1), I (f1) from transducer 132.The phase calculation as the complexity of carrying out has been avoided in this simplification in processor 310.] transmission line transform processor 320 uses the characteristic impedance Z from the electric model 330 of coaxial cable 210 _ChWith complex phase bit rate or loss factor V _Ch(f1) next I from nearly cable end piece _InAnd V _InBe transformed to the voltage V of cable end piece far away place (that is the node between coaxial cable 210 and the grid 62) _JunctionGrid is obtained radius, gap, ε to ground transform processor 340 from grid to earth capacitance model 345 _DAnd tan _DAnd produce dielectric resistance R (f1), _D(f1) and the dielectric capacitor C _DGrid is obtained radius, gap to wafer transform processor 350 from grid to wafer capacitor model 355 _P, ε _PAnd tan _PAnd produce plasma resistance R (f1), _P(f1) and plasma capacitance C _P Combined transformation processor 360 is accepted the output of every other processor 320,340,350, and calculates wafer voltage V _Wafer(f1).

Generally speaking, electrical measurement is to carry out in output place of impedance matching circuit 130.Transmission line transform processor 320 is transformed to the measurement result of the proximal end of cable 210 voltage of far-end.Grid provides near the conversion to conductive grid 62 of the ground level 64 of cable far-end to ground transform processor 340.Grid provides from conductive grid 62 to wafer 40 conversion to wafer transform processor 350.

Transmission line model 330, grid be the part of measuring instrument 140 not necessarily to earth capacitance model 345 and grid to wafer capacitor model 355.Perhaps, they can be the memories in the measuring instrument 140, and it stores coaxial cable parameter (V respectively _Ch(f1) and Z _Ch), grid is to earth capacitance parameter (gap, ε _D, tan _D(f1) and radius) and grid to wafer capacitance parameter (gap _P, ε _P, tan _P(f1) and radius).

Fig. 4 A illustrates the structure of the input phase processor 310 of Fig. 3 A.Power output (delivered power) ALU (ALU) 410 is from the output I (f1) and the P of impedance matching sensing circuit 132 _Bias(f1) calculate power output P (f1), calculating formula is P _Bias(f1)-(0.15) I (f1) ²Phase angle ALU 420 is from power output P (f1) and V (f1) and I (f1) calculating phase angle θ (f1), and calculating formula is cos ^-1[P (f1)/V (f1) I (f1)].Impedance ALU 430 calculates complex impedance Z (f1), and calculating formula is (V (f1)/I (f1)) e ^{I θ}, i=(1) wherein ^1/2 Input current ALU 440 calculates the input current I of coaxial cable 210 _In(f1), calculating formula is [P (f1)/Re (Z (f1)) ^1/2 Input voltage ALU 450 calculates the input voltage V of coaxial cable 210 _In(f1), calculating formula is Z (f1) I _In(f1).

Fig. 5 A illustrates the structure of the transmission line transform processor 320 of Fig. 3 A.The transmission line processor receives the I from the input phase processor 310 of Fig. 4 A _In(f1) and V _In(f1), and use the transmission line model V parameter as input _Ch(f1) and Z _Ch(from transmission line model or the memory 330 of Fig. 3 A) calculates the node voltage V at cable output end place as follows _Junction(f1) and admittance Y _Junction(f1): node electric current ALU 510 calculates the electric current I of the node of coaxial cable 210 and grid 62 (Figure 1A) as follows _Junction(f1):

I _in(f1){cosh[V _ch(f1)(-length)]}+V _in(f1){(1/Z _ch)sinh[V _ch(f1)(-length)]}

Node voltage ALU 520 calculates the voltage V of the node between coaxial cable 210 and the grid 62 as follows _Junction(f1):

V _in(f1){cosh[V _ch(f1)(-length)]}+I _in(f1){Z _chsinh[V _ch(f1)(-length)]}

Divider 530 receives I _JunctionAnd V _Junction, and press I _Junction/ V _JunctionCalculate Y _JunctionThe amount of each electrical quantity in the aforementioned calculating (electric current, voltage, impedance, admittance etc.) can be the plural number that existing real part has imaginary part again.

Fig. 6 A illustrates the structure of the grid of Fig. 3 A to ground transform processor 340.Grid receives parameter gap, the ε that arrives ground model or memory 345 from the grid of Fig. 3 A to ground transform processor 340 _D, tan _DAnd calculate dielectric resistance R (f1) and rad (wafer radius), _D(f1) and the dielectric capacitor C _DThe dielectric capacitor C _DCalculate as follows by CD ALU 610:

(ε ₀)(ε _D)π(rad) ²/gap

ε wherein ₀It is the dielectric constant of free space.The C that RD ALU 620 uses from CD ALU 610 _DValue, and calculate dielectric resistance R as follows _D(f1):

(tan _D(f1))/((2π)(f1)C _Dgap ²)

Fig. 7 A illustrates the structure of the grid of Fig. 3 A to wafer transform processor 350.Grid receives the parameter gap that arrives wafer model or memory 355 from the grid of Fig. 3 A to wafer transform processor 350 _P, ε _P, tan _PAnd the calculating plasma resistance R (f1) and rad, _P(f1) and plasma capacitance C _PPlasma capacitance C _PCalculate as follows by CP ALU 710:

(ε ₀)(ε _P)π(rad) ²/gap _P

ε wherein ₀It is the dielectric constant of free space.The C that RP ALU 720 uses from CP ALU 710 _PValue, and calculating plasma resistance R as follows _P(f1):

(tan _P(f1))/((2π)(f1)C _Pgap _P ²)

Fig. 8 A illustrates the structure of the combined transformation processor 360 of Fig. 3 A.The parameters R that combined transformation processor 360 receives from the processor 340 of Fig. 3 A _D(f1), C _D, receive parameters R from the processor 350 of Fig. 3 A _P(f1), C _P, and reception is from the parameter Y of the processor 320 of Fig. 3 A _Junction Grid impedance ALU 810 calculates Z as follows _Grid(impedances at grid 62 places):

[Y _junction(f1)-1/R _D(f1)+(1/(i2π(f1)C _D))] ^-1

Wafer impedance ALU 820 uses the output of grid impedance ALU 810 to calculate Z as follows _Wafer(impedances at wafer 40 places of Fig. 2):

Z _grid(f1)-1/(R _P(f1)+(1/(i2π(f1)C _P)))

Wafer voltage ALU 830 uses the output of

ALU

810 and 820 and from the V of the divider 530 of Fig. 5 A _Junction(f1), come voltage V on the wafer 120 of calculating chart 2 as follows _Wafer(f1):

V _junction(f1)Z _wafer(f1)/Z _grid(f1)。

Should be noted that Z _Grid(f1) accurate Calculation depends on the above-mentioned voltage and current V that is used for _Junction(f1), I _Junction(f1) V in the respective transmissions line equation _In(f1) and I _In(f1), thus Z _Grid(f1) constant not necessarily.In order to simplify wafer voltage V _Wafer(f1) calculating, factor Z _Wafer(f1)/Z _Grid(f1) (being assigned with the homogeneous value) is left in the basket.Perhaps, can simplify calculating in the following way: be about to available action and handle the interior Z of window _Grid(f1) mean value is elected constant as and is substituted at definite V _Wafer(f1) Z in _Grid(f1) accurate Calculation.Utilize this simplification, factor Z _Wafer(f1)/Z _Grid(f1) become constant, thus the wafer voltage V that is undertaken by ALU 830 _Wafer(f1) determine to become cable/electrode node voltage V _Junction(f1) be multiplied by constant (that is factor Z, _Wafer(f1)/Z _Grid(f1)).This may reduce precision slightly, but has simplification V _WaferThe advantage of calculating (f1).

If desired, processor 840 passes through wafer voltage V _Wafer(f1) divided by the wafer impedance Z _Wafer(f1) produce the wafer current that records.

HF measuring instrument part 140b:

With reference to figure 3B, in measuring instrument part 140b, high frequency (HF) P that input phase processor 310 ' receives from the impedance matching sensing circuit 132 of Figure 1A _Bias(f2), V (f2) and I (f2) signal, and produce the HF input current I that locates near terminal (that is, from the nearest end of impedance matching circuit 130) of indication coaxial cable 210 _In(f2) and HF input voltage V _In(f2) corresponding signal.[in one embodiment, do not adopt input phase processor 310 ', thus HF input current and voltage I _In(f2), V _In(f2) identical with HF voltage and current V (f2), I (f2) from transducer 132.] transmission line transform processor 320 ' uses the characteristic impedance Z from the electric model 330 of coaxial cable 210 _ChWith complex phase bit rate or loss factor V _Ch(f2) next I from nearly cable end piece _InAnd V _InBe transformed to the voltage V of cable end piece far away place (that is the node between coaxial cable 210 and the grid 62) _JunctionGrid is obtained radius, gap, ε to ground transform processor 340 ' from grid to earth capacitance model 345 _DAnd tan _DAnd produce dielectric resistance R (f2), _D(f2) and the dielectric capacitor C _DGrid is obtained radius, gap to wafer transform processor 350 ' from grid to wafer capacitor model 355 _P, ε _PAnd tan _PAnd produce plasma resistance R (f2), _P(f2) and plasma capacitance C _PCombined transformation processor 360 ' is accepted every other processor 320 ', 340 ', 350 ' output, and calculates wafer voltage V _Wafer(f2).

Generally speaking, electrical measurement is to carry out in output place of impedance matching circuit 130.Transmission line transform processor 320 ' is transformed to the measurement result of the proximal end of cable 210 voltage of far-end.Grid provides near the conversion to conductive grid 62 of the ground level 64 of cable far-end to ground transform processor 340 '.Grid provides from conductive grid 62 to wafer 40 conversion to wafer transform processor 350 '.

Transmission line model 330 ', grid be the part of measuring instrument 140 not necessarily to earth capacitance model 345 and grid to wafer capacitor model 355.Perhaps, they can be the memories in the measuring instrument 140, and it stores coaxial cable parameter (V respectively _Ch(f2) and Z _Ch), grid is to earth capacitance parameter (gap, ε _D, tan _D(f2) and radius) and grid to wafer capacitance parameter (gap _P, ε _P, tan _P(f2) and radius).

Fig. 4 B illustrates the structure of the input phase processor 310 ' of Fig. 3 B.Power output ALU (ALU) 410 ' is from the output I (f2) and the P of impedance matching sensing circuit 132 _Bias(f2) calculate power output P (f2), calculating formula is P _Bias(f2)-(0.15) I (f2) ²Phase angle ALU 420 ' is from power output P (f2) and V (f2) and I (f2) calculating phase angle θ (f2), and calculating formula is cos ^-1[P (f2)/V (f2) I (f2)].Impedance ALU 430 ' calculates complex impedance Z (f2), and calculating formula is (V (f2)/I (f2)) e ^{I θ}, i=(1) wherein ^1/2Input current ALU 440 ' calculates the input current I of coaxial cable 210 _In(f2), calculating formula is [P (f2)/Re (Z (f2))] ^1/2Input voltage ALU 450 ' calculates the input voltage V of coaxial cable 210 _In(f2), calculating formula is Z (f2) I _In(f2).

Fig. 5 B illustrates the structure of the transmission line transform processor 320 ' of Fig. 3 B.The transmission line processor receives the I from the input phase processor 310 ' of Fig. 4 B _In(f2) and V _In(f2), and use the transmission line model V parameter as input _Ch(f2) and Z _Ch(from transmission line model or the memory 330 ' of Fig. 3 B) calculates the node voltage V at cable output end place as follows _Junction(f2) and admittance Y _Junction(f2): node electric current ALU 510 ' calculates the electric current I at the node place of coaxial cable 210 and grid 62 (Figure 1A) as follows _Junction(f2):

I _in(f2){cosh[V _ch(f2)(-length)]}+V _in(f2){(1/Z _ch)sinh[V _ch(f2)(-length)]}。

Junction voltage ALU 520 ' calculates the voltage V of the node between coaxial cable 210 and the grid 62 as follows _Junction(f2):

V _in(f2){cosh[V _ch(f2)(-length)]}+I _in(f2){Z _chsinh[V _ch(f2)(-length)]}。

Divider 530 ' receives I _JunctionAnd V _Junction, and press I _Junction/ V _JunctionCalculate Y _JunctionThe amount of each electrical quantity in the aforementioned calculating (electric current, voltage, impedance, admittance etc.) can be the plural number that existing real part has imaginary part again.

Fig. 6 B illustrates the structure of the grid of Fig. 3 B to ground transform processor 340 '.Grid receives parameter gap, the ε that arrives ground model or memory 345 from the grid of Fig. 3 B to ground transform processor 340 ' _D, tan _DAnd calculate dielectric resistance R (f2) and rad (wafer radius), _D(f2) and the dielectric capacitor C _DThe dielectric capacitor C _DCalculate as follows by CD ALU 610 ':

(ε ₀)(ε _D)π(rad) ²/gap

ε wherein ₀It is the dielectric constant of free space.The C that RD ALU 620 ' uses from CD ALU 610 ' _DValue, and calculate dielectric resistance R as follows _D(f2):

(tan _D(f2))/((2π)(f2)C _Dgap ²)。

Fig. 7 B illustrates the structure of the grid of Fig. 3 B to wafer transform processor 350 '.Grid receives the parameter gap that arrives wafer model or memory 355 from the grid of Fig. 3 B to wafer transform processor 350 ' _P, ε _P, tan _PAnd the calculating plasma resistance R (f2) and rad, _P(f2) and plasma capacitance C _PPlasma capacitance C _PCalculate as follows by CP ALU 710 ':

(ε ₀)(ε _P)π(rad) ²/gap _P

ε wherein ₀It is the dielectric constant of free space.The C that RP ALU 720 ' uses from CP ALU 710 ' _PValue, and calculating plasma resistance R as follows _P(f2):

(tan _P(f2))/((2π)(f2)C _Pggp _P ²)

Fig. 8 B illustrates the structure of the combined transformation processor 360 ' of Fig. 3 B.The parameters R that combined transformation processor 360 ' receives from the processor 340 ' of Fig. 3 B _D(f2), C _D, receive parameters R from the processor 350 ' of Fig. 3 B _P(f2), C _P, and reception is from the parameter Y of the processor 320 ' of Fig. 3 B _JunctionGrid impedance ALU 810 ' calculates Z as follows _Grid(impedances at grid 62 places):

[Y _junction(f2)-1/R _D(f2)+(1/(i2π(f1)C _D))] ^-1

Wafer impedance ALU 820 ' uses the output of grid impedance ALU 810 ' to calculate Z as follows _Wafer(impedances at wafer 120 places of Fig. 2):

Z _grid(f2)-1/(R _P(f2)+(1/(i2π(f1)C _P)))。

Wafer voltage ALU 830 ' uses the output of ALU 810 ' and 820 ' and from the V of the divider 530 ' of Fig. 5 B _Junction(f2), come voltage V on the wafer 40 of calculating chart 2 as follows _Wafer(f2):

V _junction(f2)Z _wafer(f2)/Z _grid(f2)

Should be noted that Z _Grid(f2) accurate Calculation depends on the above-mentioned voltage and current V that is used for _Junction(f2), I _Junction(f2) V in the respective transmissions line equation _In(f2) and I _In(f2), thus Z _Grid(f2) constant not necessarily.In order to simplify wafer voltage V _Wafer(f2) calculating, factor Z _Wafer(f2)/Z _Grid(f2) (being assigned with the homogeneous value) is left in the basket.Perhaps, in order to simplify calculating, available action can be handled the Z in the window _Grid(f2) mean value is elected constant as and is substituted at definite V _Wafer(f2) Z in _Grid(f2) accurate Calculation.Utilize this simplification, factor Z _Wafer(f2)/Z _Grid(f2) become constant, thus the wafer voltage V that is undertaken by ALU 830 ' _Wafer(f2) determine to become cable/electrode node voltage V _Junction(f2) be multiplied by constant (that is factor Z, _Wafer(f2)/Z _Grid(f2)).This may reduce precision slightly, but has simplification V _WaferThe advantage of calculating (f2).

If desired, the wafer current at f2 place can be measured by processor 840 ', and processor 840 ' is with wafer voltage V _Wafer(f2) divided by the wafer impedance Z _Wafer(f2).

Determining of the constant that the processor of Figure 1A is used:

Two measuring instrument part 140a, 140b provide the LF and the HF component V of wafer voltage respectively _Wafer(f1), V _Wafer(f2).These two components are used in the processor of Figure 1B, are used for calculating total wafer dc voltage when considering the voltage loss that causes owing to the inter-modulation between two frequencies, and are as above described with reference to Figure 1B.The processor 90 of Figure 1B is used for determining that LF constant K 1 (f1), the K2 (f1) of the LF component of wafer voltage are according to the open definition as follows of Fig. 3 A, 4A, 5A, 6A, 7A and 8A:

K1(f1)＝[Z _wafer(f1)/Z _grid(f1)]cosh[V _ch(f1)(-length)]

K2(f1)＝[Z _wafer(f1)/Z _grid(f1)]Z _chsinh[V _ch(f1)(-length)]

The processor 91 of Figure 1B is used for determining that HF constant K 1 (f2), the K2 (f2) of the HF component of wafer voltage are according to the open definition as follows of Fig. 3 B, 4B, 5B, 6B, 7B and 8B:

K1(f2)＝[Z _wafer(f2)/Z _grid(f2)]cosh[V _ch(f2)(-length)]

K2(f2)＝[Z _wafer(f2)/Z _grid(f2)]Z _chsinh[V _ch(f2)(-length)]

Fig. 9 shows the

processor

95,96,97,98 that is respectively applied for formation constant K1 (f1), K2 (f1), K1 (f2), K2 (f2).For

processor

95 and 96, Z _Wafer(f1) and Z _Grid(f1) value is respectively from (Fig. 8 A's)

processor

820 and 810, as shown in Figure 9.For

processor

97 and 98, Z _Wafer(f2) and Z _Grid(f2) value is respectively from (Fig. 8 B's) processor 820 ' and 810 ', as shown in Figure 9.These constants can be stored in respectively among

register

90a, 90b, 91a, the 91b of Figure 1B.

In implementation efficiently, be unwanted from the phase information of transducer 132.In this implementation, do not adopt Phase Processing device 310, and sensor voltage and electric current V (f1), I (f1), V (f2), I (f2) are multiplied by the constant that is stored among

register

90a, 90b, 91a, the 91b in the mode shown in Figure 1B.In order to ensure K1 (f1), K2 (f1), K1 (f2), K2 (f2) is true constant, amount Z _GridReplaced with available Z on the operational processes window of prediction _GridMean value, as preceding described in the specification.

Although described each operation of in measuring instrument 140, carrying out in conjunction with independent processor, but the some processors in the measuring instrument 140 also can be implemented in the single processor, the resource of this single processor be share to carry out different operations at different time.Perhaps, all processors in the measuring instrument 140 are realized by single processor, this single processor is the shared resource between the performed different operating of measuring instrument, thereby measuring instrument 140 can be embodied as the computer that utilizes CPU (CPU) to carry out all operations.

Phase Processing device 310a, 310b are transformed to input voltage and electric current V with the measured value of the voltage and current that transducer 132 is sensed _In(f1), I _In(f1), V _In(f2), I _In(f2).Therefore, for the reason of claim, Phase Processing device 310a, 310b can be considered to the part of transducer 132, thus the output V of Phase Processing device 310a, 310b _In(f1), I _In(f1), V _In(f2), I _In(f2) be considered to measuring voltage and electric current from transducer 132.In fact, in some cases, can remove or bypass Phase Processing device 310.

The calculating of wafer voltage frequency component has greatly been simplified in the use of storage constant K 1 (f1), K2 (f1), K1 (f2), K2 (f2), its with this computational short cut be the simple multiplication of sense current and voltage and corresponding constant and resulting product add with.This makes and there is no need Measurement Phase to determine wafer voltage.

Some advantage of the present invention

The present invention can be used in the etch processes Johnson-Raybeck electrostatic chuck (ESC) (promptly, the chuck type of in Figure 1A, describing), with control wafer dc voltage accurately, thereby bias power can be increased to be in the capacity (for example 10kW) of the ESC that very high chip temperature (for example 60 degrees centigrade) locates, with the more straight etch profile characteristic of realization under low-down constant pressure strong (for example 5mT), thereby obtain better etching selectivity.Heat conduction from wafer is regulated by the control static power of clamping down on, as mentioned above.If do not have the accurate measurement and the control of wafer dc voltage provided by the present invention, then the high like this wafer bias power of operation has following risk: promptly the error in the wafer dc voltage may cause one of two kinds of catastrophic event: (1) is if the DC wafer voltage is too little, then wafer may be clamped down on inadequately, thereby its temperature rises out of control or wafer and ESC disengaging; (2) if the DC wafer voltage is too big, then wafer may be clamped down on excessively, causes handling owing to the DC wafer current is excessive failure.Problem is, although Johnson-Raybeck ESC can tolerate the very high wafer bias power level (for example 10kW) under the low constant pressure strong (for example 5-10mT) and can not cause puncture, the very rapid wear but its insulating barrier becomes under the required high temperature of etching, thereby require more bias power to keep given DC wafer voltage, this causes higher wafer current.Before the present invention, this problem has to can allow limit to be avoided by restriction chip temperature or wafer bias voltage (or both) to prevent that any error in the wafer dc voltage from surpassing.Utilize the present invention, with fully harmless mode real time monitoring wafer dc voltage (and electric current) accurately.Utilization is to the Control and Feedback of bias power level, can be so that wafer dc voltage and (causing thus) wafer be clamped down on voltage near allowing limit (promptly, clamp down on voltage near maximum wafer current limit or near minimum), and do not have a possibility of any these limits of violation, this be by accurate wafer dc voltage of the present invention measure and RF bias power level between real-time feedback control system prevent.As a result, bias power can increase to the very high level (for example 10kW) that is under high chip temperature (for example 60 degrees centigrade) and the relatively low constant pressure strong (for example 5mT).These process parameter values define new high-performance etch processes window, and this window has only the present invention just can obtain.

Although by having described the present invention, should be appreciated that under the prerequisite that does not break away from true spirit of the present invention and scope and can change and revise with reference to certain preferred embodiment.

Claims

1. plasma reactor comprises:

Vacuum chamber and the described indoor electrostatic chuck that is used to support wafer to be processed, and electrostatic chuck supply-voltage source;

Be used for being fed to described indoor processing gas access with handling gas;

Supply of plasma rf bias power and radio-frequency power path, described radio-frequency power path has the input that is coupled to the supply of described plasma rf bias power and is coupled to the output of described electrostatic chuck, and the measuring voltage of the input vicinity of representing described radio-frequency power path and the sensor circuit of the measuring-signal of measuring electric current are provided;

Be used to provide wafer voltage Signal Processing device, described wafer voltage signal be described measuring voltage and described measurement electric current be multiplied by respectively adding of first coefficient and second coefficient and, described wafer voltage signal is represented the voltage on the wafer of described electrostatic chuck upper support; And

The direct current supply voltage of controlling described electrostatic chuck is clamped down on the feedback control loop of voltage with management, describedly clamps down on poor between the voltage of described supply-voltage source that voltage comprises the DC component of described wafer voltage signal and described electrostatic chuck.

2. reactor as claimed in claim 1, wherein said feedback control loop make that described to clamp down on the difference that voltage and target clamp down between the voltage minimum.

3. reactor as claimed in claim 2 also comprises being used for selecting described target to clamp down on the controller of voltage according to the expectation chip temperature.

4. reactor as claimed in claim 1, wherein said radio-frequency power path comprises coaxial transmission line, and described first coefficient and second coefficient comprise voltage coefficient and current coefficient corresponding to the equation for transmission line of described coaxial transmission line respectively.

5. reactor as claimed in claim 4, wherein:

Described electrostatic chuck comprises the conductive grid of the output that is coupled to described coaxial transmission line;

Each comprises such factor in described first coefficient and second coefficient, and the described factor comprises that grid is to the wafer impedance Z _WaferArrive the ground impedance Z with grid _GridBetween the ratio.

6. reactor as claimed in claim 1 also comprises being respectively applied for first application specific processor and second application specific processor that described first coefficient and second coefficient are provided.

7. plasma reactor comprises:

Vacuum chamber and comprise the described indoor electrostatic chuck that is used for the support that wafer supports;

Be used for the plasma rf bias power supply that supply comprises the rf bias power of first frequency component f (1) and second frequency component f (2) respectively, and have the input that is coupled to the supply of described plasma rf bias power and be coupled to the radio-frequency power path of the output of described electrostatic chuck, and provide the described radio-frequency power of representative path the input vicinity measuring voltage first frequency component and second frequency component and measure the first frequency component of electric current and the sensor circuit of the measuring-signal of second frequency component;

Be used to provide the first frequency component of wafer voltage signal and the processor of second frequency component, the first frequency component of described wafer voltage signal and second frequency component be respectively described measuring voltage and the first frequency component of measuring electric current be multiplied by respectively that first of first coefficient and second coefficient adds and and described measuring voltage and the second frequency component of measuring electric current are multiplied by respectively that second of tertiary system number and Quaternary system number adds and; And

Be used for generating by the DC component of utilizing correction factor to make up the described first frequency component of described wafer voltage signal and second frequency component the processor of direct current wafer voltage, described correction factor comprises the product of the described DC component of the described first frequency component of the described wafer voltage that is lifted to selected power and is multiplied by selected coefficient and second frequency component.

8. reactor as claimed in claim 7, wherein said selected power is about 0.5, and described selected coefficient is about 0.3.

9. reactor as claimed in claim 7, wherein said selected power is about 0.43, and described selected coefficient is about 1.

10. reactor as claimed in claim 7, wherein said wafer support comprise electrostatic chuck and are connected to the direct current supply-voltage source of described electrostatic chuck that described reactor also comprises:

The described direct current supply-voltage source of controlling described electrostatic chuck is clamped down on the feedback control loop of voltage with management, describedly clamps down on poor between the voltage of described direct current supply voltage that voltage comprises described direct current wafer voltage and described electrostatic chuck.

11. reactor as claimed in claim 10, wherein said feedback control loop make, and described to clamp down on the difference that voltage and target clamp down between the voltage minimum.

12. reactor as claimed in claim 11 also comprises being used for selecting described target to clamp down on the controller of voltage according to the expectation chip temperature.

13. reactor as claimed in claim 7, wherein said radio-frequency power path comprises coaxial transmission line, and wherein:

Described first coefficient and second coefficient comprise respectively corresponding to the first frequency voltage coefficient of the equation for transmission line of described coaxial transmission line and first frequency current coefficient; And

Described tertiary system number and Quaternary system number comprise respectively corresponding to the second frequency voltage coefficient of the equation for transmission line of described coaxial transmission line and second frequency current coefficient.

14. reactor as claimed in claim 13, wherein:

Described first adds and comprised the first frequency component Z of grid to the wafer impedance by being multiplied by in described processor _Wafer(f1) and grid to ground impedance first frequency component Z _GridThe correction factor of the ratio (f1); And

Described second adds and comprised the second frequency component Z of grid to the wafer impedance by being multiplied by in described processor _Wafer(f2) and grid to ground impedance second frequency component Z _GridThe correction factor of the ratio (f2).

15. reactor as claimed in claim 14, wherein said processor comprise the transmission line transform processor that is used to generate described first frequency voltage coefficient, second frequency voltage coefficient and first frequency current coefficient, second frequency current coefficient, be used to generate described first frequency component and second frequency component grid to the ground impedance Z _Grid(f1), Z _Grid(f2) grid is to the ground transform processor and be used to generate described first frequency component and second frequency component grid to the wafer impedance Z _Wafer(f1), Z _Wafer(f2) grid is to the wafer transform processor.

16. reactor as claimed in claim 7, wherein said first frequency component is corresponding to the low frequency of a few MHz magnitudes, described second frequency component is corresponding to the high frequency that is about the 10MHz magnitude, and described correction factor has compensated the inter-modulation between described first and second frequency components.