KR20160141735A - 캐시 오염을 감소시키기 위해서 전용 캐시 세트들에서의 경합 전용 프리페치 정책들에 기초한 적응형 캐시 프리페칭 - Google Patents

캐시 오염을 감소시키기 위해서 전용 캐시 세트들에서의 경합 전용 프리페치 정책들에 기초한 적응형 캐시 프리페칭 Download PDF

Info

Publication number
KR20160141735A
KR20160141735A KR1020167027328A KR20167027328A KR20160141735A KR 20160141735 A KR20160141735 A KR 20160141735A KR 1020167027328 A KR1020167027328 A KR 1020167027328A KR 20167027328 A KR20167027328 A KR 20167027328A KR 20160141735 A KR20160141735 A KR 20160141735A
Authority
KR
South Korea
Prior art keywords
cache
dedicated
prefetch
miss
policy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020167027328A
Other languages
English (en)
Korean (ko)
Inventor
3세 하롤드 웨이드 케인
데이비드 존 팔프라만
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20160141735A publication Critical patent/KR20160141735A/ko
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28—Using a specific disk cache architecture
    • G06F2212/283—Plural cache memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/602—Details relating to cache prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6024—History based prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6042—Allocation of cache space to multiple users or processors
    • G06F2212/6046—Using a specific cache allocation policy other than replacement policy
    • Y02B60/1225—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020167027328A 2014-04-04 2015-04-02 캐시 오염을 감소시키기 위해서 전용 캐시 세트들에서의 경합 전용 프리페치 정책들에 기초한 적응형 캐시 프리페칭 Withdrawn KR20160141735A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/245,356 2014-04-04
US14/245,356 US20150286571A1 (en) 2014-04-04 2014-04-04 Adaptive cache prefetching based on competing dedicated prefetch policies in dedicated cache sets to reduce cache pollution
PCT/US2015/024030 WO2015153855A1 (en) 2014-04-04 2015-04-02 Adaptive cache prefetching based on competing dedicated prefetch policies in dedicated cache sets to reduce cache pollution

Publications (1)

Publication Number Publication Date
KR20160141735A true KR20160141735A (ko) 2016-12-09

Family

ID=53039591

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020167027328A Withdrawn KR20160141735A (ko) 2014-04-04 2015-04-02 캐시 오염을 감소시키기 위해서 전용 캐시 세트들에서의 경합 전용 프리페치 정책들에 기초한 적응형 캐시 프리페칭

Country Status (6)

Country Link
US (1) US20150286571A1 (enExample)
EP (1) EP3126985A1 (enExample)
JP (1) JP2017509998A (enExample)
KR (1) KR20160141735A (enExample)
CN (1) CN106164875A (enExample)
WO (1) WO2015153855A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180117463A (ko) * 2017-04-19 2018-10-29 서울시립대학교 산학협력단 데이터 처리 장치 및 데이터 처리 방법

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9519549B2 (en) * 2012-01-11 2016-12-13 International Business Machines Corporation Data storage backup with lessened cache pollution
US10117058B2 (en) 2016-03-23 2018-10-30 At&T Intellectual Property, I, L.P. Generating a pre-caching schedule based on forecasted content requests
US10223278B2 (en) * 2016-04-08 2019-03-05 Qualcomm Incorporated Selective bypassing of allocation in a cache
EP3239848A1 (en) * 2016-04-27 2017-11-01 Advanced Micro Devices, Inc. Selecting cache aging policy for prefetches based on cache test regions
US10509732B2 (en) 2016-04-27 2019-12-17 Advanced Micro Devices, Inc. Selecting cache aging policy for prefetches based on cache test regions
US10740260B2 (en) * 2016-05-12 2020-08-11 Lg Electronics Inc. Cache self-clean engine
US10430349B2 (en) * 2016-06-13 2019-10-01 Advanced Micro Devices, Inc. Scaled set dueling for cache replacement policies
US9928176B2 (en) 2016-07-20 2018-03-27 Advanced Micro Devices, Inc. Selecting cache transfer policy for prefetched data based on cache test regions
US10055158B2 (en) * 2016-09-22 2018-08-21 Qualcomm Incorporated Providing flexible management of heterogeneous memory systems using spatial quality of service (QoS) tagging in processor-based systems
KR102671073B1 (ko) * 2016-10-06 2024-05-30 에스케이하이닉스 주식회사 반도체장치
US11182306B2 (en) * 2016-11-23 2021-11-23 Advanced Micro Devices, Inc. Dynamic application of software data caching hints based on cache test regions
CN110018971B (zh) * 2017-12-29 2023-08-22 华为技术有限公司 缓存替换技术
CN110765034B (zh) 2018-07-27 2022-06-14 华为技术有限公司 一种数据预取方法及终端设备
CN111124955B (zh) * 2018-10-31 2023-09-08 珠海格力电器股份有限公司 一种高速缓存控制方法及设备和计算机存储介质
US20210182214A1 (en) * 2019-12-17 2021-06-17 Advanced Micro Devices, Inc. Prefetch level demotion
CN111723058B (zh) 2020-05-29 2023-07-14 广东浪潮大数据研究有限公司 一种预读数据缓存方法、装置、设备及存储介质
CN114297100B (zh) * 2021-12-28 2023-03-24 摩尔线程智能科技(北京)有限责任公司 用于缓存的写策略调整方法、缓存装置及计算设备
US11947461B2 (en) 2022-01-10 2024-04-02 International Business Machines Corporation Prefetch unit filter for microprocessor
CN115495681B (zh) * 2022-09-01 2025-12-09 北京达佳互联信息技术有限公司 缓存更新方法、装置、电子设备及计算机可读存储介质
US20250181510A1 (en) * 2023-12-03 2025-06-05 Mellanox Technologies, Ltd. Prune policies

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5732242A (en) * 1995-03-24 1998-03-24 Silicon Graphics, Inc. Consistently specifying way destinations through prefetching hints
US6243791B1 (en) * 1998-08-13 2001-06-05 Hewlett-Packard Company Method and architecture for data coherency in set-associative caches including heterogeneous cache sets having different characteristics
US6496902B1 (en) * 1998-12-31 2002-12-17 Cray Inc. Vector and scalar data cache for a vector multiprocessor
JP3812258B2 (ja) * 2000-01-13 2006-08-23 株式会社日立製作所 キャッシュ記憶装置
US6529998B1 (en) * 2000-11-03 2003-03-04 Emc Corporation Adaptive prefetching of data from a disk
US7146467B2 (en) * 2003-04-14 2006-12-05 Hewlett-Packard Development Company, L.P. Method of adaptive read cache pre-fetching to increase host read throughput
US7228387B2 (en) * 2003-06-30 2007-06-05 Intel Corporation Apparatus and method for an adaptive multiple line prefetcher
US20060174228A1 (en) * 2005-01-28 2006-08-03 Dell Products L.P. Adaptive pre-fetch policy
US20070239940A1 (en) * 2006-03-31 2007-10-11 Doshi Kshitij A Adaptive prefetching
JP4491500B2 (ja) * 2007-01-30 2010-06-30 富士通株式会社 演算処理装置、情報処理装置及び演算処理装置の制御方法
US7917702B2 (en) * 2007-07-10 2011-03-29 Qualcomm Incorporated Data prefetch throttle
US7899996B1 (en) * 2007-12-31 2011-03-01 Emc Corporation Full track read for adaptive pre-fetching of data
CN101236530B (zh) * 2008-01-30 2010-09-01 清华大学 高速缓存替换策略的动态选择方法
US8250303B2 (en) * 2009-09-30 2012-08-21 International Business Machines Corporation Adaptive linesize in a cache
US8307164B2 (en) * 2009-12-15 2012-11-06 International Business Machines Corporation Automatic determination of read-ahead amount
CN101763226B (zh) * 2010-01-19 2012-05-16 北京航空航天大学 一种虚拟存储设备的缓存方法
CN101866318B (zh) * 2010-06-13 2012-02-22 北京北大众志微系统科技有限责任公司 一种高速缓存替换策略的管理系统及方法
US8850123B2 (en) * 2010-10-19 2014-09-30 Avago Technologies General Ip (Singapore) Pte. Ltd. Cache prefetch learning
US11494188B2 (en) * 2013-10-24 2022-11-08 Arm Limited Prefetch strategy control for parallel execution of threads based on one or more characteristics of a stream of program instructions indicative that a data access instruction within a program is scheduled to be executed a plurality of times

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180117463A (ko) * 2017-04-19 2018-10-29 서울시립대학교 산학협력단 데이터 처리 장치 및 데이터 처리 방법

Also Published As

Publication number Publication date
CN106164875A (zh) 2016-11-23
EP3126985A1 (en) 2017-02-08
US20150286571A1 (en) 2015-10-08
JP2017509998A (ja) 2017-04-06
WO2015153855A1 (en) 2015-10-08

Similar Documents

Publication Publication Date Title
KR20160141735A (ko) 캐시 오염을 감소시키기 위해서 전용 캐시 세트들에서의 경합 전용 프리페치 정책들에 기초한 적응형 캐시 프리페칭
US10353819B2 (en) Next line prefetchers employing initial high prefetch prediction confidence states for throttling next line prefetches in a processor-based system
US9201796B2 (en) System cache with speculative read engine
US9218286B2 (en) System cache with partial write valid states
US10169240B2 (en) Reducing memory access bandwidth based on prediction of memory request size
JP6599898B2 (ja) 中央処理装置（ｃｐｕ）搭載システム内の圧縮メモリコントローラ（ｃｍｃ）を使用したメモリ帯域圧縮の提供
US9558120B2 (en) Method, apparatus and system to cache sets of tags of an off-die cache memory
JP6859361B2 (ja) 中央処理ユニット（ｃｐｕ）ベースシステムにおいて複数のラストレベルキャッシュ（ｌｌｃ）ラインを使用してメモリ帯域幅圧縮を行うこと
EP3440552A1 (en) Selective bypassing of allocation in a cache
US10496550B2 (en) Multi-port shared cache apparatus
US20180173623A1 (en) Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compressed memory system to avoid stalling write operations
US11762660B2 (en) Virtual 3-way decoupled prediction and fetch
US20140244920A1 (en) Scheme to escalate requests with address conflicts
US11301250B2 (en) Data prefetching auxiliary circuit, data prefetching method, and microprocessor
KR20180103907A (ko) 태그 디렉터리 캐시들을 이용한 확장 가능 동적 랜덤 액세스 메모리(dram) 캐시 관리의 제공
US12099451B2 (en) Re-reference interval prediction (RRIP) with pseudo-LRU supplemental age information
US9311251B2 (en) System cache with sticky allocation
US10061698B2 (en) Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur
US20190034354A1 (en) Filtering insertion of evicted cache entries predicted as dead-on-arrival (doa) into a last level cache (llc) memory of a cache memory system
US9460018B2 (en) Method and apparatus for tracking extra data permissions in an instruction cache
KR20180113536A (ko) Dram(dynamic random access memory) 캐시 표시자 캐시들을 사용하는 스케일러블 dram 캐시 관리의 제공
US10067706B2 (en) Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system
JP5971036B2 (ja) 演算処理装置及び演算処理装置の制御方法
US12380026B2 (en) Optimizing cache energy consumption in processor-based devices
US20240176742A1 (en) Providing memory region prefetching in processor-based devices

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20160930

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination