KR20160132053A - Semiconductor device and method comprising thickened redistribution layers - Google Patents

Abstract

A method of fabricating a semiconductor package includes: forming a plurality of thick rebound line (RDL) traces electrically connected to a contact pad on a plurality of semiconductor dies on an active surface of a plurality of semiconductor dies; Singulating a plurality of semiconductor dies including a plurality of thick RDL traces; Mounting a plurality of semiconductor dies singulated over a temporary carrier, the active surface of the plurality of semiconductor dies being oriented away from the temporary carrier; Disposing the seal material over the plurality of thick RDL traces and over the temporary carrier over the active surface and at least four sides of each of the plurality of semiconductor dies; Forming vias through the seal material to expose at least one thick RDL trace of the plurality of thick RDL traces to the seal material; Removing the temporary carrier; And singulating the plurality of semiconductor dies.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device including a thick re-

Cross reference of related application

This application claims the benefit of U.S. Provisional Patent Application No. 61 / 950,743, filed Mar. 10, 2014, entitled " Wafer-Level-Chip-Scale-Packages with Thick Redistribution Layer Traces "; This application is also a continuation-in-part of U.S. Serial No. 14 / 584,978, filed on December 29, 2014, entitled " Die Up Fully Molded Fan-Out Wafer Level Packaging " This application is a continuation-in-part of U.S. Application No. 14 / 024,928 filed on March 12 and entitled " Die Up Fully Molded Fan-Out Wafer Level Packaging ", filed on September 30, 2012, No. 13 / 632,062, entitled " Die Up Fully Molded Fan-Out Wafer Level Packaging ", filed on December 30, 2011 and now filed as U.S. Patent No. 8,604,600 Which is a continuation of part of U.S. Application No. 13 / 341,654 entitled " Fully Molded Fan-Out ", filed on July 18, 2012 and entitled " Fan-Out Semiconductor Package " Filing of application Ser. No. 61 / 672,860 The disclosures of which are incorporated herein by reference in their entirety.

The present invention relates generally to semiconductor devices and, more particularly, to panelized packaging for embedded semiconductor die packages including a thick redistribution layer (RDL).

Semiconductor devices are usually found in modern electronics. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally include one type of electrical component, such as a light emitting diode (LED), a small signal transistor, a resistor, a capacitor, an inductor, and a metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically include hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCD), solar cells, and digital micro-mirror devices (DMDs).

Semiconductor devices perform a wide variety of functions such as signal processing, high speed computation, sending and receiving electromagnetic signals, controlling electronic devices, converting electricity to sunlight, and creating visual projections for television display. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, the aircraft industry, automotive, industrial controllers, and office equipment.

Semiconductor devices utilize the electrical properties of semiconductor materials. The atomic structure of the semiconductor material allows its electrical conductivity to be manipulated by application of an electric field or base current or through a doping process. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.

Semiconductor devices include active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying the doping level and the application level of the electric field or base current, the transistor promotes or limits the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create the relationship between voltage and current required to perform a variety of electrical functions. The passive and active structures are electrically connected to form a circuit, which allows the semiconductor device to perform high speed calculations and other useful functions.

Semiconductor devices are generally fabricated using two complex manufacturing processes: front-end manufacturing and back-end manufacturing, with each process potentially involving hundreds of steps . Front end fabrication entails the formation of a plurality of semiconductor dies on the surface of a semiconductor wafer. Each semiconductor die is typically the same and includes circuitry formed by electrically connecting the active and passive components. Back-end fabrication involves singulating individual semiconductor dies from the finished wafer and packaging the die to provide structural support and environmental isolation. The term "semiconductor die" as used herein refers to both the singular and plural versions of the word, and thus may refer to both a single semiconductor device and a plurality of semiconductor devices.

One purpose of semiconductor fabrication is to fabricate smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be manufactured more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller final products. Smaller semiconductor die sizes may be achieved by improvements in the front end process that result in semiconductor die with smaller and denser active and passive components. The back-end process can create a semiconductor device package with a smaller footprint by improving electrical interconnect and packaging materials.

One approach to backend processing to more efficiently manufacture packaged semiconductor devices is the use of panel-type packaging where a plurality of semiconductor dies are formed in the panel and processed simultaneously at the level of the reconstructed wafer or panel. Panel-type packaging can be used to form an embedded die package in backend manufacturing. One type of panel-type packaging used to package semiconductor die is FOWLP. FOWLP involves placing a plurality of semiconductor die "facedown" or placing the active surface of the semiconductor die in a state oriented toward a temporary carrier or substrate such as a temporary tape carrier. The semiconductor die and the substrate or carrier are overmolded into encapsulants, such as epoxy molding compounds, for example, using a compression molding process. After molding, the carrier tape is removed to expose the active surfaces of the plurality of semiconductor die formed together as the reconstituted wafer. Subsequently, a wafer level chip scale package (WLCSP) build-up interconnect structure, typically comprising a redistribution layer (RDL), is formed on top of the reconstituted wafer or panel. A conductive bump is then formed over the build-up interconnect structure as a ball grid array (BGA) attached to the reconstituted wafer. After formation of the BAG, the reconstituted wafers are singulated to form individual semiconductor devices or packages.

Thus, in one aspect, the present invention provides a method of manufacturing a semiconductor device comprising a step of forming a plurality of thick rewiring layer (RDL) traces electrically connected to contact pads on a plurality of semiconductor dies on an active surface of a plurality of semiconductor dies, Package manufacturing method. A plurality of semiconductor dies including a plurality of thick RDL traces may be singulated. A plurality of singulated semiconductor dies may be mounted on a temporary carrier, wherein the active surface of the plurality of semiconductor dies is oriented away from the temporary carrier. The seal material may be disposed over a plurality of thick RDL traces, and on a temporary carrier, over the active surface and at least four sides of each of the plurality of semiconductor dies. Vias through the seal material can be formed to expose at least one thick RDL trace of a plurality of thick RDL traces relative to the seal material. The temporary carrier may be removed, and the plurality of semiconductor dies may be singulated.

A method of fabricating a semiconductor device includes forming a plurality of thick RDL traces comprising a thickness or height greater than 5 micrometers and forming vias through the seal material using laser ablation, The re-material may be a non-photoimagable material. The method may further include forming a plurality of thick RDL traces in the footprint of each of their respective semiconductor die as a fan-in structure for each of the plurality of semiconductor dies. The method includes forming an electrical interconnect that is coupled to at least one thick trace, the electrical interconnect extending out of the semiconductor package, and connecting the electrical interconnect to an under bump metallization (UBM) pad, a land grid array (LGA) Pad, a quad-flat non-leads (QFN) pad, or a bump. The method may further include the step of directly attaching the electrical interconnect to a plurality of thick RDL traces. The method may also include forming a backside epoxy coating or dielectric film on the backside of the plurality of semiconductor die opposite the active surface.

In another aspect, the present invention is a method of manufacturing a semiconductor package comprising forming a plurality of thick RDL traces on an active surface of a semiconductor die, wherein the plurality of thick RDL traces are connected to contact pads on the active surface of the semiconductor die have. The seal material may be disposed over the active surface and at least four sides of the semiconductor die and over a plurality of thick RDL traces. At least one thick RDL trace of a plurality of thick RDL traces may be exposed to the seal material. Electrical interconnects may be formed and coupled to at least one thick trace.

A method of fabricating a semiconductor device includes forming a plurality of thick RDL traces comprising a thickness or height of greater than 5 micrometers and forming a plurality of thick RDL traces on the plurality of thick RDL traces, Forming a via through the seal material using a sealant, wherein the sealant material is a non-photoimageable material. The method includes forming a plurality of thick RDL traces comprising a thickness or height greater than 20 micrometers so that the height of the thick RDL traces is greater than the minimum width of the thick RDL traces and forming a plurality of thick RDL traces Exposing at least one thick RDL trace of the trace by grinding. The method may further comprise forming a plurality of thick RDL traces for each of the plurality of semiconductor dies in a respective footprint of the respective semiconductor die. The method includes forming an electrical interconnect that is coupled to at least one thick trace, wherein the electrical interconnect extends out of the semiconductor package, and forming the electrical interconnect as a UBM pad, an LGA pad, a QFN pad, or a bump Step < / RTI > The method may further comprise forming a fan-out build-up interconnect structure disposed between the thick RDL trace and the electrical interconnect. The method may further comprise forming a backside epoxy coating or dielectric film on the backside of the plurality of semiconductor die opposite the active surface. The method may further include placing the seal material over the active surface and at least four sides of the semiconductor die in a single step and over a plurality of thick RDL traces. The method includes forming a plurality of thick RDL traces on an active surface of a semiconductor die, the semiconductor die being part of a native semiconductor wafer; And isolating a semiconductor die comprising a plurality of thick RDL traces from the native wafer.

In another aspect, the present invention provides a lithographic apparatus comprising: a plurality of thick RDL traces disposed on an active surface of a semiconductor die and disposed within a footprint of a semiconductor die; A seal material disposed over the active surface, on at least four sides of the semiconductor die, and over a plurality of thick RDL traces; And a conductive interconnect coupled to a portion of the at least one thick RDL trace of the plurality of thick RDL traces, wherein at least a portion of the at least one thick RDL trace of the plurality of thick RDL traces is exposed to the seal material May be a semiconductor package.

The semiconductor package may further include a plurality of thick RDL traces including a thickness or height of greater than 5 micrometers. The plurality of thick RDL traces may include a thickness or height greater than the width. A plurality of thick RDL traces may be placed in the footprint of the semiconductor die. A backside epoxy coating or dielectric film may be formed on the backside of the semiconductor die opposite the active surface.

The foregoing and other aspects, features, and advantages will be apparent to those skilled in the art from the following detailed description and drawings, and from the claims.

FIGS. 1A through 1E illustrate a plurality of semiconductor dies including a thick conductive RDL trace for use in a semiconductor package or an embedded die package, in accordance with an embodiment of the invention.
Figures 2a-2g illustrate views of a method of forming a semiconductor package or embedded die package including a thick conductive RDL trace.
3 shows a side cross-sectional view of one embodiment of a semiconductor package including a thick conductive RDL trace.
4 shows a side cross-sectional view of another embodiment of a semiconductor package including a thick conductive RDL trace.
5A-5D illustrate views of a method of forming a semiconductor package or embedded die package including a thick conductive RDL trace.
Figure 6 shows a side cross-sectional view of another embodiment of a semiconductor package including a thick conductive RDL trace.
Figure 7 shows a side cross-sectional view of another embodiment of a semiconductor package including a thick conductive RDL trace.
8 shows a side cross-sectional view of another embodiment of a semiconductor package including a thick conductive RDL trace.
Figure 9 shows a side cross-sectional view of another embodiment of a semiconductor package including a thick conductive RDL trace.
10 shows a side cross-sectional view of another embodiment of a semiconductor package including a thick conductive RDL trace.
11 shows a side cross-sectional view of another embodiment of a semiconductor package including a thick conductive RDL trace.
Figure 12 shows a side cross-sectional view of another embodiment of a semiconductor package including a thick conductive RDL trace.

The present invention includes one or more embodiments in the following description with reference to the drawings in which like numerals represent like or similar elements. The description is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the present invention as defined by the following claims and appended claims, Will be understood by those skilled in the art.

In the following description, numerous specific details are set forth, such as specific configurations, compositions, and processes, in order to provide a thorough understanding of the present invention. In other instances, well-known process and manufacturing techniques have not been described in detail to avoid unnecessarily obscuring the present invention. In addition, the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

The terms " over, "" between, " and "on ", as used herein, refer to the relative location of one layer to another layer. One layer deposited or disposed on or under another layer may be in direct contact with another layer, or it may have one or more intervening layers. One layer deposited or disposed between the layers may be in direct contact with the layers, or may have one or more intervening layers. In contrast, the first layer of the second layer "on " contacts the second layer.

Semiconductor devices are generally fabricated using two complex manufacturing processes: front-end fabrication and back-end fabrication. Front end fabrication involves the formation of a plurality of dies on the surface of a semiconductor wafer. Each die on the wafer includes active and passive electrical components that are electrically connected to form a functional electrical circuit. Active electrical components such as transistors and diodes have the ability to control the flow of electrical current. Passive electrical components such as capacitors, inductors, resistors, and transformers create the relationship between voltage and current required to perform electrical circuit functions.

The passive and active components are formed on the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process alters the electrical conductivity of the semiconductor material in the active device, converting the semiconductor material into an insulator, a conductor, or dynamically changing the semiconductor material conductivity in response to an electric field or a base current. The transistor includes regions of varying doping type and doping degree that are arranged as needed to enable the transistor to facilitate or limit the flow of electric current upon application of an electric field or base current.

The active and passive components are formed by a layer of material having different electrical properties. The layer may be formed by various deposition techniques, which are determined in part by the type of material being deposited. For example, thin film deposition may involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, and electroless plating processes. Each layer is typically patterned to form an active component, a passive component, or an electrical connection portion between the components.

The layer may be patterned using photolithography. Patterning is the basic operation that causes a portion of the top layer on the semiconductor wafer surface to be removed. Portions of the semiconductor wafer may be removed using photolithography, photomasking, masking, oxide or metal removal, photolithography and stenciling, and microlithography. Photolithography involves forming a pattern in a reticle or photomask, and transferring the pattern to a layer to be patterned, such as a surface layer of a semiconductor wafer. Photolithography forms the horizontal dimension of the active and passive components on the surface of the semiconductor wafer in a two-step process. First, a pattern on the reticle or mask is transferred to the layer of photoresist. Photoresists are photosensitive materials that undergo changes in structure and properties when exposed to light. The process of changing the structure and properties of the photoresist takes place either as a negative-acting photoresist or as a positive-acting photoresist. Second, the photoresist layer is transferred to the wafer surface. The transfer occurs when the etching removes a portion of the top layer of the semiconductor wafer that is not covered by the photoresist. Alternatively, some types of material are patterned by direct deposition of the material into regions or voids formed by photoresist or by a previous deposition / etch process using techniques such as electroless and electrolytic plating. The chemistry of the photoresist is such that the photoresist remains substantially intact and that a portion of the top layer of the semiconductor wafer that is not covered by the photoresist is removed or added to the chemical etching solution or plating chemistry To be able to withstand the removal by. The process of forming, exposing, and removing photoresist as well as the process of removing a portion of the semiconductor wafer or adding a portion of the wafer may vary depending on the particular resist used and the desired result.

In a negative working photoresist, the photoresist is exposed to light and is changed from a soluble state to an insoluble state in a process known as polymerization. During polymerization, the unpolymerized material is exposed to light or an energy source, and the polymer forms a cross-linking material resistant to etching. In most negative resists, the polymer is polyisoprene. Removing the soluble portion (i.e., the portion not exposed to light) with a chemical solvent or developer leaves a hole in the resist layer corresponding to the opaque pattern on the reticle. A mask in which a pattern is present in an opaque region is referred to as a clear-field mask.

In positive working photoresists, the photoresist is exposed to light and is changed from a relatively insoluble state to a much more soluble state in processes known as photosolubilization. Upon photolysis, a relatively insoluble resist is exposed to suitable light energy and is converted to a more soluble state. The photodegraded portion of the resist can be removed by the solvent in the developing process. The basic positive photoresist polymer is a phenol-formaldehyde polymer, also referred to as phenol-formaldehyde novolak resin. Removing the soluble portion (i.e., the portion exposed to light) with a chemical solvent or developer leaves a hole in the resist layer corresponding to the transparent pattern on the reticle. A mask in which a pattern exists in a transparent region is referred to as a dark-field mask.

After removal of the upper portion of the semiconductor wafer not covered by the photoresist, the residue of the photoresist is removed leaving a patterned layer behind.

Alternatively, photolithography can be accomplished without the use of a photoresist if the material to be patterned is itself photosensitive. In this case, the photosensitive material is coated on the device surface using spin coating, lamination, or other suitable deposition techniques. The pattern is then transferred from the photomask to the photosensitive material using light, typically in an operation referred to as exposure. In one embodiment, a portion of the light sensitive material to which light is applied is removed or developed using a solvent to expose a portion of the underlying layer. Alternatively, in another embodiment, a portion of the photosensitive material to which light is not applied is removed or developed using a solvent to expose a portion of the underlying layer. The remainder of the photosensitive film can be a permanent part of the device structure.

Depositing a thin film of material on top of the existing pattern can overestimate the underlying pattern and create a non-uniformly flat surface. A uniformly flat surface is needed to create smaller, more densely packed active and passive components. Planarization can be used to remove material from the surface of the wafer and to produce a uniformly flat surface. Planarization involves polishing the surface of the wafer with a polishing pad. Abrasive materials and corrosive chemicals are added to the surface of the wafer during polishing. Alternatively, mechanical abrasion is used for planarization without the use of corrosive chemicals. In some embodiments, pure mechanical polishing is accomplished by using a belt grinding machine, a standard wafer back grinder, a surface lapping machine, or other similar machine. The combination of the mechanical action of the abrasive and the corrosive action of the chemical removes any irregular topography resulting in a uniformly flat surface.

Back-end fabrication refers to packaging a semiconductor die for structural support and environmental isolation, followed by cutting or singulating the finished wafer into individual semiconductor die. To isolate a semiconductor die, the wafer may be cut along a non-functional region of the wafer, referred to as a saw street or scribe. The wafers are singulated using a laser cutting tool or a saw blade. After individualization, the individual semiconductor die is mounted on a package substrate comprising pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor die are then connected to the contact pads in the package. Electrical connections may be made using solder bumps, stud bumps, conductive pastes, rewiring layers, or wire bonds. A sealant or other molding material is deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into the electrical system, and the functionality of the semiconductor device becomes available to other system components.

The electrical system may be a stand-alone system that performs one or more electrical functions using the semiconductor device. Alternatively, the electrical system may be a subcomponent of a larger system. For example, the electrical system may be part of a cellular phone, a personal digital assistant (PDA), a digital video camera (DVC), or other electronic communication device. Alternatively, the electrical system may be a graphics card, a network interface card, or other signal processing card that may be inserted into the computer. The semiconductor package may include a microprocessor, memory, application specific integrated circuit (ASIC), logic circuit, analog circuit, RF circuit, discrete device, or other semiconductor die or electrical component. Miniaturization and weight reduction are essential to ensure that products are accepted in the market. The distance between the semiconductor devices must be reduced to achieve a higher density.

By combining one or more semiconductor packages on a single substrate, the manufacturer can incorporate prebuilt components into electronic devices and systems. Because semiconductor packages include sophisticated functionality, electronic devices can be fabricated using less expensive components and simplified manufacturing processes. The resulting device is less likely to fail, less expensive to manufacture and lower cost for the consumer.

In the following discussion, certain embodiments are described with respect to the formation of a single die FOWLP, although embodiments of the invention are not so limited. Embodiments of the present invention may be implemented in a single die application, multiple die module, printed wiring board panel or die embedded in a PCB, some combination of die (s) and passive component (s) in a module, And some combination of other component (s) within the module. In an aspect, embodiments of the present invention may eliminate or reduce the yield loss of a package or module assembly caused by misalignment of a device unit or other component during paneling. In another aspect, embodiments of the present invention may maintain the provisions of the package or module outline and may not require a change in the position of the UBM pad or BGA ball. Maintaining the provisions of the package or module outline can be continuously achieved in the end product, for example as a final product package, test socket, and the like. In another aspect, embodiments of the present invention may allow for a smaller bond pad opening on the device unit.

Figure la shows a top view of a semiconductor wafer 20 having unlimited base substrate material 22 for structural support, e.g., silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide. A plurality of semiconductor dies or components 24 are formed on the wafer 20 separated by an inert die-to-die wafer area or saw-street 26 as described above. Saw Street 26 provides a cutting area for singulating semiconductor wafers 20 into individual semiconductor dies 24.

FIG. 1B shows a cross-sectional view of a portion of the semiconductor wafer 20 already shown in the plan view of FIG. 1A. Each semiconductor die 24 has a back surface 28 and an active surface 30 opposite the back surface. The active surface 30 includes analog or digital circuitry embodied as active devices, passive devices, conductive layers, and dielectric layers formed in the die and electrically interconnected according to the electrical design and function of the semiconductor die. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 30 to implement analog or digital circuitry such as a DSP, ASIC, memory, or other signal processing circuitry . The semiconductor die 24 may also include an integrated passive device (IPD) such as inductors, capacitors, and resistors for RF signal processing.

The electrically conductive layer 32 is formed on the active surface 30 using PVD, CVD, electroplating, electroless plating, or other suitable metal deposition process. The conductive layer 32 may be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive material. The conductive layer 32 acts as a contact pad or bond pad electrically connected to circuitry on the active surface 30. The conductive layer 32 may be formed as a contact pad disposed side by side at a first distance from the edge of the semiconductor die 24 as shown in FIG. Alternatively, the conductive layer 32 may be patterned such that the contact pads of the first row are disposed a first distance from the edge of the die and the contact pads of the second row alternating with the first row are spaced a second distance from the edge of the die. May be formed as contact pads offset from the plurality of rows to be disposed. In another embodiment, the conductive layer 32 may be formed as a contact pad disposed in the array over the entire surface area of the semiconductor die 24. The entire array of contact pads may be formed in a regular or irregular pattern over the entire surface of the semiconductor die 24, depending on the configuration and design of the semiconductor die. Similarly, the size, shape, or orientation of the contact pads may also be irregular with respect to each other and include the length of the conductive material that traverses the signal transversely across the active surface 30 of the semiconductor die 24 .

1B also shows a selective isolation or passivation layer 36 formed over the active surface 30 of the semiconductor die 24. The insulating layer 36 may be conformally applied to the semiconductor die 24 and may have a bottom or first surface along its contour. The insulating layer 36 has an upper or second planar surface 37 opposite the first surface. The insulating layer 36 may be an organic or inorganic layer and may be formed of a photosensitive low temperature cure dielectric resist, a photosensitive composite resist, a laminate composite film, a solder mask resist film, a liquid molding compound, silicon dioxide (SiO2), silicon nitride (Si3N4) Nitride (SiON), aluminum oxide (Al2O3), or other materials having similar insulation and structural properties. The insulating layer 36 may be deposited using printing, spin coating, spray coating, lamination, or other suitable processes. A portion of the insulating layer 36 may be subjected to laser ablation, etching, or other suitable process to expose the bottom surfaces of the contact pads 32 and openings 38 of the semiconductor die 24, . The insulating layer 36 may be patterned to form an opening 38 that extends completely through the insulating layer 36, after which the insulating layer 36 may also optionally be cured.

Figure 1C illustrates an electrically conductive layer or RDL comprising a plurality of thick RDL traces 40 that may be formed using patterning and metal deposition processes such as sputtering, electroless plating, and electroless plating. The thick RDL trace 40 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material, including seeds, The thick RDL trace 40 may be electrically connected to the contact pad 32. Other portions of the thick RDL trace 40, such as individual RDL traces, may be electrically common or electrically isolated depending on the design and functionality of the semiconductor die 24.

Figure 1C illustrates one embodiment in which a thick RDL trace 40 may be formed by first depositing and patterning a temporary insulating or passivation layer 42. [ The insulating layer 42 may be conformally applied to the semiconductor die 24, the insulating layer 36, or both, and may have a first surface along their contour. The insulating layer 42 may have a second planar surface opposite the first surface. The insulating layer 42 may be an organic or inorganic layer and may be formed of a photosensitive low temperature cure dielectric resist, a photosensitive composite resist, a laminate composite film, a solder mask resist film, a liquid molding compound, SiO2, Si3N4, SiON, Al2O3, polyimide, And one or more layers of other materials having structural properties. The insulating layer 36 may be deposited using printing, spin coating, spray coating, lamination, or other suitable processes. The insulating layer 42 may be patterned to fully penetrate the insulating layer and, when present, form an opening through the insulating layer 36 to expose the contact pad 32. The insulating layer 36 can also optionally be cured and form part of the permanent structure of the final semiconductor package. Alternatively, the insulating layer 36 may be a temporary layer, such as a photoresist layer, and the temporary layer is subsequently removed to form a portion of the final structure of the semiconductor die. The insulating layer 42 may be deposited on and contacted the insulating layer 36, or on the semiconductor die 24 if the optional insulating layer 36 is omitted. A portion of the insulating layer 42 can be removed by a laser or, if it is a photoresist layer, exposed and removed by an etch process. The thick RDL trace 40 may then be formed in the removed portion of the insulating layer 42, and in the opening 38, if present. The openings in the openings 38 and the insulating layer 42 may be formed at the same time or at different times. The entire thick RDL trace 40 can be formed at the same time, or a portion of the conductive layer can be formed at different times. The insulating layer 42 may be removed after the formation of the thick RDL trace 40 is completed.

The completed thick RDL trace 40 may be a thick RDL layer that includes a plurality of thick RDL traces for routing electrical signals from the semiconductor die 24 to points outside the semiconductor package including the semiconductor die. The thickness or height of the thick RDL trace 40 is such that the thickness or height of the thick RDL trace 40 is at right angles to the x and y directions extending across the top surface of the wafer 20 including the active surface 30 of the semiconductor die 24, Or can be measured in the z direction perpendicular. The thickness or height of the thick RDL trace 40 may start at the top surface 37 of the insulating layer 36 and may be directed upward from the active surface or away from it in the opposite direction of the backside 28, (42) to form a thickness T2. Alternatively, the thickness or height of the thick RDL trace 40 may be initiated at the active surface 30 of the semiconductor die 24 and may be directed upward from the active surface or away from the backside 28, And may extend to the surface 42 to form the thickness T2. The thicknesses T1 and T2 may include a height of more than 4 micrometers (μm), or a height of 5, 10, 20, 30, or more than 35 micrometers. In some embodiments, the thick RDL trace 40 includes a thickness in the range of 4 to 35 or 5 to 30 占 퐉. The formation of the thick RDL trace 40 allows for a single process and structure to be achieved with a number of different processes and structures, such as the formation of separate rewiring layers and separate vertical interconnects, e.g., pillars or copper posts This provides the advantage.

1D, the semiconductor wafer 20 undergoes an optional grinding operation to planarize the surface of the semiconductor wafer with the grinder 46 and reduce its thickness. A chemical etch may also be used to remove and planarize the semiconductor wafer 20.

Figure 1e illustrates that after the final thickness of the semiconductor wafer 20 is achieved a selective insulating or passivation layer 50 is formed on the back or bottom surface of the wafer 20 to cover the backside 28 of the semiconductor die 24 Lt; / RTI > The insulating layer 50 may be an epoxy film, a thermal epoxy, an epoxy resin, a B-stage epoxy film, an ultraviolet (UV) B-stage film with optional acrylic polymer, a dielectric film, or other suitable material. The insulating layer 50 may be disposed over or entirely over the entire backside 28 of the semiconductor die 24 and may be in direct contact therewith so that the footprint of the semiconductor die 24 is substantially And may include the same footprint. 1E also shows that the semiconductor wafer 20 can be singulated into individual semiconductor dies 24 via saw streets 26 using saw blades or laser cutting tools 52 after application of the insulating layer 50 Lt; / RTI > Because the thick RDL traces 40 may be formed on the semiconductor die 24 before the semiconductor dies are singulated from their native semiconductor wafers 20, the thick RDL traces may be formed on the respective semiconductor die 24, May be formed as a fan-in interconnect structure that includes a footprint or region that is smaller than, or contained within, the region.

Figure 2a shows a temporary carrier or substrate 56 comprising a temporary or sacrificial base material such as silicon, polymer, stainless steel, or other suitable low cost hard material for structural support. An optional interfacial layer or double-sided tape 58 is formed on the carrier 56 as a temporary adhesive bonded film or etch-stop layer. In one embodiment, the carrier 56 may be a ring-shaped film frame that includes an open center portion that supports the tape 58 at the periphery of the tape. Alternatively, as shown in FIGS. 2A and 2B, the carrier 56 may be a flat plate without an open central region that supports the tape 58 over the top surface of the carrier 56. A plurality of reference alignment marks may be placed on or attached to the substrate 56 or interface layer 58 for use in properly positioning the semiconductor die 24 on the carrier 56. [ Alternatively, a portion of substrate 56 or interfacial layer 58 may be removed or marked to form a reference.

Figure 2a further illustrates that the semiconductor die 24 from Figure 1e is mounted face up in the carrier 56 and interface layer 58 with the backside 28 and the insulating layer < RTI ID = 0.0 > 50 are oriented toward the substrate, and the active surface 30 is oriented away from the carrier. Semiconductor die 24 may be placed on carrier 36 using pick and place operation or other suitable operation. The semiconductor die 24 is positioned relative to the reference 39 in accordance with a nominal or predetermined position and spacing for the semiconductor die. The semiconductor die 24 may be formed as part of the final semiconductor package by a space or gap 60 that may provide a region for a subsequent formed interconnect structure, such as a fan-out interconnect structure, And is mounted on the carrier 56 so that the semiconductor die is separated. The size of the gap 60 includes sufficient area for selectively mounting a semiconductor device or component in a subsequent formed semiconductor package.

FIG. 2B illustrates that the seal 62 is deposited using paste printing, compression molding, transfer molding, liquid seal molding, lamination, vacuum lamination, spin coating, or other suitable applicator. 2B illustrates a plurality of side walls 66 that are provided with a plate 65, a carrier 56, and an upper portion of the interface layer 58 for subsequent sealing to encapsulate the semiconductor die 24 within the mold. Lt; RTI ID = 0.0 > 64 < / RTI > The mold 64 may also include a bottom portion in which the carrier 56 is disposed and the side wall 66 can contact. In one embodiment, the carrier 56 and interface layer 58 may serve as a bottom mold portion for a subsequent sealing process. Alternatively, the semiconductor die 24, the carrier 56, and the interface layer 58 may be disposed in a mold that includes a plurality of portions such as an upper portion and a lower portion. The mold 64 is provided together by moving the mold 64 around the semiconductor die 24, or, alternatively, by moving the semiconductor die into the mold.

Fig. 2b further illustrates the mold 64 sealing the semiconductor die 24 into a cavity or open space 70. Fig. The cavity 70 extends between the mold 64 and the semiconductor die 24 and the interface layer 58. A predetermined volume of seal 62 is disposed over semiconductor die 24 and carrier 56. The inlet 68 may be a drain port that does not provide a leak path to the seal 62. Seal 62 may be a polymer composite, such as an epoxy resin with filler, an epoxy acrylate with filler, or a polymer with a suitable filler. The volume of the seal 62 is measured according to the spatial requirements of the cavity 60 below the area occupied by the semiconductor die 24 and any additional semiconductor devices that may be present. The seal 62 is disposed on its periphery above the semiconductor die 24 and between the side walls 64. Seal 62 may also be placed around it on the thick RDL trace 40 so that the same seam and stitching process is placed between the thick RDL traces of the RDL and among them the seams. The seal 62 is used to seal the semiconductor die 24 and the thick RDL trace 40 so that a single seal 62 can extend directly along the sides of the semiconductor die 24 and the thick RDL trace 40, And can contact the sidewalls of the RDL trace.

The upper portion 65 of the mold 64 is in contact with the sealing material 62 until the upper portion is in contact with the sealing material so as to evenly diffuse and evenly distribute the sealing material 62 within the cavity 70 around the semiconductor die 24. [ (S) 62 and the semiconductor die 24 along the sidewalls 66. The viscosity and high temperature of the seal 62 may be selected for uniform coverage, e.g., lower viscosity and higher temperature may increase the flow of seal material for molding, paste printing, and spin coating. The temperature of the seal 62 may also be controlled within the cavity 70 to facilitate curing of the seal. The semiconductor die 24 is embedded together in a seam 62 that is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.

The sacrificial release film is disposed in the cavity between the upper portion 65 of the cavity 70 and the sidewall 66 and the sealant 62 so that the sealant is applied to the upper portion of the cavity and to the side wall It can be prevented from adhering or adhering. If other types of molding, such as transfer molding, are used, the sacrificial release film may be omitted and the sealant 62 may comprise a mold release agent, or the inner surface of the cavity 70 may be treated with a mold releasing agent, Thereby preventing the ashes from adhering to the inner surface of the mold.

2C, the semiconductor die 24 is removed from the mold 64 having the sealing material 62 as a panel or embedded die panel 72. The panel 72 may optionally undergo a curing process to cure the sealant 62. The carrier 56 and the interfacial layer 58 may be formed by chemical etching, mechanical stripping, CMP, mechanical grinding, thermal bake, UV light, or the like to expose the backside 76 of the sealing material opposite the front side 78 of the sealing material 62. [ , Laser scanning, wet stripping, or other suitable process. In one embodiment, the seal 62 is partially or fully cured prior to removal of the carrier 56, interface layer 58, or both. Alternatively, the seal 62 may be partially or fully cured after the carrier 56, interface layer 58, or both sides have been removed.

The back surface 76 of the panel 72 may be substantially coplanar with the back surface 77 of the insulating layer 50. Both the back surface 76 and the back surface 77 can be exposed by removal of the carrier 56 and the interface layer 58. After removal of the carrier 56 and interfacial layer 58, Figure 2C shows the seal 62 disposed around the semiconductor die 24 within the embedded die panel 72. [ Panel 72 may include a form factor or footprint of any shape and size to allow and enable subsequent processing necessary to form a semiconductor package, as will be described in more detail below. As a non-limiting example, the panel 72 may include a form factor similar to that of a 300 millimeter (mm) semiconductor wafer and may include a circular footprint with a diameter of 300 mm. The panel 72 may also be of any other desired size and may include shapes or formats such as rectangles or squares. In one embodiment, the panel 72 may be one known in the art as a reconstituted wafer.

Figure 2c shows the panel 72 is removed to remove the surface 78 and expose a portion of the thick RDL trace 40, e.g., the surface 44 of the RDL trace, And may experience a grinding operation using a grinder 80 to reduce the thickness of the panel 72 to expose the new front surface 82 of the sealing material 62 or panel 72 that is coplanar with the surface 72 of the panel 72. [ Chemical etching can also be used to remove and planarize a portion of the seal 62 at the panel 72. [ The RDL trace 40 coupled to the contact pads 32 of the semiconductor die 24 is exposed to the sealing material 62 at the surface 82 of the panel 72 so that the semiconductor die 24 and subsequent Lt; RTI ID = 0.0 > semiconductor package. ≪ / RTI > The thickness of the sealing material 62 on the active surface 30 of the semiconductor die 24 is also less than the thickness of the sealing material 62 because the thickness of the sealing material 62 is reduced to expose the thick RDL traces 40, T1 or substantially the same as T1. The thickness of the insulating layer 50 disposed on or on the backside 28 of the semiconductor die 24 may also be formed to have the same or substantially the same thickness as the thickness T1 so that the backside 28 of the semiconductor die 24, The thickness of the insulating layer 50 disposed on the active surface 30 may be similar or equal to the final thickness of the sealing material 62 disposed on or above the active surface 30 to offset the package force and reduce warpage. have.

In embodiments in which a portion of the thick RDL trace 40 is exposed by grinding with the grinder 80, the thickness of the thick RDL trace 40 may be substantially equal to or within the range of 15 to 35 占 퐉 or 20 to 30 占 퐉 . In other embodiments where a portion of the thick RDL trace 40 is exposed by laser ablation, the thickness of the thick RDL trace 40, as discussed with respect to FIG. 5A, may be adjusted by grinding the thick RDL trace 40 May be less than the thickness of the thick RDL trace 40 when exposed. As a non-limiting example, the thickness of the thick RDL trace 40 may be substantially equal to or greater than 4 to 20 占 퐉 when the thick RDL trace 40 is exposed by laser ablation or other non- And may include thicknesses within the range. As used herein, substantially the same may include plus or minus 1 [mu] m, 2 [mu] m, or even 3 [mu] m, as well as less than 1 [mu] m of the thickness of the thick RDL trace 40. [

Figure 2D shows another embodiment in which the semiconductor die 24 from Figure IE can be mounted face down on the carrier 56 and interface layer 58 where the active surface 30 is oriented toward the carrier And the back surface 28 is oriented away from the carrier. Semiconductor die 24 may be placed on carrier 56 using pick-and-place motion or other suitable operation. The mounting of the semiconductor die 24 in a face-down configuration allows the thick RDL trace 40 to be formed on the semiconductor die 24 prior to placement of the semiconductor die over the carrier 36 or interface layer 38, 32 and connected to the top surface 44 of the thick RDL trace 40 and the active surface 30 of the semiconductor die 24 or the top surface 37 of the insulating layer 36 to form a sealant 62 May be advantageous in providing sufficient offsets to be placed within a predetermined thickness, height, or offset.

2D shows that the mold 64 may seal the semiconductor die 24 with the sealant 62 of a predetermined volume in a manner similar to that described above with respect to Fig. 2B by sealing the semiconductor die 24 with the cavity 70 Lt; / RTI >

2E, the semiconductor die 24 is removed from the mold 64 having the sealing material 62 as a panel or embedded die panel 92. Panel 72 may include a form factor or footprint of any shape and size to allow and enable subsequent processing necessary to form a semiconductor package, as will be described in more detail below. As a non-limiting example, the panel 72 may include a form factor similar to that of a 300 mm semiconductor wafer and may include a circular footprint with a diameter of 300 mm. The panel 72 may also be of any other desired size and may include shapes or formats such as rectangles or squares. In one embodiment, the panel 72 may be one known in the art as a reconstituted wafer.

The panel 92 may optionally undergo a curing process to cure the sealant 62. The carrier 56 and the interfacial layer 58 may be formed by chemical etching, mechanical peeling, CMP, mechanical grinding, thermal bake, UV light, or the like, to expose the front side 96 of the sealing material opposite the back side 98 of the sealing material 62. [ , Laser scanning, wet stripping, or other suitable process. In one embodiment, the seal 62 is partially or fully cured prior to removal of the carrier 56, interface layer 58, or both. Alternatively, the seal 62 may be partially or fully cured after the carrier 56, interface layer 58, or both sides have been removed.

2E shows that the front surface 96 of the panel 92 may be substantially coplanar with the surface 44 of the RDL trace 40 after removal of the carrier 56 and interface layer 58. [ The RDL trace 40 coupled to the contact pad 32 of the semiconductor die 24 is exposed to the sealing material 62 at the surface 96 of the panel 92 so that the semiconductor die 24 and subsequent Lt; RTI ID = 0.0 > semiconductor package. ≪ / RTI >

2E shows a panel 92 with a grinding operation 80 using a grinder 80 to reduce the thickness of the panel 92 to remove the surface 98 and expose a portion of the backside 28 of the semiconductor die 24 ≪ / RTI > Chemical etching can also be used to remove and planarize a portion of the seal 62 at the panel 72. [ Reducing the thickness of panel 92 may occur before or after removal of carrier 56 and tape 58. In some embodiments, the seal 62 may be in direct contact with the backside 28 of the semiconductor die 24, and the removal or grinding of the sealant to ensure that the sealant 62 of a certain thickness is placed on the backside 28 The sealing material 62 of a certain thickness may be left. In some embodiments, the thickness of the sealing material remaining on the backside 28 may be equal to or substantially equal to the thickness T1, or the thickness of the sealing material disposed on the active surface 30 of the semiconductor die. As such, the opposite thickness of the seal on the backside 28 and active surface 30 may be the same or substantially the same to balance the forces on the opposite sides of the subsequent formation package to reduce or minimize distortion in the package.

2F shows a top view of the build-up interconnect structure 106 over the panel 72 or on the panel 92 to provide electrical connection between the semiconductor die 24 and thick RDL trace 44 and a point outside the subsequent- Lt; / RTI > Thus, the processing shown subsequently to Figs. 2F and 2G can proceed from the panel 72 shown in Figs. 2B and 2C or from the panel 92 shown in Figs. 2D and 2E. However, for convenience, FIGS. 2F and 2G are described for panel 72. FIG. The build-up interconnect structure 106 may include a plurality of RDLs, including RDL traces, which may include portions of the fan-out interconnect structure. The build-up interconnect structure 106 may be formed by deposition and patterning of various insulating or passivation layers and deposition and patterning of various conductive layers.

2F illustrates the ratio of the build-up interconnect structures that can be applied conformally to the top surface 44 of the sealant 62 and the thick RDL trace 42 and to have a first surface along their contour, Limiting example. The insulating layer 108 may have a second planar surface opposite the first surface. The insulating layer 108 may be formed from any of a variety of materials including, but not limited to, photosensitive low temperature curable dielectric resists, photosensitive composite resist, liquid crystal polymer (LCP), laminate synthetic film, insulating paste with filler, solder mask resist film, liquid molding compound, Butene (BCB), polybenzoxazole (PBO), SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulation and structural properties. The insulating layer 108 may be deposited using printing, spin coating, spray coating, lamination, or other suitable processes. Insulating layer 108 may then be patterned and cured using UV exposure, development or other suitable process. A portion of the insulating layer 108 may be subjected to laser ablation, etching, or the like to form openings that expose portions of the upper surface 44 of the thick RDL trace 42, according to the configuration and design of the semiconductor die 24 and the final semiconductor package. Or other suitable process.

The electrically conductive layer 110 may be patterned and deposited over the thick RDL trace 42, the sealant 62, and the insulating layer 108, and may be in contact therewith. The conductive layer 110 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material and may include one or more of a seed layer, an adhesive layer, or a barrier layer. Deposition of the conductive layer 110 may utilize PVD, CVD, electroplating, electroless plating, or other suitable processes. The opening in the insulating layer 108 may extend completely through the insulating layer on the thick RDL trace 40. The conductive layer 110 may operate as an RDL that includes a plurality of RDL traces to help extend electrical connections from the semiconductor die 24 and the thick conductive RDL trace 40 to a point outside the semiconductor die 24. [ A portion of the conductive layer 110 formed in the opening in the insulating layer 108 may form a vertical interconnection structure or vias that penetrate the insulating layer 108 to provide electrical interconnection. Although a non-limiting example of the build-up interconnect structure 106 is shown in Figure 2f, which includes a single RDL 110, additional RDLs may also be used to connect the build-up interconnect structure < May be formed in the semiconductor die 106 to provide additional flexibility for routing signals between the semiconductor die 24 and a point external to the semiconductor die 24.

Figure 2f further illustrates that the insulating or passivation layer 112 is conformally applied to the insulating layer 108 and the conductive layer 110 and follows their contour. The insulating layer 112 may be formed of a material selected from the group consisting of photosensitive low temperature cure dielectric resist, photosensitive composite resist, LCP, laminate composite film, insulating paste with filler, solder mask resist film, liquid molding compound, particle forming compound, polyimide, BCB, PBO, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulation and structural properties. The insulating layer 112 may be deposited using printing, spin coating, spray coating, lamination, or other suitable processes. Insulating layer 112 may then be patterned and cured using UV exposure, development or other suitable processes. A portion of the insulating layer 112 may be removed by laser ablation, etching, or other suitable process to create an opening through the insulating layer to expose a portion of the conductive layer 110.

The electrically conductive layer 114 may be patterned and deposited over the conductive layer 110 and the insulating layer 112 and may contact them. Conductive layer 114 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Deposition of the conductive layer 114 may utilize PVD, CVD, electroplating, electroless plating, or other suitable processes. The opening in the insulating layer 112 in which the conductive layer 114 may be disposed may extend completely through the insulating layer on the conductive layer 110. At least a portion of the conductive layer 114 may be formed in the opening in the insulating layer 112 and may be formed by forming a vertical interconnection structure or via to provide electrical interconnection through the insulating layer 112, .

The conductive layer 114 may comprise a top portion or surface formed as a pad 116. The pad 116 includes a horizontal component that includes a region that is larger than the area of the opening formed in the insulating layer 112 such that the pad 116 of the conductive layer 114 extends over the top or top surface of the insulating layer 112 can do. The pad 116 of the conductive layer 114 may be an input / output (I / O) interconnect at the periphery of the completed semiconductor package. As such, the pad 116 may be formed as a UBM pad, which is between the signals transferred to the semiconductor die 24 and the package I / O interconnect, as described in more detail below with respect to FIG. 2G. Lt; / RTI > interface. Alternatively, the pad 116 may be formed as an LGA pad that is itself an I / O interconnect in the periphery of the completed semiconductor package and is not coupled to other I / O interconnects, such as, for example, solder bumps. Pad 116 may be a stack of multiple metal layers including adhesion, barrier, seed, and wet layer. The pad 116 may be formed of a material selected from the group consisting of Ti, titanium nitride (TiN), titanium tungsten (TiW), Al, Cu, Cr, CrCu, Ni, NiV, Pd, , Ag, or any other suitable material or combination of materials. In one embodiment, the pad 116 may comprise a TiW seed layer, a Cu seed layer, and a Cu UBM layer.

Figure 2g illustrates that the electrically conductive bump material is deposited over the pad 116, which may be a UBM pad, which acts as an intermediate conductive layer between the semiconductor die 24 and the subsequently formed solder bump or other I / O interconnect structure, Lt; / RTI > The pad 116 may include a conductive layer 110 and a UBM pad that provides a low resistance interconnect to the thick RDL trace 40 and may also provide increased barrier-solder diffusion and solder wettability. The electrically conductive bump material may be deposited on the pad 116 using evaporation, electrolytic plating, electroless plating, ball drop, or screen printing processes. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof with an optional flux solution. For example, the bump material may be eutectic Sn / Pb, high-lead solder, or solderless solder. The bump material may be bonded to the pad 116 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a spherical ball or bump 118. In some applications, the bump 118 is reflowed again to improve electrical contact to the pad 116. The bump 118 may also be compress bonded to the pad 116. Bump 118 represents one type of interconnect structure that may be formed on pad 116. Other interconnect structures, including conductive paste, stud bumps, micro bumps, or other electrical interconnections, may also be used. Additionally, the bumps 118 may be omitted to form a QFN package or an LGA package.

Figure 2g also shows that after the formation of a package I / O interconnect, such as bump 116, the panel or reconstructed wafer 72 is transferred to the respective semiconductor package or embedded die package < RTI ID = 0.0 > RTI ID = 0.0 > 122 < / RTI >

FIG. 3 illustrates an individual semiconductor package or embedded die package 122 fabricated by the process shown in FIGS. 1A-2G. Thus, the method illustrated in FIGS. 1A-2G and semiconductor package 122 illustrates a process wherein a thick RDL layer may comprise a fan-in build-up structure formed on and in contact with a semiconductor wafer or native device wafer. The thick RDL layer may comprise a plurality of RDL traces that include a thickness or height greater than or equal to 20 占 퐉 in the z-direction perpendicular to and extending away from the active surface of the semiconductor die. The thickness of the semiconductor wafer or native device wafer may also be reduced or thinned, for example, by a grinding process. An epoxy film (e.g., a solder mask laminate film or a die-attached epoxy film) can be applied on the back surface of the semiconductor wafer. The individual semiconductor die may be formed or separated from the semiconductor wafer by dicing the semiconductor wafer.

The device of Fig. 3 and the process shown in Figs. 1A-2G also indicate that the release film or tape can be applied to a temporary carrier or substrate. The plurality of semiconductor die may be disposed in the array in a face-up position in which the active surface of the semiconductor die is oriented away from the carrier, or alternatively in the face-down position, across the surface of the carrier. The spacing between the semiconductor dies mounted on the carrier may be sufficient to allow additional fan-out structures to be coupled into the semiconductor die while being formed in the final semiconductor package. The semiconductor die may be compression molded to seal at least four sides of the semiconductor die as well as the front side or active surface. The insulating layer or film may be disposed on the back side of the semiconductor die. The thickness of the film disposed on the backside of the semiconductor die may be similar or equal to the final thickness of the sealing material, epoxy mold compound, or laminate film disposed on or on the active surface of the semiconductor die. The sealed semiconductor die may form a molded panel that is removed from the carrier, after which the sealant may be cured. After curing, the sealant can be cured and then polished or ground to ensure that the surface of all thick RDL traces is exposed. The fan-out RDL build-up structure and the solder ball may then be formed on the molded panel and coupled or electrically connected to the thick RDL trace. In some embodiments, the solder balls or bumps may be omitted to make a QFN or LGA package. Alternatively, a solder mask (either dry film or liquid type) may be applied on or directly above the molded panel and the desired portion of the fan-in thick RDL trace or the desired portion of the fan-out RDL build- And then a solder ball or bump may be placed in the solder mask opening. The panel can then be singulated or saw-to-singulated into individual devices.

By forming a semiconductor package as shown for FIG. 3, the final semiconductor package can include an active surface that is sealed with a single mold compound and at least four sides. The mold compound can also be placed around a thick RDL trace that can be formed or plated on a semiconductor die, but the semiconductor die is still a part of its native semiconductor wafer. Semiconductor die and thick RDL traces can be molded after being placed face-up on a temporary carrier. The thick RDL traces may be exposed by grinding or removing portions of the mold to create a sealed fan-in package. The build-up fan-out structure can then be constructed on the sealed pan-in-thick RDL structure. As such, the sealing or molding process can be more easily achieved in a single step than previous structures and methods requiring a second or separate molded underfill material. In addition, when the thick RDL trace is exposed, good adjustment of the package thickness is achieved through removal of the sealing material to a known thickness or grinding down to achieve improved distortion of the semiconductor package through modulation of the epoxy thickness, Allow optimization.

By forming the semiconductor package as described above, flipping of the semiconductor die after the singulation from the native wafer is not required for subsequent placement of the semiconductor die on the temporary carrier. By eliminating the need for dip flipping as part of the batch process, semiconductor die placement can be achieved faster and with less equipment cost. Reducing the cost of semiconductor die placement during packaging can result in substantial cost savings since the cost of semiconductor die placement can be a significant cost for packaging semiconductor die. Similarly, forming thick RDL traces allows for a single process and structure, providing the benefits to be achieved with many different processes and structures, such as the formation of separate redistribution layers and vertical interconnects, e.g., copper posts. Thus, advantageously, a fan-out semiconductor package can be formed in which the fan-out RDL build-up structure is entirely applied to the mold compound. Thus, the semiconductor devices and methods described herein provide a QFN package and a flip-chip ball grid array (FGBA) device by providing a low-cost, manufacturable process with additional design flexibility over conventional fan-out structures, It can potentially replace large package techniques such as packages.

FIG. 4 illustrates an individual semiconductor package or embedded die package 130 similar to the semiconductor package 122 from FIG. The semiconductor package 130 is different from the semiconductor package 122 by including a build-up interconnect structure 132 instead of the build-up interconnect structure 106. [ 2c or 2e, the build-up interconnect structure 132 may be formed by depositing an insulating layer 134 over the thick conductive RDL trace 40 and the seal material 62, can do. The insulating layer 134 may be conformally applied to the top surface 44 of the sealant 62 and the thick RDL trace 42 and may have a first surface along their contour. The insulating layer 134 may have a second planar surface opposite the first surface. The insulating layer 134 may be formed of any suitable material including, but not limited to, photosensitive low temperature cure dielectric resist, photosensitive composite resist, LCP, laminate composite film, insulating paste with filler, solder mask resist film, liquid molding compound, particle forming compound, polyimide, BCB, PBO, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulation and structural properties. The insulating layer 134 may be deposited using printing, spin coating, spray coating, lamination, or other suitable processes. Insulation layer 134 may then be patterned and cured using UV exposure, development, or other suitable process. A portion of the insulating layer 134 may be formed by laser ablation, etching, or other suitable process to form openings that expose portions of the upper surface 44 of the thick RDL trace 42, Lt; / RTI > In one embodiment, the insulating layer 134 may be an organic or inorganic passivation film that can help prevent reliability failure under an electrical bias.

Figure 4 also shows that the electrically conductive bump material can be deposited on the thick conductive RDL trace 40 and can be in direct contact with them. The electrically conductive bump material may be deposited on the pad 116 using evaporation, electrolytic plating, electroless plating, ball drop, or screen printing processes. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder having a selective flux solution, and combinations thereof. For example, the bump material may be eutectic Sn / Pb, high solder, or solderless solder. The bump material may be bonded to the thick conductive RDL trace 40 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material beyond its melting point to form a spherical ball or bump 136. In some applications, the bump 136 is reflowed again to improve electrical contact to the thick conductive RDL trace 40. The bump 136 may also be compressively bonded to the thick conductive RDL trace 40. The bumps 136 represent one type of interconnect structure that may be formed on the thick conductive RDL traces 40. Other interconnect structures, including conductive paste, stud bumps, micro bumps, or other electrical interconnections, may also be used.

5A-5D illustrate another embodiment of a method of manufacturing a semiconductor package including a thick conductive RDL trace. Continuing from FIG. 2B, FIG. 5A illustrates that the semiconductor die 24 is removed from the mold 64 having the sealant 62 as a panel or embedded die panel 142. The panel 142 may optionally undergo a curing process to cure the sealant 62. The back surface 146 of the panel 142 may be comprised of the back surface 146 of the sealing material 62 and the back surface 77 of the insulating layer 50 which may be substantially coplanar with respect to each other. Both the backside 146 of the seal 62 and the backside 77 of the insulating layer 50 can be exposed by removal of the carrier 56 and the interface layer 58 as shown in Figure 5b below have. As shown in FIG. 5A, the seal 62 may be disposed about the semiconductor die 24 within the embedded die panel 142. The panel 142 may include a form factor or footprint of any shape and size that allows and enables subsequent processing necessary to form a semiconductor package, as described in more detail below. As a non-limiting example, the panel 142 may include a form factor similar to that of a 300 mm semiconductor wafer and may include a circular footprint with a diameter of 300 mm. The panel 142 may also be of any other desired size and may include shapes or formats such as rectangles or squares. In one embodiment, the panel 142 may be one known in the art as a reconstituted wafer.

5A illustrates that the panel 142 may undergo a grinding operation with the grinder 150 to reduce the thickness of the panel 142 and to remove or planarize the front surface 148 of the sealing material 62 . Chemical etching may also be used to remove and planarize a portion of the sealant 62 in the panel 142. The grinding operation may create or reveal a new front surface 152 of the seam 62 disposed over the thick RDL trace 40. The new front surface 152 may be exposed by removing the thickness T3 of the sealing material 62 from the front surface 148 of the sealing material. The front surface 152 may be offset from the surface 44 of the RDL trace 40 by a thickness or distance T4. Alternatively, if the desired thickness T4 is substantially equal to the thickness or offset between the trace 40 and the front surface 148, which is adjusted during the forming process, the thickness T4 of the seal can be maintained substantially the same, Or the thickness T4 can be maintained substantially equal to the thickness after molding by planarizing the front surface 148 without chemical etching removing the substantial thickness T4 of the sealing material 62. [

Figure 5b illustrates that the carrier 56 and the interfacial layer 58 may be chemically etched, mechanically peeled, CMP, mechanically etched to expose the backside 146 of the sealing material 62 opposite the front side 148 of the sealing material 62 And may be removed from the panel 142 by grinding, thermal bake, UV light, laser scanning, wet stripping, or other suitable process. In one embodiment, the seal 62 is partially or fully cured prior to removal of the carrier 56, interface layer 58, or both. Alternatively, the seal 62 may be partially or fully cured after the carrier 56, interface layer 58, or both sides have been removed. Similarly, the carrier 56 and interface layer 58 may be removed before or after grinding or planarizing the sealant 62.

The opening 156 may be formed in the front surface 148 or the front surface 152 of the sealing material 62 by laser ablation, etching, or other suitable process, such as a non-grinding process . The opening 156 may extend completely through a portion of the seal 62 to expose at least a portion of the thick RDL trace 40, e.g., the surface 44 of the thick RDL trace, to enable subsequent electrical interconnection. have. The opening 156 may be formed with a straight, curved, oblique, or angled side wall 158. Thus, the side wall 158 of the opening 156 can also be formed perpendicular or substantially perpendicular to the front surface 148 or 152. The opening 156 may have one or more widths or diameters W1 that extend in the x and y directions across the surface 152 of the panel 142. The cross-sectional shape of aperture 156 may be circular, oval, square, rectangular, or any other shape, including elongate trenches. The height of the opening or side wall 158 may be greater than, equal to, or less than the width W1 of the opening. In one embodiment, opening 156 may be formed before sealant 62 is cured and before carrier 56, interface layer 58, or both are removed. Alternatively, the openings 156 may be formed after the sealant 62 is cured and after the carrier 56, the interface layer 58, or both are removed.

In embodiments in which a portion of the thick RDL trace 40 is exposed by laser ablation or other non-grinding process, the thickness of the thick RDL trace 40 is greater than the thickness of the thick RDL trace 40 when exposed by grinding. May be less than the thickness of the RDL trace (40). By way of non-limiting example, the thickness of the thick RDL trace 40 may range from 4 to 20 [mu] m, from 4 to 15 [mu] m, from 4 to 10 [mu] m, or from 4 to 20 [mu] m when the thick RDL trace 40 is exposed by laser ablation or other non- Lt; RTI ID = 0.0 > 5 < / RTI > As used herein, substantially the same may include not only less than 1 [mu] m, but also plus or minus 1 [mu] m, 2 [mu] m, or 3 [mu] m.

5C illustrates that build-up interconnect structure 160 may be formed over panel 142 to provide electrical connection between semiconductor die 24 and thick RDL trace 44 and a point outside the subsequently formed semiconductor package. do. The build-up interconnect structure 160 may include a plurality of RDLs, including RDL traces, which may include portions of the fan-out interconnect structure. The build-up interconnect structure 160 may be formed by deposition and patterning of various insulating or passivation layers and deposition and patterning of various conductive layers.

Figure 5c illustrates a build-up interconnect structure 160 (shown in Figure 5) in which an insulating layer 162 is conformally applied to the top surface 44 of the sealant 62 and the thick RDL trace 42 and may have a first surface along their contour ). ≪ / RTI > The insulating layer 162 may have a second planar surface opposite the first surface. The insulating layer 162 may be formed of any suitable material including, but not limited to, photosensitive low temperature cure dielectric resist, photosensitive composite resist, LCP, laminate composite film, insulating paste with filler, solder mask resist film, liquid molding compound, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulation and structural properties. The insulating layer 162 may be deposited using printing, spin coating, spray coating, lamination, or other suitable processes. The insulating layer 162 may then be patterned and cured using UV exposure, development or other suitable processes. A portion of the insulating layer 162 may be subjected to laser ablation, etching, or other processes to form openings that expose portions of the upper surface 44 of the thick RDL trace 42, depending on the configuration and design of the semiconductor die 24 and the final semiconductor package. Or other suitable process. In some embodiments, the insulating layer 162 is formed or deposited prior to formation of the openings 158 in the sealant 62 such that openings are formed within and through the insulating layer 162 and the sealant 62 . Alternatively, the insulating layer 162 may be formed or formed after the formation of the openings 158 in the sealing material 62 such that openings in the insulating layer are formed through the insulating layer only and extend to the surface 44 of the thick RDL trace 40 Can be deposited.

The electrically conductive layer 164 may be patterned and deposited over the thick RDL trace 42, the sealant 62, and the insulating layer 162 and may contact them. The conductive layer 164 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material and may include one or more of a seed layer, an adhesive layer, or a barrier layer. Deposition of the conductive layer 164 may utilize PVD, CVD, electroplating, electroless plating, or other suitable processes. The opening in the insulating layer 162 may extend completely through the insulating layer on the thick RDL trace 40. The conductive layer 164 may operate as an RDL that includes a plurality of RDL traces to help extend the electrical connection from the semiconductor die 24 and the thick conductive RDL trace 40 to a point external to the semiconductor die 24. [ A portion of the conductive layer 164 formed in the opening in the insulating layer 162 may form a vertical interconnection structure or a via that provides electrical interconnection through the insulating layer 162. [ Although a non-limiting example of a build-up interconnect structure 160 is shown in FIG. 2C, which includes a single RDL 110, additional RDLs may also be provided between the conductive layer 168 and the thick RDL 40, May be formed in the semiconductor die 160 to provide additional flexibility for routing signals between the semiconductor die 24 and a point external to the semiconductor die.

Figure 5c further illustrates that the insulating or passivation layer 166 is conformally applied to the insulating layer 162 and the conductive layer 164 and follows their contour. The insulating layer 166 may be formed of any suitable material including, but not limited to, photosensitive low temperature cure dielectric resist, photosensitive composite resist, LCP, laminate composite film, insulating paste with filler, solder mask resist film, liquid molding compound, particle forming compound, polyimide, BCB, PBO, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulation and structural properties. The insulating layer 166 may be deposited using printing, spin coating, spray coating, lamination, or other suitable processes. The insulating layer 166 may then be patterned and cured using UV exposure followed by development or using other suitable processes. A portion of the insulating layer 166 may be removed by laser ablation, etching, or other suitable process to create an opening through the insulating layer to expose a portion of the conductive layer 164.

The electrically conductive layer 168 may be patterned and deposited over the conductive layer 164 and the insulating layer 166 and may be in contact therewith. Conductive layer 168 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Deposition of the conductive layer 168 may utilize PVD, CVD, electroplating, electroless plating, or other suitable processes. The opening in the insulating layer 166 in which the conductive layer 168 is disposed may extend completely through the insulating layer over the conductive layer 164. At least a portion of the conductive layer 168 may be formed within the opening in the insulating layer 166 and may be formed by forming a vertical interconnection structure or via through the insulating layer 166 to provide electrical interconnection, .

The conductive layer 168 may comprise a top portion or surface formed as a pad 170. The pad 170 includes a horizontal component including a region larger than the area of the opening formed in the insulating layer 166 such that the pad 170 of the conductive layer 168 extends over the top or top surface of the insulating layer 166 can do. The pad 170 of the conductive layer 168 may be an I / O interconnect at the periphery of the completed semiconductor package. As such, the pad 170 may be formed as a UBM pad or LGA pad coupled to the I / O interconnect at the periphery of the completed semiconductor package, such as, for example, a solder bump, or alternatively, May be an I / O interconnect. Pad 170 may be a stack of multiple metal layers including adhesion, barrier, seed, and wet layer. The pad 170 may comprise one or more layers of Ti, TiN, TiW, Al, Cu, Cr, CrCu, Ni, NiV, Pd, Pt, Au, Ag, or any other suitable material or combination of materials. In one embodiment, the pad 170 may comprise a TiW seed layer, a Cu seed layer, and a Cu UBM layer.

Figure 5d illustrates that the electrically conductive bump material is deposited over the pad 170, which may be a UBM pad, which acts as an intermediate conductive layer between the semiconductor die 24 and a subsequent formed solder bump or other I / O interconnect structure, Lt; / RTI > The pad 170 may include a conductive layer 164 and a UBM pad that provides a low resistance interconnect to the thick RDL trace 40 and may also provide for barrier-solder diffusion and solder wettability. The electrically conductive bump material may be deposited on the pad 170 using evaporation, electrolytic plating, electroless plating, ball drop, or screen printing processes. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder having a selective flux solution, and combinations thereof. For example, the bump material may be eutectic Sn / Pb, high solder, or solderless solder. The bump material may be bonded to pad 170 using a suitable attaching or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a spherical ball or bump 172. In some applications, the bumps 172 are reflowed again to improve electrical contact to the pad 170. The bumps 172 may also be compression bonded to the pad 170. Bump 172 represents one type of interconnect structure that may be formed on pad 170. Other interconnect structures, including conductive paste, stud bumps, micro bumps, or other electrical interconnections, may also be used.

Figure 5d also shows that after the formation of a package I / O interconnect, such as bump 170, the panel or reconstructed wafer 142 is transferred to a respective semiconductor package or embedded die package < RTI ID = 0.0 > RTI ID = 0.0 > 176 < / RTI > FIG. 6 illustrates an individual semiconductor package or embedded die package 176 fabricated by the process shown in FIGS. 5A-5D.

FIG. 7 illustrates an individual semiconductor package or embedded die package 180 similar to the semiconductor package 176 from FIG. The semiconductor package 180 is different from the semiconductor package 176 by omitting the build-up interconnect structure 160. Instead, the package 180 includes a backing 184 and a sealant 182 that includes a front face 186 that is opposite the back face. Both the back surface 184 and the front surface 186 may be substantially planar and the back surface may also be substantially coplanar with the back surface 77 of the insulating layer 50. The front surface 186 of the sealant 182 is positioned such that the thickness T5 of the sealant 182 extends from the front surface 186 of the sealant 182 to the surface 44 of the thick RDL trace 40. In this manner, Can be offset by a distance from the surface 44 of the substrate 40.

A plurality of apertures 188 may be formed in the sealant 182 through the front face 186 of the sealant 182 by laser ablation, etching, or other suitable process, . The opening 188 may extend completely through a portion of the sealant 182 to expose at least a portion of the thick RDL trace 40, e.g., the surface 44 of the thick RDL trace, to enable subsequent electrical interconnection. have. The opening 188 may be formed with a straight, curved, oblique, or angled side wall. Thus, the side walls of opening 188 may also be formed perpendicular or substantially perpendicular to front surface 186. The opening 188 may have one or more widths or diameters W2 that extend in the x and y directions across the front face 186 of the semiconductor package 180. The cross-sectional shape of opening 188 may be circular, oval, square, rectangular, or any other shape, including elongate trenches. The height of the opening 188 may be greater than, equal to, or less than the width W2 of the opening. The opening 188 may be formed before the sealant 182 is cured or sufficiently cured and before the carrier, interfacial layer, or both are removed from the semiconductor die 24 and sealant 182 have. Alternatively, the opening 188 may be formed after the sealant 182 has cured and after the carrier, interfacial layer, or both sides have been removed. The opening 188 may be configured to include a compatible and preferred size and shape for receiving or interfacing with the conductive bump structure, as will be described in greater detail below. As such, the size, volume, or cross-sectional area of the opening 188 may be greater than the size, volume, or cross-sectional area of the opening 156 shown in Figures 5B-5D.

Figure 7 also shows that the electrically conductive bump material can be deposited on and contacted with the thick RDL trace 40. The electrically conductive bump material may be deposited on the thick RDL trace 40 using evaporation, electrolytic plating, electroless plating, ball drop, or screen printing processes. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder having a selective flux solution, and combinations thereof. For example, the bump material may be eutectic Sn / Pb, high solder, or solderless solder. The bump material may be bonded to the thick RDL trace 40 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material beyond its melting point to form a spherical ball or bump 190. In some applications, bump 190 is reflowed again to improve electrical contact to thick RDL trace 40. Bump 190 may also be compression bonded to thick RDL trace 40. Bump 190 represents one type of interconnect structure that may be formed on thick RDL trace 40. Other interconnect structures, including conductive paste, stud bumps, micro bumps, or other electrical interconnections, may also be used.

FIG. 8 illustrates an individual semiconductor package or embedded die package 194 similar to the semiconductor package 180 from FIG. The semiconductor package 194 is different from the semiconductor package 180 by omitting the insulating layer 50. 8 shows that the backside 28 can be exposed as part of the semiconductor package 194, instead of having the insulating layer 50 disposed on the backside 28 of the semiconductor die 24. The semiconductor package 194 includes a sealing material 196 that includes a back side 198 and a front side 200 opposite the back side. Both the back surface 198 and the front surface 200 may be substantially planar and the back surface may also be substantially coplanar with the backside 28 of the semiconductor die 24. The front face 200 of the sealing material 196 is positioned so that the thickness T6 of the sealing material 196 extends from the front surface 200 of the sealing material 196 to the surface 44 of the thick RDL trace 40. [ Can be offset by a distance from the surface 44 of the substrate 40.

A plurality of apertures 202 may be formed in the sealant 196 through the front face 200 of the sealant 196 by laser ablation, etching, or other suitable process, as shown further in FIG. . The opening 202 may extend completely through a portion of the sealant 196 to expose at least a portion of the thick RDL trace 40, e.g., the surface 44 of the thick RDL trace, to enable subsequent electrical interconnection. have. The opening 202 may be formed with a straight, curved, oblique, or angled side wall. Thus, the sidewalls of the openings 202 may also be formed perpendicular or substantially perpendicular to the front face 200. The opening 202 may have one or more widths or diameters W3 that extend in the x and y directions across the front face 200 of the semiconductor package 194. The cross-sectional shape of opening 202 may be circular, oval, square, rectangular, or any other shape, including elongate trenches. The height of the opening 202 may be greater than, equal to, or less than the width W3 of the opening. The opening 202 may be formed before the sealant 196 is cured or sufficiently cured and before the carrier, interfacial layer, or both are removed from the semiconductor die 24 and the sealant 196 have. Alternatively, the openings 202 may be formed after the sealant 196 has cured and after the carrier, interfacial layer, or both sides have been removed. The openings 202 may be configured to include compatible and preferred sizes and shapes for receiving or interfacing with the conductive bump structure, as will be described in greater detail below. As such, the size, volume, or cross-sectional area of the opening 202 may be greater than the size, volume, or cross-sectional area of the opening 156 shown in Figures 5B-5D.

Figure 8 also shows that the electrically conductive bump material can be deposited on and contacted with the thick RDL trace 40. The electrically conductive bump material may be deposited on the thick RDL trace 40 using evaporation, electrolytic plating, electroless plating, ball drop, or screen printing processes. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder having a selective flux solution, and combinations thereof. For example, the bump material may be eutectic Sn / Pb, high solder, or solderless solder. The bump material may be bonded to the thick RDL trace 40 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material beyond its melting point to form a spherical ball or bump 204. In some applications, the bumps 204 are reflowed again to improve electrical contact to the thick RDL trace 40. The bumps 204 may also be compression bonded to the thick RDL trace 40. Bump 204 represents one type of interconnect structure that may be formed over thick RDL trace 40. Other interconnect structures, including conductive paste, stud bumps, micro bumps, or other electrical interconnections, may also be used.

FIG. 9 illustrates an individual semiconductor package or embedded die package 208 similar to the semiconductor package 194 from FIG. The semiconductor package 208 is different from the semiconductor package 194 by the inclusion of an insulating or passivation layer 210. The insulating layer 210 may be an epoxy film, a thermal epoxy, an epoxy resin, a B-stage epoxy film, a UV B-stage film with optional acrylic polymer, a dielectric film, or other suitable material. The insulating layer 210 may be disposed over substantially the entire backside of the semiconductor package 208 and thus may be substantially aligned with the region of the semiconductor die 24, But may include a footprint that is substantially the same as the footprint of semiconductor package 208. < RTI ID = 0.0 > The insulating layer 210 may include a backside 212 and a front side 214 opposite the backside. Both the back surface 212 and the front surface 214 may be substantially planar and the front surface may also be substantially flush with the back surface 198 of the sealant 196 and the back surface 28 of the semiconductor die 24. [ have.

FIG. 10 illustrates an individual semiconductor package or embedded die package 218 similar to the semiconductor package 180 from FIG. The semiconductor package 218 may be formed by the inclusion of an insulating or passivation layer 220 that may include a first planar surface that is conformally applied to and directly in contact with the front surface 200 of the sealant 196. [ (194). The insulating layer 220 may have a second planar surface opposite the first surface. The insulating layer 220 may be formed of any suitable material including, but not limited to, photosensitive low temperature cure dielectric resist, photosensitive composite resist, LCP, laminate composite film, insulating paste with filler, solder mask resist film, liquid molding compound, particle forming compound, polyimide, BCB, PBO, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulation and structural properties. The insulating layer 220 may be deposited using printing, spin coating, spray coating, lamination, or other suitable processes. The insulating layer 220 may then be patterned and cured using UV exposure, development, or other suitable processes. In one embodiment, the insulating layer 220 may be an organic or inorganic passivation film formed over the sealant 196 prior to formation of the opening 222 by laser drilling to help prevent reliability defects under an electrical bias.

The opening 222 may be formed in the insulating layer 220 and the sealing material 182 through the front face 186 of the sealing material 182 by laser ablation, etching, or other suitable process. The opening 222 extends completely through the insulating layer 220 and a portion of the sealant 182 to expose at least a portion of the thick RDL trace 40, e.g., the surface 44 of the thick RDL trace, Connection can be made possible. The opening 220 may have a straight, curved, oblique, or angled side wall. Thus, the sidewalls of the opening 220 may also be formed perpendicular or substantially perpendicular to the front surface 186. The opening 220 may have one or more widths or diameters W4 that extend in the x and y directions across the front surface 186 of the semiconductor package 218. The cross-sectional shape of opening 222 may be circular, oval, square, rectangular, or any other shape, including elongate trenches. The height of the opening 222 may be greater than, equal to, or less than the width W2 of the opening. In one embodiment, the openings 222 are spaced apart from the semiconductor die 24 and the sealant 182 before the sealant 182 and the insulating layer 220 are cured or sufficiently cured and the carrier, interface layer, May be formed before being removed. Alternatively, the openings 222 may be formed after the sealant 182 and the insulating layer 220 are cured and after the carrier, interfacial layer, or both are removed. The openings 222 may be configured to include compatible and preferred sizes and shapes for receiving or interfacing with the conductive bump structure, as will be described in greater detail below. As such, the size, volume, or cross-sectional area of the opening 222 may be greater than the size, volume, or cross-sectional area of the opening 156 shown in Figures 5B-5D.

Figure 10 also shows that the electrically conductive bump material can be deposited on and contacted with the thick RDL trace 40, the sealant 182, and the insulating layer 220. The electrically conductive bump material may be deposited on the thick RDL trace 40 using evaporation, electrolytic plating, electroless plating, ball drop, or screen printing processes. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder having a selective flux solution, and combinations thereof. For example, the bump material may be eutectic Sn / Pb, high solder, or solderless solder. The bump material may be bonded to the thick RDL trace 40 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material beyond its melting point to form a spherical ball or bump 224. In some applications, bump 224 is reflowed again to improve electrical contact to thick RDL trace 40. The bump 224 may also be compress bonded to the thick RDL trace 40. Bump 224 represents one type of interconnect structure that may be formed on thick RDL trace 40. Other interconnect structures, including conductive paste, stud bumps, micro bumps, or other electrical interconnections, may also be used.

FIG. 11 illustrates an individual semiconductor package or embedded die package 225 similar to the semiconductor package 180 from FIG. The semiconductor package 225 is coupled to the semiconductor package 180 by the inclusion of a conductive interconnect 226 that extends between the thick RDL 40 and a point external to the semiconductor package 225 and provides electrical interconnection connections therebetween. It is different. Conductive interconnect 226 may be formed at least partially within opening 228. The opening 228 may be formed in the sealant 182 through the front face 186 of the sealant 182 by laser ablation, etching, or other suitable process. The opening 228 may extend completely through a portion of the sealant 182 to expose at least a portion of the thick RDL trace 40, e.g., the surface 44 of the thick RDL trace, to enable subsequent electrical interconnection. have. The opening 228 may be formed with a straight, curved, oblique, or angled side wall. Thus, the sidewalls of the openings 228 may also be formed perpendicular or substantially perpendicular to the front surface 186. The opening 220 may have one or more widths or diameters W5 extending in the x and y directions across the front surface 186 of the semiconductor package 225. The cross-sectional shape of opening 228 may be circular, oval, square, rectangular, or any other shape, including elongate trenches. The height of the opening 228 may be greater than, equal to, or less than the width W5 of the opening. In one embodiment, the opening 228 is formed with a height greater than the width such that the conductive interconnect 226 formed in the opening 228 is configured as a conductive post comprising a height greater than the width W5. Conductive interconnect 226 may comprise a height in the range of 20 to 100 [mu] m or substantially the same. The openings 228 may be formed before the sealant 182 is cured or sufficiently cured and before the carrier, interfacial layer, or both are removed from the semiconductor die 24 and the sealant 182 have. Alternatively, the openings 228 may be formed after the sealant 182 has cured and after the carrier, interface layer, or both sides have been removed.

The conductive interconnect 226 may also be formed such that a portion of the conductive interconnect 226 is formed as a pad 227. The pad 227 may be adjacent the front surface 186 of the sealant 182 and the pad 227 of the conductive interconnect 226 may extend over or over the upper surface 186 of the front surface 186 of the sealant 182. [ An area larger than the area of the opening 228 and a width larger than the width W5. The pad 227 of the conductive interconnect 226 may be an I / O interconnect at the periphery of the completed semiconductor package. As such, the pad 227 may be formed as a UBM pad that can form an interface between the semiconductor die 24 and the signals transferred to the package I / O interconnect, as described in more detail below . Alternatively, the pad 227 is itself an I / O interconnect at the periphery of the completed semiconductor package and may be formed as an LGA pad that is not coupled to other I / O interconnects, such as, for example, solder bumps. The pad 227 can be a stack of multiple metal layers including adhesion, barrier, seed, and wet layer. The pad 227 may comprise one or more layers of Ti, TiN, TiW, Al, Cu, Cr, CrCu, Ni, NiV, Pd, Pt, Au, Ag, or any other suitable material or combination of materials. In one embodiment, the pad 227 may comprise a TiW seed layer, a Cu seed layer, and a Cu UBM layer.

11 also illustrates that an electrically conductive bump material may be deposited over the conductive interconnect 226 and contacted with the sealant 182 and the conductive interconnect 226. The electrically conductive bump material may be deposited on the conductive interconnect 226 using evaporation, electrolytic plating, electroless plating, ball drop, or screen printing processes. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder having a selective flux solution, and combinations thereof. For example, the bump material may be eutectic Sn / Pb, high solder, or solderless solder. The bump material may be bonded to the conductive interconnect 226 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material beyond its melting point to form a spherical ball or bump 230. In some applications, the bumps 230 are reflowed again to improve electrical contact to the conductive interconnects 226. The bumps 230 may also be compression bonded to the conductive interconnects 226. Bump 230 represents one type of interconnect structure that may be formed over conductive interconnect 226. Other interconnect structures, including conductive paste, stud bumps, micro bumps, or other electrical interconnections, may also be used.

FIG. 12 shows an individual semiconductor package or embedded die package 234 similar to the semiconductor package 225 from FIG. The semiconductor package 234 may be formed by the inclusion of an insulating or passivation layer 236 that may include a first planar surface that is conformally applied to and directly in contact with the front surface 186 of the sealing material 182. [ (225). The insulating layer 236 may have a second planar surface opposite the first surface. The insulating layer 236 may be formed of any suitable material including, but not limited to, photosensitive low temperature cure dielectric resist, photosensitive composite resist, LCP, laminate synthetic film, insulating paste with filler, solder mask resist film, liquid molding compound, particle forming compound, polyimide, BCB, PBO, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulation and structural properties. The insulating layer 236 may be deposited using printing, spin coating, spray coating, lamination, or other suitable processes. The insulating layer 236 may then be patterned and cured using UV exposure, development, or other suitable process. In one embodiment, the insulating layer 236 may be an organic or inorganic passivation film formed over the sealant 182 prior to formation of the opening 228 by laser drilling to help prevent reliability defects under an electrical bias. In other embodiments, the openings 228 may be formed prior to formation of the insulating layer 236.

Alternatively, the openings 228, the conductive interconnects 226, the pads 227, and the bumps 230 may be the same or substantially the same as those of the package 225, as described above with respect to FIG.

In the foregoing specification, various embodiments of the invention have been described. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense.

Claims (20)

A method of manufacturing a semiconductor package,
Forming a plurality of thick redistribution layer (RDL) traces electrically connected to the contact pads on the plurality of semiconductor dies on the active surface of the plurality of semiconductor dies;
Isolating the plurality of semiconductor dies including the plurality of thick RDL traces;
Mounting the plurality of single-sided semiconductor die on a temporary carrier, the active surface of the plurality of semiconductor die being oriented away from the temporary carrier;
Placing a seal material over the plurality of thick RDL traces and over the temporary carrier over the active surface and at least four sides of each of the plurality of semiconductor dies;
Forming vias through the seam material to expose at least one thick RDL trace of the plurality of thick RDL traces to the seam material;
Removing the temporary carrier; And
And singulating the plurality of semiconductor dies. The method according to claim 1,
Forming the plurality of thick RDL traces including a thickness or height of greater than 5 micrometers; And
Forming the vias through the seam material using laser ablation, wherein the seam material is a non-photoimagable material. ≪ Desc / Clms Page number 13 > 3. The method of claim 2 further comprising forming the plurality of thick RDL traces in a footprint of each of their respective semiconductor die as a fan-in structure for each of the plurality of semiconductor dies, / RTI > The method of claim 3,
Forming an electrical interconnect that is coupled to the at least one thick trace, the electrical interconnect extending out of the semiconductor package; And
Further comprising forming the electrical interconnect as an under bump metallization (UBM) pad, a land grid array (LGA) pad, a quad-flat non-leads (QFN) pad, or a bump. 5. The method of claim 4, further comprising attaching the electrical interconnect directly to the plurality of thick RDL traces. 5. The method of claim 4, further comprising forming a backside epoxy coating or dielectric film on the backside of the plurality of semiconductor die opposite the active surface. A method of manufacturing a semiconductor package,
Forming a plurality of thick redistribution layer (RDL) traces on the active surface of the semiconductor die, the plurality of thick RDL traces being connected to the contact pads on the active surface of the semiconductor die;
Placing the seal material over the active surface and at least four sides of the semiconductor die and over the plurality of thick RDL traces;
Exposing at least one thick RDL trace of the plurality of thick RDL traces to the seam material; And
And forming electrical interconnects coupled to the at least one thick trace. 8. The method of claim 7,
Forming the plurality of thick RDL traces including a thickness or height of greater than 5 micrometers; And
Forming a via through the seam material using laser ablation to expose the at least one thick RDL trace of the plurality of thick RDL traces to the seam material, Wherein the method further comprises: 9. The method of claim 8,
Forming the plurality of thick RDL traces including a thickness or height greater than 20 micrometers such that the height of the thick RDL trace is greater than the minimum width of the thick RDL trace; And
Further comprising exposing the at least one thick RDL trace of the plurality of thick RDL traces to the seam material material by grinding. 9. The method of claim 8, further comprising forming the plurality of thick RDL traces for each of the plurality of semiconductor dies in a footprint of each of the respective semiconductor dies. 11. The method of claim 10,
Forming an electrical interconnect that is coupled to the at least one thick trace, the electrical interconnect extending out of the semiconductor package; And
Further comprising forming the electrical interconnect as a UBM pad, an LGA pad, a QFN pad, or a bump. 12. The method of claim 11, further comprising forming a fan-out build-up interconnect structure disposed between the thick RDL trace and the electrical interconnect. 12. The method of claim 11, further comprising forming a backside epoxy coating or dielectric film on the backside of the plurality of semiconductor die opposite the active surface. 12. The method of claim 11, further comprising placing a seal material over the active surface and at least four sides of the semiconductor die in a single step and over the plurality of thick RDL traces. 8. The method of claim 7,
Forming the plurality of thick RDL traces over the active surface of the semiconductor die, the semiconductor die being part of a native semiconductor wafer; And
Further comprising singulating the semiconductor die comprising the plurality of thick RDL traces from the native wafer. A semiconductor package comprising:
A plurality of thick RDL traces disposed on the active surface of the semiconductor die and disposed within a footprint of the semiconductor die;
A seal material disposed over the active surface, over at least four sides of the semiconductor die, and over the plurality of thick RDL traces; And
A conductive interconnect coupled to a portion of at least one thick RDL trace of the plurality of thick RDL traces wherein the portion of the at least one thick RDL trace of the plurality of thick RDL traces is exposed to the seaming material / RTI > 17. The semiconductor package of claim 16, wherein the plurality of thick RDL traces comprise a thickness or height of greater than 5 micrometers. 18. The semiconductor package of claim 17, wherein the plurality of thick RDL traces comprise a thickness or height greater than a width. 18. The semiconductor package of claim 17, wherein the plurality of thick RDL traces are disposed within a footprint of the semiconductor die. 20. The semiconductor package of claim 19, further comprising a backside epoxy coating or dielectric film formed on a backside of the semiconductor die opposite the active surface.

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