KR20160107255A - Elimination of 3d parasitic effects on microphone power supply rejection - Google Patents

Abstract

Comprising a first node having a substantially equivalent 3D parasitic capacitance with respect to the preamplifier of the microphone package and a second node, such that any noise generated for the first node is equivalent to any noise generated for the second node, A microphone package is described. An external power source is connected to the first node and provides a bias voltage signal to the MEMS microphone package through the first node. The inverting amplifier is connected between the power supply and the second node. The third node is connected to the first node via a packaging parasitic capacitor, while the second node is coupled to the third node through an intended parasitic capacitor or an apparent capacitor. The noise coupled to the third node from the external power source is then canceled by summing the inverse power noise to the third node.

Description

[0001] ELIMINATION OF 3D PARASITIC EFFECTS ON MICROPHONE POWER SUPPLY REJECTION [0002]

Related Applications

This application claims the benefit of U.S. Provisional Patent Application No. 61 / 937,711, filed February 10, 2014, the entire contents of which are incorporated herein by reference.

The present invention relates to microphone systems and methods for reducing signal noise caused by the power supply of a microphone system.

It is an object of the present invention to provide microphone systems and methods for reducing signal noise caused by the power supply of a microphone system.

In some embodiments, the present invention provides a technique for eliminating the effects of power supply noise coupling to a high impedance preamplifier input due to packaging parasitic capacitors. The technique creates an inversion of the power supply noise and recombines it back into the preamplifier input, which will reduce or even eliminate the effects of packaging parasitic power supply noise coupling.

In some embodiments, the present invention provides a microphone system that is not limited to Power Supply Rejection Ratio (PSRR) performance due to packaging parasitic capacitors. Without this technique, the best achievable PSRR in a system will be determined by the packaging parasitics and the capacitive divider set by the MEMS sensor. Thus, through this technique we can allow PSRR to be dominated by circuit performance instead of packaging environment, which should allow for greater power noise rejection.

In one embodiment, the present invention provides a microphone system including a MEMS microphone package and a power source external to the MEMS microphone package. The MEMS microphone package includes a first node and a substantially parabolic 3D parasitic with respect to the preamplifier of the microphone package such that any noise generated on the first node is reduced or canceled by any noise generated on the second node on the preamplifier input. And a second node having capacitances. A power source is connected to the first node and provides a bias voltage signal to the MEMS microphone package via the first node. The microphone system also includes an inverting amplifier located within the MEMS microphone package and on an application specific integrated circuit (ASIC). The inverting amplifier is connected between the power supply and the second node. The inverting amplifier provides the inverted voltage signal to the preamplifier of the MEMS microphone package through the second node. A third node located within the MENS microphone package is connected to both the first node and the second node through the parasitic capacitors such that the noise for the bias voltage signal is reduced or canceled by the corresponding noise for the inverted voltage signal. The noise reduction bias voltage signal from the third node is applied to the microphone. The microphone provides an output signal to the preamplifier located within the MEMS microphone package.

Other aspects of the invention will become apparent upon consideration of the detailed description and the accompanying drawings.

1 is a perspective view of a microphone die package in accordance with one embodiment.
Fig. 2 is a circuit diagram showing the electronic effect of power supply noise coupling to the amplifier of the microphone system of Fig. 1; Fig.
3 is a circuit diagram of a power noise rejection system for the microphone system of FIG.
Figure 4 is a flow chart illustrating a method for setting a gain trim module for use by the power noise rejection system of Figure 3;
Figure 5 is a graph of power rejection ratios as a function of gain for various microphone system packages.

Before any embodiments of the invention are described in detail, it is to be understood that the invention is not limited in its application to the details of construction and the arrangement of the components set forth in the following description or illustrated in the following drawings Will be. The invention is capable of other embodiments and of being practiced or of being carried out in various ways.

Figure 1 shows the 3D parasitic capacitances present both inside and outside the die 100 including the integrated circuit of the microphone. The die 100 is connected to bond wires and the bond wires are electrically connected to power (bond wire 102A), ground (bond wire 102B), and input / output signals (bond wire 102C) ). The proximity of the bond wires 102A, 102B, 102C to each other creates a parasitic capacitance 106 between the bond wires 102A, 102B, 102C. The parasitic capacitance 106 may also arise from solder joints that connect the bond wires 102A, 102B, and 102C to the connection pads 104A, 104B, and 104C, respectively. In addition to the parasitic capacitance 106 between the bond wires 102A, 102B and 102C, the parasitic capacitance 108 is connected to the bond wires 102A, 102B and 102C (and the connection pads 104A, 104B and 104C) And between metal rods 112 on die 100. Additional parasitic capacitances 110 occur between the various metal roots 112 on the die 100.

Figure 2 shows the electronic effect of 3D parasitic capacitances (as described in Figure 1) on the quality of the microphone output signal. The first terminal of the capacitive microphone 200 is connected directly to the input of the preamplifier 202. The other terminal of the capacitive microphone 200 is connected to ground. The power supply line 204 supplies power (a biasing voltage for the capacitive microphone 200) to the node 210. The location of the power supply 204 creates a capacitive coupling 206 between the circuit nodes 208. In some embodiments, the pad 210 is one or more of the contact pads 104A, 104B, 104C and has one or more solder balls that secure the bond wires to the chip. The capacitive coupling 206 produces unwanted noise at the input of the preamplifier 208. [ As shown by Figure 1, the additional capacitive coupling produces undesired signals to couple directly to preamplifier < RTI ID = 0.0 > 208. < / RTI &

By design, the input of the preamplifier 202 to which the microphone 200 is connected is a very high impedance, which means that unwanted noise from the power supply line 204 is coupled to this node and the size determined by the total 3D parasitic capacitance . This size directly affects the total achievable power rejection ratio (PSRR) that the circuit can achieve. In order to achieve a high PSRR not limited by the package parasitic capacitances for this node, the effect of power supply noise coupling needs to be mitigated.

Figure 3 illustrates one embodiment of a microphone system 300 that improves achievable PSRR. The system includes an inverting amplifier 304 that produces an inverted duplicate of the power supply signal 302. The gain trim module 306 allows the magnitude of the inverted signal to be adjusted. The power supply signal 302 and the trimmed and inverted signal are each coupled by solder balls to separate pads 308A, 308B located approximately the same distance from the preamplifier 314 input. Pads 308 couple to the connection node within the microphone package through the parasitic capacitors so that a capacitive divider is formed. The coupling capacitance is approximately the same for the power supply signal 302 and the inverted signal from the inverting amplifier 304. Thus, any noise generated from the power source considers an approximately equivalent transfer function for the preamplifier input as the inverting amplifier output for the preamplifier input. As a result, the noise present in both the primary and inverted signals is reduced or canceled at the preamplifier 314 input. This reduction or elimination of the noise component of the supply voltage signal 302 at the preamplifier input causes a higher PSRR for the microphone system 300.

In other embodiments, the equivalent coupling capacitance required to match the 3D parasitic capacitance may be generated in other manners. Another way is to route the output of the inverting amplifier on the die so that the inverting amplifier produces a capacitance that matches the parasitic capacitance of the voltage supply signal. Additionally, the coupling capacitors can be adjusted to change the amplitude of the inverted signal instead of, or in combination with, the inverting amplifier.

The schematic in FIG. 3 shows an architecture of one embodiment that allows the PSRR to be adjusted in the final device testing. It should be understood that in other configurations, the PSRR may be adjusted for post-fabrication. In such an embodiment, the microprocessor and the memory module may intermittently perform gain trim adjustments, for example, at the start of every actuation of the device.

In one embodiment, the gain trim module 206 is manually adjusted using transistor level switches. Figure 4 illustrates this method 400. The tester (automated test system or user) sets the gain trim module 206 to the lowest gain setting (step 402). The tester then measures the PSRR with the external device (step 404). As long as there is a higher available gain setting (step 406), the tester measures the PSRR at each gain setting (step 404) and then adjusts the gain setting to the next highest gain settings ( Step 408). When the PSRR value for all gain settings is measured 410, the tester sets the gain trim module to the gain value associated with the highest measured PSRR value (step 410).

The parameters that determine the gain setting needed for maximum PSRR in the microphone will typically not change noticeably over time. Thus, this test may be sufficient during one final device test. In embodiments where calibration is performed only once, the gain setting is set via transistor level switches in the microphone system.

Figure 5 shows an example of PSRR values for increasing the trim gain settings for a series of microphone packages (HAC22, HAC26, HAC35, HAC42, HAC46, HAC53, HAC54, HAC62, HAC66) using the method of Figure 4 . On the vertical axis, the change in PSSR is displayed in decibels. On the horizontal axis, the gain trim codes for inverting amplifier 304 are displayed from lowest to highest. The gain trim codes represent successive steps for the transistor level switches, each representing an increase in gain for the inverting amplifier 304. The curves of the body of the plot represent characteristic curves for different microphone designs, respectively. These curves are normalized to zero PSRR values without any noise cancellation. The straight line at the bottom of the plot shows the microphone in Fig. 3 that does not use noise cancellation of the system.

For each of the microphone devices, a single gain setting that achieves the highest change in PSRR is identified. For HAC66, the optimal gain setting is 4. For HAC35, the optimal gain setting is 6. For all other microphone systems shown in FIG. 5, the optimum gain setting to provide the best power noise cancellation is the gain setting 5.

Accordingly, the present invention, among other things, provides a microphone system that enables improved power supply noise cancellation to achieve an optimal power noise rejection setting and a method of adjusting the gain setting of an inverting amplifier of such a microphone system. Various features and advantages are set forth in the following claims.

100: die
102A, 102B, 102C: Bond wire
104A, 104B, 104C: connection pad
106, 108, 110: parasitic capacitance 112: metal root
200: capacitive microphone
202, 208, 314: Preamplifier 204: Power line
206: capacitive coupling 208: circuit node
210: Pad 300: Microphone system
302: power supply signal 304: inverting amplifier
306: Gain trim module 308A, 308B: separate pad

Claims (15)

A microphone system comprising:
As a MEMS microphone package,
Microphone components,
A preamplifier coupled to the microphone component and configured to receive an output signal from the microphone component, and
A first node having substantially equivalent 3D parasitic capacitance with respect to the preamplifier and a second node having substantially equivalent 3D parasitic capacitance with respect to the preamplifier, such that any noise generated from the power supply is regarded as an inverting amplifier output for the preamplifier input, The MEMS microphone package including a node;
A power source external to the MEMS microphone package and connected to the first node to provide a bias voltage signal to the MEMS microphone package;
An inverting amplifier within the MEMS microphone package connected between the power supply and the second node, the inverting amplifier providing an inverted voltage signal to the MEMS microphone package; And
And an adder node located within the MEMS microphone package and connected to both the first node and the second node such that noise for an adder node is reduced or canceled by noise for the inverted voltage signal. Microphone system. The method according to claim 1,
Wherein the inverting amplifier comprises an adjustable gain inverting amplifier. 3. The method of claim 2,
Further comprising one or more level switches, wherein the gain of the inverting amplifier is manually adjusted using the one or more level switches. 3. The method of claim 2,
And a gain trim module configured to provide a gain setting to the inverting amplifier. 3. The method of claim 2,
Further comprising a microprocessor,
The microprocessor,
Setting the inverting amplifier with a first gain setting,
Determines a power supply rejection ratio at the first gain setting,
Adjusting a gain of the inverting amplifier with a second gain setting,
Determines a power supply rejection ratio at the second gain setting,
Comparing the power supply rejection ratio at the first gain setting with the power supply rejection ratio at the second gain setting,
And to operate the microphone system with the first gain setting when the power supply rejection ratio at the first gain setting is greater than the power supply rejection ratio at the second gain setting. 3. The method of claim 2,
Further comprising a microprocessor and a non-volatile computer readable memory module,
Wherein the microprocessor and the non-volatile computer readable memory module are configured to determine a power rejection ratio at each of a plurality of gain settings and configured to identify an optimum gain setting based on the determined power rejection ratio at each gain setting The microphone system. The method according to claim 1,
Wherein the first node and the second node are external pad connections to solder joints. A method for biasing a MEMS microphone, comprising:
Comprising the steps of: configuring a MEMS microphone package comprising a microphone component, a preamplifier, a first node, and a second node, wherein the first node and the second node are configured such that noises generated for the second node Constructing the MEMS microphone package having a substantially equivalent 3D parasitic capacitance with respect to the preamplifier such that the noise generated for one node is an inverse of the generated noise;
Connecting the power source to the exterior of the MEMS microphone package to provide a bias voltage signal to the MEMS microphone;
Connecting the inverting amplifier between the power supply and the second node such that an inverting amplifier supplies the inverted voltage signal to the second node; And
And coupling the first node and the second node to a summation node through capacitive coupling, wherein the summation node is configured such that the noise for the summation node is a combination of the noise from the first node and the noise from the second node And connecting the first node and the second node to an additive node, wherein the first node and the second node are located within and connected to the MEMS microphone package such that they are reduced or eliminated by the additive node. 9. The method of claim 8,
And adjusting the gain of the inverting amplifier. ≪ Desc / Clms Page number 21 > 10. The method of claim 9,
Wherein adjusting the gain of the inverting amplifier is manually adjusted using one or more level switches. 10. The method of claim 9,
≪ / RTI > further comprising coupling an adjustable gain trim module to the inverting amplifier. 10. The method of claim 9,
Further comprising coupling the microprocessor and the non-volatile computer readable memory module to the adjustable gain trim module such that the microprocessor controls the gain of the inverting amplifier. 13. The method of claim 12,
The microprocessor comprising:
Setting the inverting amplifier with a first gain setting;
Determining a power rejection ratio at the first gain setting;
Adjusting a gain of the inverting amplifier with a second gain setting;
Determining a power rejection ratio at the second gain setting;
Comparing the power rejection ratio at the first gain setting with the power supply rejection ratio at the second gain setting; And
Operating the microphone system with the first gain setting when the power supply rejection ratio at the first gain setting is greater than the power supply rejection ratio at the second gain setting, Way. 13. The method of claim 12,
Determining the power supply rejection ratio at each of a plurality of gain settings;
Identifying an optimal gain setting by selecting a gain setting with a highest power rejection ratio;
Operating the microphone system with the optimal gain setting; And
Further comprising: storing the value of the optimal gain setting that caused the peak power rejection ratio in the non-volatile computer readable memory module,
Wherein determining the power supply rejection ratio at the various gain settings comprises driving the signal on a voltage supply. 9. The method of claim 8,
Further comprising adjusting the capacitance of a parasitic capacitor located between the first node and the second node.

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