KR20160104523A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
KR20160104523A
KR20160104523A KR1020150084339A KR20150084339A KR20160104523A KR 20160104523 A KR20160104523 A KR 20160104523A KR 1020150084339 A KR1020150084339 A KR 1020150084339A KR 20150084339 A KR20150084339 A KR 20150084339A KR 20160104523 A KR20160104523 A KR 20160104523A
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KR
South Korea
Prior art keywords
buffer layer
elastic buffer
substrate
wiring pattern
disposed
Prior art date
Application number
KR1020150084339A
Other languages
Korean (ko)
Inventor
배한준
정원덕
Original Assignee
에스케이하이닉스 주식회사
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Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to US14/850,385 priority Critical patent/US9543384B2/en
Priority to CN201610041608.8A priority patent/CN105932000B/en
Publication of KR20160104523A publication Critical patent/KR20160104523A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A semiconductor package comprising: a substrate; An elastic buffer layer disposed in one direction of the substrate; A wiring pattern disposed on one surface of the elastic buffer layer; A semiconductor chip disposed on the other surface of the elastic buffer layer and having a trench disposed on one surface thereof; And an interconnecting member having one end connected to the wiring pattern and the other end electrically connected to the substrate.

Description

Semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package technology, and more particularly, to a semiconductor device incorporating an elastic buffer layer including an elastic material and a structure provided with a trench.

As electronic products become smaller and higher performance, portable electronic products increase, space for mounting semiconductor devices is further reduced, while functions required for electronic products are becoming more diverse. As a result, there is an increasing demand for a semiconductor memory having a small size and a large capacity. In addition, with the growing interest in wearable electronics requiring mobility, electronic products are required to have flexible characteristics, such as bending and folding functions.

A semiconductor chip disposed on a substrate or a substrate can be realized to have a thin thickness at a level that can be bent, but an interconnection for electrically connecting the semiconductor chip and the substrate has flexibility There are difficulties. When the package is warped or warped, tensile stress or compressive stress may be applied to the interconnecting member connecting the semiconductor chip and the substrate, and such stresses cause the interconnecting member to separate from or break from the connection pad. If the interconnection member is detached or the contact is dropped, a problem may occur in the operation of the package, and further, the reliability of the package may be deteriorated. Accordingly, there is a demand for a package structure capable of maintaining electrical connection with the interconnect member even when the semiconductor chip and the substrate are bent or bent.

An object of the present invention is to provide an elastic buffer layer containing an elastic material and a wiring pattern having elasticity between the semiconductor chip and the package substrate to ensure the flexibility of the interconnecting member.

Accordingly, it is an object of the present invention to provide a semiconductor device in which an interconnecting member can be flexibly moved so that an electrical connection can be maintained even when an external force is applied to a semiconductor package to bend or warp.

One embodiment of the present application includes a substrate; An elastic buffer layer disposed in one direction of the substrate; A wiring pattern disposed on one side of the elastic buffer layer; A semiconductor chip disposed on the other surface of the elastic buffer layer and having a trench disposed on one surface thereof; And an interconnecting member having one end connected to the wiring pattern and the other end electrically connected to the substrate.

Another embodiment of the present application is a semiconductor chip comprising: a semiconductor chip having a first surface and a second surface opposite to the first surface; A substrate disposed in the first surface direction of the semiconductor chip; An insulating layer disposed on a first surface of the semiconductor chip and having trenches of a predetermined depth formed on one surface thereof; An elastic buffer layer disposed on the one surface of the insulating layer; A lower wiring pattern disposed inside the elastic buffer layer and including a landing pad portion arranged to be aligned with the trench; And an interconnecting member connected at one end to the landing pad portion and at the other end to the substrate to electrically connect the substrate and the semiconductor chip.

Another embodiment of the present application is a light emitting device comprising: a first substrate; A second substrate disposed on the first substrate and having a first surface and a second surface opposite to the first surface, the trench being formed on the second surface; An elastic buffer layer disposed on a second surface of the second substrate and having an opening disposed on a surface facing the first substrate; A lower wiring pattern disposed inside the elastic buffer layer and including a landing pad portion arranged to be aligned with the trench; And an interconnection member having one end connected to the lower wiring pattern and the other end connected to the first substrate to electrically connect the first substrate and the second substrate.

According to the embodiments of the present application, an elastic buffer layer including an elastic material and a wiring pattern having elasticity are introduced and a trench is introduced into a structure disposed under the wiring pattern to secure connection flexibility between the wiring pattern and the interconnecting member . Thereby, there is an advantage that the interconnection member can be moved smoothly even when an external force is applied to the semiconductor package to bend or warp.

Therefore, even when an external force is applied, the electrical connection between the semiconductor chip and the package substrate can be maintained to ensure the reliability of the semiconductor package.

1 is a view illustrating a semiconductor device according to an embodiment.
Fig. 2 is a bottom view for explaining the wiring pattern of Fig. 1. Fig.
FIG. 3 is a view for explaining a stress relaxing action of a semiconductor device according to an embodiment.
4 is a view for explaining a semiconductor device according to another embodiment.
5 is a bottom view showing the lower wiring pattern of FIG.
6 is a diagram illustrating a semiconductor device according to another embodiment.

The embodiments of the present application are illustrated and described in the drawings, which are intended to illustrate what is being suggested by the present application and are not intended to limit what is presented in the present application in a detailed form.

Like reference numerals refer to like elements throughout the specification. Accordingly, although the same reference numerals or similar reference numerals are not mentioned or described in the drawings, they may be described with reference to other drawings. Further, even if the reference numerals are not shown, they can be described with reference to other drawings.

1 is a view illustrating a semiconductor device according to an embodiment. Fig. 2 is a bottom view for explaining the wiring pattern of Fig. 1. Fig. 3 is a view for explaining a stress relaxation operation of a semiconductor device according to an embodiment.

1 and 2, a semiconductor device 1000 according to an embodiment of the present invention includes a substrate 100, an elastic buffer layer 110, a semiconductor chip 130 having a trench 125 on one surface thereof, And an interconnection member 140 connecting the substrate 100 and the semiconductor chip 120.

The substrate 100 may include a body and may be a plate member including a first surface 100a and a second surface 100b opposed to the first surface 100a. A plurality of substrate pads 105 may be arranged on the first surface 100a of the substrate 100 so as to be spaced apart from each other. The substrate pad 105 may be made of aluminum (Al) or copper (Cu). The substrate 100 may include a printed circuit board (PCB), an organic substrate, or an insulating substrate. When the substrate 100 is formed of a printed circuit board (PCB), a rigid type printed circuit board can be used. Although not shown in the drawing, wiring patterns may be disposed inside the body portion of the substrate 100. In addition, an insulating layer (not shown) may be disposed on the first surface 100a or the second surface 100b of the substrate 100 except for the portion where the substrate pad 105 is exposed. The insulating layer may comprise a solder resist material.

The elastic buffer layer 110 may be disposed on the first surface 100a of the substrate 100. [ The elastic buffer layer 110 includes a first surface 110a and a second surface 110b opposite to the first surface 110a. The body portion of the elastic buffer layer 110 may be formed of a thin film made of an insulating material. The insulating material constituting the body portion includes a material having elasticity such that it can bend or bend when an external force is applied to the semiconductor element 1000. Specifically, the insulating material comprises a material having a tensile modulus in the range of 0.01 GPa to 0.1 GPa. In one example, the flexible material may comprise silicone resin or silicone rubber.

The wiring patterns 115a and 115b may be disposed on the first surface 110a of the elastic buffer layer 110. [ The wiring patterns 115a and 115b include a first wiring pattern 115a and a second wiring pattern 115b. The first wiring pattern 115a serves to connect to the interconnecting member 140. [

2 showing one of the first wiring patterns 115a in FIG. 1, the first wiring pattern 115a includes a first portion 115a-1, a second portion 115a-2, And a third portion 115a-3. The first portion 115a-1 and the third portion 115a-3 of the first wiring pattern 115a have a fixed shape while the second portion 115a-2 has a shape of a curved line that can be expanded and contracted . In one example, the first portion 115a-1 and the third portion 115a-3 may be formed in a straight line shape, and the second portion 115a-2 may be formed in a sine wave shape. The first portion 115a-1 of the first wiring pattern 115a is a portion contacting the interconnection member 140 while overlapping with the trench 125 disposed on the semiconductor chip 130. The second portion 115a-2 and the third portion 115a-3 of the first wiring pattern 115a are formed extending from the first portion 115a-1. Specifically, the second portion 115a-2 extends in both directions from the first portion 115a-1 and the third portion 115a-3 extends from the second portion 115a-2. Accordingly, the first portion 115a-1 of the first wiring pattern 115a serves as a landing pad portion contacting the interconnecting member 140. [ The elastic buffer layer 110 may further include an opening 113 exposing a part of the surface of the second wiring pattern 115b. The second wiring pattern 115b exposed by the opening 113 may be a connection pad portion 117 serving to connect to the metal wire 135. [ The first wiring pattern 115a or the second wiring pattern 115b may include aluminum (Al) or copper (Cu).

A semiconductor chip (130) may be disposed on the second surface (110b) of the elastic buffer layer (110). The semiconductor chip 130 may be fixed to the elastic buffer layer 110 via the adhesive member 119. The adhesive member 119 may be made of an adhesive or an adhesive tape, for example, a die attach film (DAF).

Active elements such as transistors are formed in the semiconductor chip 130. In some cases, passive elements such as capacitors, resistors and the like may also be formed. The active surface of the semiconductor chip 130 may face upward. One side of the semiconductor chip 130 is a front side 130a on which an active region exists and the other side opposite to the side is a back side, 130b. A plurality of chip pads 133 may be disposed on the front surface 130a of the semiconductor chip 130. [ The chip pads 133 are located at both side edges of the semiconductor chip 130, but the present invention is not limited thereto. For example, although not shown in the drawings, the chip pad portion 133 may be disposed at a central portion of the semiconductor chip 130. [ Here, the chip pad portion 133 may include aluminum (Al) or copper (Cu).

A plurality of trenches 125 are spaced apart from each other on the rear surface 130b of the semiconductor chip 130. [ Each of the trenches 125 may be formed to have a first depth T1 to the bottom surface 125a. The trench 125 is formed to have a predetermined depth from the surface of the semiconductor chip 130 opposed to the elastic buffer layer 110 and extends from the front surface portion 130a of the semiconductor chip 130 to have at least a first distance D1. Are spaced apart. Each of the trenches 125 may be disposed at a position corresponding to the position where the first wiring pattern 115a of the elastic buffer layer 110 is disposed. In one example, the trenches 125 may be spaced apart from each other on a surface of the semiconductor chip 130 that faces the elastic buffer layer 110. The open region above the trenches 125 is covered with an elastic buffer layer 110 so that a cavity S1 can be disposed between the elastic buffer layer 120 from the bottom surface 125a of the trench 125 .

Although one embodiment of the present invention shows four trenches 125 formed on the back surface 130b of the semiconductor chip 130, the present invention is not limited thereto, and the number and depth of the trenches 125 may be changed .

The semiconductor chip 130 and the elastic buffer layer 110 may be connected through a metal wire 135. The metal wire 135 is used as a medium for electrically connecting the elastic buffer layer 110 and the semiconductor chip 130. One end portion of the metal wire 135 is bonded to the chip pad portion 133 formed on the front portion 130a of the semiconductor chip 130 and the other end portion is bonded to the connection pad portion 117 of the elastic buffer layer 110 do. The metal wire 135 may be formed of gold (Au), silver (Ag), or copper (Cu). The molding member 160 is disposed on the front portion 130a of the semiconductor chip 130. [ The molding member 160 is disposed so as to cover the second surface 110b of the elastic buffer layer 110 and the exposed portion of the semiconductor chip 130. [ The molding member 160 may be made of an insulating material having a relatively higher tensile modulus than the elastic buffer layer 110. In one example, the molding member 160 may comprise an epoxy molding compound (EMC). The molding member 160 may physically or chemically protect the semiconductor chip 130 from the outside.

The interconnecting member 140 connects the semiconductor chip 130 and the substrate 100 through the elastic buffer layer 110 and is formed in a vertically erected pillar shape. The interconnecting member 140, in one example, may be formed to include copper (Cu). One end of the interconnection member 140 is bonded to the first wiring pattern 115a of the elastic buffer layer 110 and the other end is bonded to the substrate pad 105 of the substrate 100. [ The interconnection member 140 may be disposed to overlap with the trench 125. One end of the columnar portion 144 joined to the first wiring pattern 115a in the interconnection member 140 is connected to the hemisphere portion of the interconnection member 140, Shaped protruding portion 142, as shown in FIG. Here, the protrusion 142 of the interconnection member 140 may be bonded to the first portion 115a-1 of the first wiring pattern 115a shown in FIG. 2, that is, to the landing pad portion.

Between the elastic buffer layer 110 where the interconnection member 140 is disposed and the substrate 100 may be filled with the flexible molding material 150. The flexible molding material 150 includes a flexible material that can be bent when an external force is applied to the substrate 100 in the upward and downward directions. The flexible material that may be bent here may include silicon or rubber.

The trenches 125 disposed on the rear surface portion 130b of the semiconductor chip 130 are electrically connected to the first wiring patterns 115a and the elastic buffer layer 110 including the elastic material, Plane. With this structure, when the semiconductor element 1000 is bent or curved, the interconnection member 140 can be prevented from being separated or broken from the substrate 100 or the first wiring pattern 115a. 3, when an external force F1 is applied to the semiconductor device 1000, for example, when a force is applied in a vertical direction, the elastic buffer layer 110 made of a material having elasticity is bent, The interconnection member 140 may move into a cavity S1 between the first electrode layer 125 and the elastic buffer layer 110. [ That is, a space in which the interconnection member 140 can move is secured by the height of the cavity S1 disposed between the trench 125 and the elastic buffer layer 110. [ Accordingly, even when stress due to the external force Fl is applied to the semiconductor device 1000, the electrical / physical connection between the interconnecting member 140 and the elastic buffer layer 110 can be achieved without deformation of the interconnecting member 140 Can be maintained continuously.

The interconnection member 140 is inserted into the cavity S1 of the trench 125 when a force in the direction of the elastic buffer layer 110 is applied to the interconnection member 140 by an external force. In this process, the elastic buffer layer 110 is bent toward the bottom surface 125a of the trench 125, and tensile stress is applied thereto. At the same time, tensile stress is applied to the first conductive pattern 115a disposed on the first surface 110a of the elastic buffer layer 110, but the tensile stress is applied to the second conductive pattern 115a- 2 can be stretched and expanded so that the first wiring pattern 115a can be prevented from being separated or broken from the elastic buffer layer 110. [ 1) and the first portion 115a-1 of the first wiring pattern 115a is increased as the elastic buffer layer 110 is bent, The contact resistance can be reduced while maintaining the electrical connection. The first portion 115a-1 of the first wiring pattern 115a is deformed by the external pressure or the tensile force because the protruding portion 142 of the interconnection member 140 has a hemispherical shape, The area of contact with each other during the process can be maintained more than a certain level.

4 is a view for explaining a semiconductor device according to another embodiment. And FIG. 5 is a bottom view for explaining the lower wiring pattern of FIG.

4, a semiconductor device 2000 according to another embodiment of the present application includes a first substrate 200, a second substrate 231 having a trench 232a on one surface thereof, 210). The semiconductor device 2000 may further include an elastic bonding member 270.

The first substrate 200 may be a plate member including a first surface 200a and a second surface 200b facing the first surface 200a. A plurality of substrate pads 205 may be arranged on the first surface 200a of the first substrate 200 so as to be spaced apart from each other. The first substrate 200 may include an insulating material or a layer of dielectric material. The first substrate 200 may include a printed circuit board (PCB) structure. Although not shown in the drawings, internal wiring patterns may be disposed inside the body portion of the first substrate 200.

The second substrate 231 is disposed in the direction of the first surface 200a of the first substrate 200. [ The second substrate 231 includes a substrate core 230, outer layer circuit wiring patterns 240, an outer insulating layer 260, an elastic buffer layer 220 in which a lower wiring pattern 250 is formed, (255). The substrate core 230 may be formed by laminating an organic insulating material and a metal conductor to mount a semiconductor chip, a semiconductor package, another substrate, or the like on the substrate core 230. The substrate core 230 comprises an insulating material having a relatively high Young's modulus. Specifically, the substrate core 230 may be an insulating material having a tensile modulus of 20 GPa to 40 GPa. In one example, the substrate core 230 may include glass fibers, epoxy resin, an inorganic filler, and the like, so that the substrate core 230 may be hardly deformed by an external force.

The substrate core 230 includes a first surface 230a and a second surface 230b facing the first surface 230a. A plurality of trenches 232a may be disposed on the second surface 230b of the substrate core 230. [ The trenches 232a are recessed from the surface of the second surface 230b of the substrate core 230 by a predetermined depth, and adjacent trenches 232a are spaced apart from each other by a predetermined distance. Each of the trenches 232a may be formed to have a second depth T2 from the second surface 230b. The bottom surfaces of the trenches 232a are spaced apart from the first surface 230a of the substrate core 230 by a predetermined distance D2. Here, the cavity S2 may be disposed between the trench 232a and the elastic buffer layer 220. The cavity S2 is a free space in which the interconnection member 212 can move while the elastic buffer layer 220 is deformed when an external force is applied to the semiconductor device 2000. [ Accordingly, the interconnecting member 212 can stably maintain the electrical connection even if the semiconductor device 1000 is deformed by an external force. Meanwhile, in another example, the trenches 232a may be formed in the shape of a through hole penetrating from the first surface 230a of the substrate core 230 to the second surface 230b.

The outer layer circuit wiring patterns 240 may be disposed on the first surface 230a of the substrate core 230. [ The outer layer circuit wiring patterns 240 may be electrically separated from each other, or may be electrically connected to each other in other areas. An outer insulating layer 260 may be further disposed on the first surface 230a of the substrate core 230. [ In one example, the outer insulating layer 260 may be a solder resist. The outer insulating layer 260 has a plurality of first openings 261. A part of the upper surface of the outer layer circuit wiring patterns 240 may be exposed by each of the first openings 261 formed on the outer insulating layer 260 to serve as the bonding pad 240a. The lower surface of the outer layer circuit wiring patterns 240 may be electrically connected to the via electrodes 255. Each of the via electrodes 255 may be formed to penetrate from the first surface 200a to the second surface 200b of the substrate core 230. [ In one example, the via electrodes 255 may comprise an extension protruding from the surface of the second surface 200b of the substrate core 230 to a predetermined height.

One end of the via electrodes 255 is electrically connected to the lower surface of the outer layer circuit wiring patterns 240 and the other end is electrically connected to the upper surface of the lower wiring pattern 250. The lower wiring pattern 250 may be disposed inside the elastic buffer layer 220. The elastic buffer layer 220 is disposed on the second surface 230b of the substrate core 230. [ The elastic buffer layer 220 is formed so as to cover all the side portions of the extended portion of the via electrodes 255. The elastic buffer layer 220 may be composed of a thin film including an insulating material. The elastic buffer layer 220 may include an insulating material that is flexible enough to bend or flex when an external force is applied physically. The insulating material comprising the flexible material comprises a material having a tensile modulus in the range of 0.01 GPa to 0.1 GPa, which is relatively lower than the substrate core 230. In one example, the flexible material may comprise silicone resin or silicone rubber.

The lower wiring patterns 250 having elasticity may be disposed inside the elastic buffer layer 220. The upper surface 250a of the lower wiring patterns 250 may be electrically connected to the lower surface of the via-electrode electrodes 255, respectively. The elastic buffer layer 220 may have an opening 220a partially exposing a surface of the lower surface 250b of the lower wiring patterns 250. [ The opening 220a may be formed by etching the surface of the lower surface of the elastic buffer layer 220 by a predetermined depth. A portion of the lower wiring patterns 250 exposed by the opening portion 220a becomes the landing pad portion 272. [ The elastic buffer layer 220 may be disposed across the open portion above the trenches 232a. In other words, the trenches 230a are covered with the elastic buffer layer 220, so that the cavity S2 is formed between the trench 232a and the elastic buffer layer 22. The landing pad portion 272 is disposed on an open portion of the trenches 232a. In other words, the landing pad portion 272 and the trenches 232a are arranged to overlap with each other. Therefore, the landing pad portion 272 is formed not to be directly supported by the substrate core 230 but to have a certain distance d4 from the bottom surface of the trenches 232a.

5 is a plan view of a portion X of the lower wiring patterns 250 of FIG. 4 viewed from below. Referring to FIG. 5, the lower wiring patterns 250-1, 250-2 and 250-3 are connected to the first landing pad portion 272a, which is one of the landing pad portions 272 (see FIG. 4) A second conductive pattern 251b extending in one direction to the left with reference to the second landing pad portion 272b, or a third landing pad portion 272c extending in a left direction with respect to the second landing pad portion 272b, And the third conductive pattern 251c extending in one direction on the right side with respect to the first conductive pattern 251c. The second landing pad portion 272b may further include a first extended conductive pattern 253a extending in a second direction opposite to the first direction in which the second conductive pattern 251b is connected. The first extended conductive pattern 253a may be disposed to extend outside the sidewall of the trench 232a. The third landing pad portion 272c may further include a second extended conductive pattern 253b extending in a first direction opposite to the second direction in which the third conductive pattern 251c is connected. And the second extended conductive pattern 253b may extend to the outside of the side wall of the trench 232a. The first or second conductive patterns 253a and 253b extending in this way can suppress displacement of the landing pad portions in only one direction when the landing pad portions are deformed. The first landing pad portion 272a, the second landing pad portion 272b or the third landing pad portion 272c includes contact portions a, b and c, respectively, which contact the interconnecting member 212.

The first conductive pattern 251a, the second conductive pattern 251b, or the third conductive pattern 251c may be formed so that a curve extends in one direction. In one example, a curve is formed to have a sine wave shape . The sine wave shape is configured to have at least two floors and valleys. Here, the first conductive pattern 251a, the second conductive pattern 251b, or the third conductive pattern 251c includes contact points 252a, 252b, and 252c that are in contact with the via electrodes (255 in FIG. 4) . The landing pad portions 272a, 272b and 272c are exposed through the opening 232a and the remaining conductive patterns 251a, 251b and 251c are covered with the elastic buffer layer 220. In one embodiment, the opening 220a may be formed to be smaller than the landing pad portions 272a, 272b, and 272c and may be solder mask depined (SMD), which exposes only a portion of the landing pad portions 272a, 272b, Mask Defined) land pattern. In another embodiment, the opening may be formed in a non-solder mask defined (NSMD) land pattern so as to be larger than the landing pad portions to expose all of the landing pad portions. Also, although not shown, the lower wiring pattern 250 may be arranged to connect between the adjacent via-electrodes without being connected to the landing pad portion 272. The lower wiring patterns 250 may be composed of aluminum (Al) or copper (Cu).

When an external force is applied to the semiconductor element 2000 to apply force to the interconnecting member 212 toward the substrate core 230, pressure is transferred to the landing pad portion 272 adjacent to the interconnecting member 212 . The elastic buffer layer 220 supporting the landing pad portion 272 is bent and the interconnecting member 212 is moved to the cavity S2 between the trench 232a and the elastic buffer layer 220. [ In this process, the sine wave structure of the first conductive pattern 251a, the second conductive pattern 251b, or the third conductive pattern 251c is elongated in the longitudinal direction so that the conductive pattern is separated from the elastic buffer layer 220, . In addition, the contact area between the hemispherical end portion 211 of the interconnecting member 212 and each of the landing pads 272a, 272b, and 272c is increased. Accordingly, the electrical connection can be maintained while reducing the contact resistance.

Referring again to FIG. 4, the interconnecting member 212 is disposed to electrically contact the first substrate 200 and the second substrate 230 in contact with the landing pad portions 272. Each interconnection member 212 may be disposed to overlap with the trench 232a. The interconnecting member 212 may be formed in a vertically erected columnar shape. The interconnecting member 212 may include a protrusion 211 having a hemispherical shape extending from the columnar portion 210 and the columnar portion 210. The interconnecting member 212, in one example, is formed to include copper (Cu), but is not limited thereto. For example, the protrusion 211 located at the distal end of the interconnecting member 212 can be composed of a material including solder. In this case, the projection 211 composed of solder can be completely bonded to the landing pad portion 272. Meanwhile, the protrusion 211 may be made of a material such as copper (Cu) and may be detachable from the landing pad portion 272.

The other end of the interconnecting member 212 is bonded to the substrate pad 205 of the first substrate 200. An elastic bonding member 270 may be disposed in a space between the elastic buffer layer 220 and the first substrate 200. The elastic bonding member 270 may be disposed to cover both the interconnecting member 212, the substrate pad 205, and the first surface 200a of the first substrate 200. [ In one example, the elastic bonding member 270 may be arranged to fix only a part of the elastic buffer layer 220 and the first substrate 200. For example, the elastic bonding member 270 may be disposed so as to surround only the edges of the four sides of the first substrate 200.

6 is a diagram illustrating a semiconductor device according to another embodiment.

6, a semiconductor device 3000 according to another embodiment of the present application includes a substrate 300, a semiconductor chip 400, a first insulation layer 420 provided with a trench 431, An elastic buffer layer 445 provided with a lower wiring pattern 415, and an interconnecting member 312. The semiconductor element 3000 may further include an elastic bonding member 450.

The substrate 300 may be a plate member including a first surface 300a and a second surface 300b facing the first surface 300a. A plurality of substrate pads 305 may be arranged on the first surface 300a of the substrate 300 so as to be spaced apart from each other. The substrate 300 may comprise an insulating material or a layer of dielectric material. The substrate 300 may include a printed circuit board (PCB) structure. Although not shown in the drawing, internal wiring patterns may be disposed inside the body portion of the substrate 300.

The semiconductor chip 400 is disposed in the direction of the first surface 300a of the substrate 300. [ Active elements such as transistors are formed in the semiconductor chip 400, and passive elements such as capacitors, resistors and the like may be formed in some cases. The active surface of the semiconductor chip 400 may be directed downward. One side of the semiconductor chip 400 may be defined as a front portion 400a in which the active region is present and the other side opposite to the one side may be defined as a rear portion 400b opposite to the front portion 400a have. A plurality of chip pads 405 may be disposed on the front surface 400a of the semiconductor chip 400. [ The chip pad portion 405 may include aluminum (Al) or copper (Cu).

The insulating layer 420 is disposed in the direction of the front portion 400a of the semiconductor chip 400. [ One surface of the insulating layer 420 may be in contact with the front surface portion 400a of the semiconductor chip 400. In one example, the insulating layer 420 may be formed of a single material or a mixture of one or more polymeric materials, among insulating polymeric materials made of a group of BCB (Benzocyclobutene) or polyimide. BCB or polyimide has a relatively high tensile modulus of 2.9 GPa to 3.2 GPa. Accordingly, deformation due to external force is not large. A plurality of trenches 431 may be disposed on the insulating layer 420. The trenches 431 are recessed by a predetermined depth from the surface of the other surface opposite to one surface of the insulating layer 420 which is joined to the front surface portion 400a of the semiconductor chip 400, Are spaced apart from each other by a predetermined distance. Each of the trenches 431 may be formed to have a third depth T3 from the other surface of the insulating layer 420. Meanwhile, in another example, the trenches 431 may be formed in the shape of a through hole passing through the insulating layer 420.

First internal wiring patterns 407 electrically connected to the chip pads 405 of the semiconductor chip 400 are provided in the insulating layer 420. The first internal wiring patterns 407 may be formed to extend from the surface of the other surface of the insulating layer 420 by a predetermined height. An elastic buffer layer 445 is disposed on the other surface of the insulating layer 420, including an extended portion of the first internal wiring patterns 407. The elastic buffer layer 445 may have a multi-layer structure in which a first elastic buffer layer 440 and a second elastic buffer layer 442 are sequentially stacked. The first elastic buffer layer 440 may be formed to cover the surface of the other surface of the insulating layer 420. The first elastic buffer layer 440 is formed while covering the top of each of the trenches 431 formed in the insulating layer 420. Accordingly, the cavity S3 may be disposed between the first elastic buffer layer 440 and the trenches 431. [ When an external force is applied to the semiconductor element 3000 and a force is applied to the interconnecting member 312 in the direction of the semiconductor chip 400, pressure is applied to the landing pad portion 272 in contact with the interconnecting member 312 do. Then, the elastic buffer layer 445 supporting the landing pad portion 272 is bent, and the interconnecting member 312 moves to the inside of the cavity S3.

The first elastic buffer layer 440 and / or the second elastic buffer layer 442 may include an insulating material that is flexible enough to bend or flex when an external force is applied physically. The flexible insulating material includes a material having a tensile modulus in the range of 0.01 GPa to 0.1 GPa relatively lower than the insulating layer 420. In one example, the flexible material may comprise silicone resin or silicone rubber.

The lower interconnection patterns 415 and the second internal interconnection patterns 417 may be disposed on the first elastic buffer layer 440. The lower wiring patterns 415 may be electrically connected to one end of the first inner wiring patterns 407 and the second inner wiring patterns 417 may be electrically connected to the other end of the first inner wiring patterns 407 And can be electrically connected. The lower wiring patterns 415 may be formed to have the same configuration as the wiring patterns described in FIG. For example, the lower wiring patterns 415 may have a curved shape extending in one direction, and the curved shape may have a sine wave shape. The lower wiring patterns 415 may be made of aluminum (Al) or copper (Cu).

A second elastic buffer layer 442 covering the lower wiring patterns 415 and the second internal wiring patterns 417 is disposed on a surface of the first elastic buffer layer 440 opposite to the insulating layer 420. The second elastic buffer layer 442 may have an opening 445a partially exposing the lower surface of the lower wiring patterns 415. The opening 445a may be formed by etching the surface of the lower surface of the second elastic buffer layer 442 by a predetermined depth. The lower wiring pattern 415 exposed by the opening 445a becomes the landing pad portion 420. [

The interconnecting member 312 is in contact with the landing pad portions 420 to electrically connect the substrate 300 and the semiconductor chip 400. Each interconnection member 312 may be disposed to overlap the landing pad portion 420 and the trenches 431. The interconnecting member 312 may be formed in a vertically erected columnar shape. The interconnection member 312 may include a protrusion 311 having a semispherical shape extending from the column portion 310 and the column portion 310. The interconnecting member 312, in one example, is formed of copper (Cu), but is not limited thereto. For example, the protrusion 311 located at the distal end of the interconnecting member 312 can be composed of a material including solder. In one embodiment, the protrusion 311 composed of solder can be completely bonded to the landing pad portion 420.

The other end of the interconnecting member 312 is bonded to the substrate pad 305 of the substrate 300. The space between the elastic buffer layer 445 and the substrate 300 may be disposed with an elastic bonding member 450. The elastic bonding member 450 may be arranged to cover both the interconnecting member 312, the substrate pad 305 and the first surface 300a of the substrate 300. [ In one example, the elastic bonding member 450 may be arranged to fix only the elastic buffer layer 445 and a part of the substrate 300. For example, the elastic bonding member 450 may be arranged so as to surround only the rim of the four sides of the substrate 300.

1000, 2000, 3000: semiconductor device
100, 200, 300: substrate
120, 220, 445: elastic buffer layer
130, 400: semiconductor chip
140, 212, 312: Interconnection member

Claims (47)

Board;
An elastic buffer layer disposed in one direction of the substrate;
A wiring pattern disposed on one side of the elastic buffer layer;
A semiconductor chip disposed on the other surface of the elastic buffer layer and having a trench disposed on one surface thereof; And
And an interconnecting member having one end connected to the wiring pattern and the other end electrically connected to the substrate. The method according to claim 1,
Wherein the elastic buffer layer comprises an insulating material having a tensile modulus in a range of 0.01 GPa to 0.1 GPa. 3. The method of claim 2,
Wherein the insulating material comprises a silicone resin or a silicone rubber. The method according to claim 1,
Wherein a plurality of the trenches are spaced apart from each other on a surface of the semiconductor chip opposite to the elastic buffer layer. 5. The method of claim 4,
Wherein the trench has a predetermined depth from the surface of the semiconductor chip facing the elastic buffer layer. 6. The method of claim 5,
Wherein the trench includes a cavity formed by covering the elastic buffer layer. The semiconductor device according to claim 1,
A first portion disposed to overlap the trench;
A second portion extending in both directions from the first portion and having a curved line shape; And
And a third portion extending from the second portion and having a straight line shape. 8. The method of claim 7,
And the second portion has a sine wave shape. 8. The method of claim 7,
And the first portion of the wiring pattern is a landing pad connected to the interconnecting member. The method according to claim 1,
And the interconnection member is arranged to overlap with the trench. The method according to claim 1,
Wherein the interconnecting member comprises: a pillar; And
And a protruding portion connected to the wiring pattern and having a hemispherical shape. The method according to claim 1,
And the interconnection member includes copper (Cu). The method according to claim 1,
Wherein an exposed portion of the semiconductor chip and the elastic buffer layer is covered with a molding member. The method according to claim 1,
Wherein the elastic buffer layer and the substrate are filled with a flexible molding material. 15. The method of claim 14,
Wherein the flexible molding material comprises silicon or rubber. A semiconductor chip having a first surface and a second surface opposite to the first surface;
A substrate disposed in the first surface direction of the semiconductor chip;
An insulating layer disposed on a first surface of the semiconductor chip and having trenches of a predetermined depth formed on one surface thereof;
An elastic buffer layer disposed on the one surface of the insulating layer;
A lower wiring pattern disposed inside the elastic buffer layer and including a landing pad portion arranged to be aligned with the trench; And
And an interconnection member connected at one end to the landing pad portion and at the other end to the substrate to electrically connect the substrate and the semiconductor chip. The method of claim 16, wherein the elastic buffer layer
A first elastic buffer layer disposed on one side of the insulating layer and disposed to cover an open portion of the upper portion of the trench; And
And a second elastic buffer layer formed on the first elastic buffer layer and the lower wiring pattern and having an opening exposing the landing pad portion. 17. The method of claim 16,
Wherein the insulating layer comprises a first insulating material having a tensile modulus of 2.9 GPa to 3.2 GPa,
Wherein the elastic buffer layer comprises a second insulating material having a tensile modulus in the range of 0.01 GPa to 0.1 GPa. 19. The method of claim 18,
Wherein the first insulating material is formed by mixing a single material or at least one polymer material among insulating polymer materials composed of a group of BCB (Benzocyclobutene) or polyimide. 19. The method of claim 18,
Wherein the second insulating material comprises a silicone resin or a silicone rubber. 17. The method of claim 16,
Wherein the insulating layer includes one surface in the direction of the elastic buffer layer and the other surface facing the one surface and attached to the semiconductor chip,
Wherein the plurality of trenches are spaced apart from each other on one surface of the insulating layer. 22. The method of claim 21,
Wherein the trench is formed to have a predetermined depth from a surface of the one surface of the insulating layer and the elastic buffer layer is disposed so as to cover an open portion of the trench and includes a cavity between the trench and the elastic buffer layer Semiconductor device. 17. The method of claim 16,
Wherein the insulating layer further includes an inner wiring pattern, the lower wiring pattern including the landing pad portion is connected to the inner wiring pattern at least on one surface thereof, and the inner wiring pattern is provided on the front surface of the semiconductor chip And connected to the chip pad portion to electrically connect the chip pad portion and the lower wiring pattern. 17. The method of claim 16,
Wherein the lower wiring pattern is covered with the elastic buffer layer in a remaining portion except for the landing pad portion. 17. The method of claim 16,
Wherein the landing pad portion is disposed at a position spaced apart from the bottom surface of the trench by a predetermined distance. 24. The method of claim 23,
Wherein the lower wiring pattern further includes a conductive pattern extending in at least one direction from the landing pad portion and connected to the internal wiring pattern and having a curved line shape. 27. The method of claim 26,
Wherein the conductive pattern has a sine wave shape. 24. The semiconductor device according to claim 23, wherein the lower wiring pattern
A conductive pattern extending from the landing pad portion in a first direction and connected to the internal wiring pattern and formed as a curved line; And
Further comprising an elongated conductive pattern extending in a second direction that is opposite to the first direction in which the conductive pattern is connected and further extending in an outward direction of the trench sidewall. 17. The method of claim 16,
And the interconnecting member is arranged to be aligned with the trench. 17. The method of claim 16,
Wherein the interconnecting member comprises: a pillar; And
And a protruding portion connected to the lower wiring pattern and having a hemispherical shape. 30. The method of claim 29,
Wherein the projecting portion of the interconnecting member is made of a material including solder. A first substrate;
A second substrate disposed on the first substrate and having a first surface and a second surface opposite to the first surface, the trench being formed on the second surface;
An elastic buffer layer disposed on a second surface of the second substrate and having an opening disposed on a surface facing the first substrate;
A lower wiring pattern disposed inside the elastic buffer layer and including a landing pad portion arranged to be aligned with the trench; And
And an interconnection member having one end connected to the lower wiring pattern and the other end connected to the first substrate to electrically connect the first substrate and the second substrate. 33. The method of claim 32, wherein the second substrate
An outer layer circuit wiring pattern disposed on the first surface; And
Further comprising a via electrode penetrating the second substrate in a direction from the first surface to the second surface and connected at one end to the outer layer circuit wiring pattern and at the other end to the lower wiring pattern. 33. The method of claim 32,
Wherein the elastic buffer layer is disposed on the second surface of the second substrate so as to cover an open portion of the trench upper portion, and the landing pad portion is formed on the elastic buffer layer. 33. The method of claim 32,
Wherein the trench is formed to have a predetermined depth from a surface of the second surface of the second substrate and is disposed so as to cover an open portion of the trench and includes a cavity between the trench and the elastic buffer layer. 33. The method of claim 32,
Wherein the second substrate comprises a substrate core composed of a first insulating material having a tensile modulus of 20 GPa to 40 GPa, the elastic buffer layer having a tensile modulus in the range of 0.01 GPa to 0.1 GPa And a second insulating material. 37. The method of claim 36,
Wherein the first insulating material includes glass fiber, epoxy resin, inorganic filler and the like. 37. The method of claim 36,
Wherein the second insulating material comprises a silicone resin or a silicone rubber. 33. The method of claim 32,
Wherein the second substrate has a plurality of trenches spaced apart from each other on a second surface in contact with the elastic buffer layer. 33. The method of claim 32,
Wherein the lower wiring pattern is covered with the elastic buffer layer in a remaining portion except for the landing pad portion. 33. The method of claim 32,
Wherein the landing pad portion is disposed at a position spaced apart from the bottom surface of the trench by a predetermined distance. 34. The method of claim 33,
Wherein the lower wiring pattern further includes a conductive pattern extending in at least one direction from the landing pad portion and connected to the via electrode and having a curved line shape. 43. The method of claim 42,
Wherein the conductive pattern has a sine wave shape. The semiconductor device according to claim 33, wherein the lower wiring pattern
A conductive pattern extending in a first direction from the landing pad portion and connected to the via electrode and formed of a curved line; And
Further comprising an elongated conductive pattern extending in a second direction that is opposite to the first direction in which the conductive pattern is connected and further extending in an outward direction of the trench sidewall. 33. The method of claim 32,
And the interconnecting member is arranged to be aligned with the trench. 33. The method of claim 32,
Wherein the interconnecting member comprises: a pillar; And
And a protruding portion connected to the lower wiring pattern and having a hemispherical shape. 47. The method of claim 46,
Wherein the projecting portion of the interconnecting member is made of a material including solder.
KR1020150084339A 2015-02-26 2015-06-15 Semiconductor device KR20160104523A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US14/850,385 US9543384B2 (en) 2015-02-26 2015-09-10 Semiconductor package
CN201610041608.8A CN105932000B (en) 2015-02-26 2016-01-21 Semiconductor device with a plurality of transistors

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20150027589 2015-02-26
KR1020150027589 2015-02-26

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