JP2006173493A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor Download PDF

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JP2006173493A
JP2006173493A JP2004366621A JP2004366621A JP2006173493A JP 2006173493 A JP2006173493 A JP 2006173493A JP 2004366621 A JP2004366621 A JP 2004366621A JP 2004366621 A JP2004366621 A JP 2004366621A JP 2006173493 A JP2006173493 A JP 2006173493A
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substrate
semiconductor device
transfer mold
semiconductor chip
mold resin
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JP4489575B2 (en
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Akinobu Inoue
明宣 井上
Atsunori Kajiki
篤典 加治木
Hiroyuki Takatsu
浩幸 高津
Takashi Tsubota
崇 坪田
Satoo Yamanishi
学雄 山西
Sadakazu Akaike
貞和 赤池
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device provided with a shield material which can be miniaturized and in which productivity can be enhanced, and to provide a manufacturing method therefor. <P>SOLUTION: A transfer mold resin 90 is provided to cover an individual component 71, a first and a second semiconductor chip 75, 81, and a wire 79, which are mounted on a substrate 51, with the top face 90A of the transfer mold resin 90 being made to be flat. A shield material 91 is electrically connected to a ground terminal 54 by a solder paste 93 while the shield material 91 is brought into contact with the top face 90A of the transfer mold resin 90. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置及びその製造方法に係り、特にシールド材を備えた半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a shield material and a manufacturing method thereof.

従来の半導体装置には、基板上に実装された複数の電子部品（個別部品や半導体チップ等）を電磁波から保護するためのシールドケースを備えたものがある。図１及び図２は、シールドケースを備えた従来の半導体装置の断面図である。なお、図１及び図２において、Ｈ１はポッティング樹脂３５の高さ（以下、「高さＨ１」とする）、Ｈ２は半導体装置１０の高さ（以下、「高さＨ２」とする）、Ｈ３は半導体装置４０の高さ（以下、「高さＨ３」とする）、Ａはポッティング樹脂３５とシールドケース３６との間の隙間（以下、「隙間Ａ」とする）をそれぞれ示している。また、図２において、図１と同一構成部分には同一の符号を付す。   Some conventional semiconductor devices include a shield case for protecting a plurality of electronic components (individual components, semiconductor chips, etc.) mounted on a substrate from electromagnetic waves. 1 and 2 are cross-sectional views of a conventional semiconductor device provided with a shield case. 1 and 2, H1 is the height of the potting resin 35 (hereinafter referred to as “height H1”), H2 is the height of the semiconductor device 10 (hereinafter referred to as “height H2”), and H3. Denotes the height of the semiconductor device 40 (hereinafter referred to as “height H3”), and A denotes the gap between the potting resin 35 and the shield case 36 (hereinafter referred to as “gap A”). In FIG. 2, the same components as those in FIG.

図１に示すように、半導体装置１０は、大略すると、基板１１と、個別部品２６と、半導体チップ３１と、はんだボール２５と、シールドケース３６とを有した構成とされている。基板１１は、大略すると基材１２と、貫通ビア１３と、接続部１４，１５と、グラウンド端子１６と、ソルダーレジスト１７，２３と、配線２１とを有した構成とされている。貫通ビア１３は、基材１２を貫通するよう配設されている。貫通ビア１３は、接続部１４，１５と配線２１との間を電気的に接続するためのものである。   As shown in FIG. 1, the semiconductor device 10 generally includes a substrate 11, individual components 26, a semiconductor chip 31, solder balls 25, and a shield case 36. The substrate 11 is roughly configured to include a base material 12, a through via 13, connection portions 14 and 15, a ground terminal 16, solder resists 17 and 23, and wiring 21. The through via 13 is disposed so as to penetrate the base material 12. The through via 13 is for electrically connecting the connection portions 14 and 15 and the wiring 21.

接続部１４，１５は、基材１２の上面に設けられており、貫通ビア１３と電気的に接続されている。接続部１４は、金ワイヤ３４を介して半導体チップ３１と電気的に接続されるものである。接続部１５は、個別部品２６と電気的に接続されるものである。グラウンド端子１６は、グラウンド電位とされた導体であり、個別部品２６及び半導体チップ３１が設けられた領域よりも外側に位置する基材１２上に設けられている。ソルダーレジスト１７は、接続部１４と接続部１５との間を隔てるように基材１２上に形成されている。   The connection parts 14 and 15 are provided on the upper surface of the base material 12 and are electrically connected to the through via 13. The connection portion 14 is electrically connected to the semiconductor chip 31 via the gold wire 34. The connection unit 15 is electrically connected to the individual component 26. The ground terminal 16 is a conductor having a ground potential, and is provided on the base material 12 positioned outside the region where the individual component 26 and the semiconductor chip 31 are provided. The solder resist 17 is formed on the base material 12 so as to separate the connection portion 14 and the connection portion 15.

配線２１は、はんだボール２５が接続される接続パッド２２を有した構成とされている。配線２１は、貫通ビア１３と接続されるよう基材１２の下面に設けられている。ソルダーレジスト２３は、接続パッド２２を露出すると共に、接続パッド２２以外の配線２１を覆うよう基材１２の下面側に設けられている。   The wiring 21 has a connection pad 22 to which the solder ball 25 is connected. The wiring 21 is provided on the lower surface of the substrate 12 so as to be connected to the through via 13. The solder resist 23 is provided on the lower surface side of the substrate 12 so as to expose the connection pads 22 and cover the wirings 21 other than the connection pads 22.

個別部品２６は、トランジスタ、ダイオード、抵抗、コンデンサ等の基本となる電気的素子であり、１つの機能が１つの部品となっているものである。個別部品２６は、はんだペースト２７により接続部１５と電気的に接続されている。   The individual component 26 is a basic electrical element such as a transistor, a diode, a resistor, or a capacitor, and has one function as one component. The individual component 26 is electrically connected to the connection portion 15 by a solder paste 27.

半導体チップ３１は、半導体チップ本体３２と、電極パッド３３とを有した構成とされている。半導体チップ本体３２は、接着剤２４により基材１２上に接着されている。半導体チップ３１は、電極パッド３３と接続部１４との間を接続する金ワイヤ３４により基板１１と電気的に接続されている。また、半導体チップ３１は、金ワイヤ３４を保護するためのポッティング樹脂３５（ポッティング法により形成された樹脂）により覆われている（例えば、特許文献１参照）。   The semiconductor chip 31 is configured to include a semiconductor chip body 32 and electrode pads 33. The semiconductor chip body 32 is bonded onto the substrate 12 with an adhesive 24. The semiconductor chip 31 is electrically connected to the substrate 11 by a gold wire 34 that connects between the electrode pad 33 and the connection portion 14. The semiconductor chip 31 is covered with a potting resin 35 (resin formed by a potting method) for protecting the gold wire 34 (see, for example, Patent Document 1).

はんだボール２５は、接続パッド２２と電気的に接続されている。はんだボール２５は、半導体装置１０をマザーボード等の他の基板に接続するための外部接続端子である。   The solder ball 25 is electrically connected to the connection pad 22. The solder ball 25 is an external connection terminal for connecting the semiconductor device 10 to another substrate such as a mother board.

シールドケース３６は、個別部品２６及び半導体チップ３１を覆うと共に、ポッティング樹脂３５との間に隙間Ａを設けた状態で、はんだペースト３７によりグラウンド端子１６と電気的に接続されている。このようなシールドケース３６を半導体装置１０に設けることで、電磁波から個別部品２６及び半導体チップ３１を保護することができる。   The shield case 36 covers the individual component 26 and the semiconductor chip 31 and is electrically connected to the ground terminal 16 by the solder paste 37 with a gap A provided between the shield case 36 and the potting resin 35. By providing such a shield case 36 in the semiconductor device 10, the individual component 26 and the semiconductor chip 31 can be protected from electromagnetic waves.

図２に示すように、半導体装置４０は、グラウンド端子４２を基材４１の側面に設け、ポッティング樹脂３５とシールドケース４４との間に隙間Ａを設けた状態で、はんだペースト３７によりグラウンド端子４２とシールドケース４４とを電気的に接続した構成とされている。このように、基材４１の側面にグラウンド端子４２を設けて、グラウンド端子４２とシールドケース４４とを接続することで、基材１２の上面にグラウンド端子１６を設けた半導体装置１０と比較して、半導体装置４０を小型化することができる。なお、図１及び図２には、図示していないが半導体装置１０，４０には、フリップチップ接続された他の半導体チップが設けられており、このフリップチップ接続された他の半導体チップは、ポッティング樹脂３５により覆われることもある。
特開２００１−２６７６２８号公報 As shown in FIG. 2, in the semiconductor device 40, the ground terminal 42 is provided by the solder paste 37 in a state where the ground terminal 42 is provided on the side surface of the base material 41 and the gap A is provided between the potting resin 35 and the shield case 44. And the shield case 44 are electrically connected. As described above, the ground terminal 42 is provided on the side surface of the base material 41, and the ground terminal 42 and the shield case 44 are connected to each other as compared with the semiconductor device 10 provided with the ground terminal 16 on the top surface of the base material 12. The semiconductor device 40 can be downsized. Although not shown in FIGS. 1 and 2, the semiconductor devices 10 and 40 are provided with other semiconductor chips that are flip-chip connected. The potting resin 35 may be covered.
JP 2001-267628 A

しかしながら、ポッティング法により形成されたポッティング樹脂３５は、高さＨ１の制御が難しいという問題や、樹脂形成に時間を要するため、半導体装置１０，４０の生産性が低下してしまうという問題があった。また、ポッティング樹脂３５の凸形状がシールドケース３６，４４に転写されることを防止するため、ポッティング樹脂３５とシールドケース３６，４４との間に隙間Ａを設ける必要があり、これにより、半導体装置１０，４０の高さＨ２，Ｈ３が高くなってしまい、半導体装置１０，４０を小型化することが困難であるという問題があった。   However, the potting resin 35 formed by the potting method has a problem that it is difficult to control the height H1, and since it takes time to form the resin, there is a problem that productivity of the semiconductor devices 10 and 40 is lowered. . In addition, in order to prevent the convex shape of the potting resin 35 from being transferred to the shield cases 36 and 44, it is necessary to provide a gap A between the potting resin 35 and the shield cases 36 and 44. Thus, the semiconductor device The heights H2 and H3 of 10 and 40 become high, and there is a problem that it is difficult to downsize the semiconductor devices 10 and 40.

そこで本発明は、上述した問題点に鑑みなされたものであり、小型化ができると共に、生産性を向上させることのできる半導体装置及びその製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and an object thereof is to provide a semiconductor device that can be reduced in size and improved in productivity and a method for manufacturing the same.

上記課題を解決するために本発明では、次に述べる各手段を講じたことを特徴とするものである。   In order to solve the above-mentioned problems, the present invention is characterized by the following measures.

請求項１記載の発明では、基板と、該基板に実装された半導体チップと、前記基板に設けられ、所定の電位とされた導体と、前記半導体チップを覆うと共に、前記導体と接続されたシールド材とを備えた半導体装置において、前記半導体チップを覆うようトランスファーモールド樹脂を設け、該トランスファーモールド樹脂の上面と前記シールド材とを接触させたことを特徴とする半導体装置により、解決できる。   According to the first aspect of the present invention, a substrate, a semiconductor chip mounted on the substrate, a conductor provided on the substrate and having a predetermined potential, and a shield that covers the semiconductor chip and is connected to the conductor In a semiconductor device including a material, a transfer mold resin is provided so as to cover the semiconductor chip, and the semiconductor device is characterized in that the upper surface of the transfer mold resin and the shield material are brought into contact with each other.

上記発明によれば、半導体チップを覆うようトランスファーモールド樹脂を設け、シールド材をトランスファーモールド樹脂の上面と接触するように配設することで、ポッティング樹脂を用いた従来の半導体装置と比較して、半導体装置の高さ方向のサイズを小型化することができる。また、トランスファーモールド法により形成されるトランスファーモールド樹脂を用いることで、ポッティング法を用いた従来の半導体装置と比較して、半導体装置の生産性を向上させることができる。なお、ここでの所定の電位とは、例えば、グラウンド電位や、半導体チップの電源電位等の電位のことである。   According to the above invention, the transfer mold resin is provided so as to cover the semiconductor chip, and the shield material is disposed so as to be in contact with the upper surface of the transfer mold resin, thereby comparing with a conventional semiconductor device using a potting resin, The size of the semiconductor device in the height direction can be reduced. Further, by using a transfer mold resin formed by a transfer mold method, productivity of the semiconductor device can be improved as compared with a conventional semiconductor device using a potting method. Here, the predetermined potential is, for example, a ground potential or a potential such as a power supply potential of the semiconductor chip.

請求項２記載の発明では、前記トランスファーモールド樹脂の上面は、平坦な面とされていることを特徴とする請求項１に記載の半導体装置により、解決できる。   The invention according to claim 2 can be solved by the semiconductor device according to claim 1, wherein the upper surface of the transfer mold resin is a flat surface.

上記発明によれば、トランスファーモールド樹脂の上面を平坦な面とすることで、トランスファーモールド樹脂に接触されるシールド材とトランスファーモールド樹脂との間に隙間が形成されることを防いで、半導体装置の高さ方向のサイズを小型化することができる。また、半導体装置を、他の基板（例えば、マザーボード）等に実装する際のハンドリング性を向上させることができる。   According to the above invention, by making the upper surface of the transfer mold resin a flat surface, it is possible to prevent a gap from being formed between the shield material that is in contact with the transfer mold resin and the transfer mold resin. The size in the height direction can be reduced. In addition, handling properties when the semiconductor device is mounted on another substrate (for example, a mother board) can be improved.

請求項３記載の発明では、前記導体は、前記基板の側面に設けられていることを特徴とする請求項１または２に記載の半導体装置により、解決できる。   The invention according to claim 3 can be solved by the semiconductor device according to claim 1 or 2, wherein the conductor is provided on a side surface of the substrate.

上記発明によれば、導体を基板の側面に設けることで、半導体装置の基材の面方向の大きさを小さくすることができる。   According to the said invention, the magnitude | size of the surface direction of the base material of a semiconductor device can be made small by providing a conductor in the side surface of a board | substrate.

請求項４記載の発明では、基板と、該基板に実装された半導体チップと、前記基板に設けられ、所定の電位とされた導体と、前記半導体チップを覆うと共に、前記導体と接続されたシールド材とを備えた半導体装置の製造方法において、前記基板が形成される基材は、複数の基板形成領域を有し、前記複数の基板形成領域は隣り合うように配置されており、前記基板形成領域の境界線上に、前記基材を貫通すると共に、前記所定の電位とされた導電部材を形成する導電部材形成工程と、前記基板形成領域に形成された複数の基板に、前記半導体チップを実装する半導体チップ実装工程と、前記基板形成領域に形成された複数の基板に、半導体チップを覆うようトランスファーモールド樹脂を形成するトランスファーモールド樹脂形成工程と、該トランスファーモールド樹脂形成工程後、前記基板形成領域の境界線に沿って前記基材を切断することにより、前記導電部材を切断して前記導体を形成する導体形成工程と、前記トランスファーモールド樹脂の上面と接触すると共に、前記導体と電気的に接続されるようシールド材を配設するシールド材配設工程とを備えたことを特徴とする半導体装置の製造方法により、解決できる。   According to a fourth aspect of the present invention, a substrate, a semiconductor chip mounted on the substrate, a conductor provided on the substrate and having a predetermined potential, a shield that covers the semiconductor chip and is connected to the conductor In the method of manufacturing a semiconductor device comprising a material, the base material on which the substrate is formed has a plurality of substrate formation regions, and the plurality of substrate formation regions are arranged adjacent to each other, and the substrate formation A conductive member forming step of forming a conductive member having the predetermined potential while penetrating the base material on a boundary line of the region, and mounting the semiconductor chip on a plurality of substrates formed in the substrate forming region A semiconductor chip mounting step, a transfer mold resin forming step of forming a transfer mold resin on the plurality of substrates formed in the substrate formation region so as to cover the semiconductor chip, After the transfer mold resin forming step, by cutting the base material along the boundary line of the substrate forming region, the conductor forming step of cutting the conductive member to form the conductor; and the upper surface of the transfer mold resin This can be solved by a method for manufacturing a semiconductor device, comprising: a shield material disposing step of contacting the conductor and disposing a shield material so as to be electrically connected to the conductor.

上記発明によれば、１つの基材に複数の基板形成領域が隣り合うように配置させ、基板形成領域の境界線上に、基材を貫通すると共に、所定の電位とされた導電部材を設け、半導体チップを実装後、半導体チップを覆うようトランスファーモールド樹脂を形成し、基板形成領域の境界線に沿って基材を切断して導体を形成し、導体とシールド材とを電気的に接続することで、１つの基材に従来よりも多くの半導体装置を製造され、半導体装置の生産性を向上させることができる。なお、ここでの所定の電位とは、例えば、グラウンド電位や、半導体チップの電源電位等の電位のことである。   According to the above invention, a plurality of substrate forming regions are arranged adjacent to one base material, and a conductive member that penetrates the base material and has a predetermined potential is provided on the boundary line of the substrate forming region, After mounting the semiconductor chip, form a transfer mold resin to cover the semiconductor chip, cut the base material along the boundary line of the substrate forming area to form a conductor, and electrically connect the conductor and the shield material Thus, more semiconductor devices can be manufactured on one base material than before, and the productivity of the semiconductor devices can be improved. Here, the predetermined potential is, for example, a ground potential or a potential such as a power supply potential of the semiconductor chip.

本発明によれば、小型化ができると共に、生産性を向上させることのできる半導体装置及びその製造方法を提供できる。   ADVANTAGE OF THE INVENTION According to this invention, while being able to reduce in size, the semiconductor device which can improve productivity, and its manufacturing method can be provided.

次に、図面に基づいて本発明の実施例を説明する。
（実施例）
始めに、図３及び図４を参照して、本発明の実施例による半導体装置５０の構成について説明する。図３は、本発明の実施例による半導体装置の斜視図であり、図４は、図３に示した半導体装置のＢ−Ｂ線方向の断面図である。なお、図４において、Ｘ，Ｘ方向は基材５２の面方向を示しており、Ｙ，Ｙ方向はＸ，Ｘ方向に直交する半導体装置５０の高さ方向を示している。また、図４に示したＨ４は基材５２の上面５２Ａを基準にした際のトランスファーモールド樹脂９０の高さ（以下、「高さＨ４」とする）、Ｈ５は半導体装置５０の高さ（以下、「高さＨ５」とする）をそれぞれ示している。 Next, embodiments of the present invention will be described with reference to the drawings.
(Example)
First, the configuration of the semiconductor device 50 according to the embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a perspective view of a semiconductor device according to an embodiment of the present invention, and FIG. 4 is a cross-sectional view of the semiconductor device shown in FIG. In FIG. 4, the X and X directions indicate the surface direction of the base material 52, and the Y and Y directions indicate the height direction of the semiconductor device 50 orthogonal to the X and X directions. 4 is the height of the transfer mold resin 90 (hereinafter referred to as “height H4”) when the upper surface 52A of the base material 52 is used as a reference, and H5 is the height of the semiconductor device 50 (hereinafter referred to as “height H4”). , “Height H5”).

半導体装置５０は、大略すると基板５１と、個別部品７１と、第１の半導体チップ７５と、第２の半導体チップ８１と、トランスファーモールド樹脂９０と、シールド材９１と、はんだボール９４とを有した構成とされている。基板５１は、大略すると基材５２と、貫通ビア５３と、グラウンド端子５４と、第１乃至第３の接続部５６〜５８と、ソルダーレジスト６１，６４と、配線６２とを有した構成とされている。基板５１の外形は、例えば、９ｍｍ□とすることができる。 貫通ビア５３は、基材５２を貫通するように設けられている。貫通ビア５３は、第１乃至第３の接続部５６〜５８と配線６２との間を電気的に接続するためのものである。   The semiconductor device 50 roughly includes a substrate 51, individual components 71, a first semiconductor chip 75, a second semiconductor chip 81, a transfer mold resin 90, a shield material 91, and solder balls 94. It is configured. The substrate 51 is roughly configured to include a base material 52, a through via 53, a ground terminal 54, first to third connection portions 56 to 58, solder resists 61 and 64, and wiring 62. ing. The outer shape of the substrate 51 can be 9 mm □, for example. The through via 53 is provided so as to penetrate the base material 52. The through via 53 is for electrically connecting the first to third connection portions 56 to 58 and the wiring 62.

図５は、本実施例のグラウンド端子の斜視図である。グラウンド端子５４は、グラウンド電位（請求項に記載の「所定の電位」）とされた導体である。グラウンド端子５４は、基材５２の４つの側面にそれぞれ形成された切欠き部９５に配設されている。切欠き部９５は、上下の底面が半円の柱状形状とされている。切欠き部９５は、後述する第２の貫通孔１０２（図９及び図１８参照）を、基板形成領域Ｅの境界線に沿って二等分したもののうちの１つである。グラウンド端子５４は、はんだペースト９３によりシールド材９１と電気的に接続されるものである。グラウンド端子５４の材料には、例えば、Ｃｕを用いることができる。   FIG. 5 is a perspective view of the ground terminal of the present embodiment. The ground terminal 54 is a conductor having a ground potential (“predetermined potential” described in claims). The ground terminal 54 is disposed in a notch 95 formed on each of the four side surfaces of the substrate 52. The notch 95 has a columnar shape whose upper and lower bottom surfaces are semicircular. The notch 95 is one of the two through holes 102 (see FIG. 9 and FIG. 18), which will be described later, divided into two equal parts along the boundary line of the substrate formation region E. The ground terminal 54 is electrically connected to the shield material 91 by the solder paste 93. For example, Cu can be used as the material of the ground terminal 54.

このように、グラウンド端子５４を基材５２の側面に設けることで、基材５２の上面５２Ａにグラウンド端子を設けた場合と比較して、基材５２の面方向（Ｘ，Ｘ方向）の半導体装置５０のサイズを小型化することができる。   Thus, by providing the ground terminal 54 on the side surface of the base material 52, the semiconductor in the surface direction (X, X direction) of the base material 52 is compared with the case where the ground terminal is provided on the upper surface 52A of the base material 52. The size of the device 50 can be reduced.

第１乃至第３の接続部５６〜５８は、基材５２の上面５２Ａに設けられており、それぞれ貫通ビア５３と電気的に接続されている。第１の接続部５６は、個別部品７１の電極７２と電気的に接続されるものである。第２の接続部５７は、第１の半導体チップ７５と電気的に接続されたワイヤ７９が配設されるものである。第３の接続部５８は、スタッドバンプ８３を介して第２の半導体チップ８１が電気的に接続されるものである。   The first to third connection portions 56 to 58 are provided on the upper surface 52 </ b> A of the base material 52, and are electrically connected to the through vias 53, respectively. The first connection portion 56 is electrically connected to the electrode 72 of the individual component 71. The second connection portion 57 is provided with a wire 79 electrically connected to the first semiconductor chip 75. The third connection portion 58 is for electrically connecting the second semiconductor chip 81 via the stud bump 83.

ソルダーレジスト６１は、第１乃至第３の接続部５６〜５８の間を隔てるように基材５２の上面５２Ａに設けられている。配線６２は、接続パッド６３を有しており、貫通ビア５３と電気的に接続されるよう基材５２の下面５２Ｂに配設されている。接続パッド６３は、はんだボール９４と電気的に接続されるものである。ソルダーレジスト６４は、接続パッド６３を露出すると共に、接続パッド６３以外の配線６２を覆うよう基材５２の下面５２Ｂ側に設けられている。はんだボール９４は、半導体装置５０をマザーボード等の他の基板に接続するための外部接続端子であり、接続パッド６２に配設されている。   The solder resist 61 is provided on the upper surface 52A of the base member 52 so as to separate the first to third connection portions 56 to 58. The wiring 62 has a connection pad 63 and is disposed on the lower surface 52 </ b> B of the base material 52 so as to be electrically connected to the through via 53. The connection pad 63 is electrically connected to the solder ball 94. The solder resist 64 is provided on the lower surface 52 </ b> B side of the base material 52 so as to expose the connection pads 63 and cover the wirings 62 other than the connection pads 63. The solder balls 94 are external connection terminals for connecting the semiconductor device 50 to another substrate such as a mother board, and are disposed on the connection pads 62.

個別部品７１は、電極７２を有した構成とされている。電極７２は、個別部品７１と第１の接続部５６との間を電気的に接続するためのものである。電極７２は、はんだペースト７３により第１の接続部５６と接続されている。個別部品７１は、例えば、トランジスタ、ダイオード、抵抗、コンデンサ等の基本となる電気的素子であり、１つの機能が１つの部品となっているものである（「ディスクリート部品」ともいう。）。   The individual component 71 is configured to have an electrode 72. The electrode 72 is for electrically connecting the individual component 71 and the first connection portion 56. The electrode 72 is connected to the first connection portion 56 by a solder paste 73. The individual component 71 is a basic electrical element such as a transistor, a diode, a resistor, or a capacitor, and has one function as one component (also referred to as “discrete component”).

第１の半導体チップ７５は、電極パッド７６を有しており、基板５１に対してワイヤボンディング接続されている。電極パッド７６が設けられていない側の第１の半導体チップ７５は、接着剤７８により基材５２と接着されている。電極パッド７６は、ワイヤ７９と接続されており、ワイヤ７９を介して第２の接続部５７と電気的に接続されている。   The first semiconductor chip 75 has an electrode pad 76 and is connected to the substrate 51 by wire bonding. The first semiconductor chip 75 on the side where the electrode pad 76 is not provided is bonded to the base material 52 with an adhesive 78. The electrode pad 76 is connected to the wire 79 and is electrically connected to the second connecting portion 57 via the wire 79.

第２の半導体チップ８１は、電極パッド８２を有しており、基板５１に対してフリップチップ接続されている。電極パッド８２には、スタッドバンプ８３が設けられており、スタッドバンプ８３は、第３の接続部５８に設けられたはんだペースト８５により第３の接続部５８と電気的に接続されている。また、第２の半導体チップ８１と基板５１との間には、第２の半導体チップ８５と基板５１との間の熱膨張係数のミスマッチを防止するためのアンダーフィル樹脂８７が設けられている。   The second semiconductor chip 81 has an electrode pad 82 and is flip-chip connected to the substrate 51. A stud bump 83 is provided on the electrode pad 82, and the stud bump 83 is electrically connected to the third connection portion 58 by a solder paste 85 provided on the third connection portion 58. In addition, an underfill resin 87 is provided between the second semiconductor chip 81 and the substrate 51 in order to prevent a mismatch in thermal expansion coefficient between the second semiconductor chip 85 and the substrate 51.

トランスファーモールド樹脂９０は、トランスファーモールド法により形成された樹脂であり、個別部品７１、第１及び第２の半導体チップ７５，８１、及びワイヤ７９を覆うように基板５１の上面５２Ａ側に設けられている。トランスファーモールド法とは、封止したい部材（本実施例の場合は、個別部品７１、第１の半導体チップ７５、及び第２の半導体チップ８１が実装された基板５１）を金型成型機にセットして、温度を上げて流動性を持たせた樹脂に圧力をかけて、金型内に流し込んで（圧送）、金型の形に樹脂を成型する方法である。   The transfer mold resin 90 is a resin formed by a transfer mold method, and is provided on the upper surface 52A side of the substrate 51 so as to cover the individual components 71, the first and second semiconductor chips 75 and 81, and the wires 79. Yes. In the transfer molding method, a member to be sealed (in the case of this embodiment, a substrate 51 on which the individual component 71, the first semiconductor chip 75, and the second semiconductor chip 81 are mounted) is set in a mold molding machine. In this method, pressure is applied to the resin that has been made fluid by raising the temperature, and the resin is poured into the mold (pressure feeding) to mold the resin into the mold.

このようなトランスファーモールド樹脂９０を用いることで、ポッティング樹脂３５を用いた場合と比較して、高さＨ４（トランスファーモールド樹脂９０の厚さ）の制御性を向上させることができる。また、樹脂封止に要する時間を短縮して、半導体装置５０の生産性を向上させることができる。なお、トランスファーモールド樹脂９０の高さＨ４は、例えば、０．３ｍｍ〜１．２ｍｍとすることができる。   By using such a transfer mold resin 90, the controllability of the height H4 (the thickness of the transfer mold resin 90) can be improved as compared with the case where the potting resin 35 is used. Further, the time required for resin sealing can be shortened, and the productivity of the semiconductor device 50 can be improved. The height H4 of the transfer mold resin 90 can be set to 0.3 mm to 1.2 mm, for example.

トランスファーモールド樹脂９０の上面９０Ａは、平坦な面とされている。このように、トランスファーモールド樹脂９０の上面９０Ａを平坦な面とすることにより、トランスファーモールド樹脂９０の上面９０Ａとシールド材９１とを接触させた際、トランスファーモールド樹脂９０とシールド材９１との間に隙間が形成されることがなくなり、ポッティング樹脂３５を用いた従来の半導体装置１０，４０の高さＨ２，Ｈ３よりも半導体装置５０の高さＨ５を小さくして、半導体装置５０を小型化することができる。   The upper surface 90A of the transfer mold resin 90 is a flat surface. Thus, when the upper surface 90A of the transfer mold resin 90 is brought into contact with the shield material 91 by making the upper surface 90A of the transfer mold resin 90 flat, the transfer mold resin 90 is interposed between the shield material 91 and the shield material 91. The gap is not formed, and the height H5 of the semiconductor device 50 is made smaller than the heights H2 and H3 of the conventional semiconductor devices 10 and 40 using the potting resin 35, thereby reducing the size of the semiconductor device 50. Can do.

また、トランスファーモールド樹脂９０の上面９０Ａを平坦な面にすると共に、トランスファーモールド樹脂９０の上面９０Ａとシールド材９１とを接触させることにより、半導体装置５０のハンドリング性が向上し、他の基板（例えば、マザーボード）に半導体装置５０を実装する際、容易に実装することができる。
なお、トランスファーモールド樹脂９０には、例えば、エポキシ系樹脂を用いることができる。 Further, by making the upper surface 90A of the transfer mold resin 90 a flat surface and bringing the upper surface 90A of the transfer mold resin 90 and the shield material 91 into contact with each other, the handling property of the semiconductor device 50 is improved and another substrate (for example, When the semiconductor device 50 is mounted on the mother board), it can be easily mounted.
For example, an epoxy resin can be used for the transfer mold resin 90.

シールド材９１は、トランスファーモールド樹脂９０の上面９０Ａ及び側面９０Ｂを覆う形状とされている。シールド材９１は、トランスファーモールド樹脂９０の上面９０Ａと接触した状態で、はんだペースト９３によりグラウンド端子５４と電気的に接続されている。   The shield material 91 has a shape that covers the upper surface 90 </ b> A and the side surface 90 </ b> B of the transfer mold resin 90. The shield material 91 is electrically connected to the ground terminal 54 by the solder paste 93 while being in contact with the upper surface 90A of the transfer mold resin 90.

このように、シールド材９１をトランスファーモールド樹脂９０の上面９０Ａと接触させることにより、半導体装置５０を小型化できるだけでなく、シールド材９１に放熱機能を持たせて、トランスファーモールド樹脂９０の熱を半導体装置５０外に放熱させることができる。シールド材９１の材料には、例えば、洋白（nickel silver）を用いることができる。洋白は、展延性や耐食性に優れたＣｕ−Ｎｉ−Ｚｎ合金である。Ｃｕ−Ｎｉ−Ｚｎ合金の混合比としては、例えば、Ｃｕを６２ｗｔ％、Ｎｉを１４ｗｔ％、Ｚｎを２４ｗｔ％とすることができる。   Thus, by bringing the shield material 91 into contact with the upper surface 90A of the transfer mold resin 90, not only the semiconductor device 50 can be miniaturized, but also the shield material 91 has a heat dissipation function, and the heat of the transfer mold resin 90 is transferred to the semiconductor. Heat can be dissipated outside the device 50. As a material of the shield material 91, for example, nickel silver can be used. Yohaku is a Cu—Ni—Zn alloy with excellent spreadability and corrosion resistance. As a mixing ratio of the Cu—Ni—Zn alloy, for example, Cu may be 62 wt%, Ni may be 14 wt%, and Zn may be 24 wt%.

はんだボール９４は、半導体装置５０をマザーボード等の他の基板に接続するための外部接続端子である。はんだボール９４は、接続パッド６３に配設されており、接続パッド６３と電気的に接続されている。   The solder ball 94 is an external connection terminal for connecting the semiconductor device 50 to another board such as a mother board. The solder ball 94 is disposed on the connection pad 63 and is electrically connected to the connection pad 63.

上記説明したように、基材５２の側面にグラウンド端子５４を設け、個別部品７１、第１及び第２の半導体チップ７５，８１、及びワイヤ７９を覆うと共に、上面９０Ａが平坦とされたトランスファーモールド樹脂９０を設け、シールド材９１をトランスファーモールド樹脂９０の上面９０Ａと接触させた状態で、シールド材９１とグラウンド端子５４とを電気的に接続した構成とすることにより、従来の半導体装置１０，４０よりも半導体装置５０を小型化することができる。また、ポッティング樹脂３５を用いた従来の半導体装置１０，４０と比較して、半導体装置５０の生産性を向上させることができる。なお、切欠き部９５が形成される位置は、基材５２の側面であれば良く、本実施例に限定されない。例えば、切欠き部９５を基材５２側面の角部に設けても良い。また、切欠き部９５の形状は、本実施例に限定されない。さらに、基材５２の側面にグラウンド端子５４の代わりに、所定の電位、例えば、半導体チップの電源電位（例えば、３．３Ｖ，１．８Ｖ）とされた導体を設けても良い。   As described above, the transfer terminal in which the ground terminal 54 is provided on the side surface of the base material 52 to cover the individual component 71, the first and second semiconductor chips 75 and 81, and the wire 79, and the upper surface 90A is flat. By providing the resin 90 and electrically connecting the shield material 91 and the ground terminal 54 in a state where the shield material 91 is in contact with the upper surface 90A of the transfer mold resin 90, the conventional semiconductor devices 10 and 40 are provided. Thus, the semiconductor device 50 can be reduced in size. Further, the productivity of the semiconductor device 50 can be improved as compared with the conventional semiconductor devices 10 and 40 using the potting resin 35. The position where the notch 95 is formed is not limited to this embodiment as long as it is on the side surface of the substrate 52. For example, you may provide the notch part 95 in the corner | angular part of the base material 52 side surface. Moreover, the shape of the notch part 95 is not limited to a present Example. Furthermore, instead of the ground terminal 54, a conductor having a predetermined potential, for example, a power supply potential (eg, 3.3V, 1.8V) of a semiconductor chip, may be provided on the side surface of the substrate 52.

図６は、従来の基材と基板形成領域との位置関係を示した平面図であり、図７は、本実施例の基材と基板形成領域との位置関係を示した平面図であり、図８は、図７に示した基材を拡大した平面図である。なお、図６において、Ｃは従来の基板が形成される領域（以下、「基板形成領域Ｃ」とする）を示しており、図７において、Ｅは本実施例の基板５１が形成される領域（以下、「基板形成領域Ｅ」とする）を示している。また、図８において、ダイサーが切断する基板形成領域Ｅの境界線（以下、「境界線Ｄ」とする）を示している。   FIG. 6 is a plan view showing the positional relationship between the conventional base material and the substrate forming region, and FIG. 7 is a plan view showing the positional relationship between the base material and the substrate forming region of this example, FIG. 8 is an enlarged plan view of the base material shown in FIG. In FIG. 6, C indicates a region where a conventional substrate is formed (hereinafter referred to as “substrate forming region C”), and in FIG. 7, E indicates a region where the substrate 51 of this embodiment is formed. (Hereinafter referred to as “substrate forming region E”). Further, FIG. 8 shows a boundary line (hereinafter referred to as “boundary line D”) of the substrate formation region E cut by the dicer.

図６に示すように、従来は、１つの基材９８に１つの基板形成領域Ｃが対応していたため、基板の形成に寄与しない基材９８部分が多く存在し、基材９８を有効に活用することができなかった。本実施例の半導体装置５０では、図７に示すように、１つの基材５２に対して複数の基板形成領域Ｅ（図７では９つ）を設けると共に、複数の基板形成領域Ｅを隣り合うように配置させ、複数の基板形成領域Ｅに一括してトランスファーモールド樹脂９０を設けて半導体装置５０を製造するため、基材５２を有効に活用して、半導体装置５０の生産性を向上させることができる。なお、基板形成領域Ｅの大きさは、例えば、９ｍｍ□とすることができる。   As shown in FIG. 6, conventionally, since one substrate forming region C corresponds to one base material 98, there are many base material 98 portions that do not contribute to the formation of the substrate, and the base material 98 is effectively used. I couldn't. In the semiconductor device 50 of the present embodiment, as shown in FIG. 7, a plurality of substrate formation regions E (nine in FIG. 7) are provided for one base material 52 and the plurality of substrate formation regions E are adjacent to each other. In order to manufacture the semiconductor device 50 by providing the transfer mold resin 90 collectively in a plurality of substrate formation regions E, the base material 52 is effectively used to improve the productivity of the semiconductor device 50. Can do. The size of the substrate formation region E can be set to 9 mm □, for example.

次に、図９乃至図１７を参照して、半導体装置５０の製造方法について説明する。図９乃至図１７は、本実施例の半導体装置の製造工程を示した図である。なお、図９乃至図１７において、図４に示した半導体装置５０と同一構成部分には同一の符号を付す。   Next, a method for manufacturing the semiconductor device 50 will be described with reference to FIGS. 9 to 17 are views showing a manufacturing process of the semiconductor device of this embodiment. 9 to 17, the same components as those of the semiconductor device 50 shown in FIG. 4 are denoted by the same reference numerals.

始めに、図９に示すように、基板形成領域Ｅに対応した基材５２に第１の貫通孔１０１と、基板形成領域Ｅの境界線Ｄ上の基材５２に第２の貫通孔１０２とを形成する。第１の貫通孔１０１は、貫通ビア５３を配設するためのものである。図１８は、第２の貫通孔が形成された基材の平面図である。第２の貫通孔１０２は、グラウンド端子５４の母材となるグラウンド端子母材１０４（図１０参照）を配設するためのものである。図１８に示すように、第２の貫通孔１０２は、基板形成領域Ｅの境界線Ｄ上に形成される。第１及び第２の貫通孔１０１，１０２は、例えば、ドリルを用いたドリル加工、レーザ加工、異方性エッチングのいずれかの方法により形成することができる。また、基板形成領域Ｅの大きさが９ｍｍ□の場合、第２の貫通孔１０２の直径Ｒ１の大きさは、例えば、０．５ｍｍ〜１．０ｍｍとすることができる。   First, as shown in FIG. 9, the first through hole 101 is formed in the base material 52 corresponding to the substrate forming region E, and the second through hole 102 is formed in the base material 52 on the boundary line D of the substrate forming region E. Form. The first through hole 101 is for arranging the through via 53. FIG. 18 is a plan view of a substrate on which a second through hole is formed. The second through hole 102 is for arranging a ground terminal base material 104 (see FIG. 10) that is a base material of the ground terminal 54. As shown in FIG. 18, the second through hole 102 is formed on the boundary line D of the substrate formation region E. The first and second through holes 101 and 102 can be formed, for example, by any one of drilling using a drill, laser processing, and anisotropic etching. Further, when the size of the substrate formation region E is 9 mm □, the size of the diameter R1 of the second through hole 102 can be set to 0.5 mm to 1.0 mm, for example.

次に、図１０に示すように、第１及び第２の貫通孔１０１，１０２に導電部材を設け、第１の貫通孔１０１に貫通ビア５３と、第２の貫通孔１０２にグラウンド端子母材１０４とを形成する（導電部材形成工程）。グラウンド端子母材１０４は、グラウンド電位とされた導電部材であり、後述するダイサーにより二等分されて２つのグラウンド端子５４となるものである。導電部材の材料には、例えば、Ｃｕを用いることができる。図１９は、グラウンド端子母材の他の例を示した平面図である。なお、図１０においては、第２の貫通孔１０２を充填するように導電部材を設けてグラウンド端子母材１０４を形成したが、図１９に示すように、第２の貫通孔１０２の中心部に貫通孔Ｇが形成されるように導電部材を設けて、グラウンド端子母材１０５を形成しても良い。   Next, as shown in FIG. 10, conductive members are provided in the first and second through holes 101, 102, a through via 53 is provided in the first through hole 101, and a ground terminal base material is provided in the second through hole 102. 104 (conductive member forming step). The ground terminal base material 104 is a conductive member having a ground potential, and is divided into two equal parts by a dicer described later to become two ground terminals 54. For example, Cu can be used as the material of the conductive member. FIG. 19 is a plan view showing another example of the ground terminal base material. In FIG. 10, the ground terminal base material 104 is formed by providing a conductive member so as to fill the second through-hole 102. However, as shown in FIG. 19, in the central portion of the second through-hole 102. The ground terminal base material 105 may be formed by providing a conductive member so that the through hole G is formed.

次に、図１１に示すように、基材５２の上面５２Ａに、貫通ビア５３と電気的に接続される第１乃至第３の接続部５６〜５８と、ソルダーレジスト６１とを形成する。続いて、基材５２の下面５２Ｂに、接続パッド６３を備えた配線６２と、接続パッド６３以外の配線６２を覆うソルダーレジスト６４とを形成する。なお、図１１に示したＦは、第１の半導体チップ７５が配設される基材５２上の領域（以下、「第１の半導体チップ配設領域Ｆ」とする）を示している。   Next, as illustrated in FIG. 11, first to third connection portions 56 to 58 that are electrically connected to the through via 53 and the solder resist 61 are formed on the upper surface 52 </ b> A of the base material 52. Subsequently, the wiring 62 including the connection pads 63 and the solder resist 64 that covers the wirings 62 other than the connection pads 63 are formed on the lower surface 52 </ b> B of the base material 52. In addition, F shown in FIG. 11 indicates a region on the base material 52 where the first semiconductor chip 75 is disposed (hereinafter referred to as “first semiconductor chip disposition region F”).

次に、図１２に示すように、図１１に示した構造体に個別部品７１と第１及び第２の半導体チップ７５，８１とを実装する（半導体チップ実装工程）。具体的には、個別部品７１の電極７２を、はんだペースト７３により第１の接続部５６と電気的に接続する。続いて、基材５２上の第１の半導体チップ配設領域Ｆに第１の半導体チップ７５を接着剤７８により接着し、電極パッド７６と第２の接続パッド５７との間をワイヤ７９により接続して、第１の半導体チップ７５を実装する。次に、電極パッド８２に配設されたスタッドバンプ８３を、第３の接続５８にはんだペースト８５により接続して、第２の半導体チップ８１を実装し、その後、第２の半導体チップ８１と基材５２との間にアンダーフィル樹脂８７を配設する。   Next, as shown in FIG. 12, the individual component 71 and the first and second semiconductor chips 75 and 81 are mounted on the structure shown in FIG. 11 (semiconductor chip mounting step). Specifically, the electrode 72 of the individual component 71 is electrically connected to the first connection portion 56 by the solder paste 73. Subsequently, the first semiconductor chip 75 is bonded to the first semiconductor chip arrangement region F on the base member 52 with an adhesive 78, and the electrode pad 76 and the second connection pad 57 are connected by the wire 79. Then, the first semiconductor chip 75 is mounted. Next, the stud bump 83 provided on the electrode pad 82 is connected to the third connection 58 by the solder paste 85 to mount the second semiconductor chip 81, and then the second semiconductor chip 81 and the base are mounted. An underfill resin 87 is disposed between the material 52.

次に、図１３に示すように、基材５２と対向する面１０６Ａが平坦な面とされた金型１０６を、基材５２の上面５２Ａ側に配置させて、金型１０６と基材５２との間に、個別部品７１、第１及び第２の半導体チップ７５，８１、及びワイヤ７９を覆うようにトランスファーモールド樹脂９０を充填し、その後、図１４に示すように、金型１０６を基材５２から取り外して、上面９０Ａが平坦な面とされたトランスファーモールド樹脂９０を形成する（トランスファーモールド樹脂形成工程）。本実施例の場合、９つの基板形成領域Ｅに対して、一括してトランスファーモールド樹脂９０を形成する。このように、複数の基板形成領域Ｅに対して、一括してトランスファーモールド樹脂９０を設けることにより、ポッティング樹脂３５を用いた場合と比較して、樹脂封止に要する時間が短縮され、半導体装置５０の生産性を向上させることができる。なお、トランスファーモールド樹脂９０の高さＨ４は、例えば、０．３ｍｍ〜１．２ｍｍとすることができる。   Next, as shown in FIG. 13, the mold 106 having a flat surface 106 </ b> A facing the base material 52 is disposed on the upper surface 52 </ b> A side of the base material 52. In the meantime, the transfer mold resin 90 is filled so as to cover the individual parts 71, the first and second semiconductor chips 75, 81, and the wires 79, and then, as shown in FIG. The transfer mold resin 90 is formed so that the upper surface 90A is a flat surface that is removed from the surface 52 (transfer mold resin forming step). In the case of the present embodiment, the transfer mold resin 90 is formed collectively on the nine substrate formation regions E. As described above, by providing the transfer mold resin 90 collectively for the plurality of substrate formation regions E, the time required for resin sealing is shortened as compared with the case where the potting resin 35 is used. The productivity of 50 can be improved. The height H4 of the transfer mold resin 90 can be set to 0.3 mm to 1.2 mm, for example.

次に、図１５に示すように、図１４に示した構造体を基板形成領域Ｅの境界線Ｄに沿って、ダイサーにより個片化する。これにより、グラウンド端子母材１０４が二等分されて、グラウンド端子５４が形成される（導体形成工程）。続いて、図１６に示すように、シールド材９１をトランスファーモールド樹脂９０の上面９０Ａと接触するよう配置させ、グラウンド端子５４と対向するシールド材９１とグラウンド端子５４とをはんだペースト９３により電気的に接続する（シールド材配設工程）。その後、図１７に示すように、接続パッド６３にはんだボール９４を配設することにより、半導体装置５０が製造される。   Next, as illustrated in FIG. 15, the structure illustrated in FIG. 14 is separated into pieces by a dicer along the boundary line D of the substrate formation region E. Thereby, the ground terminal base material 104 is divided into two equal parts, and the ground terminal 54 is formed (conductor forming step). Subsequently, as shown in FIG. 16, the shield material 91 is disposed so as to be in contact with the upper surface 90 </ b> A of the transfer mold resin 90, and the shield material 91 and the ground terminal 54 facing the ground terminal 54 are electrically connected by the solder paste 93. Connect (shield material placement step). Thereafter, as shown in FIG. 17, the semiconductor device 50 is manufactured by disposing the solder balls 94 on the connection pads 63.

上記説明したように、基材５２に複数の基板形成領域Ｅを隣り合うように設け、複数の基板形成領域Ｅに対して、一括してトランスファーモールド樹脂９０を設けることにより、１つの基材５２当たりの基板５１の取れ数が増加すると共に、樹脂封止に要する時間を短縮して、半導体装置５０の生産性を向上させることができる。   As described above, a plurality of substrate formation regions E are provided adjacent to each other on the base material 52, and a transfer mold resin 90 is collectively provided on the plurality of substrate formation regions E, whereby one base material 52 is provided. It is possible to increase the productivity of the semiconductor device 50 by increasing the number of the substrates 51 per hit and reducing the time required for resin sealing.

以上、本発明の好ましい実施例について詳述したが、本発明はかかる特定の実施形態に限定されるものではなく、特許請求の範囲内に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。図２０は、グラウンド端子母材が形成された基材の平面図である。なお、グラウンド端子母材を設ける位置は、基板形成領域Ｅの境界線Ｄ上であれば良く、本実施例の位置に限定されない。例えば、図２０に示すように、基板形成領域Ｅの角部に形成されたた第２の貫通孔１０９にグラウンド端子母材１１０を設けても良い。また、グラウンド端子５４は、基材５２の上面５２Ａに設けても良い。   The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims. Deformation / change is possible. FIG. 20 is a plan view of a base material on which a ground terminal base material is formed. The position where the ground terminal base material is provided may be on the boundary line D of the substrate formation region E, and is not limited to the position of this embodiment. For example, as shown in FIG. 20, the ground terminal base material 110 may be provided in the second through hole 109 formed in the corner portion of the substrate formation region E. The ground terminal 54 may be provided on the upper surface 52 </ b> A of the base material 52.

本発明によれば、小型化ができると共に、生産性を向上させることのできる半導体装置及びその製造方法を提供できる。   ADVANTAGE OF THE INVENTION According to this invention, while being able to reduce in size, the semiconductor device which can improve productivity, and its manufacturing method can be provided.

シールドケースを備えた従来の半導体装置の断面図（その１）である。It is sectional drawing (the 1) of the conventional semiconductor device provided with the shield case. シールドケースを備えた従来の半導体装置の断面図（その２）である。It is sectional drawing (the 2) of the conventional semiconductor device provided with the shield case. 本発明の実施例による半導体装置の斜視図である。1 is a perspective view of a semiconductor device according to an embodiment of the present invention. 図３に示した半導体装置のＢ−Ｂ線方向の断面図である。FIG. 4 is a sectional view of the semiconductor device shown in FIG. 3 in the BB line direction. 本実施例のグラウンド端子の斜視図である。It is a perspective view of the ground terminal of a present Example. 従来の基材と基板形成領域との位置関係を示した平面図である。It is the top view which showed the positional relationship of the conventional base material and a board | substrate formation area. 本実施例の基材と基板形成領域との位置関係を示した平面図である。It is the top view which showed the positional relationship of the base material and board | substrate formation area of a present Example. 図７に示した基材を拡大した平面図である。It is the top view to which the base material shown in FIG. 7 was expanded. 本実施例の半導体装置の製造工程を示した図（その１）である。It is FIG. (The 1) which showed the manufacturing process of the semiconductor device of a present Example. 本実施例の半導体装置の製造工程を示した図（その２）である。It is FIG. (The 2) which showed the manufacturing process of the semiconductor device of a present Example. 本実施例の半導体装置の製造工程を示した図（その３）である。It is FIG. (The 3) which showed the manufacturing process of the semiconductor device of a present Example. 本実施例の半導体装置の製造工程を示した図（その４）である。It is FIG. (The 4) which showed the manufacturing process of the semiconductor device of a present Example. 本実施例の半導体装置の製造工程を示した図（その５）である。It is FIG. (The 5) which showed the manufacturing process of the semiconductor device of a present Example. 本実施例の半導体装置の製造工程を示した図（その６）である。It is FIG. (The 6) which showed the manufacturing process of the semiconductor device of a present Example. 本実施例の半導体装置の製造工程を示した図（その７）である。It is FIG. (The 7) which showed the manufacturing process of the semiconductor device of a present Example. 本実施例の半導体装置の製造工程を示した図（その８）である。It is FIG. (The 8) which showed the manufacturing process of the semiconductor device of a present Example. 本実施例の半導体装置の製造工程を示した図（その９）である。It is FIG. (The 9) which showed the manufacturing process of the semiconductor device of a present Example. 第２の貫通孔が形成された基材の平面図（その１）である。It is a top view (the 1) of a substrate in which the 2nd penetration hole was formed. グラウンド端子母材の他の例を示した平面図である。It is the top view which showed the other example of the ground terminal base material. グラウンド端子母材が形成された基材の平面図（その２）である。It is a top view (the 2) of the base material in which the ground terminal base material was formed.

符号の説明Explanation of symbols

１０，４０，５０ 半導体装置
１１，５１ 基板
１２，４１，５２，９８ 基材
１３，５３ 貫通ビア
１４，１５ 接続部
１６，４２，５４ グラウンド端子
１７，２３，６１，６４ ソルダーレジスト
２１，６２ 配線
２２，６３ 接続パッド
２４，７８ 接着剤
２５，９４ はんだボール
２６，７１ 個別部品
２７，３７，７３，８５，９３ はんだペースト
３１ 半導体チップ
３２ 半導体チップ本体
３３，７６，８２ 電極パッド
３４ 金ワイヤ
３５ ポッティング樹脂
３６，４４ シールドケース
５２Ａ，９０Ａ 上面
５２Ｂ 下面
５６ 第１の接続部
５７ 第２の接続部
５８ 第３の接続部
７２ 電極
７５ 第１の半導体チップ
７９ ワイヤ
８１ 第２の半導体チップ
８３ スタッドバンプ
８７ アンダーフィル樹脂
９０ トランスファーモールド樹脂
９０Ｂ 側面
９１ シールド材
９５ 切欠き部
１０１ 第１の貫通孔
１０２，１０９ 第２の貫通孔
１０４，１０５，１１０ グラウンド端子母材
１０６ 金型
１０６Ａ 面
Ａ 隙間
Ｃ，Ｅ 基板形成領域
Ｆ 第１の半導体チップ配設領域
Ｇ 貫通孔
Ｈ１〜Ｈ５ 高さ
Ｒ１ 直径 10, 40, 50 Semiconductor device 11, 51 Substrate 12, 41, 52, 98 Base material 13, 53 Through-via 14, 15 Connection portion 16, 42, 54 Ground terminal 17, 23, 61, 64 Solder resist 21, 62 Wiring 22, 63 Connection pads 24, 78 Adhesives 25, 94 Solder balls 26, 71 Individual parts 27, 37, 73, 85, 93 Solder paste 31 Semiconductor chip 32 Semiconductor chip body 33, 76, 82 Electrode pads 34 Gold wires 35 Potting Resin 36, 44 Shield case 52A, 90A Upper surface 52B Lower surface 56 First connection portion 57 Second connection portion 58 Third connection portion 72 Electrode 75 First semiconductor chip 79 Wire 81 Second semiconductor chip 83 Stud bump 87 Underfill resin 90 Transfer mold resin 90B Side surface 91 Shield material 95 Notch portion 101 First through hole 102, 109 Second through hole 104, 105, 110 Ground terminal base material 106 Mold 106A Surface A Clearance C, E Substrate formation region F First semiconductor Tip placement area G Through hole H1 to H5 Height R1 Diameter

Claims (4)

基板と、
該基板に実装された半導体チップと、
前記基板に設けられ、所定の電位とされた導体と、
前記半導体チップを覆うと共に、前記導体と接続されたシールド材とを備えた半導体装置において、
前記半導体チップを覆うようトランスファーモールド樹脂を設け、
該トランスファーモールド樹脂の上面と前記シールド材とを接触させたことを特徴とする半導体装置。 A substrate,
A semiconductor chip mounted on the substrate;
A conductor provided on the substrate and having a predetermined potential;
In a semiconductor device that covers the semiconductor chip and includes a shield material connected to the conductor,
A transfer mold resin is provided so as to cover the semiconductor chip,
A semiconductor device, wherein an upper surface of the transfer mold resin and the shield material are brought into contact with each other. 前記トランスファーモールド樹脂の上面は、平坦な面とされていることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein an upper surface of the transfer mold resin is a flat surface. 前記導体は、前記基板の側面に設けられていることを特徴とする請求項１または２に記載の半導体装置。 The semiconductor device according to claim 1, wherein the conductor is provided on a side surface of the substrate. 基板と、
該基板に実装された半導体チップと、
前記基板に設けられ、所定の電位とされた導体と、
前記半導体チップを覆うと共に、前記導体と接続されたシールド材とを備えた半導体装置の製造方法において、
前記基板が形成される基材は、複数の基板形成領域を有し、前記複数の基板形成領域は隣り合うように配置されており、
前記基板形成領域の境界線上に、前記基材を貫通すると共に、前記所定の電位とされた導電部材を形成する導電部材形成工程と、
前記基板形成領域に形成された複数の基板に、前記半導体チップを実装する半導体チップ実装工程と、
前記基板形成領域に形成された複数の基板に、半導体チップを覆うようトランスファーモールド樹脂を形成するトランスファーモールド樹脂形成工程と、
該トランスファーモールド樹脂形成工程後、前記基板形成領域の境界線に沿って前記基材を切断することにより、前記導電部材を切断して前記導体を形成する導体形成工程と、
前記トランスファーモールド樹脂の上面と接触すると共に、前記導体と電気的に接続されるようシールド材を配設するシールド材配設工程とを備えたことを特徴とする半導体装置の製造方法。
A substrate,
A semiconductor chip mounted on the substrate;
A conductor provided on the substrate and having a predetermined potential;
In the method of manufacturing a semiconductor device that covers the semiconductor chip and includes a shield material connected to the conductor,
The substrate on which the substrate is formed has a plurality of substrate forming regions, and the plurality of substrate forming regions are arranged adjacent to each other,
A conductive member forming step of forming a conductive member penetrating the base material and having the predetermined potential on the boundary line of the substrate forming region;
A semiconductor chip mounting step of mounting the semiconductor chip on a plurality of substrates formed in the substrate formation region;
A transfer mold resin forming step of forming a transfer mold resin on the plurality of substrates formed in the substrate forming region so as to cover the semiconductor chip;
After the transfer mold resin forming step, by cutting the base material along a boundary line of the substrate forming region, a conductor forming step of cutting the conductive member to form the conductor;
A method of manufacturing a semiconductor device, comprising: a shield material disposing step of contacting a top surface of the transfer mold resin and disposing a shield material so as to be electrically connected to the conductor.
JP2004366621A 2004-12-17 2004-12-17 Semiconductor device and manufacturing method thereof Expired - Fee Related JP4489575B2 (en)

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